US20020004339A1 - System level test socket - Google Patents
System level test socket Download PDFInfo
- Publication number
- US20020004339A1 US20020004339A1 US09/610,867 US61086700A US2002004339A1 US 20020004339 A1 US20020004339 A1 US 20020004339A1 US 61086700 A US61086700 A US 61086700A US 2002004339 A1 US2002004339 A1 US 2002004339A1
- Authority
- US
- United States
- Prior art keywords
- test socket
- semiconductor package
- grid array
- test
- socket
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 131
- 239000004065 semiconductor Substances 0.000 claims abstract description 89
- 229910000679 solder Inorganic materials 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims description 8
- 230000006835 compression Effects 0.000 claims 1
- 238000007906 compression Methods 0.000 claims 1
- 239000007787 solid Substances 0.000 abstract 1
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229920001971 elastomer Polymers 0.000 description 1
- 239000000806 elastomer Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0433—Sockets for IC's or transistors
- G01R1/0483—Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips
Definitions
- the present invention relates to a system level test socket for a semiconductor package having a non-pin grid array footprint.
- the present invention has particular applicability in testing a semiconductor package having either a land grid array footprint or a ball grid array footprint.
- Burn-in boards are used to test semiconductor packages, such as integrated circuit (IC) chips, to ensure that the semiconductor packages are operating in a proper manner.
- the semiconductor package to be tested is inserted into a socket mounted on a burn-in board.
- an IC chip is inserted into an IC socket on a burn-in board.
- the burn-in board is then placed in a testing chamber and power, ground and test signals are coupled to the burn-in board.
- the semiconductor packages in the IC chip are then tested for a period of time under stress conditions to ensure that the semiconductor packages are performing according to set standards or specifications.
- the semiconductor package can be placed directly into a pin grid array socket on the circuit board.
- semiconductor packages having non-pin grid array footprints such as land grid array or ball grid array footprints are becoming more commonly employed. Problems arise when these non-pin grid array semiconductor packages need to be tested.
- the footprint of the semiconductor package needs to be adapted for connection to the pin grid array socket. Therefore, a device such as an interposer, is used to convert the semiconductor package footprints. For example, a semiconductor package having a ball grid array footprint is inserted into an interposer having a pin grid array and the interposer is inserted into a pin grid array socket on a circuit board.
- using an interposer or other converting device creates a high profile with long electrical connections. Moreover, requiring an additional device unnecessarily increases the chance of a defective component and as a result, can damage the semiconductor package.
- embodiments of the present invention which provide method ad apparatus for testing a semiconductor package having either a land grid array footprint or a ball grid array footprint, without requiring an additional component to convert the footprint.
- the test socket and method of using the socket of the present invention connect a semiconductor package having a non-pin grid array to a circuit board.
- the test socket includes a plurality of solder pads, wherein the solder pads are positioned to be aligned with corresponding leads from the non-pin grid array of a semiconductor package and a plurality of corresponding internal leads for connecting the plurality of solder pads to a plurality of leads on the bottom surface of the test socket.
- the test socket allows for the testing of semiconductor packages having non-pin grid array without having to use an interposer to convert the non-pin grid array. Also, the test socket allows for a lower profile since the interposer is not needed.
- the testing system of the present invention includes a test socket for connecting a semiconductor package having a non-pin grid array to a circuit board.
- the test socket includes a plurality of solder pads, wherein the solder pads are positioned to be aligned with corresponding leads from the non-pin grid array of a semiconductor package and a plurality of corresponding internal leads for connecting the plurality of solder pads to a plurality of leads on the bottom surface of the test socket.
- the testing system includes one or more test sockets on a circuit board with a fastener for pressing a semiconductor package against a test socket. The testing system allows for a plurality of semiconductor packages having a non-pin grid array to be inserted into the test sockets on a circuit board and tested at the same time.
- Figure 1 a is a front view of an exemplary semiconductor package having a land grid array footprint.
- Figure 1 b is a front view of an exemplary semiconductor package having a ball grid array footprint.
- FIG. 2 is top view of an exemplary system level test socket in accordance with an embodiment of the present invention.
- FIG. 3 a is a front view of an exemplary system level test socket having a pin grid array in accordance with an embodiment of the present invention.
- FIG. 3 b is a front view of an exemplary system level test socket having a ball grid array in accordance with an embodiment of the present invention.
- FIG. 3 c is a front view of an exemplary system level test socket having a land grid array in accordance with an embodiment of the present invention.
- FIG. 4 is a front view of an exemplary testing system with an exemplary system level test socket in accordance with an embodiment of the present invention.
- FIG. 5 is a flow diagram of the steps for using an exemplary system level test socket in accordance with an embodiment of the present invention.
- a system level test socket is able to provide electrical connections between a semiconductor package having a non-pin grid array footprint and the circuit board. Moreover, the system level test socket provides a low profile, thereby providing shorter electrical connections between the semiconductor package and the circuit board.
- FIGS. 1 a and 1 b front views of semiconductor packages having a land grid array footprint and a ball grid array footprint, respectively, are illustrated.
- a semiconductor package 10 has a plurality of lands 12 a - h on the bottom surface of the semiconductor package 10 .
- semiconductor package 14 has a plurality of solder balls 16 a - h .
- the lands 12 a - h and solder balls 16 a - g provide electrical signals to and from the semiconductor packages 10 , 14 , respectively.
- the test socket 20 includes a socket body 22 , solder pads 24 , and guide pins 26 a , 26 b .
- the socket body 22 and guide pins 26 a , 26 b are preferably made of a metal material, such as stainless steel.
- the socket body 22 includes walls 28 a - d which allow a semiconductor package to be inserted into the cavity created by the walls 28 a - d .
- the solder pads 24 are positioned to align with the footprint of the semiconductor package that will be tested. Therefore, test sockets 20 are designed for semiconductor packages having standard footprints.
- a test socket 20 can be custom designed for semiconductor packages having non-standard footprints.
- the guide pins 26 a , 26 b are used to guide a hydraulic cylinder having guide slots which fit around the guide pins 26 a , 26 b .
- the hydraulic cylinder uses pressure to press a semiconductor package against the test socket 20 .
- the semiconductor package is pressed against the test socket 20 using a fastener, such as a clamp or screwed down fastener.
- a fastener such as a clamp or screwed down fastener.
- the test socket 20 includes internal leads 30 a - h which provide electrical connections between the leads on the bottom of the non-pin grid array package and the leads on the bottom of the test socket 20 .
- the leads on the bottom of the test socket 20 are pins 32 a - h .
- FIGS. 3 b and 3 c illustrate solder balls 34 a - h and lands 36 a - h on the bottom of the test socket 20 , respectively.
- the leads on the bottom of the test socket 20 can be other leads as known in the art.
- the leads on the bottom of the test socket 20 are used to provide electrical connections between the test socket 20 and a circuit board.
- FIG. 4 a front view of a testing system for testing a semiconductor package in a test socket in accordance with an embodiment of the present invention is illustrated.
- a test socket 20 having a semiconductor package 10 with a land grid array footprint is mounted on a circuit board 48 .
- the test socket 20 can be mounted by either soldering it directly to the circuit board 48 or using other methods of attachments known in the art, such as pressure or an elastomer.
- the circuit board 48 is a burn-in board.
- the circuit board 48 can be a motherboard or a fatherboard which plugs into a motherboard. Therefore, the test socket 20 of the present invention functions as a system test level socket for inserting a semiconductor package into the test socket 20 and to test the semiconductor package in an oven for a period of time under stress conditions such as heat and humidity.
- a hydraulic cylinder 40 having guide slots 44 a , 44 b is used to press the semiconductor package 10 against the test socket 20 .
- the hydraulic cylinder 40 causes the leads 12 a - h on the bottom of the semiconductor package 10 to press against the solder pads 24 a - h on the test socket 20 , thereby ensuring electrical connectivity between the leads 12 a - h on the bottom of the semiconductor package 10 and the solder pads 24 a - h of the test socket 20 .
- the amount of pressure applied is controlled by a controller 46 such that the package leads (pins, solder balls, lands, etc.) are not damaged.
- the guide pins 26 a , 26 b are used to guide the hydraulic cylinder 40 onto the test socket 20 with the guide slots 44 a , 44 b lining up with and sliding over the guide pins 26 a , 26 b on the test socket 20 .
- FIG. 5 a flow chart of the steps for using the test socket in accordance with an embodiment of the present invention is illustrated.
- the process starts with a semiconductor package being inserted into the test socket mounted on a burn-in board at step 50 .
- the semiconductor package is pressed against the test socket ensuring electrical connectivity between the connections on the bottom of the semiconductor package and the solder pads in the test socket at step 52 . In some embodiments, it is not necessary to press the semiconductor package against the test socket as long as there are adequate connections between the semiconductor package and test socket.
- the semiconductor package is electrically tested at step 54 .
- the pressure is removed from the semiconductor package at step 56 .
- the semiconductor package is removed from the test socket at step 58 .
- the present invention allows for the testing of semiconductor packages having non-pin grid array footprints without requiring an interposer to convert the footprint of the semiconductor package to a pin grid array footprint so it can be inserted into a pin grid array test socket. Therefore, the test socket of the present invention provides connections between the semiconductor package having a non-pin grid array footprint and the circuit board on which the test socket is mounted. In addition, the test socket includes guide pins to assist in guiding a hydraulic cylinder onto the test socket to compress the semiconductor package to the test socket.
Abstract
Description
- The present invention relates to a system level test socket for a semiconductor package having a non-pin grid array footprint. The present invention has particular applicability in testing a semiconductor package having either a land grid array footprint or a ball grid array footprint.
- Burn-in boards are used to test semiconductor packages, such as integrated circuit (IC) chips, to ensure that the semiconductor packages are operating in a proper manner. Typically, the semiconductor package to be tested is inserted into a socket mounted on a burn-in board. For example, an IC chip is inserted into an IC socket on a burn-in board. The burn-in board is then placed in a testing chamber and power, ground and test signals are coupled to the burn-in board. The semiconductor packages in the IC chip are then tested for a period of time under stress conditions to ensure that the semiconductor packages are performing according to set standards or specifications.
- As long as the semiconductor package has a pin grid array footprint, the semiconductor package can be placed directly into a pin grid array socket on the circuit board. However, semiconductor packages having non-pin grid array footprints, such as land grid array or ball grid array footprints are becoming more commonly employed. Problems arise when these non-pin grid array semiconductor packages need to be tested. In order to test such semiconductor packages, the footprint of the semiconductor package needs to be adapted for connection to the pin grid array socket. Therefore, a device such as an interposer, is used to convert the semiconductor package footprints. For example, a semiconductor package having a ball grid array footprint is inserted into an interposer having a pin grid array and the interposer is inserted into a pin grid array socket on a circuit board. However, using an interposer or other converting device creates a high profile with long electrical connections. Moreover, requiring an additional device unnecessarily increases the chance of a defective component and as a result, can damage the semiconductor package.
- Therefore, there is a need for a system level test socket capable of receiving a semiconductor package having either a land grid array footprint or a ball grid array footprint, without requiring an additional component to convert the footprint.
- There also exists a need for a simplified methodology for testing a semiconductor package having either a land grid array footprint or a ball grid array footprint, using a system level test socket on a circuit board, where the semiconductor package and socket have a low profile and short electrical paths between the semiconductor package and the circuit board.
- These and other needs are met by embodiments of the present invention which provide method ad apparatus for testing a semiconductor package having either a land grid array footprint or a ball grid array footprint, without requiring an additional component to convert the footprint.
- The test socket and method of using the socket of the present invention connect a semiconductor package having a non-pin grid array to a circuit board. The test socket includes a plurality of solder pads, wherein the solder pads are positioned to be aligned with corresponding leads from the non-pin grid array of a semiconductor package and a plurality of corresponding internal leads for connecting the plurality of solder pads to a plurality of leads on the bottom surface of the test socket. The test socket allows for the testing of semiconductor packages having non-pin grid array without having to use an interposer to convert the non-pin grid array. Also, the test socket allows for a lower profile since the interposer is not needed.
- The testing system of the present invention includes a test socket for connecting a semiconductor package having a non-pin grid array to a circuit board. The test socket includes a plurality of solder pads, wherein the solder pads are positioned to be aligned with corresponding leads from the non-pin grid array of a semiconductor package and a plurality of corresponding internal leads for connecting the plurality of solder pads to a plurality of leads on the bottom surface of the test socket. The testing system includes one or more test sockets on a circuit board with a fastener for pressing a semiconductor package against a test socket. The testing system allows for a plurality of semiconductor packages having a non-pin grid array to be inserted into the test sockets on a circuit board and tested at the same time.
- Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
- Reference is made to the attached drawings, wherein elements having the same reference numeral designations represent like elements throughout, and wherein:
- Figure 1a is a front view of an exemplary semiconductor package having a land grid array footprint.
- Figure 1b is a front view of an exemplary semiconductor package having a ball grid array footprint.
- FIG. 2 is top view of an exemplary system level test socket in accordance with an embodiment of the present invention.
- FIG. 3a is a front view of an exemplary system level test socket having a pin grid array in accordance with an embodiment of the present invention.
- FIG. 3b is a front view of an exemplary system level test socket having a ball grid array in accordance with an embodiment of the present invention.
- FIG. 3c is a front view of an exemplary system level test socket having a land grid array in accordance with an embodiment of the present invention.
- FIG. 4 is a front view of an exemplary testing system with an exemplary system level test socket in accordance with an embodiment of the present invention.
- FIG. 5 is a flow diagram of the steps for using an exemplary system level test socket in accordance with an embodiment of the present invention.
- Current system level test sockets are incapable of receiving a semiconductor package having either a land grid array footprint or a ball grid array footprint. Conventional test sockets for semiconductor packages require a component to convert the footprint of semiconductor package having a non-pin grid array footprint to a pin grid array footprint. Moreover, the component for converting the footprint increases the profile of the test package semiconductor package and as a result, increases the length of the electrical connection between the semiconductor package and the test socket. The present invention addresses and solves these and other problems stemming from conventional test sockets requiring a component to convert the footprint of a semiconductor package having a non-pin grid array footprint.
- According to the methodology of the present invention, a system level test socket is able to provide electrical connections between a semiconductor package having a non-pin grid array footprint and the circuit board. Moreover, the system level test socket provides a low profile, thereby providing shorter electrical connections between the semiconductor package and the circuit board.
- Referring to FIGS. 1a and 1 b, front views of semiconductor packages having a land grid array footprint and a ball grid array footprint, respectively, are illustrated. As shown, a
semiconductor package 10 has a plurality of lands 12 a-h on the bottom surface of thesemiconductor package 10. Similarly,semiconductor package 14 has a plurality ofsolder balls 16 a-h. The lands 12 a-h andsolder balls 16 a-g provide electrical signals to and from thesemiconductor packages - Referring to FIG. 2, the top view of a system level test socket in accordance with an embodiment of the present invention is illustrated. As shown, the
test socket 20 includes asocket body 22,solder pads 24, andguide pins socket body 22 andguide pins socket body 22 includes walls 28 a-d which allow a semiconductor package to be inserted into the cavity created by the walls 28 a-d. Thesolder pads 24 are positioned to align with the footprint of the semiconductor package that will be tested. Therefore,test sockets 20 are designed for semiconductor packages having standard footprints. In addition, atest socket 20 can be custom designed for semiconductor packages having non-standard footprints. Theguide pins guide pins test socket 20. In alternate embodiments, the semiconductor package is pressed against thetest socket 20 using a fastener, such as a clamp or screwed down fastener. By pressing the semiconductor package onto thetest socket 20, the connections or leads on the bottom of the semiconductor package, such as solder balls or lands, are pressed against thesolder pads 24 of thetest socket 20, thereby ensuring electrical connectivity between them. - Referring to FIG. 3a, a front view of an exemplary system level test socket having a pin grid array in accordance with an embodiment of the present invention is illustrated. As shown, the
test socket 20 includes internal leads 30 a-h which provide electrical connections between the leads on the bottom of the non-pin grid array package and the leads on the bottom of thetest socket 20. In FIG. 3a, the leads on the bottom of thetest socket 20 are pins 32 a-h. FIGS. 3b and 3 c illustrate solder balls 34 a-h and lands 36 a-h on the bottom of thetest socket 20, respectively. In alternate embodiments, the leads on the bottom of thetest socket 20 can be other leads as known in the art. The leads on the bottom of thetest socket 20 are used to provide electrical connections between thetest socket 20 and a circuit board. - Referring to FIG. 4, a front view of a testing system for testing a semiconductor package in a test socket in accordance with an embodiment of the present invention is illustrated. As shown, a
test socket 20 having asemiconductor package 10 with a land grid array footprint is mounted on acircuit board 48. Thetest socket 20 can be mounted by either soldering it directly to thecircuit board 48 or using other methods of attachments known in the art, such as pressure or an elastomer. - In the preferred embodiment, the
circuit board 48 is a burn-in board. Thecircuit board 48 can be a motherboard or a fatherboard which plugs into a motherboard. Therefore, thetest socket 20 of the present invention functions as a system test level socket for inserting a semiconductor package into thetest socket 20 and to test the semiconductor package in an oven for a period of time under stress conditions such as heat and humidity. - As shown, a
hydraulic cylinder 40 having guide slots 44 a, 44 b is used to press thesemiconductor package 10 against thetest socket 20. Thehydraulic cylinder 40 causes the leads 12 a-h on the bottom of thesemiconductor package 10 to press against thesolder pads 24 a-h on thetest socket 20, thereby ensuring electrical connectivity between the leads 12 a-h on the bottom of thesemiconductor package 10 and thesolder pads 24 a-h of thetest socket 20. The amount of pressure applied is controlled by a controller 46 such that the package leads (pins, solder balls, lands, etc.) are not damaged. The guide pins 26 a, 26 b, are used to guide thehydraulic cylinder 40 onto thetest socket 20 with the guide slots 44 a, 44 b lining up with and sliding over the guide pins 26 a, 26 b on thetest socket 20. - Referring to FIG. 5, a flow chart of the steps for using the test socket in accordance with an embodiment of the present invention is illustrated. As shown, the process starts with a semiconductor package being inserted into the test socket mounted on a burn-in board at
step 50. The semiconductor package is pressed against the test socket ensuring electrical connectivity between the connections on the bottom of the semiconductor package and the solder pads in the test socket atstep 52. In some embodiments, it is not necessary to press the semiconductor package against the test socket as long as there are adequate connections between the semiconductor package and test socket. The semiconductor package is electrically tested atstep 54. The pressure is removed from the semiconductor package atstep 56. The semiconductor package is removed from the test socket atstep 58. - The present invention allows for the testing of semiconductor packages having non-pin grid array footprints without requiring an interposer to convert the footprint of the semiconductor package to a pin grid array footprint so it can be inserted into a pin grid array test socket. Therefore, the test socket of the present invention provides connections between the semiconductor package having a non-pin grid array footprint and the circuit board on which the test socket is mounted. In addition, the test socket includes guide pins to assist in guiding a hydraulic cylinder onto the test socket to compress the semiconductor package to the test socket.
- Only the preferred embodiment of the present invention and but a few examples of its versatility are shown and described in the present disclosure. It is to be understood that the present invention is capable of use in various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein.
Claims (17)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/610,867 US6341963B1 (en) | 2000-07-06 | 2000-07-06 | System level test socket |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/610,867 US6341963B1 (en) | 2000-07-06 | 2000-07-06 | System level test socket |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020004339A1 true US20020004339A1 (en) | 2002-01-10 |
US6341963B1 US6341963B1 (en) | 2002-01-29 |
Family
ID=24446738
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/610,867 Expired - Lifetime US6341963B1 (en) | 2000-07-06 | 2000-07-06 | System level test socket |
Country Status (1)
Country | Link |
---|---|
US (1) | US6341963B1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040196057A1 (en) * | 2003-01-09 | 2004-10-07 | Infineon Technologies Ag | Socket or adapter device for semiconductor devices, method for testing semiconductor devices, and system comprising at least one socket or adapter device |
US20040196061A1 (en) * | 2003-01-09 | 2004-10-07 | Infineon Technologies Ag | Socket or adapter device for semiconductor devices, method for testing semiconductor devices, and system comprising at least one socket or adapter device |
US20160322164A1 (en) * | 2014-08-06 | 2016-11-03 | Murata Manufacturing Co., Ltd. | Composite electronic component |
CN111707929A (en) * | 2020-06-29 | 2020-09-25 | 深圳赛西信息技术有限公司 | PGA packaging microwave test fixture |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7077659B2 (en) * | 1999-12-16 | 2006-07-18 | Paricon Technologies Corporation | Separable electrical interconnect with anisotropic conductive elastomer and a rigid adapter |
US6331836B1 (en) * | 2000-08-24 | 2001-12-18 | Fast Location.Net, Llc | Method and apparatus for rapidly estimating the doppler-error and other receiver frequency errors of global positioning system satellite signals weakened by obstructions in the signal path |
US6551134B1 (en) * | 2001-06-11 | 2003-04-22 | Picolight Incorporated | Mounted transceivers |
US6702587B2 (en) * | 2001-08-08 | 2004-03-09 | Paricon Technologies Corporation | Separable electrical connector using anisotropic conductive elastomer interconnect medium |
US7249954B2 (en) | 2002-02-26 | 2007-07-31 | Paricon Technologies Corporation | Separable electrical interconnect with anisotropic conductive elastomer for translating footprint |
WO2003076957A1 (en) * | 2002-03-05 | 2003-09-18 | Rika Denshi America, Inc. | Apparatus for interfacing electronic packages and test equipment |
KR100510501B1 (en) * | 2002-12-05 | 2005-08-26 | 삼성전자주식회사 | Test kit for semiconductor package and test method thereof |
US7520761B2 (en) * | 2006-07-17 | 2009-04-21 | Paricon Technologies | Separable electrical interconnect with anisotropic conductive elastomer and adaptor with channel for engaging a frame |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3838413A1 (en) * | 1988-11-12 | 1990-05-17 | Mania Gmbh | ADAPTER FOR ELECTRONIC TEST DEVICES FOR PCBS AND THE LIKE |
US5810607A (en) * | 1995-09-13 | 1998-09-22 | International Business Machines Corporation | Interconnector with contact pads having enhanced durability |
US5475317A (en) * | 1993-12-23 | 1995-12-12 | Epi Technologies, Inc. | Singulated bare die tester and method of performing forced temperature electrical tests and burn-in |
TW441227B (en) * | 1995-05-26 | 2001-06-16 | E Tec Ag | Contact arrangement for detachably attaching an electric component, especially an integrated circuit to a printed circuit board |
US5702255A (en) * | 1995-11-03 | 1997-12-30 | Advanced Interconnections Corporation | Ball grid array socket assembly |
US6016254A (en) * | 1996-07-15 | 2000-01-18 | Pfaff; Wayne K. | Mounting apparatus for grid array packages |
US5883788A (en) * | 1996-10-31 | 1999-03-16 | Hewlett-Packard Company | Backing plate for LGA mounting of integrated circuits facilitates probing of the IC's pins |
JPH11329648A (en) * | 1998-05-19 | 1999-11-30 | Molex Inc | Ic device socket |
-
2000
- 2000-07-06 US US09/610,867 patent/US6341963B1/en not_active Expired - Lifetime
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040196057A1 (en) * | 2003-01-09 | 2004-10-07 | Infineon Technologies Ag | Socket or adapter device for semiconductor devices, method for testing semiconductor devices, and system comprising at least one socket or adapter device |
US20040196061A1 (en) * | 2003-01-09 | 2004-10-07 | Infineon Technologies Ag | Socket or adapter device for semiconductor devices, method for testing semiconductor devices, and system comprising at least one socket or adapter device |
DE10300532B4 (en) * | 2003-01-09 | 2010-11-11 | Qimonda Ag | System having at least one test socket device for testing semiconductor devices |
US20160322164A1 (en) * | 2014-08-06 | 2016-11-03 | Murata Manufacturing Co., Ltd. | Composite electronic component |
CN111707929A (en) * | 2020-06-29 | 2020-09-25 | 深圳赛西信息技术有限公司 | PGA packaging microwave test fixture |
Also Published As
Publication number | Publication date |
---|---|
US6341963B1 (en) | 2002-01-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6939143B2 (en) | Flexible compliant interconnect assembly | |
US6344684B1 (en) | Multi-layered pin grid array interposer apparatus and method for testing semiconductor devices having a non-pin grid array footprint | |
US6341963B1 (en) | System level test socket | |
US6420681B1 (en) | Method and process of contact to a heat softened solder ball array | |
US6957963B2 (en) | Compliant interconnect assembly | |
US7192806B2 (en) | Method of establishing non-permanent electrical connection between an integrated circuit device lead element and a substrate | |
US6094059A (en) | Apparatus and method for burn-in/testing of integrated circuit devices | |
US6562641B1 (en) | Apparatus and methods of semiconductor packages having circuit-bearing interconnect components | |
JP4911495B2 (en) | Socket for semiconductor integrated circuit | |
US5923176A (en) | High speed test fixture | |
CN209746014U (en) | Test fixture for communication port in chip integrated module | |
US7368814B1 (en) | Surface mount adapter apparatus and methods regarding same | |
US20060091538A1 (en) | Low profile and tight pad-pitch land-grid-array (LGA) socket | |
US6300781B1 (en) | Reliable method and apparatus for interfacing between a ball grid array handler and a ball grid array testing system | |
US20060105594A1 (en) | Method for package burn-in testing | |
US6100585A (en) | Structure for mounting device on circuit board | |
US20030051338A1 (en) | Method of assembling a land grid array module and alignment tool for use therewith | |
US6597189B1 (en) | Socketless/boardless test interposer card | |
SG124229A1 (en) | Testing integrated circuits | |
US6251695B1 (en) | Multichip module packaging process for known good die burn-in | |
US6433565B1 (en) | Test fixture for flip chip ball grid array circuits | |
US20100330830A1 (en) | Vertical probe intrface system | |
US6638080B2 (en) | Integrated ball grid array-pin grid array-flex laminate test assembly | |
US20020043984A1 (en) | Support carrier for temporarily attaching integrated circuit chips to a chip carrier and method | |
US6710369B1 (en) | Liquid metal socket system and method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: ADVANCED MICRO DEVICES, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HUSSAIN, RAFIQUL;REEL/FRAME:010922/0726 Effective date: 20000628 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: AFFIRMATION OF PATENT ASSIGNMENT;ASSIGNOR:ADVANCED MICRO DEVICES, INC.;REEL/FRAME:023119/0083 Effective date: 20090630 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION, DELAWARE Free format text: SECURITY AGREEMENT;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049490/0001 Effective date: 20181127 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:054636/0001 Effective date: 20201117 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001 Effective date: 20201117 |