US20020005050A1 - Method for making integrated optical waveguides and micromachined features - Google Patents
Method for making integrated optical waveguides and micromachined features Download PDFInfo
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- US20020005050A1 US20020005050A1 US09/862,593 US86259301A US2002005050A1 US 20020005050 A1 US20020005050 A1 US 20020005050A1 US 86259301 A US86259301 A US 86259301A US 2002005050 A1 US2002005050 A1 US 2002005050A1
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/13—Integrated optical circuits characterised by the manufacturing method
- G02B6/136—Integrated optical circuits characterised by the manufacturing method by etching
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B2006/12166—Manufacturing methods
- G02B2006/12176—Etching
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/26—Optical coupling means
- G02B6/30—Optical coupling means for use between fibre and thin-film device
Definitions
- the present invention generally relates to optical devices, and more particularly, the present invention relates to the fabrication of optical devices having integrated optical waveguides.
- Optical integrated circuit (OIC) and optical bench fabrication often involves transferring patterns to a substrate. These patterns may be used to form a variety of structures to include conductive circuit lines, planar waveguides, mesas and recesses. Typically, the desired structures are formed using lithography. Lithography may be achieved by techniques such as photolithography, x-ray lithography and e-beam lithography.
- a layer of photo-reactive film may be formed over the substrate.
- a photolithographic mask containing the image of a desired pattern is then placed in contact with the photoresist film. Radiation of a wavelength to which the photoresist is sensitive is incident upon the mask. The radiation passes through the transparent areas of the mask and the exposed areas of the photoresist are reactive to the radiation. The photoresist film is then chemically developed, leaving behind a pattern of photoresist substantially identical to the pattern on the mask.
- the patterned photoresist on the substrate may be used in a variety of applications to form the structures referenced above.
- a pattern photoresist may act as a mask for selective etching of a substrate. This selective etching may be used to fabricate recesses and as mesas in the substrate.
- the mesas and recesses may be used for a variety of purposes, including passive alignment of optical elements.
- an optical device is fabricated having at least one integrated waveguide and at least one micro-machined feature.
- exemplary micro-machined features include grooves, recesses and inclined surfaces formed in the substrate surface.
- a mask layer is deposited over a surface of a substrate structure, and the mask layer is patterned to obtain a mask pattern over the surface of the substrate structure.
- a first etching process is then carried out for obtaining the at least one integrated optical waveguide core at the surface of the substrate structure, and a second etching process is carried out for obtaining the at least one micro-machined feature at the surface of the substrate structure.
- the same previously formed mask pattern is used as a mask in both the first and second etching processes, thereby resulting in accurate positioning of the waveguide core relative to the micro-machined feature.
- FIGS. 1 ( a ) through 1 ( m ) are side views for describing a method of fabricating an optical device according to an embodiment of the present invention.
- FIGS. 2 ( a ) through 2 ( i ) are top views for describing a method of fabricating an optical device according to another embodiment of the present invention.
- FIGS. 3 ( a ) through 3 ( m ) are side views for describing a method of fabricating an optical device according to the embodiment of FIGS. 2 ( a ) through 2 ( i ).
- FIG. 4 is a top view for describing a variation of the embodiment of FIGS. 2 ( a ) through 2 ( i ).
- FIGS. 5 ( a ) and 5 ( b ) are side views corresponding to the variation of FIG. 4.
- FIG. 6 is a side view of another embodiment of the present invention.
- FIGS. 7 ( a ) through 7 ( e ) are side views for describing a method of fabricating an optical device according to another embodiment of the present invention.
- FIGS. 8 ( a ) through 8 ( l ) are side views for describing a method of fabricating an optical device according to another embodiment of the present invention.
- the present invention is at least partially characterized by the use of the same, preferably planar, mask pattern as an etching mask in defining the horizontal location of micro-machined (etched) features at the substrate surface of an optical device relative to the waveguide cores also at the substrate surface of the optical device.
- exemplary micro-machined features include grooves, recesses and inclined surfaces formed in the substrate surface for any of a variety of purposes.
- grooves may be machined (etched) into the substrate surface for holding optical fibers which are to be optically coupled to the integrated waveguide cores.
- recesses may be formed for holding spherical elements which function as guide balls in an optical switch device.
- inclined substrate surfaces may fabricated as alignment surfaces for accurate mounting of the optical device into a system. The accurate horizontal positioning of these features relative to the integrated waveguide cores fosters accurate optical coupling between the integrated waveguide cores and external and/or internal components.
- FIGS. 1 ( a ) through 1 ( m ) of the drawings An illustrative embodiment of a method of fabricating an optical device according to the present invention will now be described with reference to FIGS. 1 ( a ) through 1 ( m ) of the drawings. Throughout these figures, like elements are designated by the same reference numbers.
- FIG. 1( a ) generally depicts a substrate 101 .
- the substrate 101 is a silicon substrate.
- any of a variety of substrate structures may be adopted, including silicon-on-insulator (SOI) substrates.
- SOI silicon-on-insulator
- a pit 102 is etched in the substrate 101 as shown in FIG. 1( b ).
- the pit 102 is optionally formed so as to define inclined sidewalls 103 .
- a cladding material layer 104 is deposited over the surface of the substrate 101 and within the pit 102 .
- the cladding material layer 104 is formed of silicon dioxide (SiO 2 ), although other materials may be readily adopted.
- FIG. 1( c ) The structure of FIG. 1( c ) is then planarized to obtain the structure shown in FIG. 1( d ).
- the cladding layer material 104 is contained with the pit 102 , and the remaining surface of the substrate 101 is exposed.
- a core material layer 105 is deposited over the surface of the structure of FIG. 1( d ) so as to cover the exposed surface of the substrate 101 and the surface of the cladding material layer 104 contained within the pit 102 .
- the core material layer 105 is formed of silica.
- other materials such as silicon and silicon nitride.
- a mask layer 106 a / 106 b is then deposited and patterned over the core material layer 105 .
- the patterned mask layer includes portions 106 a which define etched features and portions 106 b which define waveguides.
- the patterned mask layer may be formed of a metal such as chromium (Cr).
- Cr chromium
- Other materials may be used, however, such as aluminum, titanium, copper, gold, nickel, metal silicides, silicon nitride, and other etch resistant materials.
- Exposed portions of the core material layer 105 are then removed by reactive ion etching (RIE) as illustrated in FIG. 1( g ).
- RIE reactive ion etching
- the remaining core material layer is defined by etched feature portions 105 a and waveguide portions 105 b .
- the mask layer portions 106 b (FIG. 1( f )) are then removed from the respective tops of the waveguide portions 105 b , and another cladding material layer 107 is deposited over a resultant structure as shown in FIG. 1( h ).
- the cladding material layer 107 may, for example, be formed of SiO 2 or other materials.
- a mask 108 is deposited over the cladding material layer 107 so as to cover the waveguide portions 105 b and partially overlap the mask layer portions 106 a and underlying etched feature portions 105 a .
- Another etch process e.g., wet etching or RIE
- RIE wet etching
- FIG. 1( i ) The structure of FIG. 1( i ) is then subjected to a wet etch to obtain the structure of FIG. 1( j ) in which inclined surface features 109 are formed at opposite sides of the silicon substrate 101 .
- the inclined surface features 109 are defined here by the same mask pattern what was previously used to defined the waveguide portions 105 a of the core material layer.
- the inclined surface features 109 may actually define half of a V-shaped groove in the case where another device is being simultaneously formed in the substrate 101 adjacent to the device illustrated in the drawings.
- FIG. 1( k ) Another mask is applied as shown in FIG. 1( k ).
- the mask includes a portion 110 a which covers the waveguide portions 105 b of the core layer, and portions 110 b which cover the inclined surfaces 109 of the substrate 101 .
- This structure is then etched in hydroflouric acid (HF) to obtain the structure shown in FIG. 1( l ).
- the side surfaces 111 a of the upper cladding layer 107 may exhibit a slight concave configuration.
- the mask portions 110 a and 110 b are then removed to obtain the device structure of FIG. 1( m ) having the waveguide cores 105 b sandwiched between lower and upper cladding layers 104 and 107 , respectively.
- the distance D of FIG. 1( m ) is a horizontal distance between the waveguide core 105 a and the inclined surface feature 109 . Since the same mask pattern 106 a / 106 b is used to etch both the waveguide 105 a and the feature 109 , this distance D may be precisely set, and the device characteristics and alignment tolerances are thereby improved.
- like elements are designated by the same reference numbers.
- a generally V-shaped groove is aligned with an integrate optical waveguide core(s).
- FIGS. 2 ( a ) and 3 ( a ) illustrate a structure which is similar to that obtained in FIG. 1( e ) described above. That is, in FIGS. 2 ( a ) and 3 ( a ), reference number 201 denotes a substrate, reference number 204 denotes a lower cladding material layer, and reference number 205 denotes a core material layer.
- a mask layer is deposited over the cladding material layer 205 as shown in FIGS. 2 ( b ) and 3 ( b ).
- the mask layer includes a first portion 206 a which surrounds and thereby defines a groove region 213 , and a second portion 206 b which covers and thereby defines a waveguide region 214 .
- the waveguide region 214 and the groove region 213 are aligned with one another along their respective lengths.
- the drawings depict a continuous second mask portion 206 b .
- the mask portion 206 b can actually comprise a number of parallel masks for defined a corresponding number of parallel waveguide cores within the waveguide region 214 .
- the exposed portions of the core material layer 205 are removed by RIE using the first and second mask portions 206 a and 206 b as a mask.
- a portion 205 a of the core material layer remains below the first mask portion 206 a
- another portion 205 b of the core material layer remains below the second mask 206 b .
- the portion 206 b of the mask layer is removed from atop the portion 205 b of the core material layer within the waveguide region 214 .
- FIGS. 2 ( e ) and 3 ( d ) An upper cladding material layer is then deposited over the entire surface of the structure shown in FIGS. 2 ( d ) and 3 ( d ).
- the resultant configuration is depicted in FIGS. 2 ( e ) and 3 ( e ) in which reference number 207 denotes the upper cladding material layer.
- a mask 208 is deposited over the upper cladding material layer 207 such that edges 231 of an opening 230 thereof are aligned with the portion 206 a .
- FIG. 3( f ) is a side view of FIG. 2( f )
- FIG. 3( g ) is a cross-sectional view of FIG. 2( f ) along line 2 - 2 ′.
- FIGS. 2 ( g ), 3 ( h ) and 3 ( i ) Exposed portions of the upper cladding material layer 207 are then removed by RIE using the mask 208 as a mask, whereby the surface of the substrate 201 within the groove region 213 becomes exposed.
- the resultant configuration is shown in FIGS. 2 ( g ), 3 ( h ) and 3 ( i ).
- FIG. 3( h ) is a side view of FIG. 2( g )
- FIG. 3( i ) is a cross-sectional view of FIG. 2( g ) along line 4 - 4 ′.
- FIGS. 2 ( g ), 3 ( h ) and 3 ( i ) is then subjected to a wet etching process using the mask 208 as a mask, to thereby form a groove 240 in the exposed surface portion of the substrate 201 .
- the groove 240 is defined here by the same mask pattern what was previously used to defined the waveguide portions 205 a of the core material layer.
- the mask 208 is then removed, and the resultant configuration is illustrated in FIGS. 2 ( h ), 3 ( j ) and 3 ( k ), where FIG. 3( j ) is a side view of FIG. 2( h ), and FIG. 3( k ) is a cross-sectional view of FIG. 2( h ) along line 6 - 6 ′.
- the groove 240 extends lengthwise in alignment with the waveguide region 214 .
- FIGS. 2 ( i ), 3 ( l ) and 3 ( m ) The resultant configuration is shown in FIGS. 2 ( i ), 3 ( l ) and 3 ( m ), where FIG. 3( l ) is a side view of FIG. 2( i ), and FIG. 3( m ) is a cross-sectional view of FIG. 2( i ) along line 8 - 8 ′.
- reference number 260 denotes the dicing saw cut.
- the waveguide region 214 and the groove 240 i.e., “feature” are precisely aligned since the same mask pattern was used in the fabrication of each.
- FIGS. 4 , 5 ( a ) and 5 ( b ) A modification of the previous embodiment is shown in FIGS. 4 , 5 ( a ) and 5 ( b ), where FIG. 5( a ) is a cross-sectional view of FIG. 4 along line 10 - 10 ′ after the RIE process, and FIG. 5( b ) is a cross-sectional view of FIG. 4 along line 10 - 10 ′ after the wet etch process.
- the first mask portion 406 a extends in two parallel strips on either side of the groove region 413 . This is contrasted with the configuration of the previous embodiment in which the first mask portion surrounds the groove region on three sides. Otherwise, the process is carried out in the same manner as the previous embodiment.
- FIG. 6 illustrates an alternative process in which a layer of silicon nitride 680 is disposed under the core material layer in a vicinity of the machined features. Silicon nitride exhibits superior masking properties (compared to SiO 2 ) for anisotropic wet etching of the silicon substrate 601 .
- FIGS. 7 ( a ) through ( e ) Another embodiment of the present invention will now be described with reference to FIGS. 7 ( a ) through ( e ).
- the core material layer is not etched to define the micro-machined features until after the waveguides are defined.
- FIG. 7( a ) illustrates a structure similar to that described above in connection with FIG. 1( f ).
- a lower cladding layer 704 is contained with a pit 702 formed in the surface of a substrate 701 .
- a core material layer 705 extends over the surface of the substrate 701 and the lower cladding layer 704 , and a mask pattern is formed over the core material layer 705 .
- the mask pattern includes etched feature portions 706 a and waveguide portions 706 b.
- a mask 790 is formed over the core material layer 705 and the mask pattern 706 a / 706 b so as to have an opening aligned with the lower cladding layer 704 .
- the exposed portions of the core material layer 705 are then removed by RIE and the mask 790 is removed to obtain the structure depicted in FIG. 7( c ).
- reference number 705 b denotes the waveguide portions of the core material layer remaining after etching.
- the portions 706 b of the first mask are then removed, and an upper cladding layer 707 is deposited as shown in FIG. 7( d ).
- This structure is then subjected to an etch process (e.g., wet etching or RIE) to remove portions of the upper cladding layer 707 and thereby define the machined features as shown in FIG. 7( e ).
- RIE wet etching or RIE
- the process then proceeds as in the first described embodiment (see FIG. 1 ( i )).
- One advantage of the present embodiment is that the machined features can be more accurate since the core layer defining the machined features is etched only once.
- FIGS. 8 ( a ) through 8 ( l ) of the drawings are illustrative embodiments of the present invention.
- a pit 802 is etched in a substrate 801 as shown in FIG. 8( a ).
- the substrate 801 is a silicon substrate.
- SOI silicon-on-insulator
- the pit 802 is optionally formed so as to define inclined sidewalls 803 .
- a cladding material layer 804 is deposited over the surface of the substrate 801 and within the pit 802 .
- the cladding material layer 804 is formed of silicon dioxide (SiO 2 ), although other materials may be adopted. Deposition of the cladding material layer 804 is halted prior to completely filling the pit 802 , such that an upper surface of cladding material layer 804 is a displaced a distance “D” below a level of an upper surface of the substrate 801 .
- a core material layer 805 is deposited over the surface of the cladding material layer 804 .
- the core material layer 105 is formed of silica.
- other materials may be used, including but not limited to silicon and silicon nitride.
- the structure of FIG. 8( c ) is then planarized to obtain the structure of FIG. 8( d ). As shown, both the core material layer 805 and the cladding layer material 804 are contained with the pit 802 , and the remaining surface of the substrate 801 is exposed.
- a mask layer is then deposited and patterned over the surface of the structure shown in FIG. 8( d ).
- the patterned mask layer includes portions 806 a which define etched features and portions 806 b which define waveguides.
- the patterned mask layer 806 a / 806 b may be formed of a metal such as chromium (Cr).
- Cr chromium
- Other materials may be used, however, such as aluminum, titanium, copper, gold, nickel, metal silicides, silicon nitride, and other etch resistant materials.
- a mask 820 is then deposited with an opening that exposes the pit 802 , and portions of the core material layer 805 are then removed by RIE as illustrated in FIG. 8( f ). As a result, the remaining core material layer is defined by the waveguide portions 805 b .
- the mask layer portions 806 b are then removed from the respective tops of the waveguide portions 805 b , and another cladding material layer 807 is deposited over a resultant structure as shown in FIG. 8( g ).
- the cladding material layer 807 may, for example, be formed of SiO 2 .
- a mask 808 is deposited over the cladding material layer 807 so as to cover the waveguide portions 805 b and partially overlap the mask layer portions 806 a and underlying etched feature portions 805 a .
- Another etch process e.g., wet etching or RIE
- RIE wet etching
- FIG. 8( i ) The structure of FIG. 8( i ) is then subjected to a wet etch to obtain the structure of FIG. 8( j ) in which inclined surface portions 809 are formed at opposite sides of the silicon substrate 801 . It is noted that the inclined surface portions 809 may actually define half of a V-shaped groove in the case where another device is being simultaneously formed in the substrate 801 adjacent to the device illustrated in the drawings.
- FIG. 8( k ) Another mask is applied as shown in FIG. 8( k ).
- the mask includes a portion 810 a which covers the waveguide portions 805 b of the core layer, and portions 810 b which cover the inclined surface features 809 of the substrate 801 .
- This structure is then etched in HF to obtain the structure shown in FIG. 8( k ).
- the side surfaces 811 a of the upper cladding layer 807 may exhibit a slight concave configuration.
- the mask portions 810 a and 810 b are then removed to obtain the device structure of FIG. 8( l ) having the waveguides 805 b sandwiched between lower and upper cladding layers 804 and 807 , respectively.
- the horizontal distance between the waveguide cores 805 a and the inclined surface feature 809 is precisely set since the same mask pattern 106 a / 106 b is used to etch both the waveguide 805 a and the feature 809 , and the device characteristics and alignment tolerances are thereby improved.
Abstract
Description
- Priority is claimed to U.S. Provisional Application Serial No. 60/206,485, filed May 23, 2000, and entitled “Single Mask Method For Making IO Waveguides And Micromachined Features”, the entirety of which is incorporated herein by reference.
- In addition, this is a continuation-in-part (CIP) of co-pending application Ser. No. (not yet assigned: Atty. Dock. No. ACT.003), filed May 16, 2001, and entitled “Multi-Level Optical Structure And Method Of Manufacture”, which in turn is a continuation-in-part (CIP) of co-pending application Ser. No. 09/853,250, filed May 9, 2001, and entitled “Multi-Level Lithography Masks.” The entireties of these applications are incorporated herein by reference.
- 1. Field of the Invention
- The present invention generally relates to optical devices, and more particularly, the present invention relates to the fabrication of optical devices having integrated optical waveguides.
- 2. Description of the Related Art
- Optical integrated circuit (OIC) and optical bench fabrication often involves transferring patterns to a substrate. These patterns may be used to form a variety of structures to include conductive circuit lines, planar waveguides, mesas and recesses. Typically, the desired structures are formed using lithography. Lithography may be achieved by techniques such as photolithography, x-ray lithography and e-beam lithography.
- In photolithography, for example, a layer of photo-reactive film, known as photoresist, may be formed over the substrate. A photolithographic mask containing the image of a desired pattern is then placed in contact with the photoresist film. Radiation of a wavelength to which the photoresist is sensitive is incident upon the mask. The radiation passes through the transparent areas of the mask and the exposed areas of the photoresist are reactive to the radiation. The photoresist film is then chemically developed, leaving behind a pattern of photoresist substantially identical to the pattern on the mask.
- The patterned photoresist on the substrate may be used in a variety of applications to form the structures referenced above. For example, a pattern photoresist may act as a mask for selective etching of a substrate. This selective etching may be used to fabricate recesses and as mesas in the substrate. In OIC and optical bench technologies, the mesas and recesses may be used for a variety of purposes, including passive alignment of optical elements.
- The above described photolithographic process is often referred to as contact printing, because the mask is placed in contact with the substrate. Contact printing has facilitated the fabrication of highly integrated structures in both electrical and optical integrated circuits. However, conventional contact printing techniques have certain limitations. For example, conventional contact printing techniques generally are useful only in processing flat substrates. If a substrate has a relief (i.e. has a non-planar topography) it is exceedingly difficult to fabricate structures on the substrate by flat conventional contact printing techniques. To this end, conventional photolithographic masks are substantially flat. As a result, it is exceedingly difficult to place the mask in contact with, or in close enough proximity to, all points on the surface of a substrate to enable accurate image projection onto the substrate. In regions of the substrate where the photolithographic mask is not in contact with, or in close enough proximity to, the substrate, diffractive effects result in poor resolution and ultimately a poor transfer of the pattern from the mask to the photoresist.
- The above referenced limitations of image lithography processing typically result in inaccurate location and spacing of features in a multi-level substrate. These inaccuracies are unacceptable as the integration of various elements at multiple levels in OIC's and optical bench technologies gains industry acceptance. Accordingly, what is needed are optical integrated circuits and optical benches which incorporate a variety of features at multiple levels which overcome the inaccuracies of conventional structures and methods of manufacture as referenced above.
- According to an aspect of the present invention, an optical device is fabricated having at least one integrated waveguide and at least one micro-machined feature. Although not so limited, exemplary micro-machined features include grooves, recesses and inclined surfaces formed in the substrate surface. A mask layer is deposited over a surface of a substrate structure, and the mask layer is patterned to obtain a mask pattern over the surface of the substrate structure. A first etching process is then carried out for obtaining the at least one integrated optical waveguide core at the surface of the substrate structure, and a second etching process is carried out for obtaining the at least one micro-machined feature at the surface of the substrate structure. Advantageously, the same previously formed mask pattern is used as a mask in both the first and second etching processes, thereby resulting in accurate positioning of the waveguide core relative to the micro-machined feature.
- The invention is best understood from the following detailed description when read with the accompanying drawings. It is emphasized that the various features are not necessarily drawn to scale. In fact, the dimensions may be arbitrarily increased or decreased for clarity of discussion.
- FIGS.1(a) through 1(m) are side views for describing a method of fabricating an optical device according to an embodiment of the present invention.
- FIGS.2(a) through 2(i) are top views for describing a method of fabricating an optical device according to another embodiment of the present invention.
- FIGS.3(a) through 3(m) are side views for describing a method of fabricating an optical device according to the embodiment of FIGS. 2(a) through 2(i).
- FIG. 4 is a top view for describing a variation of the embodiment of FIGS.2(a) through 2(i).
- FIGS.5(a) and 5(b) are side views corresponding to the variation of FIG. 4.
- FIG. 6 is a side view of another embodiment of the present invention.
- FIGS.7(a) through 7(e) are side views for describing a method of fabricating an optical device according to another embodiment of the present invention.
- FIGS.8(a) through 8(l) are side views for describing a method of fabricating an optical device according to another embodiment of the present invention.
- In the following detailed description, for purposes of explanation and not limitation, exemplary embodiments disclosing specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one having ordinary skill in the art having the benefit of the present disclosure, that the present invention may be practiced in other embodiments that depart from the specific details disclosed herein. Moreover, descriptions of well-known devices, methods and materials may be omitted so as to not obscure the description of the present invention.
- As will become apparent below, the present invention is at least partially characterized by the use of the same, preferably planar, mask pattern as an etching mask in defining the horizontal location of micro-machined (etched) features at the substrate surface of an optical device relative to the waveguide cores also at the substrate surface of the optical device. Although not so limited, exemplary micro-machined features include grooves, recesses and inclined surfaces formed in the substrate surface for any of a variety of purposes. For example, grooves may be machined (etched) into the substrate surface for holding optical fibers which are to be optically coupled to the integrated waveguide cores. Also, recesses may be formed for holding spherical elements which function as guide balls in an optical switch device. Likewise, inclined substrate surfaces may fabricated as alignment surfaces for accurate mounting of the optical device into a system. The accurate horizontal positioning of these features relative to the integrated waveguide cores fosters accurate optical coupling between the integrated waveguide cores and external and/or internal components.
- An illustrative embodiment of a method of fabricating an optical device according to the present invention will now be described with reference to FIGS.1(a) through 1(m) of the drawings. Throughout these figures, like elements are designated by the same reference numbers.
- FIG. 1(a) generally depicts a
substrate 101. In this embodiment, thesubstrate 101 is a silicon substrate. However, any of a variety of substrate structures may be adopted, including silicon-on-insulator (SOI) substrates. - Using known masking and etching techniques, a
pit 102 is etched in thesubstrate 101 as shown in FIG. 1(b). Thepit 102 is optionally formed so as to defineinclined sidewalls 103. Then, as shown in FIG. 1(c), acladding material layer 104 is deposited over the surface of thesubstrate 101 and within thepit 102. In this embodiment, thecladding material layer 104 is formed of silicon dioxide (SiO2), although other materials may be readily adopted. - The structure of FIG. 1(c) is then planarized to obtain the structure shown in FIG. 1(d). Here, the
cladding layer material 104 is contained with thepit 102, and the remaining surface of thesubstrate 101 is exposed. - Turning to FIG. 1(e), a
core material layer 105 is deposited over the surface of the structure of FIG. 1(d) so as to cover the exposed surface of thesubstrate 101 and the surface of thecladding material layer 104 contained within thepit 102. In this embodiment, thecore material layer 105 is formed of silica. However, other materials may be used, such as silicon and silicon nitride. - A
mask layer 106 a/106 b is then deposited and patterned over thecore material layer 105. In particular, as shown in FIG. 1(f), the patterned mask layer includesportions 106 a which define etched features and portions 106 b which define waveguides. The patterned mask layer may be formed of a metal such as chromium (Cr). Other materials may be used, however, such as aluminum, titanium, copper, gold, nickel, metal silicides, silicon nitride, and other etch resistant materials. - Exposed portions of the
core material layer 105 are then removed by reactive ion etching (RIE) as illustrated in FIG. 1(g). As a result, the remaining core material layer is defined byetched feature portions 105 a and waveguide portions 105 b. The mask layer portions 106 b (FIG. 1(f)) are then removed from the respective tops of the waveguide portions 105 b, and anothercladding material layer 107 is deposited over a resultant structure as shown in FIG. 1(h). Again, thecladding material layer 107 may, for example, be formed of SiO2 or other materials. - Turning to FIG. 1(i), a
mask 108 is deposited over thecladding material layer 107 so as to cover the waveguide portions 105 b and partially overlap themask layer portions 106 a and underlyingetched feature portions 105 a. Another etch process (e.g., wet etching or RIE) is then performed down to the silicon substrate to obtain the structure illustrated in FIG. 1(i). As shown, themask layer portions 106 a and underlyingetched feature portions 105 a remain on the surface of thesilicon substrate 101. - The structure of FIG. 1(i) is then subjected to a wet etch to obtain the structure of FIG. 1(j) in which inclined surface features 109 are formed at opposite sides of the
silicon substrate 101. Note that the inclined surface features 109 are defined here by the same mask pattern what was previously used to defined thewaveguide portions 105 a of the core material layer. Also note that the inclined surface features 109 may actually define half of a V-shaped groove in the case where another device is being simultaneously formed in thesubstrate 101 adjacent to the device illustrated in the drawings. - Another mask is applied as shown in FIG. 1(k). In particular, the mask includes a portion 110 a which covers the waveguide portions 105 b of the core layer, and
portions 110 b which cover theinclined surfaces 109 of thesubstrate 101. This structure is then etched in hydroflouric acid (HF) to obtain the structure shown in FIG. 1(l). As shown, the side surfaces 111 a of theupper cladding layer 107 may exhibit a slight concave configuration. Themask portions 110 a and 110 b are then removed to obtain the device structure of FIG. 1(m) having the waveguide cores 105 b sandwiched between lower and upper cladding layers 104 and 107, respectively. - In the process described above, the distance D of FIG. 1(m) is a horizontal distance between the
waveguide core 105 a and theinclined surface feature 109. Since thesame mask pattern 106 a/106 b is used to etch both thewaveguide 105 a and thefeature 109, this distance D may be precisely set, and the device characteristics and alignment tolerances are thereby improved. - Another illustrative embodiment of the present invention will now be described with reference to the top views of FIGS.2(a) through 2(i) and the side views of FIG. 3(a) through 3(n). Throughout these figures, like elements are designated by the same reference numbers. In this embodiment, a generally V-shaped groove (micro-machined feature) is aligned with an integrate optical waveguide core(s).
- FIGS.2(a) and 3(a) illustrate a structure which is similar to that obtained in FIG. 1(e) described above. That is, in FIGS. 2(a) and 3(a),
reference number 201 denotes a substrate,reference number 204 denotes a lower cladding material layer, andreference number 205 denotes a core material layer. A mask layer is deposited over thecladding material layer 205 as shown in FIGS. 2(b) and 3(b). The mask layer includes afirst portion 206 a which surrounds and thereby defines agroove region 213, and a second portion 206 b which covers and thereby defines awaveguide region 214. As shown, thewaveguide region 214 and thegroove region 213 are aligned with one another along their respective lengths. Also, for simplicity the drawings depict a continuous second mask portion 206 b. However, the mask portion 206 b can actually comprise a number of parallel masks for defined a corresponding number of parallel waveguide cores within thewaveguide region 214. - Turning to FIGS.2(c) and 3(c), the exposed portions of the
core material layer 205 are removed by RIE using the first andsecond mask portions 206 a and 206 b as a mask. As a result, a portion 205 a of the core material layer remains below thefirst mask portion 206 a, and another portion 205 b of the core material layer remains below the second mask 206 b. Then, referring to FIGS. 2(d) and 3(d), the portion 206 b of the mask layer is removed from atop the portion 205 b of the core material layer within thewaveguide region 214. - An upper cladding material layer is then deposited over the entire surface of the structure shown in FIGS.2(d) and 3(d). The resultant configuration is depicted in FIGS. 2(e) and 3(e) in which
reference number 207 denotes the upper cladding material layer. Then, as shown in FIGS. 2(f), 3(f) and 3(g), amask 208 is deposited over the uppercladding material layer 207 such that edges 231 of anopening 230 thereof are aligned with theportion 206 a. Here, FIG. 3(f) is a side view of FIG. 2(f), and FIG. 3(g) is a cross-sectional view of FIG. 2(f) along line 2-2′. - Exposed portions of the upper
cladding material layer 207 are then removed by RIE using themask 208 as a mask, whereby the surface of thesubstrate 201 within thegroove region 213 becomes exposed. The resultant configuration is shown in FIGS. 2(g), 3(h) and 3(i). FIG. 3(h) is a side view of FIG. 2(g), and FIG. 3(i) is a cross-sectional view of FIG. 2(g) along line 4-4′. - The configuration of FIGS.2(g), 3(h) and 3(i) is then subjected to a wet etching process using the
mask 208 as a mask, to thereby form agroove 240 in the exposed surface portion of thesubstrate 201. Note that thegroove 240 is defined here by the same mask pattern what was previously used to defined the waveguide portions 205 a of the core material layer. Themask 208 is then removed, and the resultant configuration is illustrated in FIGS. 2(h), 3(j) and 3(k), where FIG. 3(j) is a side view of FIG. 2(h), and FIG. 3(k) is a cross-sectional view of FIG. 2(h) along line 6-6′. As shown in these figures, thegroove 240 extends lengthwise in alignment with thewaveguide region 214. - The
groove 240 and thewaveguide region 214 are then precisely spaced apart by cutting transversely therebetween into thesubstrate 201 with a dicing blade. The resultant configuration is shown in FIGS. 2(i), 3(l) and 3(m), where FIG. 3(l) is a side view of FIG. 2(i), and FIG. 3(m) is a cross-sectional view of FIG. 2(i) along line 8-8′. Here,reference number 260 denotes the dicing saw cut. In this device, thewaveguide region 214 and the groove 240 (i.e., “feature”) are precisely aligned since the same mask pattern was used in the fabrication of each. - A modification of the previous embodiment is shown in FIGS.4, 5(a) and 5(b), where FIG. 5(a) is a cross-sectional view of FIG. 4 along line 10-10′ after the RIE process, and FIG. 5(b) is a cross-sectional view of FIG. 4 along line 10-10′ after the wet etch process. Here, the first mask portion 406 a extends in two parallel strips on either side of the
groove region 413. This is contrasted with the configuration of the previous embodiment in which the first mask portion surrounds the groove region on three sides. Otherwise, the process is carried out in the same manner as the previous embodiment. - FIG. 6 illustrates an alternative process in which a layer of
silicon nitride 680 is disposed under the core material layer in a vicinity of the machined features. Silicon nitride exhibits superior masking properties (compared to SiO2) for anisotropic wet etching of the silicon substrate 601. - Another embodiment of the present invention will now be described with reference to FIGS.7(a) through (e). In this embodiment, the core material layer is not etched to define the micro-machined features until after the waveguides are defined.
- FIG. 7(a) illustrates a structure similar to that described above in connection with FIG. 1(f). In particular, a
lower cladding layer 704 is contained with a pit 702 formed in the surface of asubstrate 701. Acore material layer 705 extends over the surface of thesubstrate 701 and thelower cladding layer 704, and a mask pattern is formed over thecore material layer 705. The mask pattern includes etched feature portions 706 a and waveguide portions 706 b. - Turning to FIG. 7(b), a
mask 790 is formed over thecore material layer 705 and the mask pattern 706 a/706 b so as to have an opening aligned with thelower cladding layer 704. The exposed portions of thecore material layer 705 are then removed by RIE and themask 790 is removed to obtain the structure depicted in FIG. 7(c). Here, reference number 705 b denotes the waveguide portions of the core material layer remaining after etching. - The portions706 b of the first mask are then removed, and an upper cladding layer 707 is deposited as shown in FIG. 7(d). This structure is then subjected to an etch process (e.g., wet etching or RIE) to remove portions of the upper cladding layer 707 and thereby define the machined features as shown in FIG. 7(e). The process then proceeds as in the first described embodiment (see FIG. 1 (i)). One advantage of the present embodiment is that the machined features can be more accurate since the core layer defining the machined features is etched only once.
- Yet another illustrative embodiment of the present invention will now be described with reference to FIGS.8(a) through 8(l) of the drawings.
- Using known masking and etching techniques, a
pit 802 is etched in asubstrate 801 as shown in FIG. 8(a). In this embodiment, thesubstrate 801 is a silicon substrate. As before, however, any of a variety of substrate structures may be adopted, including silicon-on-insulator (SOI) substrates. Thepit 802 is optionally formed so as to defineinclined sidewalls 803. - Then, as shown in FIG. 8(b), a
cladding material layer 804 is deposited over the surface of thesubstrate 801 and within thepit 802. In this embodiment, thecladding material layer 804 is formed of silicon dioxide (SiO2), although other materials may be adopted. Deposition of thecladding material layer 804 is halted prior to completely filling thepit 802, such that an upper surface ofcladding material layer 804 is a displaced a distance “D” below a level of an upper surface of thesubstrate 801. - Turning to FIG. 8(c), a
core material layer 805 is deposited over the surface of thecladding material layer 804. In this embodiment, thecore material layer 105 is formed of silica. However, other materials may be used, including but not limited to silicon and silicon nitride. The structure of FIG. 8(c) is then planarized to obtain the structure of FIG. 8(d). As shown, both thecore material layer 805 and thecladding layer material 804 are contained with thepit 802, and the remaining surface of thesubstrate 801 is exposed. - A mask layer is then deposited and patterned over the surface of the structure shown in FIG. 8(d). In particular, as shown in FIG. 8(e), the patterned mask layer includes
portions 806 a which define etched features and portions 806 b which define waveguides. The patternedmask layer 806 a/806 b may be formed of a metal such as chromium (Cr). Other materials may be used, however, such as aluminum, titanium, copper, gold, nickel, metal silicides, silicon nitride, and other etch resistant materials. - A
mask 820 is then deposited with an opening that exposes thepit 802, and portions of thecore material layer 805 are then removed by RIE as illustrated in FIG. 8(f). As a result, the remaining core material layer is defined by the waveguide portions 805 b. The mask layer portions 806 b are then removed from the respective tops of the waveguide portions 805 b, and anothercladding material layer 807 is deposited over a resultant structure as shown in FIG. 8(g). Again, thecladding material layer 807 may, for example, be formed of SiO2. - Turning to FIG. 8(h), a
mask 808 is deposited over thecladding material layer 807 so as to cover the waveguide portions 805 b and partially overlap themask layer portions 806 a and underlying etched feature portions 805 a. Another etch process (e.g., wet etching or RIE) is then performed down to thesilicon substrate 801 to obtain the structure illustrated in FIG. 8(i). As shown, themask layer portions 806 a remain on the surface of thesilicon substrate 801. - The structure of FIG. 8(i) is then subjected to a wet etch to obtain the structure of FIG. 8(j) in which inclined
surface portions 809 are formed at opposite sides of thesilicon substrate 801. It is noted that theinclined surface portions 809 may actually define half of a V-shaped groove in the case where another device is being simultaneously formed in thesubstrate 801 adjacent to the device illustrated in the drawings. - Another mask is applied as shown in FIG. 8(k). In particular, the mask includes a portion 810 a which covers the waveguide portions 805 b of the core layer, and portions 810 b which cover the inclined surface features 809 of the
substrate 801. This structure is then etched in HF to obtain the structure shown in FIG. 8(k). As shown, the side surfaces 811 a of theupper cladding layer 807 may exhibit a slight concave configuration. The mask portions 810 a and 810 b are then removed to obtain the device structure of FIG. 8(l) having the waveguides 805 b sandwiched between lower and upper cladding layers 804 and 807, respectively. - As with the previously embodiments, the horizontal distance between the waveguide cores805 a and the
inclined surface feature 809 is precisely set since thesame mask pattern 106 a/106 b is used to etch both the waveguide 805 a and thefeature 809, and the device characteristics and alignment tolerances are thereby improved. - While the invention has been described in detail with respect to a number of exemplary embodiments, it is clear that various modifications of the invention will become apparent to those having ordinary skill in art having had benefit of the present disclosure. Such modifications and variations are included in the scope of the appended claims.
Claims (30)
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US09/862,593 US6756185B2 (en) | 2000-05-09 | 2001-05-23 | Method for making integrated optical waveguides and micromachined features |
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US20259600P | 2000-05-09 | 2000-05-09 | |
US20447300P | 2000-05-16 | 2000-05-16 | |
US20648500P | 2000-05-23 | 2000-05-23 | |
US25702100P | 2000-12-20 | 2000-12-20 | |
US09/853,250 US20020031711A1 (en) | 2000-05-09 | 2001-05-09 | Multi-level lithography masks |
US09/858,999 US7255978B2 (en) | 2000-05-09 | 2001-05-16 | Multi-level optical structure and method of manufacture |
US09/862,593 US6756185B2 (en) | 2000-05-09 | 2001-05-23 | Method for making integrated optical waveguides and micromachined features |
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US09/858,999 Continuation-In-Part US7255978B2 (en) | 2000-05-09 | 2001-05-16 | Multi-level optical structure and method of manufacture |
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US6756185B2 US6756185B2 (en) | 2004-06-29 |
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US20020012885A1 (en) * | 2000-05-09 | 2002-01-31 | Steinberg Dan A. | Multi-level optical structure and method of manufacture |
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KR20110062393A (en) * | 2009-12-03 | 2011-06-10 | 삼성전자주식회사 | Optical waveguide device using bulk silicon wafer and fabrication method thereof |
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US20040029053A9 (en) | 2004-02-12 |
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