US20020017713A1 - Microcap wafer-level package - Google Patents
Microcap wafer-level package Download PDFInfo
- Publication number
- US20020017713A1 US20020017713A1 US09/969,432 US96943201A US2002017713A1 US 20020017713 A1 US20020017713 A1 US 20020017713A1 US 96943201 A US96943201 A US 96943201A US 2002017713 A1 US2002017713 A1 US 2002017713A1
- Authority
- US
- United States
- Prior art keywords
- wafer
- seal
- bonding pad
- seed layer
- micro device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/09—Packages
- B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
- B81B2207/094—Feed-through, via
- B81B2207/095—Feed-through, via through the lid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Definitions
- the present invention relates to wafer-level packaging techniques, and more specifically to wafer-level, chip-scale packaging of semiconductors.
- wafer-to-wafer bonding techniques that have been used for packaging semiconductor devices.
- Techniques used have included silicon-to-glass anodic bonding, silicon-to-silicon fusion bonding, and wafer-to-wafer bonding using intermediate materials as the actual bonding media.
- Such intermediate materials have included silicon dioxide, and soft metals such as gold, indium, and aluminum, and have been bonded using electrical, thermal and/or compression techniques.
- the present invention provides a microcap wafer-level package in which a micro device is connected to bonding pads on a base wafer.
- a peripheral pad on the base wafer encompasses the bonding pads and the micro device.
- a cap wafer has gaskets formed thereon. Bonding pad gaskets match the perimeters of the bonding pads, and a peripheral pad gasket matches the peripheral pad on the base wafer. Wells are located inside the perimeters of the bond pad gaskets and are formed to a predetermined depth in the cap wafer.
- the cap wafer is then placed over the base wafer so as to bond the gaskets to the pads and form a hermetically sealed volume between the bonding pad gaskets and the peripheral pad gasket.
- the cap wafer is thinned to form a “microcap”.
- the microcap is thinned below the predetermined depth until the wells become through holes that provide access to the bonding pads inside the package, but outside the hermetically sealed volume, for conductors from a micro device utilizing system.
- This arrangement assures a highly reliable hermetic seal for the wafer-level package, which allows electrical connections without passing through a seal. Further, this process permits the wafers to be made thinner than previously practical because it forms the microcap in situ and avoids the handling of the fragile microcap during assembly.
- the present invention further provides a microcap wafer-level package in which a micro device is connected to bonding pads on a base wafer.
- a peripheral pad on the base wafer encompasses the bonding pads and the micro device.
- a cap wafer is processed to form wells of a predetermined depth in the cap wafer.
- a conductive material is coated onto the walls of the wells in the cap wafer.
- the cap wafer has contact gaskets and a peripheral gasket formed thereon where the contact gaskets are capable of being aligned with the bonding pads on the base wafer, and the gasket matches the peripheral pad on the base wafer.
- the cap wafer is then placed over the base wafer so as to bond the contact gaskets and gasket to the pads and form a hermetically sealed volume within the peripheral gasket.
- the cap wafer is thinned below the predetermined depth until the conductive material is exposed to form conductive vias through the cap wafer to outside the hermetically sealed volume.
- This via arrangement assures a reliable, high conductivity, hermetically sealed connection into the wafer-level package. Further, this process permits the wafers to be made thinner than previously practical because it forms the microcap in situ and avoids the handling of the fragile microcap during assembly.
- the present invention provides an electrical or mechanical device in a wafer-level, chip-scale package that hermetically seals the semiconductor device while providing electrical or thermal connection through one of the wafers.
- the present invention further provides a device in a wafer-level, chip-scale package that allows an electrical connection to the device to be made through the wafer sealing the package itself.
- the present invention further provides a device in a wafer-level, chip-scale package that allows an electrical connection to the device to be made through openings in a cap wafer to bonding pads, which are individually sealed at the same time the device, is sealed.
- the present invention further provides a wafer-level, chip-scale packaging technique utilizing a low-temperature, batch process done at the wafer level which results in a hermetic seal and allows electrical contacts to be made to standard bonding pads on a base wafer.
- the present invention further provides a relatively simple process that results in a hermetic seal for semiconductor devices which does not require high voltages or temperatures.
- the present invention further provides a method of manufacturing a wafer package utilizing process steps and equipment that are standard or close to standard to the processes and equipment used in a typical semiconductor laboratory or manufacturing facility.
- FIG. 1 shows a cross-section of the microcap wafer-level package of the present invention
- FIGS. 2A through 2F show the process steps for fabricating the microcap wafer-level package of the present invention
- FIGS. 3A through 3C show the process steps for an alternative method of fabricating the microcap wafer-level package of the present invention
- FIG. 4 shows the microcap wafer-level package of the present invention after alternative processing to accommodate a large semiconductor device
- FIG. 5 shows the microcap wafer-level package of the present invention showing alternative positions for an integral integrated circuit
- FIG. 6 shows a cross-section of the microcap wafer-level package of an alternate embodiment of the present invention.
- FIGS. 7A through 7E show the process for fabricating the microcap wafer-level package of the alternate embodiment of FIG. 6.
- FIG. 1 therein is shown a cross section of a microcap wafer-level package 10 .
- the microcap wafer-level package 10 has a base wafer 12 with an associated micro device 14 , such as an active device like an integrated circuit or a passive device like a sensor. Bonding pads 16 and 18 , electrically connected to the micro device 14 by conductive leads (not shown), are also associated with the base wafer 12 .
- a peripheral pad 20 Around the perimeter of the base wafer 12 is a peripheral pad 20 which may be deposited at the same time as the bonding pads 16 and 18 .
- a peripheral pad seal, or gasket 22 extends between a cap wafer 24 and the peripheral pad 20 on the base wafer 12 and is cold weld bonded to the peripheral pad 20 to provide a hermetically sealed volume 25 around the micro device 14 .
- the cap wafer 24 can be made of an electronically non-conductive material or a high-resistivity semiconductor material, such as single crystal silicon.
- both the base wafer 12 and the cap wafer 24 are made of the same semiconductor material to avoid thermal expansion mismatch problems.
- the cap wafer 24 has through holes 26 and 28 provided therein allowing access to the bonding pads 16 and 18 , respectively.
- the through holes 26 and 28 are from 10 to 500 microns in diameter to allow access for conventional wire bonding tools.
- Conductors, such as bonding wires 30 and 32 can be respectively wire bonded to the bonding pads 16 and 18 to make the electrical connections to the micro device 14 .
- Bonding pad seals, or gaskets 34 and 36 bond to the respective perimeters of the bonding pads 16 and 18 , and the gasket 22 bonds to the peripheral pad 20 to form a hermetically sealed volume 25 .
- the hermetically sealed volume 25 encompasses the micro device 14 and the bonding pad gaskets 34 and 36 .
- electrical connections (not shown) between the micro device 14 and the bonding pads 16 and 18 are within the hermetically sealed volume 25 and do not pass through any gaskets.
- the bonding pads 16 and 18 , the gaskets 22 , 34 , and 36 , and the peripheral pad 20 in the embodiment shown are of gold; however, other materials can be used without departing from the scope of the present invention.
- other materials capable of being bonded to each other can be used, such as silicon, indium, aluminum, copper, silver, alloys thereof, and compounds thereof.
- FIGS. 2A through 2F therein are shown process steps for manufacturing the microcap wafer-level package 10 shown in FIG. 1.
- all components which are the same in the various figures, will use the same description and number notations.
- FIG. 2A shows the cap wafer 24 .
- a conductive seed layer 48 is deposited through a process such as sputtering or evaporation over the entire well-side surface of cap wafer 24 .
- the seed layer 48 is of gold.
- the gold is deposited in a sequence in which an initial deposition of a very thin adhesion layer (not shown) is sputtered.
- the adhesion layer is of a material to which the seed layer 48 adheres well and that adheres well to the cap wafer 24 .
- the adhesion layer is of a metal such as chromium, nickel-chromium, titanium, or an alloy thereof where the seed layer 48 is gold and the cap wafer 24 is silicon.
- gold is deposited on top of the adhesion layer by sputtering.
- An exemplary thickness of gold would be 2,000 to 3,000 angstroms ( ⁇ ).
- the adhesion layer is used because gold itself does not adhere well directly to silicon. Both layers, however, typically are laid down in a single sputtering or evaporation run using conventional manufacturing equipment.
- a photoresist layer 50 is deposited, exposed and developed in a conventional photolithographic process to produce the pattern openings 52 , which define the shapes of the gaskets 22 , 34 , and 36 . It is preferred that thick photoresist lithography be used to create the pattern for the formation of the gaskets 22 , 34 , and 36 . Standard photoresist forms relatively thin layers so a higher viscosity, thick photoresist layer 50 is required. If necessary, multiple layers of the thick photoresist layer 50 are used. The photoresist used to pattern the gaskets 22 , 34 , and 36 needs to be at least as thick as the final thickness of the gaskets 22 , 34 , and 36 .
- FIG. 2B shows the cap wafer 24 after it has been electroplated using the seed layer 48 as an electrode.
- the conductive material of the gaskets is deposited in the openings 52 in the photoresist layer 50 on the electrically conductive seed layer 48 .
- the photoresist layer 50 is then removed using a conventional photoresist stripping technique.
- the remaining seed layer 48 which was formerly under the photoresist layer 50 , is etched away by a conventional etching process.
- the gaskets 22 , 34 , and 36 are reduced in height and thinned by the thickness of the seed layer 48 that is removed.
- Another thick photoresist layer 54 is deposited to cover the gaskets 22 , 34 , and 36 .
- the photoresist layer 54 is patterned and developed to expose the areas of the cap wafer 24 where wells are to be etched.
- FIG. 2D shows the etched cap wafer 24 with the photoresist layer 54 removed.
- the cap wafer 24 has an initial thickness in excess of 200 microns.
- the cap wafer 24 is then etched to form wells 56 and 58 that, for illustrative purposes, are approximately 100 microns deep.
- Conventional etching processes such as a dry etch process, may be used to make the wells 56 and 58 .
- One such dry etch process is a plasma-etch process used to etch high aspect ratio channels and vias in deep silicon etching. The process uses an alternating process of etching and depositing a polymer on the etched walls so that there is minimal undercutting in the dry etch process.
- This process enables very deep etching with little undercutting.
- the object is to have a deep enough etch so that the depth of the wells 56 and 58 will exceed the final thickness of the cap wafer 24 after processing. If the final thickness of the cap wafer 24 is under 100 microns, the wells 56 and 58 will be 100 microns or deeper.
- the cap wafer 24 is turned over and aligned to match the base wafer 12 .
- the base wafer 12 has been processed using conventional manufacturing processes to produce the bonding pads 16 and 18 and the peripheral pad 20 .
- an adhesion layer (not shown) is deposited on the base wafer 12 and a conductive material is deposited by sputtering or evaporation on the adhesion layer. Patterning is done by photolithography, the unwanted conductive material is etched away, and the photoresist is removed.
- Another approach is by performing the photolithography, depositing the adhesion layer and the conductive material, and then removing the photoresist and the unwanted conductive material to form the bonding pads 16 and 18 and the peripheral pad 20 .
- Channels or wires electrically connect the micro device 14 on the base wafer 12 to the bonding pads 16 and 18 .
- the gaskets 34 and 36 respectively, contact the bonding pads 16 and 18 on the base wafer 12 near the perimeters of the bonding pads 16 and 18 , and the gasket 22 contacts the peripheral pad 20 .
- the gaskets 34 and 36 are configured to substantially match the perimeters of the respective bonding pads 16 and 18 such that there is at least enough room inside each of the gaskets 34 and 36 for the bonding wires 30 and 32 to be bonded as shown in FIG. 1.
- the base wafer 12 and the cap wafer 24 are then aligned and compressed together at temperatures up to 350 degrees Centigrade until cold weld bonding occurs.
- the gasket 22 and the peripheral pad 20 fuse together as do the gaskets 34 and 36 with their respective bonding pads 16 and 18 . This provides the completely hermetically sealed volume 25 for the micro device 14 .
- the cap wafer 24 is thinned into a “microcap” using conventional wafer grinding or lapping and polishing techniques so that the wells 56 and 58 become the through holes 26 and 28 .
- the through holes 26 and 28 extend all the way through the cap wafer 24 .
- the microcap wafer-level package 10 is then ready for connection in a micro device utilizing system (not shown). Electrical contact can be made to the bonding pads 16 and 18 on the base wafer 12 by bonding wires 30 and 32 using conventional bonding techniques, such as ball or wedge bonding. This has the advantage of applying the bonding forces on the relatively thick base wafer 12 .
- FIGS. 3A through 3C therein are shown various stages of an alternative mode of manufacturing the microcap wafer-level package 10 shown in FIG. 1.
- the cap wafer 24 is patterned for wells 56 and 58 using conventional photolithographic techniques. Again, for illustrative purposes only, the cap wafer 24 has an initial thickness in excess of 200 microns. The cap wafer 24 is then etched to form wells 56 and 58 that, for illustrative purposes, are approximately 100 microns deep. Conventional etching processes as previously described may be used to make the wells 56 and 58 . Again, the object is to have a deep enough etch so that the depth of wells 56 and 58 will exceed the final thickness of the cap wafer 24 after processing. If the wells 56 and 58 are 100 microns deep, the final thickness of the cap wafer 24 must be under 100 microns so the wells 56 and 58 will form through holes when the final thickness is reached.
- the seed layer 48 is deposited through a process such as sputtering over the entire cap wafer 24 and in the wells 56 and 58 .
- the seed layer 48 is of gold
- it is deposited in a sequence in which an initial deposition of a very thin adhesion layer (not shown) is sputtered.
- the adhesion layer is of a metal such as chromium, nickel-chromium, titanium or any other metal that adheres well to the cap wafer 24 which is silicon and to the gasket material which is gold.
- gold is deposited on top of the adhesion layer by sputtering.
- An exemplary thickness of gold would be 2,000 to 3,000 ⁇ . Both layers typically are laid down in a single sputtering run using conventional manufacturing equipment.
- a photoresist layer 50 is deposited, exposed and developed in a conventional photolithographic process to produce the pattern openings 52 which define the shapes of the gaskets 22 , 34 , and 36 . It is preferred that thick photoresist lithography be performed to create the pattern for the formation of the gaskets 22 , 34 , and 36 .
- the photoresist used to pattern the gaskets 22 , 34 , and 36 needs to be at least as high as the gaskets 22 , 34 , and 36 are going to be thick. Further, it must fill the wells 56 and 58 in as few layers as possible to avoid the formation of bubbles between the layers of thick photoresist. Multiple layers of thick photoresist may be used so that the photoresist thickness on the surface of the cap wafer 24 is more uniform.
- FIG. 3C shows the cap wafer 24 after it has been electroplated using the seed layer 48 as an electrode.
- the conductive material of the gaskets 22 , 34 , and 36 is deposited at the openings 52 on the electrically conductive seed layer 48 exposed through the photoresist layer 50 .
- the photoresist layer 50 is then removed using a conventional photoresist stripping technique.
- cap wafer 24 is then ready to be turned over and bonded to the base wafer 12 as shown in FIG. 2E, and the rest of the process is the same.
- FIG. 4 therein is shown a microcap wafer-level package 60 where a cap wafer 62 has been etched to accommodate a relatively tall, or thick, micro device 64 on the base wafer 12 .
- the gap between the cap wafer 62 and the micro device 64 can be adjusted by adding a step where the recess 66 is defined by a process such as etching in the cap wafer 62 directly above the micro device 64 .
- the additional etching can be performed using a conventional dry etch process to accommodate micro devices that are relatively high or that need to be packaged in as small a package as possible.
- the thickness of the cap wafer 62 is thereby reduced near the recess 66 . This also allows for the use of gaskets 22 , 34 , and 36 that are shorter than the thickness of the micro device 64 resulting in the use of less material, such as gold, and allowing the use of a more conventional photoresist lithography process.
- a microcap wafer-level package 70 having a cap wafer 72 and a base wafer 74 . Since the wafers are silicon, they can be easily processed using conventional semiconductor manufacturing processes to form the integrated circuits 76 and 78 , respectively, in the cap wafer 72 and/or the base wafer 74 . Since the gaskets 34 and 36 are made of a conductive material, the integrated circuit 76 is easily electrically connectable through them to the bonding pads 16 and 18 either by retaining portions of the conductive seed layers or by forming polysilicon channels on the cap wafer 72 . The integrated circuit 78 in the base wafer 74 is connectable in the same manner as the micro device 14 .
- a gap is shown between the cap wafer 24 and the micro device 14 .
- the present invention can be used to accommodate devices whether or not such a gap is necessary. For example, for some applications such as some sensors or filters, an air gap above the device is required for the device to work properly. Similarly, if a device comprises a mechanical device and moving parts that need to be free moving as in an accelerometer or pressure sensor, then a gap may be required. In the case of integrated circuit devices, for example, the gap may not be required.
- the distance of the gap can be controlled by a combination of how high the gaskets are plated and how much pressure is applied to combine the cap wafer 24 with the base wafer 12 by compressing the gaskets thereby avoiding the need for multi-layered gaskets. Approaches similar to those shown in FIGS. 4 and 5 could also be applied.
- FIG. 6 therein is shown a cross section of a microcap wafer-level package 110 having a base wafer 112 .
- the base wafer 112 has an associated micro device 114 , such as an active device like an integrated circuit or a passive device like a sensor.
- the micro device 114 is electrically connected to bonding pads 116 and 118 by conductive leads (not shown) also associated with the base wafer 112 .
- a peripheral pad 120 Around the perimeter of the base wafer 112 is a peripheral pad 120 which may be deposited at the same time as the bonding pads 116 and 118 , and may be of the same thickness.
- a peripheral pad seal, or gasket 122 extends between a cap wafer 124 and the peripheral pad 120 on the base wafer 112 and is cold weld bonded to the peripheral pad 120 to provide a hermetically-sealed volume 125 around the micro device 114 .
- the cap wafer 124 can be made of an electronically non-conductive material or a high-resistivity semiconductor material, such as single crystal silicon.
- both the base wafer 112 and the cap wafer 124 are made of the same material to avoid thermal expansion mismatch problems.
- the cap wafer 124 has conductive vias 126 and 128 provided therein.
- Contact gaskets 130 and 132 are respectively formed on the conductive vias 126 and 128 at the same time the gasket 122 is formed.
- the contact gaskets 130 and 132 are cold weld bonded to the respective bonding pads 116 and 118 to make the electrical connections to the micro device 114 .
- electrical connections (not shown) between the micro device 114 and its bonding pads, such as the bonding pads 116 and 118 , are located in the hermetically-sealed volume 125 and do not pass through the gasket 122 .
- the cap wafer 124 is further provided with outside bonding pads 134 and 135 having conductors, or bonding wires 136 and 138 , respectively, bonded thereto for connecting the microcap wafer-level package 110 and the micro device 114 to a micro device-utilizing system (not shown).
- the outside bonding pad 135 may be offset from the centerline of the conductive via 128 which is open since the contact gasket 132 provides a hermetic seal.
- the bonding pads 116 and 118 , the peripheral pad 120 , and the contact gaskets 130 and 132 , in the embodiment shown are of gold; however, other materials can be used without departing from the scope of the present invention.
- other materials capable of being bonded to each other can be used, such as silicon, indium, aluminum, copper, silver, alloys thereof, and compounds thereof.
- FIGS. 7A through 7E therein are shown the process steps for fabricating the microcap wafer-level package 110 shown in FIG. 6.
- all components which are the same in the various figures, will use the same description and number notations.
- FIG. 7A shows the cap wafer 124 with wells 140 and 142 formed having respective walls 146 and 147 .
- the wells 140 and 142 are formed using conventional photolithographic and etching processes.
- One conventional etching processes is dry etching, which is a plasma-etch process used to etch high-aspect ratio channels and vias in deep silicon etching.
- the process uses an alternating process of etching and depositing a polymer on the etched walls so that there is minimal undercutting. This process enables very deep etching with little undercutting.
- the object is to have a deep enough etch so that the depth of wells 140 and 142 will exceed the final thickness of the cap wafer 124 after processing.
- the processing involves reducing the thickness of the cap wafer 124 on the non-well side by a process such as grinding or lapping and polishing to expose the wells 140 and 142 .
- the cap wafer 124 has an initial thickness in excess of 200 microns.
- the cap wafer 124 is then etched to form wells 140 and 142 that, for illustrative purposes, are approximately 1 to 50 microns in diameter and over 100 microns deep.
- a conductive seed layer 152 is deposited through a bias sputtering or evaporation process over the entire well-side surface of the cap wafer 124 .
- the seed layer 152 is of gold and is deposited in a sequence starting with a very thin adhesion layer (not shown) being bias sputtered.
- the adhesion layer is of a material that adheres well to the cap wafer 124 and to which the seed layer 152 also adheres well.
- Metals such as chromium, nickel-chromium, titanium, or an alloy thereof are used when the seed layer 152 is gold and the cap wafer 124 is silicon.
- the adhesion layer is used because the gold itself does not adhere well directly to silicon.
- gold is deposited on top of the adhesion layer by sputtering to a 4,000 to 5,000 ⁇ thickness in the present example. Both layers, however, typically are laid down in a single sputtering or evaporation run using conventional manufacturing equipment. To further encourage gold coverage of the walls 146 and 147 , the first layer of gold may be sputter etched off throwing some of the gold material at the bottom of the wells 140 and 142 onto the walls 146 and 147 . This would be followed by a final bias sputtering of gold.
- a photoresist layer 154 is deposited, exposed and developed in a conventional photolithographic process to form the pattern openings 156 which define the shapes of the contact gaskets 130 and 132 and the gasket 122 . It is preferred that thick photoresist lithography be used to create the pattern for the formation of the contact gaskets 130 and 132 and the gasket 122 . Standard photoresist forms relatively thin layers so a higher viscosity, thick photoresist layer 154 is required. The thick photoresist layer 154 used to pattern the contact gaskets 130 and 132 and the gasket 122 needs to be at least as thick as the final thickness the contact gaskets 130 and 132 and the gasket 122 . The photoresist layer 154 can be deposited in multiple layers so that the photoresist thickness on the surface of the cap wafer 124 is more uniform.
- FIG. 7C shows the cap wafer 124 after it has been electroplated using the seed layer 152 as an electrode.
- the conductive material of the contact gaskets 130 and 132 and the gasket 122 is deposited in the pattern openings 156 in the photoresist layer 154 on the seed layer 152 .
- the photoresist layer 154 is removed by using a conventional photoresist stripping technique.
- the remaining seed layer 152 is selectively etched away by a conventional etching process. As the seed layer 152 is removed, the contact gaskets 130 and 132 and the gasket 122 are reduced in height and thinned by the thickness of the seed layer 152 that is removed.
- the base wafer 112 also has the micro device 114 associated with it, which is electrically connected to the bonding pads 116 and 118 by channels or wires (not shown).
- the base wafer 112 and the cap wafer 124 are then aligned.
- the contact gaskets 130 and 132 contact the bonding pads 116 and 118 , respectively, on the base wafer 112 while the gasket 122 contacts the peripheral pad 120 .
- the base wafer 112 and the cap wafer 124 are then compressed together at temperatures up to 350 degrees Centigrade until cold weld bonding occurs.
- the contact gaskets 130 and 132 weld with their respective bonding pads 116 and 118 .
- the gasket 122 and the peripheral pad 120 weld together. This provides the completely hermetically sealed volume 125 for the micro device 114 .
- the cap wafer 124 is thinned to form a “microcap” using a wafer grinding or lapping and polishing techniques until the wells 140 and 142 are opened up and the conductive vias 126 and 128 extend all the way through the cap wafer 124 .
- a metal layer such as nickel-chromium and gold, is bias sputtered over the cap wafer 124 to 7000 ⁇ thickness in the present example.
- a standard photolithographic and etching process is then used to form outside bonding pads 134 and 135 .
- the outside bonding pad is directly over the conductive via 126 and the outside bonding pad 135 is offset from the conductive via 128 .
- the microcap wafer-level package 110 is then ready for connection in a micro device utilizing system (not shown). Electrical contact can be made to the outside bonding pads 134 and 135 that are outside the hermetically sealed volume 125 on the cap wafer 124 .
- the bonding wires 136 and 138 shown in FIG. 6, can be bonded to the respective outside bonding pads 134 and 135 using conventional bonding techniques, such as ball or wedge bonding. In a further alternate mode, it is possible to extend the bonding pad, as shown by bonding pad 135 , so as to bond in a location offset from the conductive via 128 and thus place the wires 136 and 138 close together for a more compact wafer-level package 110 .
- a gap is shown between the cap wafer and the micro device.
- the present invention can be used to accommodate devices whether or not such a gap is necessary. For example, for some applications such as some sensors or filters, an air gap above the device is required for the device to work properly. Similarly, if a device comprises a mechanical device and moving parts that need to be free moving as in an accelerometer or pressure sensor, then a gap may be required. In the case of integrated circuit devices, for example, the gap may not be required.
- the distance of the gap can be controlled by a combination of how high the gaskets are plated and how much pressure is applied to combine the cap wafer with the base wafer by compressing the gaskets thereby avoiding the need for multi-layered gaskets.
- the present invention has applicability in any situation requiring wafer-level packaging.
- the present invention can be used to package both active and passive devices, including but not limited to integrated circuits, filters, pressure sensors, accelerometers, different types of mechanical calorimeters, and other devices.
Abstract
Description
- This is a Continuation of copending U.S. patent application by Richard C. Ruby, Tracy E. Bell, Frank S. Geefay, and Yogesh M. Desai titled “MICROCAP WAFER-LEVEL PACKAGE”, identified by Ser. No. 09/359,844 and filed on Jul. 23, 1999.
- The present invention relates to wafer-level packaging techniques, and more specifically to wafer-level, chip-scale packaging of semiconductors.
- Currently, there are a number of wafer-to-wafer bonding techniques that have been used for packaging semiconductor devices. Techniques used have included silicon-to-glass anodic bonding, silicon-to-silicon fusion bonding, and wafer-to-wafer bonding using intermediate materials as the actual bonding media. Such intermediate materials have included silicon dioxide, and soft metals such as gold, indium, and aluminum, and have been bonded using electrical, thermal and/or compression techniques.
- There are various problems with all of these techniques. The anodic bonding of a glass wafer to a silicon wafer involves the use of high voltages that can be detrimental to the electronic circuits present on the silicon wafer. Similarly, the silicon-to-silicon bonding has to be done at very high voltage and also at a high temperature. Both of these techniques can melt metals with lower melting points than the temperature required to perform the bonding so they cannot be used with certain types of semiconductor devices on silicon wafers. Materials such as glass frit involve relatively large bonding areas which results in an increased die size thereby limiting the number of devices that can be fabricated on a given wafer. Further, some of these techniques cannot assure reliable hermetic seals of the packaged device.
- One example of such packaging method is shown in U.S. Pat. No. 5,448,014 to Kong et al. However, Kong et al. requires multi-layer standoffs to adjust the distance between the two wafers. Additionally, the disclosed use of different materials for each of the wafers can cause potentially adverse consequences due to the different thermal coefficients of expansion of the materials when the package is manufactured using heat as disclosed.
- A relatively simple process that would provide a non-electrical, low temperature method for hermetically packaging micro devices on or in semiconductor wafers has long been sought. Further, a process has been sought which uses processes that are standard, or close to standard, and presently used in a typical semiconductor laboratory or manufacturing facility.
- Also, in the past, making electrical contact to the packaged devices was difficult because existing methods did not provide a wafer-to-wafer seal that allows the electrical conductor to pass through the wafer package itself without the use of epoxy, grommets, or sealing rings in the through holes around the wires. The previous sealing techniques, besides being very small and difficult to implement, were subject to leaking because of the flexing of the wire in the seal, which would open the seal.
- The present invention provides a microcap wafer-level package in which a micro device is connected to bonding pads on a base wafer. A peripheral pad on the base wafer encompasses the bonding pads and the micro device. A cap wafer has gaskets formed thereon. Bonding pad gaskets match the perimeters of the bonding pads, and a peripheral pad gasket matches the peripheral pad on the base wafer. Wells are located inside the perimeters of the bond pad gaskets and are formed to a predetermined depth in the cap wafer. The cap wafer is then placed over the base wafer so as to bond the gaskets to the pads and form a hermetically sealed volume between the bonding pad gaskets and the peripheral pad gasket. The cap wafer is thinned to form a “microcap”. Essentially, the microcap is thinned below the predetermined depth until the wells become through holes that provide access to the bonding pads inside the package, but outside the hermetically sealed volume, for conductors from a micro device utilizing system. This arrangement assures a highly reliable hermetic seal for the wafer-level package, which allows electrical connections without passing through a seal. Further, this process permits the wafers to be made thinner than previously practical because it forms the microcap in situ and avoids the handling of the fragile microcap during assembly.
- The present invention further provides a microcap wafer-level package in which a micro device is connected to bonding pads on a base wafer. A peripheral pad on the base wafer encompasses the bonding pads and the micro device. A cap wafer is processed to form wells of a predetermined depth in the cap wafer. A conductive material is coated onto the walls of the wells in the cap wafer. The cap wafer has contact gaskets and a peripheral gasket formed thereon where the contact gaskets are capable of being aligned with the bonding pads on the base wafer, and the gasket matches the peripheral pad on the base wafer. The cap wafer is then placed over the base wafer so as to bond the contact gaskets and gasket to the pads and form a hermetically sealed volume within the peripheral gasket. The cap wafer is thinned below the predetermined depth until the conductive material is exposed to form conductive vias through the cap wafer to outside the hermetically sealed volume. This via arrangement assures a reliable, high conductivity, hermetically sealed connection into the wafer-level package. Further, this process permits the wafers to be made thinner than previously practical because it forms the microcap in situ and avoids the handling of the fragile microcap during assembly.
- The present invention provides an electrical or mechanical device in a wafer-level, chip-scale package that hermetically seals the semiconductor device while providing electrical or thermal connection through one of the wafers.
- The present invention further provides a device in a wafer-level, chip-scale package that allows an electrical connection to the device to be made through the wafer sealing the package itself.
- The present invention further provides a device in a wafer-level, chip-scale package that allows an electrical connection to the device to be made through openings in a cap wafer to bonding pads, which are individually sealed at the same time the device, is sealed.
- The present invention further provides a wafer-level, chip-scale packaging technique utilizing a low-temperature, batch process done at the wafer level which results in a hermetic seal and allows electrical contacts to be made to standard bonding pads on a base wafer.
- The present invention further provides a relatively simple process that results in a hermetic seal for semiconductor devices which does not require high voltages or temperatures.
- The present invention further provides a method of manufacturing a wafer package utilizing process steps and equipment that are standard or close to standard to the processes and equipment used in a typical semiconductor laboratory or manufacturing facility.
- The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
- FIG. 1 shows a cross-section of the microcap wafer-level package of the present invention;
- FIGS. 2A through 2F show the process steps for fabricating the microcap wafer-level package of the present invention;
- FIGS. 3A through 3C show the process steps for an alternative method of fabricating the microcap wafer-level package of the present invention;
- FIG. 4 shows the microcap wafer-level package of the present invention after alternative processing to accommodate a large semiconductor device;
- FIG. 5 shows the microcap wafer-level package of the present invention showing alternative positions for an integral integrated circuit;
- FIG. 6 shows a cross-section of the microcap wafer-level package of an alternate embodiment of the present invention; and
- FIGS. 7A through 7E show the process for fabricating the microcap wafer-level package of the alternate embodiment of FIG. 6.
- Referring now to FIG. 1, therein is shown a cross section of a microcap wafer-
level package 10. The microcap wafer-level package 10 has abase wafer 12 with an associatedmicro device 14, such as an active device like an integrated circuit or a passive device like a sensor.Bonding pads micro device 14 by conductive leads (not shown), are also associated with thebase wafer 12. Around the perimeter of thebase wafer 12 is aperipheral pad 20 which may be deposited at the same time as thebonding pads - A peripheral pad seal, or
gasket 22, extends between acap wafer 24 and theperipheral pad 20 on thebase wafer 12 and is cold weld bonded to theperipheral pad 20 to provide a hermetically sealedvolume 25 around themicro device 14. Thecap wafer 24 can be made of an electronically non-conductive material or a high-resistivity semiconductor material, such as single crystal silicon. Preferably, however, both thebase wafer 12 and thecap wafer 24 are made of the same semiconductor material to avoid thermal expansion mismatch problems. - The
cap wafer 24 has throughholes bonding pads bonding wires bonding pads micro device 14. Bonding pad seals, orgaskets bonding pads gasket 22 bonds to theperipheral pad 20 to form a hermetically sealedvolume 25. The hermetically sealedvolume 25 encompasses themicro device 14 and thebonding pad gaskets micro device 14 and thebonding pads volume 25 and do not pass through any gaskets. - The
bonding pads gaskets peripheral pad 20 in the embodiment shown are of gold; however, other materials can be used without departing from the scope of the present invention. For example, other materials capable of being bonded to each other can be used, such as silicon, indium, aluminum, copper, silver, alloys thereof, and compounds thereof. - Referring now to FIGS. 2A through 2F, therein are shown process steps for manufacturing the microcap wafer-
level package 10 shown in FIG. 1. Hereinafter, all components, which are the same in the various figures, will use the same description and number notations. - FIG. 2A shows the
cap wafer 24. Aconductive seed layer 48 is deposited through a process such as sputtering or evaporation over the entire well-side surface ofcap wafer 24. In the preferred embodiment, theseed layer 48 is of gold. The gold is deposited in a sequence in which an initial deposition of a very thin adhesion layer (not shown) is sputtered. The adhesion layer is of a material to which theseed layer 48 adheres well and that adheres well to thecap wafer 24. In the best mode, the adhesion layer is of a metal such as chromium, nickel-chromium, titanium, or an alloy thereof where theseed layer 48 is gold and thecap wafer 24 is silicon. Then gold is deposited on top of the adhesion layer by sputtering. An exemplary thickness of gold would be 2,000 to 3,000 angstroms (Å). The adhesion layer is used because gold itself does not adhere well directly to silicon. Both layers, however, typically are laid down in a single sputtering or evaporation run using conventional manufacturing equipment. - A
photoresist layer 50 is deposited, exposed and developed in a conventional photolithographic process to produce thepattern openings 52, which define the shapes of thegaskets gaskets thick photoresist layer 50 is required. If necessary, multiple layers of thethick photoresist layer 50 are used. The photoresist used to pattern thegaskets gaskets - FIG. 2B shows the
cap wafer 24 after it has been electroplated using theseed layer 48 as an electrode. The conductive material of the gaskets is deposited in theopenings 52 in thephotoresist layer 50 on the electricallyconductive seed layer 48. Thephotoresist layer 50 is then removed using a conventional photoresist stripping technique. - In FIG. 2C, the remaining
seed layer 48, which was formerly under thephotoresist layer 50, is etched away by a conventional etching process. Thegaskets seed layer 48 that is removed. Anotherthick photoresist layer 54 is deposited to cover thegaskets photoresist layer 54 is patterned and developed to expose the areas of thecap wafer 24 where wells are to be etched. - FIG. 2D shows the etched
cap wafer 24 with thephotoresist layer 54 removed. For illustrative purposes only, thecap wafer 24 has an initial thickness in excess of 200 microns. Thecap wafer 24 is then etched to formwells wells wells cap wafer 24 after processing. If the final thickness of thecap wafer 24 is under 100 microns, thewells - In FIG. 2E, the
cap wafer 24 is turned over and aligned to match thebase wafer 12. Thebase wafer 12 has been processed using conventional manufacturing processes to produce thebonding pads peripheral pad 20. Briefly, an adhesion layer (not shown) is deposited on thebase wafer 12 and a conductive material is deposited by sputtering or evaporation on the adhesion layer. Patterning is done by photolithography, the unwanted conductive material is etched away, and the photoresist is removed. Another approach is by performing the photolithography, depositing the adhesion layer and the conductive material, and then removing the photoresist and the unwanted conductive material to form thebonding pads peripheral pad 20. Channels or wires (not shown) electrically connect themicro device 14 on thebase wafer 12 to thebonding pads gaskets bonding pads base wafer 12 near the perimeters of thebonding pads gasket 22 contacts theperipheral pad 20. Thegaskets respective bonding pads gaskets bonding wires - The
base wafer 12 and thecap wafer 24 are then aligned and compressed together at temperatures up to 350 degrees Centigrade until cold weld bonding occurs. Thegasket 22 and theperipheral pad 20 fuse together as do thegaskets respective bonding pads volume 25 for themicro device 14. - In FIG. 2F, after the hermetic sealing is complete, the
cap wafer 24 is thinned into a “microcap” using conventional wafer grinding or lapping and polishing techniques so that thewells holes cap wafer 24. The microcap wafer-level package 10 is then ready for connection in a micro device utilizing system (not shown). Electrical contact can be made to thebonding pads base wafer 12 bybonding wires thick base wafer 12. - Referring now to FIGS. 3A through 3C, therein are shown various stages of an alternative mode of manufacturing the microcap wafer-
level package 10 shown in FIG. 1. - In FIG. 3A, the
cap wafer 24 is patterned forwells cap wafer 24 has an initial thickness in excess of 200 microns. Thecap wafer 24 is then etched to formwells wells wells cap wafer 24 after processing. If thewells cap wafer 24 must be under 100 microns so thewells - In FIG. 3B, the
seed layer 48 is deposited through a process such as sputtering over theentire cap wafer 24 and in thewells seed layer 48 is of gold, it is deposited in a sequence in which an initial deposition of a very thin adhesion layer (not shown) is sputtered. Again, the adhesion layer is of a metal such as chromium, nickel-chromium, titanium or any other metal that adheres well to thecap wafer 24 which is silicon and to the gasket material which is gold. Then gold is deposited on top of the adhesion layer by sputtering. An exemplary thickness of gold would be 2,000 to 3,000 Å. Both layers typically are laid down in a single sputtering run using conventional manufacturing equipment. - Also, a
photoresist layer 50 is deposited, exposed and developed in a conventional photolithographic process to produce thepattern openings 52 which define the shapes of thegaskets gaskets gaskets gaskets wells cap wafer 24 is more uniform. - FIG. 3C shows the
cap wafer 24 after it has been electroplated using theseed layer 48 as an electrode. The conductive material of thegaskets openings 52 on the electricallyconductive seed layer 48 exposed through thephotoresist layer 50. Thephotoresist layer 50 is then removed using a conventional photoresist stripping technique. - The
cap wafer 24 is then ready to be turned over and bonded to thebase wafer 12 as shown in FIG. 2E, and the rest of the process is the same. - Referring now to FIG. 4, therein is shown a microcap wafer-
level package 60 where acap wafer 62 has been etched to accommodate a relatively tall, or thick,micro device 64 on thebase wafer 12. Accordingly, the gap between thecap wafer 62 and themicro device 64 can be adjusted by adding a step where therecess 66 is defined by a process such as etching in thecap wafer 62 directly above themicro device 64. The additional etching can be performed using a conventional dry etch process to accommodate micro devices that are relatively high or that need to be packaged in as small a package as possible. The thickness of thecap wafer 62 is thereby reduced near therecess 66. This also allows for the use ofgaskets micro device 64 resulting in the use of less material, such as gold, and allowing the use of a more conventional photoresist lithography process. - Referring now to FIG. 5, therein is shown a microcap wafer-
level package 70 having acap wafer 72 and abase wafer 74. Since the wafers are silicon, they can be easily processed using conventional semiconductor manufacturing processes to form theintegrated circuits cap wafer 72 and/or thebase wafer 74. Since thegaskets integrated circuit 76 is easily electrically connectable through them to thebonding pads cap wafer 72. Theintegrated circuit 78 in thebase wafer 74 is connectable in the same manner as themicro device 14. - It should be noted that a gap is shown between the
cap wafer 24 and themicro device 14. The present invention can be used to accommodate devices whether or not such a gap is necessary. For example, for some applications such as some sensors or filters, an air gap above the device is required for the device to work properly. Similarly, if a device comprises a mechanical device and moving parts that need to be free moving as in an accelerometer or pressure sensor, then a gap may be required. In the case of integrated circuit devices, for example, the gap may not be required. The distance of the gap can be controlled by a combination of how high the gaskets are plated and how much pressure is applied to combine thecap wafer 24 with thebase wafer 12 by compressing the gaskets thereby avoiding the need for multi-layered gaskets. Approaches similar to those shown in FIGS. 4 and 5 could also be applied. - Referring now to FIG. 6, therein is shown a cross section of a microcap wafer-
level package 110 having abase wafer 112. Thebase wafer 112 has an associatedmicro device 114, such as an active device like an integrated circuit or a passive device like a sensor. Themicro device 114 is electrically connected tobonding pads base wafer 112. Around the perimeter of thebase wafer 112 is aperipheral pad 120 which may be deposited at the same time as thebonding pads - A peripheral pad seal, or
gasket 122, extends between acap wafer 124 and theperipheral pad 120 on thebase wafer 112 and is cold weld bonded to theperipheral pad 120 to provide a hermetically-sealedvolume 125 around themicro device 114. Thecap wafer 124 can be made of an electronically non-conductive material or a high-resistivity semiconductor material, such as single crystal silicon. Preferably, however, both thebase wafer 112 and thecap wafer 124 are made of the same material to avoid thermal expansion mismatch problems. - The
cap wafer 124 hasconductive vias gaskets conductive vias gasket 122 is formed. Thecontact gaskets respective bonding pads micro device 114. With the present invention, electrical connections (not shown) between themicro device 114 and its bonding pads, such as thebonding pads volume 125 and do not pass through thegasket 122. - The
cap wafer 124 is further provided withoutside bonding pads bonding wires level package 110 and themicro device 114 to a micro device-utilizing system (not shown). Theoutside bonding pad 135 may be offset from the centerline of the conductive via 128 which is open since thecontact gasket 132 provides a hermetic seal. - The
bonding pads peripheral pad 120, and thecontact gaskets - Referring now to FIGS. 7A through 7E, therein are shown the process steps for fabricating the microcap wafer-
level package 110 shown in FIG. 6. Hereinafter, all components, which are the same in the various figures, will use the same description and number notations. - FIG. 7A shows the
cap wafer 124 withwells respective walls wells wells cap wafer 124 after processing. The processing involves reducing the thickness of thecap wafer 124 on the non-well side by a process such as grinding or lapping and polishing to expose thewells cap wafer 124 has an initial thickness in excess of 200 microns. Thecap wafer 124 is then etched to formwells - In FIG. 7B, a
conductive seed layer 152 is deposited through a bias sputtering or evaporation process over the entire well-side surface of thecap wafer 124. In the best mode, theseed layer 152 is of gold and is deposited in a sequence starting with a very thin adhesion layer (not shown) being bias sputtered. The adhesion layer is of a material that adheres well to thecap wafer 124 and to which theseed layer 152 also adheres well. Metals such as chromium, nickel-chromium, titanium, or an alloy thereof are used when theseed layer 152 is gold and thecap wafer 124 is silicon. The adhesion layer is used because the gold itself does not adhere well directly to silicon. Then gold is deposited on top of the adhesion layer by sputtering to a 4,000 to 5,000 Å thickness in the present example. Both layers, however, typically are laid down in a single sputtering or evaporation run using conventional manufacturing equipment. To further encourage gold coverage of thewalls wells walls - A
photoresist layer 154 is deposited, exposed and developed in a conventional photolithographic process to form thepattern openings 156 which define the shapes of thecontact gaskets gasket 122. It is preferred that thick photoresist lithography be used to create the pattern for the formation of thecontact gaskets gasket 122. Standard photoresist forms relatively thin layers so a higher viscosity,thick photoresist layer 154 is required. Thethick photoresist layer 154 used to pattern thecontact gaskets gasket 122 needs to be at least as thick as the final thickness thecontact gaskets gasket 122. Thephotoresist layer 154 can be deposited in multiple layers so that the photoresist thickness on the surface of thecap wafer 124 is more uniform. - FIG. 7C shows the
cap wafer 124 after it has been electroplated using theseed layer 152 as an electrode. The conductive material of thecontact gaskets gasket 122 is deposited in thepattern openings 156 in thephotoresist layer 154 on theseed layer 152. Thephotoresist layer 154 is removed by using a conventional photoresist stripping technique. The remainingseed layer 152 is selectively etched away by a conventional etching process. As theseed layer 152 is removed, thecontact gaskets gasket 122 are reduced in height and thinned by the thickness of theseed layer 152 that is removed. - In FIG. 7D the
cap wafer 124 is turned over and aligned to match thebase wafer 112. Thebase wafer 112 is processed using conventional photolithographic processes to produce thebonding pads peripheral pad 120. Briefly, an adhesion layer (not shown) is deposited on thebase wafer 112 and a conductive material is deposited by sputtering or evaporation. Patterning is done by photolithography, the unwanted conductive material is etched away, and the photoresist is removed. Another approach is by performing the photolithography, depositing the adhesion layer and the conductive material, and then removing the photoresist and the unwanted conductive material to form thecontact gaskets gasket 122. Thebase wafer 112 also has themicro device 114 associated with it, which is electrically connected to thebonding pads - The
base wafer 112 and thecap wafer 124 are then aligned. Thecontact gaskets bonding pads base wafer 112 while thegasket 122 contacts theperipheral pad 120. - The
base wafer 112 and thecap wafer 124 are then compressed together at temperatures up to 350 degrees Centigrade until cold weld bonding occurs. Thecontact gaskets respective bonding pads gasket 122 and theperipheral pad 120 weld together. This provides the completely hermetically sealedvolume 125 for themicro device 114. - After the hermetic sealing has been completed, the
cap wafer 124 is thinned to form a “microcap” using a wafer grinding or lapping and polishing techniques until thewells conductive vias cap wafer 124. - In FIG. 7E, a metal layer, such as nickel-chromium and gold, is bias sputtered over the
cap wafer 124 to 7000 Å thickness in the present example. A standard photolithographic and etching process is then used to form outsidebonding pads outside bonding pad 135 is offset from the conductive via 128. - The microcap wafer-
level package 110 is then ready for connection in a micro device utilizing system (not shown). Electrical contact can be made to theoutside bonding pads volume 125 on thecap wafer 124. Thebonding wires outside bonding pads bonding pad 135, so as to bond in a location offset from the conductive via 128 and thus place thewires level package 110. - It should be noted that a gap is shown between the cap wafer and the micro device. The present invention can be used to accommodate devices whether or not such a gap is necessary. For example, for some applications such as some sensors or filters, an air gap above the device is required for the device to work properly. Similarly, if a device comprises a mechanical device and moving parts that need to be free moving as in an accelerometer or pressure sensor, then a gap may be required. In the case of integrated circuit devices, for example, the gap may not be required. The distance of the gap can be controlled by a combination of how high the gaskets are plated and how much pressure is applied to combine the cap wafer with the base wafer by compressing the gaskets thereby avoiding the need for multi-layered gaskets.
- The present invention has applicability in any situation requiring wafer-level packaging. The present invention can be used to package both active and passive devices, including but not limited to integrated circuits, filters, pressure sensors, accelerometers, different types of mechanical calorimeters, and other devices.
- Although the present invention has been shown and described with respect to each microcap wafer-level package, it will be apparent to those skilled in the art that the methods described allow for wafer-level manufacturing of a plurality of microcap wafer-level packages at a time. The processes described can be implemented to all the micro devices on a given wafer. The individual packaged devices can then be cut, or diced, in a conventional manner to provide individual devices that are hermetically packaged.
- Additionally, while the present invention has been described in conjunction with specific embodiments of the best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations, which fall within the scope of the present invention as, set forth in the appended claims. All matters set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.
Claims (30)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/969,432 US6429511B2 (en) | 1999-07-23 | 2001-10-01 | Microcap wafer-level package |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/359,844 US6265246B1 (en) | 1999-07-23 | 1999-07-23 | Microcap wafer-level package |
US09/415,284 US6376280B1 (en) | 1999-07-23 | 1999-10-08 | Microcap wafer-level package |
US09/969,432 US6429511B2 (en) | 1999-07-23 | 2001-10-01 | Microcap wafer-level package |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/415,284 Division US6376280B1 (en) | 1999-07-23 | 1999-10-08 | Microcap wafer-level package |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020017713A1 true US20020017713A1 (en) | 2002-02-14 |
US6429511B2 US6429511B2 (en) | 2002-08-06 |
Family
ID=27000653
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/969,432 Expired - Lifetime US6429511B2 (en) | 1999-07-23 | 2001-10-01 | Microcap wafer-level package |
Country Status (2)
Country | Link |
---|---|
US (1) | US6429511B2 (en) |
JP (1) | JP4420538B2 (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6621163B2 (en) * | 2000-11-09 | 2003-09-16 | Koninklijke Philips Electronics N.V. | Electronic device having an electronic component with a multi-layer cover, and method |
US20060115323A1 (en) * | 2004-11-04 | 2006-06-01 | Coppeta Jonathan R | Compression and cold weld sealing methods and devices |
US20070026553A1 (en) * | 2003-03-24 | 2007-02-01 | Microemissive Displays Limited | Method of forming a semiconductor device |
US20090008728A1 (en) * | 2007-07-02 | 2009-01-08 | Denso Corporation | Semiconductor device and manufacturing method of the same |
DE102007063742B4 (en) * | 2006-06-13 | 2013-10-17 | Denso Corporation | Sensor for a physical size |
CN105293420A (en) * | 2015-10-30 | 2016-02-03 | 北京时代民芯科技有限公司 | MEMS wafer level vacuum package structure and manufacturing method thereof |
US20170032164A1 (en) * | 2015-07-27 | 2017-02-02 | Beijing Lenovo Software Ltd. | Electronic device, display screen, and panel |
CN114071892A (en) * | 2021-09-10 | 2022-02-18 | 北京控制工程研究所 | CQFP240 packaging device reinforcing and mounting method |
CN117134728A (en) * | 2023-10-23 | 2023-11-28 | 北京超材信息科技有限公司 | Filter element and preparation method thereof, filter and preparation method thereof, and radio frequency module |
Families Citing this family (116)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6853067B1 (en) | 1999-10-12 | 2005-02-08 | Microassembly Technologies, Inc. | Microelectromechanical systems using thermocompression bonding |
US6514789B2 (en) * | 1999-10-26 | 2003-02-04 | Motorola, Inc. | Component and method for manufacture |
US6512183B2 (en) * | 2000-10-10 | 2003-01-28 | Matsushita Electric Industrial Co., Ltd. | Electronic component mounted member and repair method thereof |
JP4447143B2 (en) * | 2000-10-11 | 2010-04-07 | 新光電気工業株式会社 | Semiconductor device and manufacturing method thereof |
US20020096421A1 (en) * | 2000-11-29 | 2002-07-25 | Cohn Michael B. | MEMS device with integral packaging |
US7343535B2 (en) * | 2002-02-06 | 2008-03-11 | Avago Technologies General Ip Dte Ltd | Embedded testing capability for integrated serializer/deserializers |
US6969667B2 (en) * | 2002-04-01 | 2005-11-29 | Hewlett-Packard Development Company, L.P. | Electrical device and method of making |
JP3529050B2 (en) * | 2002-07-12 | 2004-05-24 | 沖電気工業株式会社 | Method for manufacturing semiconductor device |
US7275292B2 (en) | 2003-03-07 | 2007-10-02 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Method for fabricating an acoustical resonator on a substrate |
US6777263B1 (en) | 2003-08-21 | 2004-08-17 | Agilent Technologies, Inc. | Film deposition to enhance sealing yield of microcap wafer-level package with vias |
US20050054133A1 (en) * | 2003-09-08 | 2005-03-10 | Felton Lawrence E. | Wafer level capped sensor |
US7275424B2 (en) * | 2003-09-08 | 2007-10-02 | Analog Devices, Inc. | Wafer level capped sensor |
US6982437B2 (en) * | 2003-09-19 | 2006-01-03 | Agilent Technologies, Inc. | Surface emitting laser package having integrated optical element and alignment post |
US6900509B2 (en) * | 2003-09-19 | 2005-05-31 | Agilent Technologies, Inc. | Optical receiver package |
US20050063648A1 (en) * | 2003-09-19 | 2005-03-24 | Wilson Robert Edward | Alignment post for optical subassemblies made with cylindrical rods, tubes, spheres, or similar features |
US20050063431A1 (en) * | 2003-09-19 | 2005-03-24 | Gallup Kendra J. | Integrated optics and electronics |
US6998691B2 (en) * | 2003-09-19 | 2006-02-14 | Agilent Technologies, Inc. | Optoelectronic device packaging with hermetically sealed cavity and integrated optical element |
US7520679B2 (en) * | 2003-09-19 | 2009-04-21 | Avago Technologies Fiber Ip (Singapore) Pte. Ltd. | Optical device package with turning mirror and alignment post |
US6953990B2 (en) * | 2003-09-19 | 2005-10-11 | Agilent Technologies, Inc. | Wafer-level packaging of optoelectronic devices |
WO2005031861A1 (en) * | 2003-09-26 | 2005-04-07 | Tessera, Inc. | Structure and method of making capped chips including a flowable conductive medium |
US20050116344A1 (en) * | 2003-10-29 | 2005-06-02 | Tessera, Inc. | Microelectronic element having trace formed after bond layer |
US7019605B2 (en) | 2003-10-30 | 2006-03-28 | Larson Iii John D | Stacked bulk acoustic resonator band-pass filter with controllable pass bandwidth |
US7391285B2 (en) | 2003-10-30 | 2008-06-24 | Avago Technologies Wireless Ip Pte Ltd | Film acoustically-coupled transformer |
US7358831B2 (en) | 2003-10-30 | 2008-04-15 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Film bulk acoustic resonator (FBAR) devices with simplified packaging |
US6946928B2 (en) | 2003-10-30 | 2005-09-20 | Agilent Technologies, Inc. | Thin-film acoustically-coupled transformer |
DE602004000851T2 (en) | 2003-10-30 | 2007-05-16 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Acoustically coupled thin film transformer with two piezoelectric elements having opposite C-axes orientation |
US6936918B2 (en) * | 2003-12-15 | 2005-08-30 | Analog Devices, Inc. | MEMS device with conductive path through substrate |
US20050170609A1 (en) * | 2003-12-15 | 2005-08-04 | Alie Susan A. | Conductive bond for through-wafer interconnect |
US7038559B2 (en) * | 2004-02-23 | 2006-05-02 | Ruby Richard C | Vertically separated acoustic filters and resonators |
US20050213995A1 (en) * | 2004-03-26 | 2005-09-29 | Myunghee Lee | Low power and low jitter optical receiver for fiber optic communication link |
FR2870227B1 (en) * | 2004-05-12 | 2006-08-11 | Commissariat Energie Atomique | METHOD FOR CLOSING AN EVENT AND MACHINE USING SUCH A METHOD |
US7576427B2 (en) * | 2004-05-28 | 2009-08-18 | Stellar Micro Devices | Cold weld hermetic MEMS package and method of manufacture |
US7608534B2 (en) * | 2004-06-02 | 2009-10-27 | Analog Devices, Inc. | Interconnection of through-wafer vias using bridge structures |
US7615833B2 (en) | 2004-07-13 | 2009-11-10 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Film bulk acoustic resonator package and method of fabricating same |
US20070036835A1 (en) * | 2004-07-19 | 2007-02-15 | Microchips, Inc. | Hermetically Sealed Devices for Controlled Release or Exposure of Reservoir Contents |
US7388454B2 (en) | 2004-10-01 | 2008-06-17 | Avago Technologies Wireless Ip Pte Ltd | Acoustic resonator performance enhancement using alternating frame structure |
US7422962B2 (en) * | 2004-10-27 | 2008-09-09 | Hewlett-Packard Development Company, L.P. | Method of singulating electronic devices |
US20060099733A1 (en) * | 2004-11-09 | 2006-05-11 | Geefay Frank S | Semiconductor package and fabrication method |
US8981876B2 (en) | 2004-11-15 | 2015-03-17 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Piezoelectric resonator structures and electrical filters having frame elements |
US20060125084A1 (en) * | 2004-12-15 | 2006-06-15 | Fazzio Ronald S | Integration of micro-electro mechanical systems and active circuitry |
US7202560B2 (en) * | 2004-12-15 | 2007-04-10 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Wafer bonding of micro-electro mechanical systems to active circuitry |
US7791434B2 (en) | 2004-12-22 | 2010-09-07 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Acoustic resonator performance enhancement using selective metal etch and having a trench in the piezoelectric |
KR100661350B1 (en) * | 2004-12-27 | 2006-12-27 | 삼성전자주식회사 | Mems devices package and method for manufacturing thereof |
US20060138626A1 (en) * | 2004-12-29 | 2006-06-29 | Tessera, Inc. | Microelectronic packages using a ceramic substrate having a window and a conductive surface region |
US7282433B2 (en) | 2005-01-10 | 2007-10-16 | Micron Technology, Inc. | Interconnect structures with bond-pads and methods of forming bump sites on bond-pads |
US20060183270A1 (en) * | 2005-02-14 | 2006-08-17 | Tessera, Inc. | Tools and methods for forming conductive bumps on microelectronic elements |
US7427819B2 (en) | 2005-03-04 | 2008-09-23 | Avago Wireless Ip Pte Ltd | Film-bulk acoustic wave resonator with motion plate and method |
US8143095B2 (en) | 2005-03-22 | 2012-03-27 | Tessera, Inc. | Sequential fabrication of vertical conductive interconnects in capped chips |
US7369013B2 (en) | 2005-04-06 | 2008-05-06 | Avago Technologies Wireless Ip Pte Ltd | Acoustic resonator performance enhancement using filled recessed region |
US7436269B2 (en) | 2005-04-18 | 2008-10-14 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Acoustically coupled resonators and method of making the same |
US7692521B1 (en) | 2005-05-12 | 2010-04-06 | Microassembly Technologies, Inc. | High force MEMS device |
US7485956B2 (en) * | 2005-08-16 | 2009-02-03 | Tessera, Inc. | Microelectronic package optionally having differing cover and device thermal expansivities |
US20070045812A1 (en) * | 2005-08-31 | 2007-03-01 | Micron Technology, Inc. | Microfeature assemblies including interconnect structures and methods for forming such interconnect structures |
US7868522B2 (en) | 2005-09-09 | 2011-01-11 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Adjusted frequency temperature coefficient resonator |
US7391286B2 (en) | 2005-10-06 | 2008-06-24 | Avago Wireless Ip Pte Ltd | Impedance matching and parasitic capacitor resonance of FBAR resonators and coupled filters |
US7737807B2 (en) | 2005-10-18 | 2010-06-15 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Acoustic galvanic isolator incorporating series-connected decoupled stacked bulk acoustic resonators |
US7525398B2 (en) | 2005-10-18 | 2009-04-28 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Acoustically communicating data signals across an electrical isolation barrier |
US7425787B2 (en) * | 2005-10-18 | 2008-09-16 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Acoustic galvanic isolator incorporating single insulated decoupled stacked bulk acoustic resonator with acoustically-resonant electrical insulator |
US7675390B2 (en) | 2005-10-18 | 2010-03-09 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Acoustic galvanic isolator incorporating single decoupled stacked bulk acoustic resonator |
US7423503B2 (en) | 2005-10-18 | 2008-09-09 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Acoustic galvanic isolator incorporating film acoustically-coupled transformer |
US7463499B2 (en) | 2005-10-31 | 2008-12-09 | Avago Technologies General Ip (Singapore) Pte Ltd. | AC-DC power converter |
US7393758B2 (en) * | 2005-11-03 | 2008-07-01 | Maxim Integrated Products, Inc. | Wafer level packaging process |
US7354799B2 (en) * | 2005-11-08 | 2008-04-08 | Intel Corporation | Methods for anchoring a seal ring to a substrate using vias and assemblies including an anchored seal ring |
US7561009B2 (en) | 2005-11-30 | 2009-07-14 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Film bulk acoustic resonator (FBAR) devices with temperature compensation |
US20070138644A1 (en) * | 2005-12-15 | 2007-06-21 | Tessera, Inc. | Structure and method of making capped chip having discrete article assembled into vertical interconnect |
US7936062B2 (en) | 2006-01-23 | 2011-05-03 | Tessera Technologies Ireland Limited | Wafer level chip packaging |
US7746677B2 (en) | 2006-03-09 | 2010-06-29 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | AC-DC converter circuit and power supply |
US7479685B2 (en) | 2006-03-10 | 2009-01-20 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Electronic device on substrate with cavity and mitigated parasitic leakage path |
US7629865B2 (en) | 2006-05-31 | 2009-12-08 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Piezoelectric resonator structures and electrical filters |
US7508286B2 (en) | 2006-09-28 | 2009-03-24 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | HBAR oscillator and method of manufacture |
KR100831405B1 (en) * | 2006-10-02 | 2008-05-21 | (주) 파이오닉스 | Wafer bonding packaging method |
US20080087979A1 (en) * | 2006-10-13 | 2008-04-17 | Analog Devices, Inc. | Integrated Circuit with Back Side Conductive Paths |
US7667324B2 (en) * | 2006-10-31 | 2010-02-23 | Avago Technologies Fiber Ip (Singapore) Pte. Ltd. | Systems, devices, components and methods for hermetically sealing electronic modules and packages |
US20080144863A1 (en) * | 2006-12-15 | 2008-06-19 | Fazzio R Shane | Microcap packaging of micromachined acoustic devices |
US8604605B2 (en) | 2007-01-05 | 2013-12-10 | Invensas Corp. | Microelectronic assembly with multi-layer support structure |
WO2008086530A2 (en) * | 2007-01-11 | 2008-07-17 | Analog Devices, Inc. | Mems sensor with cap electrode |
US20080231600A1 (en) | 2007-03-23 | 2008-09-25 | Smith George E | Near-Normal Incidence Optical Mouse Illumination System with Prism |
US7791435B2 (en) | 2007-09-28 | 2010-09-07 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Single stack coupled resonators having differential output |
US7732977B2 (en) | 2008-04-30 | 2010-06-08 | Avago Technologies Wireless Ip (Singapore) | Transceiver circuit for film bulk acoustic resonator (FBAR) transducers |
US7855618B2 (en) | 2008-04-30 | 2010-12-21 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Bulk acoustic resonator electrical impedance transformers |
US8956904B2 (en) | 2008-09-10 | 2015-02-17 | Analog Devices, Inc. | Apparatus and method of wafer bonding using compatible alloy |
US7981765B2 (en) | 2008-09-10 | 2011-07-19 | Analog Devices, Inc. | Substrate bonding with bonding material having rare earth metal |
US8102044B2 (en) * | 2008-10-20 | 2012-01-24 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Bonded wafer structure and method of fabrication |
US8902023B2 (en) | 2009-06-24 | 2014-12-02 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Acoustic resonator structure having an electrode with a cantilevered portion |
US8248185B2 (en) | 2009-06-24 | 2012-08-21 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Acoustic resonator structure comprising a bridge |
DE102009036033B4 (en) * | 2009-08-04 | 2012-11-15 | Austriamicrosystems Ag | Through-hole for semiconductor wafers and manufacturing process |
DE102009042479A1 (en) | 2009-09-24 | 2011-03-31 | Msg Lithoglas Ag | Method for producing an arrangement having a component on a carrier substrate and arrangement, and method for producing a semifinished product and semifinished product |
US8193877B2 (en) | 2009-11-30 | 2012-06-05 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Duplexer with negative phase shifting circuit |
US8796904B2 (en) | 2011-10-31 | 2014-08-05 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Bulk acoustic resonator comprising piezoelectric layer and inverse piezoelectric layer |
US9243316B2 (en) | 2010-01-22 | 2016-01-26 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Method of fabricating piezoelectric material with selected c-axis orientation |
US8232845B2 (en) | 2010-09-27 | 2012-07-31 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Packaged device with acoustic resonator and electronic circuitry and method of making the same |
US8962443B2 (en) | 2011-01-31 | 2015-02-24 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Semiconductor device having an airbridge and method of fabricating the same |
US9148117B2 (en) | 2011-02-28 | 2015-09-29 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Coupled resonator filter comprising a bridge and frame elements |
US9203374B2 (en) | 2011-02-28 | 2015-12-01 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Film bulk acoustic resonator comprising a bridge |
US9425764B2 (en) | 2012-10-25 | 2016-08-23 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Accoustic resonator having composite electrodes with integrated lateral features |
US9154112B2 (en) | 2011-02-28 | 2015-10-06 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Coupled resonator filter comprising a bridge |
US9083302B2 (en) | 2011-02-28 | 2015-07-14 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Stacked bulk acoustic resonator comprising a bridge and an acoustic reflector along a perimeter of the resonator |
US9048812B2 (en) | 2011-02-28 | 2015-06-02 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Bulk acoustic wave resonator comprising bridge formed within piezoelectric layer |
US9136818B2 (en) | 2011-02-28 | 2015-09-15 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Stacked acoustic resonator comprising a bridge |
US8575820B2 (en) | 2011-03-29 | 2013-11-05 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Stacked bulk acoustic resonator |
US9444426B2 (en) | 2012-10-25 | 2016-09-13 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Accoustic resonator having integrated lateral feature and temperature compensation feature |
US8350445B1 (en) | 2011-06-16 | 2013-01-08 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Bulk acoustic resonator comprising non-piezoelectric layer and bridge |
US9069005B2 (en) * | 2011-06-17 | 2015-06-30 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Capacitance detector for accelerometer and gyroscope and accelerometer and gyroscope with capacitance detector |
US8922302B2 (en) | 2011-08-24 | 2014-12-30 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Acoustic resonator formed on a pedestal |
US9667218B2 (en) | 2012-01-30 | 2017-05-30 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Temperature controlled acoustic resonator comprising feedback circuit |
US9667220B2 (en) | 2012-01-30 | 2017-05-30 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Temperature controlled acoustic resonator comprising heater and sense resistors |
US9608592B2 (en) | 2014-01-21 | 2017-03-28 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Film bulk acoustic wave resonator (FBAR) having stress-relief |
US9154103B2 (en) | 2012-01-30 | 2015-10-06 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Temperature controlled acoustic resonator |
JP2014022663A (en) * | 2012-07-20 | 2014-02-03 | Denso Corp | Semiconductor device |
US9793877B2 (en) | 2013-12-17 | 2017-10-17 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Encapsulated bulk acoustic wave (BAW) resonator device |
US9793874B2 (en) | 2014-05-28 | 2017-10-17 | Avago Technologies General Ip Singapore (Singapore) Pte. Ltd. | Acoustic resonator with electrical interconnect disposed in underlying dielectric |
US9444428B2 (en) | 2014-08-28 | 2016-09-13 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Film bulk acoustic resonators comprising backside vias |
US9680445B2 (en) | 2014-10-31 | 2017-06-13 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Packaged device including cavity package with elastic layer within molding compound |
JP6421050B2 (en) * | 2015-02-09 | 2018-11-07 | 株式会社ジェイデバイス | Semiconductor device |
US10263587B2 (en) | 2016-12-23 | 2019-04-16 | Avago Technologies International Sales Pte. Limited | Packaged resonator with polymeric air cavity package |
TWI746082B (en) * | 2020-07-24 | 2021-11-11 | 海華科技股份有限公司 | Portable electronic device and image-capturing module thereof |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3784883A (en) * | 1971-07-19 | 1974-01-08 | Communications Transistor Corp | Transistor package |
US5448014A (en) * | 1993-01-27 | 1995-09-05 | Trw Inc. | Mass simultaneous sealing and electrical connection of electronic devices |
US5373627A (en) * | 1993-11-23 | 1994-12-20 | Grebe; Kurt R. | Method of forming multi-chip module with high density interconnections |
JP3056960B2 (en) * | 1993-12-27 | 2000-06-26 | 株式会社東芝 | Semiconductor device and BGA package |
JPH0969603A (en) * | 1995-09-01 | 1997-03-11 | Mitsubishi Electric Corp | Power semiconductor device and its outer package case and its manufacturing method |
US5593919A (en) * | 1995-09-05 | 1997-01-14 | Motorola Inc. | Process for forming a semiconductor device including conductive members |
JP2894254B2 (en) | 1995-09-20 | 1999-05-24 | ソニー株式会社 | Semiconductor package manufacturing method |
US5731542A (en) * | 1996-05-23 | 1998-03-24 | Motorola, Inc. | Apparatus and method for mounting an electronic component to a substrate and method for spray-cooling an electronic component mounted to a substrate |
US5604160A (en) | 1996-07-29 | 1997-02-18 | Motorola, Inc. | Method for packaging semiconductor devices |
US5798557A (en) | 1996-08-29 | 1998-08-25 | Harris Corporation | Lid wafer bond packaging and micromachining |
US5888884A (en) | 1998-01-02 | 1999-03-30 | General Electric Company | Electronic device pad relocation, precision placement, and packaging in arrays |
US6043109A (en) | 1999-02-09 | 2000-03-28 | United Microelectronics Corp. | Method of fabricating wafer-level package |
US6228675B1 (en) | 1999-07-23 | 2001-05-08 | Agilent Technologies, Inc. | Microcap wafer-level package with vias |
US6265246B1 (en) | 1999-07-23 | 2001-07-24 | Agilent Technologies, Inc. | Microcap wafer-level package |
-
2000
- 2000-07-24 JP JP2000222128A patent/JP4420538B2/en not_active Expired - Lifetime
-
2001
- 2001-10-01 US US09/969,432 patent/US6429511B2/en not_active Expired - Lifetime
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6621163B2 (en) * | 2000-11-09 | 2003-09-16 | Koninklijke Philips Electronics N.V. | Electronic device having an electronic component with a multi-layer cover, and method |
US20070026553A1 (en) * | 2003-03-24 | 2007-02-01 | Microemissive Displays Limited | Method of forming a semiconductor device |
US8191756B2 (en) | 2004-11-04 | 2012-06-05 | Microchips, Inc. | Hermetically sealing using a cold welded tongue and groove structure |
US20060115323A1 (en) * | 2004-11-04 | 2006-06-01 | Coppeta Jonathan R | Compression and cold weld sealing methods and devices |
US9796583B2 (en) | 2004-11-04 | 2017-10-24 | Microchips Biotech, Inc. | Compression and cold weld sealing method for an electrical via connection |
DE102007063742B4 (en) * | 2006-06-13 | 2013-10-17 | Denso Corporation | Sensor for a physical size |
US20090008728A1 (en) * | 2007-07-02 | 2009-01-08 | Denso Corporation | Semiconductor device and manufacturing method of the same |
US8264051B2 (en) | 2007-07-02 | 2012-09-11 | Denso Corporation | Semiconductor device and manufacturing method of the same |
US7968958B2 (en) * | 2007-07-02 | 2011-06-28 | Denso Corporation | Semiconductor device and manufacturing method of the same |
US20110147863A1 (en) * | 2007-07-02 | 2011-06-23 | Denso Corporation | Semiconductor device and manufacturing method of the same |
US20170032164A1 (en) * | 2015-07-27 | 2017-02-02 | Beijing Lenovo Software Ltd. | Electronic device, display screen, and panel |
CN105293420A (en) * | 2015-10-30 | 2016-02-03 | 北京时代民芯科技有限公司 | MEMS wafer level vacuum package structure and manufacturing method thereof |
CN114071892A (en) * | 2021-09-10 | 2022-02-18 | 北京控制工程研究所 | CQFP240 packaging device reinforcing and mounting method |
CN117134728A (en) * | 2023-10-23 | 2023-11-28 | 北京超材信息科技有限公司 | Filter element and preparation method thereof, filter and preparation method thereof, and radio frequency module |
Also Published As
Publication number | Publication date |
---|---|
JP4420538B2 (en) | 2010-02-24 |
US6429511B2 (en) | 2002-08-06 |
JP2001068574A (en) | 2001-03-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6376280B1 (en) | Microcap wafer-level package | |
US6429511B2 (en) | Microcap wafer-level package | |
US6228675B1 (en) | Microcap wafer-level package with vias | |
US6777263B1 (en) | Film deposition to enhance sealing yield of microcap wafer-level package with vias | |
US7026223B2 (en) | Hermetic electric component package | |
KR100370398B1 (en) | Method for surface mountable chip scale packaging of electronic and MEMS devices | |
US6534341B2 (en) | Methods of wafer level fabrication and assembly of chip scale packages | |
US6846725B2 (en) | Wafer-level package for micro-electro-mechanical systems | |
US7396478B2 (en) | Multiple internal seal ring micro-electro-mechanical system vacuum packaging method | |
US20040259325A1 (en) | Wafer level chip scale hermetic package | |
US7351641B2 (en) | Structure and method of forming capped chips | |
US20080081398A1 (en) | Cap Wafer for Wafer Bonded Packaging and Method for Manufacturing the Same | |
TW200531227A (en) | Structure and method of making capped chips having vertical interconnects | |
EP1734001A2 (en) | Method of packaging mems | |
JP5721742B2 (en) | Electrical coupling of wafer structures | |
EP1199744B1 (en) | Microcap wafer-level package | |
US20040166662A1 (en) | MEMS wafer level chip scale package | |
JP3394696B2 (en) | Semiconductor device and manufacturing method thereof | |
US20040149808A1 (en) | Method for the adhesion of two elements, in particular of an integrated circuit, for example an encapsulation of a resonator, and corresponding integrated circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD., SINGAPORE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AGILENT TECHNOLOGIES, INC.;REEL/FRAME:017207/0020 Effective date: 20051201 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES WIRELESS IP (SINGAPORE) PTE. LT Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:017675/0477 Effective date: 20051201 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: MERGER;ASSIGNOR:AVAGO TECHNOLOGIES WIRELESS IP (SINGAPORE) PTE. LTD.;REEL/FRAME:030369/0703 Effective date: 20121030 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT, NEW YORK Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:032851/0001 Effective date: 20140506 Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AG Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:032851/0001 Effective date: 20140506 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD., SINGAPORE Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037689/0001 Effective date: 20160201 Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037689/0001 Effective date: 20160201 |
|
AS | Assignment |
Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH CAROLINA Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:037808/0001 Effective date: 20160201 Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:037808/0001 Effective date: 20160201 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF THE ASSIGNEE PREVIOUSLY RECORDED ON REEL 017207 FRAME 0020. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT;ASSIGNOR:AGILENT TECHNOLOGIES, INC.;REEL/FRAME:038633/0001 Effective date: 20051201 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD., SINGAPORE Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041710/0001 Effective date: 20170119 Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041710/0001 Effective date: 20170119 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITE Free format text: MERGER;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:047195/0026 Effective date: 20180509 |
|
AS | Assignment |
Owner name: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITE Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED ON REEL 047195 FRAME 0026. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:047477/0423 Effective date: 20180905 |