US20020024830A1 - Content addressable memory using part of memory region to store data which should not be erased - Google Patents
Content addressable memory using part of memory region to store data which should not be erased Download PDFInfo
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- US20020024830A1 US20020024830A1 US09/916,676 US91667601A US2002024830A1 US 20020024830 A1 US20020024830 A1 US 20020024830A1 US 91667601 A US91667601 A US 91667601A US 2002024830 A1 US2002024830 A1 US 2002024830A1
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- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
Definitions
- the present invention relates to a content addressable memory (CAM)(which is also generally called an “associative memory”).
- CAM content addressable memory
- a content addressable memory is known as a memory used such that storage data is stored in each of a plurality of word memories (which constitute a memory region) to permit overwriting, retrieval data is entered, and storage data corresponding to the retrieval data is retrieved.
- the network frame repeater will be outlined hereinbelow.
- a network system includes a network frame repeater called, for example, a “hub”.
- the network frame repeater relays transmission of network frames, each of which is a packet of information that is communicated in the network system.
- FIG. 3 is a circuit block diagram showing an example configuration of a network frame repeater 30 .
- the network frame repeater 30 includes n pieces of port controllers 32 _ 1 to 32 _n connected to a bus 31 .
- a plurality of terminals A, B, . . . , C and a plurality of terminals E, F, . . . , G are connected via local area networks 34 _ 1 to 34 _n (LANS) to ports 33 _ 1 to 33 _n, respectively, which correspond to the port controllers 32 _ 1 to 32 _n.
- local area networks 34 _ 1 to 34 _n local area networks 34 _ 1 to 34 _n
- bus 31 is connected to a CAM 35 , a random access memory 36 (RAM), a central processing unit 37 (CPU), and a packet memory 38 .
- RAM random access memory
- CPU central processing unit
- the network frame repeater 30 shown in FIG. 3 uses both the CAM 35 and the RAM 36 .
- Data directly required for retrieval is stored in the CAM 35
- data not directly required for retrieval is stored in the RAM 36 .
- the addresses of word memories of the CAM 35 are correlated to the addresses of memory regions of the RAM 36 via a signal line 39 .
- the CAM 35 stores address data representing the addresses of the individual terminals and time stamp data (which will be described hereafter).
- the RAM 36 stores the port numbers of the individual ports 33 _ 1 to 33 _n connected to the terminals.
- the RAM 36 stores other data, such as data related to a virtual LAN (VLAN), and data accessed by hardware of the network frame repeater 30 (detailed description of the data is omitted herefrom).
- VLAN virtual LAN
- the CPU 37 performs the overall control of the network frame repeater 30 .
- the packet memory 38 temporarily stores received network frames.
- the network frame repeater 30 includes various other devices. However, since the devices are not directly concerned with the intended subject matter, they are neither described nor illustrated.
- a header portion of the network frame contains data identifying a destination address representing the terminal E, and a transmission source address representing the terminal B.
- the network frame transmitted from terminal B via the port 33 _ 1 is controlled to pass through the port controller 32 _ 1 and the bus 31 , and is then temporarily stored in the packet memory 38 .
- the CPU 37 extracts the destination address representing a data transmission destination (terminal E in the example case) from the header portion of the network frame, and then sends it to the CAM 35 .
- the CAM 35 contains address data representing the individual terminals A, B, . . . , C and the individual terminals E, F, . . . , G, which constitute the network system.
- the RAM 36 stores the port numbers individually identifying destinations to which the terminals A, B, . . . , C and the terminals E, F, . . .
- G are connected via the ports 33 _ 1 to 33 _n.
- Address data representing the destination address is input into the CAM 35 .
- the CAM 35 outputs to the signal line 39 an HHA (highest hit address) of a word memory of the CAM 35 , which contains address data identical to the aforementioned input address data.
- the port number representing the destination terminal indicated by the destination address is read out of the address corresponding to the HHA of the RAM 36 .
- the CPU 37 Based on the port number that has been read out, the CPU 37 recognizes the present network frame as data that is due to be transmitted to port 33 _n.
- the network frame is input from the packet memory 38 via the bus 31 to the port controller 32 _n, and is further sent to the terminal E via the port 33 _n and the LAN 34 _n.
- the network frame repeater 30 uses CAM 35 for performing high-speed retrieval of addresses.
- FIG. 4 shows a MAC (media access control) table in the network frame repeater 30 shown in FIG. 3.
- the MAC table shown in FIG. 4 contains address data representing the addresses (MAC addresses) of the terminals A, B, . . . , C and terminals E, F, . . . , G; the corresponding port numbers; and the corresponding time stamp data.
- a destination address extracted from a network frame is used for retrieval.
- the port number to which the network frame is to be transmitted can be known from a retrieved address stored in the RAM 36 , which corresponds to the HHA.
- each of the word memories also contains time stamp data. Hereinbelow, the time stamp data will be described.
- FIG. 5 is a view for explaining time stamp data.
- a predetermined time interval is set for one time slot, and p pieces of the time slots are cycled one by one as time passes.
- their numbers for example, numerals 1 , 2 , . . . , and p are assigned to represent the time stamp data T 1 , T 2 , . . . , and Tp, respectively.
- the CAM 35 in an event where a retrieval has been carried out by using a source address extracted from a network frame, the retrieval has detected an address identical to the source address thereof, time stamp data of the corresponding word memory is overwritten with the time stamp data that represents the time slot at that time (current time). However, in an event where the retrieval has not detected an address identical to the source address, data of the source address and time stamp data representing a time slot of the current time is written into a empty address field (empty word memory). On the other hand, into the RAM 36 are written the port number of a port from which a network frame having that source address has been transmitted.
- the CAM 35 At each time interval that defines each of the time slots, retrieval is carried out by using the time stamp data of the time slot (time slot whereat the longest time has passed) immediately preceding the current time slot. As a result, if time stamp data identical to the input time stamp data is detected, data in the corresponding word memory is erased. By erasing the address data of terminals that have not been involved in communication for a long time, a empty address field is secured in the CAM 35 , thereby enabling the CAM 35 to store new data.
- the erasure of data means that, for example, one bit in the word memory is allocated as a bit (empty bit) that is used to determine the existence of data, and the bit is overwritten so as to be converted from logic representing a data-existence to logic representing a data-nonexistence.
- each of the word memories may have an empty flag as a flipflop that indicates whether valid data is stored or not in the word memory, and data can be erased by overwriting the flag.
- an object of the present invention is to provide a content addressable memory (CAM) that avoids the necessity for increasing the memory capacity and that simplifies control.
- CAM content addressable memory
- a content addressable memory of the present invention includes a memory region including a plurality of word memories, an address storage section for storing address data specifying a partial region of the memory region, and overwriting means for overwriting the contents of word memories in a region in the memory region excluding the partial region.
- a content addressable memory includes a memory region including a plurality of word memories each including a predetermined plurality of bits, an address storage section for storing address data specifying a partial region of the memory region, and an overwriting means for performing retrieval by using predetermined data as retrieval data in response to a predetermined command and for overwriting the contents of word memories that contain storage data corresponding to the predetermined data used for the retrieval and that exist in a region in the memory region excluding the partial region.
- a content addressable memory is arranged such that storage data is stored in each of a plurality of word memories constituting a memory region so as to be overwritten, retrieval data is input, and storage data corresponding to the retrieval data that has been input is retrieved.
- the content addressable memory includes:
- an address storage section for storing address data specifying a partial region of the memory region
- an aging means for performing retrieval by using predetermined time stamp data in response to a predetermined aging command and erasing the contents of word memories that contain storage data corresponding to the time stamp data used for the retrieval and that exist in a region in the memory region excluding the partial region.
- FIG. 1 is a schematic view of a content addressable memory according to an embodiment of the present invention
- FIG. 2 is flowchart showing a routine of the operations ranging from the issuance of an aging command up to termination in the content addressable memory;
- FIG. 3 is a circuit block diagram showing an example configuration of a network frame repeater
- FIG. 4 shows a MAC table in the network frame repeater shown in FIG. 3;
- FIG. 5 is a view for explaining time stamp data.
- FIG. 1 is a schematic view of a content addressable memory 100 (CAM) according to an embodiment of the present invention.
- the CAM 100 shown in FIG. 1 includes a memory region 10 , a permanent-region pointer register 20 (an example of an address storage section according to the present invention) and an overwriting means 25 (or, erasing means).
- the memory region 10 includes a plurality of word memories. Each of the word memories stores address data of each terminal, and time stamp data. The data stored therein can be overwritten.
- the memory region 10 includes two divisional regions. One of the regions is a permanent region 10 a (which corresponds to a partial region according to the present invention), and the other region is a temporary region 10 b .
- the permanent region 10 a stores data of terminals (servers) that indicates permanent MAC addresses, that is, data that is not erased even when the terminals are not involved in communication for a long time (for example, two to five minutes).
- the temporary region 10 b stores data regarding terminals, which is erased when the terminals are not involved in communication for a long time.
- the permanent-region pointer register 20 stores a desired address that determines the size of the permanent region 10 a , that is, address data representing a last address of the permanent region 10 a .
- the permanent region 10 a having addresses ranging from the first address to the desired address are set in the memory region 10 .
- the CAM 100 receives an aging command (which is also generally called a “table maintenance command”) from the CPU 37 provided in the repeater 30 (refer to FIG. 3), and performs retrieval by using predetermined time stamp data as retrieval data.
- the CAM 100 erases data in word memories that contain detected time stamp data identical to the time stamp data used for the retrieval and that belongs to the temporary region 10 b of the memory region 10 excluding permanent region 10 a . Then, the CAM 100 outputs a completion command to the CPU 37 .
- the data is erased in the following method.
- a bit at a predetermined portion of a word memory is used as a tag representing whether or not valid data is stored in the word memory.
- the above-described overwriting means 25 performs overwriting for the bit at the predetermined portion of the word memory so as to be converted from logic representing that valid data is stored to logic representing that no data is stored. Thereby, data stored in the word memory can be erased.
- the data may be erased in the following method.
- An empty flag is provided as a flipflop in each of the word memories.
- the flipflop indicates whether valid data is stored in the word memory.
- the data is erased by overwriting the flag.
- FIG. 2 is flowchart showing a routine of the operations ranging from the issuance of an aging command up to termination in the content addressable memory.
- step S 11 an aging command is issued from the CPU 37 (shown in FIG. 3) to the CAM 100 .
- the CAM 100 starts the retrieval of data from the memory region 10 by using time stamp data of the time slot (time slot whereat the longest time has passed) immediately preceding a time slot at the time when the aging command has been issued.
- time stamp data of the time slot time slot whereat the longest time has passed
- an assumption is made such that the retrieval operation has detected a plurality of hit addresses of word memories that have time stamp data identical to the time stamp data used for the retrieval.
- step S 13 one of the hit addresses is fetched, and the routine proceeds to step S 14 .
- step S 14 a determination is made whether or not the fetched hit address belongs to the permanent region 10 a . If the hit address is determined not to belong to the permanent region 10 a , since it belongs to the temporary region 10 b , the routine proceeds to step S 15 . At step S 15 , data stored in the word memory corresponding to the address is erased, and the routine proceeds to step S 16 . On the other hand, at step S 14 , if the hit address is determined to belong to the permanent region 10 a , since data stored in the word memory corresponding to the address need not be erased, the routine proceeds to step S 16 .
- step S 16 a determination is made as to whether the hit address is a last address. If the hit address is determined to be the last hit address, the CAM 100 returns a completion command to the CPU 37 , and terminates the routine. On the other hand, if the hit address is determined not to be the last hit address, the operation returns to step S 13 . In this manner, erasing processing is performed for the address data representing the hit address in the temporary region 10 b of the memory region 10 excluding the permanent region 10 a.
- data such as server address data which should not be erased is stored in the permanent region 10 a of the memory region 10 , which is specified by the permanent-region pointer register 20 .
- address data to be erased by the overwriting means 30 is stored in the temporary region 10 b of the memory region 10 .
- the storage method of the present invention is not limited to that shown in the embodiment.
- the address storage section of the present invention may be of a type that stores two addresses indicating the first address and the last address of the partial region of the memory region.
- the address storage section may be of a type that stores an address for fixedly setting the partial region of the memory region.
- the present invention avoids the necessity for increasing the memory capacity, and furthermore, simplifies the control method.
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a content addressable memory (CAM)(which is also generally called an “associative memory”).
- 2. Description of the Related Art
- Conventionally, a content addressable memory (CAM) is known as a memory used such that storage data is stored in each of a plurality of word memories (which constitute a memory region) to permit overwriting, retrieval data is entered, and storage data corresponding to the retrieval data is retrieved.
- One of the major applications is a network frame repeater that relays communications of network frames. The network frame repeater will be outlined hereinbelow.
- Conventionally, a network system includes a network frame repeater called, for example, a “hub”. The network frame repeater relays transmission of network frames, each of which is a packet of information that is communicated in the network system.
- FIG. 3 is a circuit block diagram showing an example configuration of a
network frame repeater 30. - The
network frame repeater 30 includes n pieces of port controllers 32_1 to 32_n connected to abus 31. In addition, a plurality of terminals A, B, . . . , C and a plurality of terminals E, F, . . . , G are connected via local area networks 34_1 to 34_n (LANS) to ports 33_1 to 33_n, respectively, which correspond to the port controllers 32_1 to 32_n. - In addition, the
bus 31 is connected to aCAM 35, a random access memory 36 (RAM), a central processing unit 37 (CPU), and apacket memory 38. - Compared to an ordinary RAM, the
CAM 35, to which a retrieval function is added, is expensive in terms of the cost per bit and has a small memory capacity. To solve this problem, thenetwork frame repeater 30 shown in FIG. 3 uses both theCAM 35 and theRAM 36. Data directly required for retrieval is stored in theCAM 35, and data not directly required for retrieval is stored in theRAM 36. The addresses of word memories of theCAM 35 are correlated to the addresses of memory regions of theRAM 36 via asignal line 39. TheCAM 35 stores address data representing the addresses of the individual terminals and time stamp data (which will be described hereafter). On the other hand, theRAM 36 stores the port numbers of the individual ports 33_1 to 33_n connected to the terminals. In addition, theRAM 36 stores other data, such as data related to a virtual LAN (VLAN), and data accessed by hardware of the network frame repeater 30 (detailed description of the data is omitted herefrom). - The
CPU 37 performs the overall control of thenetwork frame repeater 30. Thepacket memory 38 temporarily stores received network frames. - Ordinarily, the
network frame repeater 30 includes various other devices. However, since the devices are not directly concerned with the intended subject matter, they are neither described nor illustrated. - Hereinbelow, description will be made with reference to an example case where information in the form of a network frames is transmitted from the terminal B connected to the LAN34_1 to the terminal E connected to the LAN 34_n.
- A header portion of the network frame contains data identifying a destination address representing the terminal E, and a transmission source address representing the terminal B.
- The network frame transmitted from terminal B via the port33_1 is controlled to pass through the port controller 32_1 and the
bus 31, and is then temporarily stored in thepacket memory 38. TheCPU 37 extracts the destination address representing a data transmission destination (terminal E in the example case) from the header portion of the network frame, and then sends it to theCAM 35. TheCAM 35 contains address data representing the individual terminals A, B, . . . , C and the individual terminals E, F, . . . , G, which constitute the network system. On the other hand, theRAM 36 stores the port numbers individually identifying destinations to which the terminals A, B, . . . , C and the terminals E, F, . . . , G are connected via the ports 33_1 to 33_n. Address data representing the destination address is input into theCAM 35. Subsequently, theCAM 35 outputs to thesignal line 39 an HHA (highest hit address) of a word memory of theCAM 35, which contains address data identical to the aforementioned input address data. In response to the output, the port number representing the destination terminal indicated by the destination address is read out of the address corresponding to the HHA of theRAM 36. Based on the port number that has been read out, theCPU 37 recognizes the present network frame as data that is due to be transmitted to port 33_n. - When the port number is read out of the
RAM 36 in the above-described manner, the network frame is input from thepacket memory 38 via thebus 31 to the port controller 32_n, and is further sent to the terminal E via the port 33_n and the LAN 34_n. - In this way, the
network frame repeater 30 usesCAM 35 for performing high-speed retrieval of addresses. - FIG. 4 shows a MAC (media access control) table in the
network frame repeater 30 shown in FIG. 3. - The MAC table shown in FIG. 4 contains address data representing the addresses (MAC addresses) of the terminals A, B, . . . , C and terminals E, F, . . . , G; the corresponding port numbers; and the corresponding time stamp data.
- As described above, a destination address extracted from a network frame is used for retrieval. The port number to which the network frame is to be transmitted can be known from a retrieved address stored in the
RAM 36, which corresponds to the HHA. As shown in FIG. 4, in addition to terminal address data, each of the word memories also contains time stamp data. Hereinbelow, the time stamp data will be described. - FIG. 5 is a view for explaining time stamp data.
- As shown in FIG. 5, a predetermined time interval is set for one time slot, and p pieces of the time slots are cycled one by one as time passes. To discriminate the p pieces of the time slots from each other, their numbers, for example,
numerals - In the
CAM 35, in an event where a retrieval has been carried out by using a source address extracted from a network frame, the retrieval has detected an address identical to the source address thereof, time stamp data of the corresponding word memory is overwritten with the time stamp data that represents the time slot at that time (current time). However, in an event where the retrieval has not detected an address identical to the source address, data of the source address and time stamp data representing a time slot of the current time is written into a empty address field (empty word memory). On the other hand, into theRAM 36 are written the port number of a port from which a network frame having that source address has been transmitted. In theCAM 35, at each time interval that defines each of the time slots, retrieval is carried out by using the time stamp data of the time slot (time slot whereat the longest time has passed) immediately preceding the current time slot. As a result, if time stamp data identical to the input time stamp data is detected, data in the corresponding word memory is erased. By erasing the address data of terminals that have not been involved in communication for a long time, a empty address field is secured in theCAM 35, thereby enabling theCAM 35 to store new data. In this case, the erasure of data means that, for example, one bit in the word memory is allocated as a bit (empty bit) that is used to determine the existence of data, and the bit is overwritten so as to be converted from logic representing a data-existence to logic representing a data-nonexistence. In addition, each of the word memories may have an empty flag as a flipflop that indicates whether valid data is stored or not in the word memory, and data can be erased by overwriting the flag. - In this way, in the
CAM 35, retrieval is performed for a time stamp data that the longest time has passed after set, and data regarding a terminal that has not been involved in communication is thereby erased. However, in a configuration where, for example, a server is connected as a terminal to thenetwork frame repeater 30, a request is usually made for not erasing data regarding the server even when the server is not involved in communication for a long time. To comply with the request, a technique has been proposed. According to the proposed technique, the permanent bit corresponding to the address data of each terminal is registered in a MAC table as shown in FIG. 4, in which, when a permanent bit corresponding to data which should not be erased is set, the address data is not erased. However, the technique requires the permanent bit to be provided for each piece of terminal address data, thereby requiring an increased memory bit capacity. - According to another proposed technique, data which should not be erased among data registered in a MAC table is preliminarily saved, and the saved data is returned to the MAC table after retrieval. In this technique, however, every time a retrieval is performed by using time stamp data, read and write operations need to be performed with address data which should not be erased, thereby requiring a complicated control method.
- In view of the above-described background, an object of the present invention is to provide a content addressable memory (CAM) that avoids the necessity for increasing the memory capacity and that simplifies control.
- To achieve the above object, according to one aspect of the present invention, a content addressable memory of the present invention includes a memory region including a plurality of word memories, an address storage section for storing address data specifying a partial region of the memory region, and overwriting means for overwriting the contents of word memories in a region in the memory region excluding the partial region.
- According to another aspect of the present invention, a content addressable memory includes a memory region including a plurality of word memories each including a predetermined plurality of bits, an address storage section for storing address data specifying a partial region of the memory region, and an overwriting means for performing retrieval by using predetermined data as retrieval data in response to a predetermined command and for overwriting the contents of word memories that contain storage data corresponding to the predetermined data used for the retrieval and that exist in a region in the memory region excluding the partial region.
- According to still another aspect of the present invention, a content addressable memory is arranged such that storage data is stored in each of a plurality of word memories constituting a memory region so as to be overwritten, retrieval data is input, and storage data corresponding to the retrieval data that has been input is retrieved. The content addressable memory includes:
- (1) an address storage section for storing address data specifying a partial region of the memory region; and
- (2) an aging means for performing retrieval by using predetermined time stamp data in response to a predetermined aging command and erasing the contents of word memories that contain storage data corresponding to the time stamp data used for the retrieval and that exist in a region in the memory region excluding the partial region.
- In the content addressable memory of the present embodiment, even when a server and the like have not been involved in communication for a long time, relevant address data which should not be erased is stored in the partial region. On the other hand, terminal-related data to be erased by the aging means is stored in the region excluding the partial region. Specifically, according to the present invention, address data to be stored in the address storage section is used to specify the partial region in which the specific data which should not be erased is stored. Thereby, in the present embodiment, different from the conventional content addressable memory, to control specific address data not to be erased, there is no need to provide a permanent bit in individual address data nor is there a need to perform read and write operations for address data in a MAC table every time retrieval is performed. Consequently, the necessity for increasing memory capacity can be avoided, and furthermore, control can be simplified.
- FIG. 1 is a schematic view of a content addressable memory according to an embodiment of the present invention;
- FIG. 2 is flowchart showing a routine of the operations ranging from the issuance of an aging command up to termination in the content addressable memory;
- FIG. 3 is a circuit block diagram showing an example configuration of a network frame repeater;
- FIG. 4 shows a MAC table in the network frame repeater shown in FIG. 3; and
- FIG. 5 is a view for explaining time stamp data.
- Hereinbelow, an embodiment of the present invention will be described.
- FIG. 1 is a schematic view of a content addressable memory100 (CAM) according to an embodiment of the present invention.
- A description is made with reference to an example configuration in which the
CAM 100 is built in therepeater 30 shown in FIG. 3. - The
CAM 100 shown in FIG. 1 includes amemory region 10, a permanent-region pointer register 20 (an example of an address storage section according to the present invention) and an overwriting means 25 (or, erasing means). - The
memory region 10 includes a plurality of word memories. Each of the word memories stores address data of each terminal, and time stamp data. The data stored therein can be overwritten. Thememory region 10 includes two divisional regions. One of the regions is apermanent region 10 a (which corresponds to a partial region according to the present invention), and the other region is atemporary region 10 b. Thepermanent region 10 a stores data of terminals (servers) that indicates permanent MAC addresses, that is, data that is not erased even when the terminals are not involved in communication for a long time (for example, two to five minutes). On the other hand, thetemporary region 10 b stores data regarding terminals, which is erased when the terminals are not involved in communication for a long time. - The permanent-region pointer register20 stores a desired address that determines the size of the
permanent region 10 a, that is, address data representing a last address of thepermanent region 10 a. Thus, thepermanent region 10 a having addresses ranging from the first address to the desired address are set in thememory region 10. - The
CAM 100 receives an aging command (which is also generally called a “table maintenance command”) from theCPU 37 provided in the repeater 30 (refer to FIG. 3), and performs retrieval by using predetermined time stamp data as retrieval data. In addition, according to a procedure described below, theCAM 100 erases data in word memories that contain detected time stamp data identical to the time stamp data used for the retrieval and that belongs to thetemporary region 10 b of thememory region 10 excludingpermanent region 10 a. Then, theCAM 100 outputs a completion command to theCPU 37. The data is erased in the following method. A bit at a predetermined portion of a word memory is used as a tag representing whether or not valid data is stored in the word memory. The above-described overwriting means 25 performs overwriting for the bit at the predetermined portion of the word memory so as to be converted from logic representing that valid data is stored to logic representing that no data is stored. Thereby, data stored in the word memory can be erased. - Alternatively, the data may be erased in the following method. An empty flag is provided as a flipflop in each of the word memories. The flipflop indicates whether valid data is stored in the word memory. The data is erased by overwriting the flag.
- FIG. 2 is flowchart showing a routine of the operations ranging from the issuance of an aging command up to termination in the content addressable memory.
- At step S11, an aging command is issued from the CPU 37 (shown in FIG. 3) to the
CAM 100. In response to the aging command, in step S12, theCAM 100 starts the retrieval of data from thememory region 10 by using time stamp data of the time slot (time slot whereat the longest time has passed) immediately preceding a time slot at the time when the aging command has been issued. In this case, an assumption is made such that the retrieval operation has detected a plurality of hit addresses of word memories that have time stamp data identical to the time stamp data used for the retrieval. At step S13, one of the hit addresses is fetched, and the routine proceeds to step S14. At step S14, a determination is made whether or not the fetched hit address belongs to thepermanent region 10 a. If the hit address is determined not to belong to thepermanent region 10 a, since it belongs to thetemporary region 10 b, the routine proceeds to step S15. At step S15, data stored in the word memory corresponding to the address is erased, and the routine proceeds to step S16. On the other hand, at step S14, if the hit address is determined to belong to thepermanent region 10 a, since data stored in the word memory corresponding to the address need not be erased, the routine proceeds to step S16. - At step S16, a determination is made as to whether the hit address is a last address. If the hit address is determined to be the last hit address, the
CAM 100 returns a completion command to theCPU 37, and terminates the routine. On the other hand, if the hit address is determined not to be the last hit address, the operation returns to step S13. In this manner, erasing processing is performed for the address data representing the hit address in thetemporary region 10 b of thememory region 10 excluding thepermanent region 10 a. - As described above, in the
CAM 100 of the present embodiment, data such as server address data which should not be erased is stored in thepermanent region 10 a of thememory region 10, which is specified by the permanent-region pointer register 20. On the other hand, address data to be erased by the overwriting means 30 is stored in thetemporary region 10 b of thememory region 10. Thereby, in the present embodiment, different from the conventional CAM, to control specific address data not to be erased, there is no need to provide a permanent bit in individual address data nor is there need to perform read and write operations for address data in the MAC table every time retrieval is performed. Consequently, the necessity for increasing the memory capacity can be avoided, and in addition, the control method can be simplified. For the overwriting means 30, data-overwriting circuits (such as a word-line encoder, word-line driver, and a write-in circuit) that are normally provided in a CAM are used as they are. - In the present embodiment, description has been made with reference to the example configuration where the address indicating the last address of the
permanent region 10 a is stored in the permanent-region pointer register 20 provided as the address storage section of the present invention, and thereby, the size of thepermanent region 10 a is determined to be programmable. However, the storage method of the present invention is not limited to that shown in the embodiment. For example, the address storage section of the present invention may be of a type that stores two addresses indicating the first address and the last address of the partial region of the memory region. Alternatively, the address storage section may be of a type that stores an address for fixedly setting the partial region of the memory region. - As described above, the present invention avoids the necessity for increasing the memory capacity, and furthermore, simplifies the control method.
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JP2000233387A JP2002050184A (en) | 2000-08-01 | 2000-08-01 | Associative memory |
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Cited By (7)
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US20030081549A1 (en) * | 2001-11-01 | 2003-05-01 | International Business Machines Corporation | Weighted fair queue serving plural output ports |
US20030081552A1 (en) * | 2001-11-01 | 2003-05-01 | International Business Machines Corporation | Weighted fair queue having adjustable scaling factor |
US20030081542A1 (en) * | 2001-11-01 | 2003-05-01 | International Business Machines Corporation | Empty indicators for weighted fair queues |
US20030179706A1 (en) * | 2002-03-20 | 2003-09-25 | International Business Machines Corporation | Network processor having fast flow queue disable process |
US7177853B1 (en) * | 2002-02-21 | 2007-02-13 | Emc Corporation | Cache management via statistically adjusted time stamp queue |
US20070140285A1 (en) * | 2001-11-01 | 2007-06-21 | Ibm | Weighted fair queue having extended effective range |
US20130312109A1 (en) * | 2010-09-16 | 2013-11-21 | International Business Machines Corporation | Securing sensitive data for cloud computing |
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US7240495B2 (en) * | 2001-07-02 | 2007-07-10 | University Of Utah Research Foundation | High frequency thermoacoustic refrigerator |
JP3702950B2 (en) * | 2001-09-18 | 2005-10-05 | 日本電気株式会社 | Associative memory device |
US6760242B1 (en) * | 2002-04-10 | 2004-07-06 | Integrated Device Technology, Inc. | Content addressable memory (CAM) devices having speed adjustable match line signal repeaters therein |
US20050228938A1 (en) * | 2004-04-07 | 2005-10-13 | Rajendra Khare | Method and system for secure erasure of information in non-volatile memory in an electronic device |
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US5237671A (en) * | 1986-05-02 | 1993-08-17 | Silicon Graphics, Inc. | Translation lookaside buffer shutdown scheme |
JPH07105689A (en) * | 1993-10-04 | 1995-04-21 | Kawasaki Steel Corp | Associative memory |
KR950034265A (en) * | 1994-02-10 | 1995-12-28 | 도자끼 시노부 | Associative memory |
US5438535A (en) * | 1994-03-29 | 1995-08-01 | Panasonic Technologies, Inc. | Content addressable memory system |
US5802586A (en) * | 1995-02-27 | 1998-09-01 | Motorola, Inc. | Cache memory having a read-modify-write operation and simultaneous burst read and write operations and a method therefor |
-
2000
- 2000-08-01 JP JP2000233387A patent/JP2002050184A/en not_active Withdrawn
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2001
- 2001-07-30 US US09/916,676 patent/US6385072B1/en not_active Expired - Fee Related
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030081549A1 (en) * | 2001-11-01 | 2003-05-01 | International Business Machines Corporation | Weighted fair queue serving plural output ports |
US20030081552A1 (en) * | 2001-11-01 | 2003-05-01 | International Business Machines Corporation | Weighted fair queue having adjustable scaling factor |
US20030081542A1 (en) * | 2001-11-01 | 2003-05-01 | International Business Machines Corporation | Empty indicators for weighted fair queues |
US20070140285A1 (en) * | 2001-11-01 | 2007-06-21 | Ibm | Weighted fair queue having extended effective range |
US7280474B2 (en) | 2001-11-01 | 2007-10-09 | International Business Machines Corporation | Weighted fair queue having adjustable scaling factor |
US7310345B2 (en) * | 2001-11-01 | 2007-12-18 | International Business Machines Corporation | Empty indicators for weighted fair queues |
US7317683B2 (en) | 2001-11-01 | 2008-01-08 | International Business Machines Corporation | Weighted fair queue serving plural output ports |
US7177853B1 (en) * | 2002-02-21 | 2007-02-13 | Emc Corporation | Cache management via statistically adjusted time stamp queue |
US20030179706A1 (en) * | 2002-03-20 | 2003-09-25 | International Business Machines Corporation | Network processor having fast flow queue disable process |
US7680043B2 (en) | 2002-03-20 | 2010-03-16 | International Business Machines Corporation | Network processor having fast flow queue disable process |
US20130312109A1 (en) * | 2010-09-16 | 2013-11-21 | International Business Machines Corporation | Securing sensitive data for cloud computing |
US9053344B2 (en) * | 2010-09-16 | 2015-06-09 | International Business Machines Corporation | Securing sensitive data for cloud computing |
Also Published As
Publication number | Publication date |
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US6385072B1 (en) | 2002-05-07 |
JP2002050184A (en) | 2002-02-15 |
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