US20020027800A1 - Variable voltage isolation gate and method - Google Patents
Variable voltage isolation gate and method Download PDFInfo
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- US20020027800A1 US20020027800A1 US09/929,611 US92961101A US2002027800A1 US 20020027800 A1 US20020027800 A1 US 20020027800A1 US 92961101 A US92961101 A US 92961101A US 2002027800 A1 US2002027800 A1 US 2002027800A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
Definitions
- the present invention relates to semiconductor based memory devices, and in particular to sense amplifier isolation gates.
- Semiconductor memory devices contain memory cells for storing small electrical charges representative of bits of data. As storage densities are increasing, the cells, and circuitry used to access, sense and restore bits stored in the cells are becoming smaller and smaller. Sense amplifiers are used to detect and amplify the charges stored in the cells. As the size of the memory devices decrease, the charge to be detected decreases. In addition, the power supply voltages at which DRAMs operate are also decreasing to reduce the power consumption of the DRAMs. The lower power supply voltages, lead to slower circuit operations, or in some cases where transistors have relatively high threshold voltages, improper operation.
- Isolation gates are used to connect digit lines coupled to multiple memory cells to sense amplifiers.
- the isolation gates selectively turned on and off during read, sense and restore cycles.
- the isolation gates are coupled to the power supply Vcc during initially accessing charges from a memory cell. In most cases, they are left on during sensing, but sometimes they have been turned off by coupling the gates to ground during sensing.
- the iso gates are coupled to Vcc during restore to turn them back on.
- Vt the threshold voltage
- the threshold voltage is not easily scalable.
- Vccp Low Voltage High Speed Circuit Designs for Giga-bit DRAMs
- a variable voltage is provided to gates of isolation transistors in DRAM devices between digit lines containing many storage cells and a sense amplifier.
- the gate of the isolation transistor is provided a voltage higher than the supply voltage during access time to ensure that a small differential voltage on the digit lines is correctly detected.
- a lower voltage is provided at sense time such that the isolation gate provides a higher resistance during sense time.
- the isolation gate voltage is again raised above the supply voltage to minimize the effects of isolation transistor threshold voltage, Vt. This provides the ability to eliminate a Vt drop at access and restore times while providing better isolation of the digit lines when the sense amplifier fires.
- the voltage on the isolation gate is increased greater than Vt above Vcc at access time to Vccp, and then decreased during sense time to provide some amount of isolation from the digit lines. This provides for a faster driving of the isolated portions of the digit lines to Vcc and ground by the sense amplifiers.
- the voltage on the isolation gate is increased to Vccp both during access time and during restore time to reduce adverse effects of Vt drops.
- the isolation gate voltage during access time is dropped below Vcc. In one embodiment, it is dropped to ground.
- the voltage on the isolation gate is held at Vcc for both access and sense, and then increased to Vccp during restore time.
- Vcc is 2.5 volts
- Vccp is 4.0 volts.
- Vt of the isolation gates adversely affects accurate sensing of the digit lines. Even further reductions in Vcc exacerbate the problem.
- reducing the isolation gate voltage during read time helps speed the driving of the sense amplifier lines to Vcc and ground by providing increased resistance or isolation between the sense amplifiers and the digit lines.
- FIG. 1 is a block schematic diagram of DRAM digit lines coupled to shared sense amplifiers.
- FIG. 2 is a block schematic diagram of a pair of DRAM digit lines coupled to an n-sense amplifier.
- FIG. 3 is a timing diagram of voltages applied to gates of isolation transistors in the diagram of FIG. 2.
- FIG. 4 is a timing diagram of voltages applied to gates of isolation transistors in the diagram of FIG. 2 in a further embodiment.
- FIG. 5 is a timing diagram of voltages applied to gates of isolation transistors in the diagram of FIG. 2 in still a further embodiment.
- FIG. 6 is a timing diagram of voltages applied to gates of isolation transistors in the diagram of FIG. 2 in still a further embodiment.
- a dynamic random access memory DRAM array is shown generally at 110 in FIG. 1.
- Digit lines 112 , 114 , 116 , and 118 are labeled DL 0 , DL 1 , DL 2 and DL 3 respectively.
- Each digit line represents and is coupled to a large number of memory cells, and also is coupled to a bank of p and n sense amplifiers 120 through isolation transistors indicated at 122 , 124 , 126 and 128 .
- the isolation transistors have been used in the past to isolate the sense amplifiers from digit line parasitic capacitance as represented at 130 , 132 , 134 and 136 .
- each line becomes relatively more significant as higher density, lower voltage, DRAMs are developed, and can significantly delay proper accessing, sensing and restoring of the digit lines.
- the isolation transistors are driven by a variable-voltage during different portions of accessing, sensing and restoring memory cells coupled to the digit lines.
- the DRAM of FIG. 1 is representative of multiple subarrays of rows of memory cells sharing multiple sense amplifiers.
- a multilevel gate driver is shown in block form at 210 .
- Drivers which are capable of generating different voltage levels are known in the art and hence multilevel gate driver 210 is shown in block format.
- Multilevel gate driver 210 is coupled to gates of two isolation transistors 212 and 214 which are coupled to a pair of digit lines 216 and 218 respectively.
- the digit lines are in turn coupled through the isolation transistors to an n-sense amplifier and p-sense amplifier indicated generally at 220 .
- the n-sense amplifier comprises a pair of cross coupled n-channel transistors 222 and 224 coupled to a transistor 226 .
- the p-sense amplifier comprises a pair of cross coupled p-channel transistors 227 and 228 coupled to a transistor 229 .
- Digit line 218 is also coupled to multiple memory cells, one of which comprises an access transistor 230 series coupled to a storage capacitor 232 which holds a charge representative of desired data.
- a gate of the access transistor 230 is coupled to a word line indicated at 234 which is used to couple the storage capacitor 232 to the digit line. Multiple different word lines are shown in FIG. 2, such that firing of one word line only provides the charge from one storage capacitor on the digit line.
- Digit line 216 is also coupled to many memory cells which are also coupled to the word lines, forming rows of memory cells. In this embodiment, digit line 216 is used as a reference, and the difference in voltage of the two digit lines is detected and then amplified or sensed by the n-sense amplifier 220 .
- Isolation gate control signals and digit line voltages are shown in FIG. 3 in one embodiment of the invention as voltage versus time.
- the isolation gate voltage in this embodiment is varied from a first reference voltage, such as an array power supply voltage, Vcc to a higher, second reference voltage such as a pumped array power supply voltage Vccp.
- Vccp in one embodiment is Vcc plus an amount higher than the threshold voltage, Vt, of n-channel transistors formed on the DRAM.
- Vcc is 2.0 volts
- Vccp is 3.1 volts or higher where the Vt is 1.0 volts.
- Vcc is 2.5 volts
- Vccp is 4.0 volts to provied a significant increase compared to a Vt of 1.0 volts.
- the isolation gate voltage provided by the multilevel gate driver 210 is shown at 310 . It is varied between Vcc and Vccp as data is accessed at a time interval 312 , sensed at a time interval 314 and restored during a time interval 316 . Digit line voltages are indicated at 318 and 320 where a positive charge is read on storage capacitor 232 .
- the isolation gate voltage is at Vcc prior to read 312 .
- the isolation gate voltage 310 is raised to Vccp, and then lowered to Vcc during the sensing interval 314 . Finally, during restore 316 , the isolation gate voltage is again raised to Vccp.
- the isolation transistors By using a pumped power supply voltage, Vccp, the isolation transistors turn on better and become much more conductive and Vt becomes relatively small with respect to the pumped power supply voltage, allowing the difference in voltage on the digit lines to be reliably detected by the sense amplifiers. Since the isolation gates still present significant resistance at Vcc, it is not necessary to drop the gates down to zero volts as in the prior art during the sensing interval. In other words, there is sufficient gain in the sense amplifier to drive to full rails of Vcc and zero volts due to such resistance combined with the parasitic capacitance of the digit lines. Finally, during the restore interval, raising the isolation gate voltage to Vccp again turns on the isolation gate fully, reducing its resistance and allowing the storage capacitor 232 to be properly written.
- a further embodiment of the invention is illustrated in the voltage versus time diagram of FIG. 4. For simplicity, only the isolation gate voltage 410 is shown. The same time intervals of access, 412 , sense, 414 and restore 416 are also shown. In this embodiment, both the isolation gate voltage is held at a desired reference voltage, such as Vccp during access 412 and restore 416 intervals, but is brought to zero or near zero volts during the sensing operation to fully isolate the digit lines from the sense amplifier. This allows the sense amplifier to more quickly drive to full rail, which allows data to be transferred to I/O lines more quickly, improving the speed at which data is accessed. Similar benefits during the access and sense intervals are obtained as in the embodiment of FIG. 3, along with the benefits during the restore interval 416 .
- FIG. 5 Yet a further embodiment of the present invention is illustrated in FIG. 5. Again, only the isolation gate voltage 510 is shown, and the same time intervals of access, 512 , sense, 514 and restore 516 are shown.
- the isolation gate voltage is held fairly constant at the first reference voltage Vcc during the access 512 and sense 514 intervals. Then, during restore, the isolation gate voltage is rapidly ramped up to the second reference voltage Vccp to more quickly perform the restore operation by lowering the resistance provided by the isolation gates as in the previous embodiments. In this case, however, since the voltage during the sense interval is already at Vcc, less time is required to ramp up the isolation gate voltage 510 to Vccp. This allows the restore operation to complete more quickly.
- a further embodiment of the invention is illustrated in the voltage versus time diagram of FIG. 6.
- the isolation gate voltage 610 is shown.
- the same time intervals of access, 612 , sense, 614 and restore 616 are also shown.
- the isolation gate voltage is held at the second reference voltage before and during access 612 and during restore 616 intervals, but is brought to the first reference voltage during the sensing operation to provide increased resistance between the sense amplifiers and the digit lines. This allows the sense amplifier to more quickly drive to full rail, improving the speed at which data is read. In addition, it takes less time to change the power supply voltage levels applied. Similar benefits during the access and sense intervals are obtained as in the embodiment of FIG. 3, along with the benefits during the restore interval 416 .
- the first reference voltage during the sense interval 614 may be any voltage between Vcc and zero, or perhaps less than zero if desired. It should serve to increase the resistance or isolation provided by the isolation gates.
- Vcc voltage higher than the first reference voltage by more than Vt. This need not be the case.
- the higher, second reference voltage could also be less than Vt above the supply voltage and at least some of the benefits of significantly affecting the resistance of the isolation gates as compared to their resistance at a gate voltage of Vcc will be obtained.
Abstract
Description
- The present invention relates to semiconductor based memory devices, and in particular to sense amplifier isolation gates.
- Semiconductor memory devices contain memory cells for storing small electrical charges representative of bits of data. As storage densities are increasing, the cells, and circuitry used to access, sense and restore bits stored in the cells are becoming smaller and smaller. Sense amplifiers are used to detect and amplify the charges stored in the cells. As the size of the memory devices decrease, the charge to be detected decreases. In addition, the power supply voltages at which DRAMs operate are also decreasing to reduce the power consumption of the DRAMs. The lower power supply voltages, lead to slower circuit operations, or in some cases where transistors have relatively high threshold voltages, improper operation.
- Isolation gates are used to connect digit lines coupled to multiple memory cells to sense amplifiers. In normal operation, the isolation gates selectively turned on and off during read, sense and restore cycles. First, the isolation gates are coupled to the power supply Vcc during initially accessing charges from a memory cell. In most cases, they are left on during sensing, but sometimes they have been turned off by coupling the gates to ground during sensing. Finally, the iso gates are coupled to Vcc during restore to turn them back on. As Vcc decreases, the threshold voltage, Vt, of the isolation gates becomes relatively large, and affects the ability of the sense amplifiers to sense the charge stored on the cells. The threshold voltage is not easily scalable. Further, high Vt relative to Vcc can affect the ability to restore the sensed cell due to significant resistance presented by the isolation gate. Some prior attempts to solve this problem on restore resulted in a pumped Vcc, Vccp, being applied to the isolation gates to reduce this resistance as seen in an IEEE paper entitled “Low Voltage High Speed Circuit Designs for Giga-bit DRAMs” by Lee et al., Symposium on VLSI Circuits Digest of Technical Papers, 1996, pp 104, 105.
- There is a need for accurate reading of memory cells in DRAM devices. There is a further need for better detection of voltage differences on digit lines during access operations, especially when the supply voltage of the DRAM is decreased. There is yet a further need for faster accessing, sensing and restoring of memory cells in DRAM devices.
- A variable voltage is provided to gates of isolation transistors in DRAM devices between digit lines containing many storage cells and a sense amplifier. The gate of the isolation transistor is provided a voltage higher than the supply voltage during access time to ensure that a small differential voltage on the digit lines is correctly detected. A lower voltage is provided at sense time such that the isolation gate provides a higher resistance during sense time. In a further embodiment, during restore time, the isolation gate voltage is again raised above the supply voltage to minimize the effects of isolation transistor threshold voltage, Vt. This provides the ability to eliminate a Vt drop at access and restore times while providing better isolation of the digit lines when the sense amplifier fires.
- In one embodiment, the voltage on the isolation gate is increased greater than Vt above Vcc at access time to Vccp, and then decreased during sense time to provide some amount of isolation from the digit lines. This provides for a faster driving of the isolated portions of the digit lines to Vcc and ground by the sense amplifiers.
- In a further embodiment, the voltage on the isolation gate is increased to Vccp both during access time and during restore time to reduce adverse effects of Vt drops. In yet a further embodiment, the isolation gate voltage during access time is dropped below Vcc. In one embodiment, it is dropped to ground.
- In yet a further embodiment, the voltage on the isolation gate is held at Vcc for both access and sense, and then increased to Vccp during restore time. A typical value for Vcc is 2.5 volts, and for Vccp is 4.0 volts. When Vt is almost 1 volt, and the digit or bit lines are equilibrated at 1.25 volts, Vt of the isolation gates adversely affects accurate sensing of the digit lines. Even further reductions in Vcc exacerbate the problem. By increasing the voltage of the isolation gates above Vcc at selected times, sensing accuracy is greatly improved, and restore operations are enhanced. In addition, reducing the isolation gate voltage during read time helps speed the driving of the sense amplifier lines to Vcc and ground by providing increased resistance or isolation between the sense amplifiers and the digit lines.
- FIG. 1 is a block schematic diagram of DRAM digit lines coupled to shared sense amplifiers.
- FIG. 2 is a block schematic diagram of a pair of DRAM digit lines coupled to an n-sense amplifier.
- FIG. 3 is a timing diagram of voltages applied to gates of isolation transistors in the diagram of FIG. 2.
- FIG. 4 is a timing diagram of voltages applied to gates of isolation transistors in the diagram of FIG. 2 in a further embodiment.
- FIG. 5 is a timing diagram of voltages applied to gates of isolation transistors in the diagram of FIG. 2 in still a further embodiment.
- FIG. 6 is a timing diagram of voltages applied to gates of isolation transistors in the diagram of FIG. 2 in still a further embodiment.
- In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
- A dynamic random access memory DRAM array is shown generally at110 in FIG. 1.
Digit lines n sense amplifiers 120 through isolation transistors indicated at 122, 124, 126 and 128. The isolation transistors have been used in the past to isolate the sense amplifiers from digit line parasitic capacitance as represented at 130, 132, 134 and 136. The parasitic capacitance of each line becomes relatively more significant as higher density, lower voltage, DRAMs are developed, and can significantly delay proper accessing, sensing and restoring of the digit lines. In the present invention, the isolation transistors are driven by a variable-voltage during different portions of accessing, sensing and restoring memory cells coupled to the digit lines. In further embodiments, the DRAM of FIG. 1 is representative of multiple subarrays of rows of memory cells sharing multiple sense amplifiers. - Further detail of a portion of the DRAM array is shown in FIG. 2. A multilevel gate driver is shown in block form at210. Drivers which are capable of generating different voltage levels are known in the art and hence
multilevel gate driver 210 is shown in block format.Multilevel gate driver 210 is coupled to gates of twoisolation transistors digit lines channel transistors transistor 226. The p-sense amplifier comprises a pair of cross coupled p-channel transistors transistor 229.Digit line 218 is also coupled to multiple memory cells, one of which comprises anaccess transistor 230 series coupled to astorage capacitor 232 which holds a charge representative of desired data. A gate of theaccess transistor 230 is coupled to a word line indicated at 234 which is used to couple thestorage capacitor 232 to the digit line. Multiple different word lines are shown in FIG. 2, such that firing of one word line only provides the charge from one storage capacitor on the digit line.Digit line 216 is also coupled to many memory cells which are also coupled to the word lines, forming rows of memory cells. In this embodiment,digit line 216 is used as a reference, and the difference in voltage of the two digit lines is detected and then amplified or sensed by the n-sense amplifier 220. - Isolation gate control signals and digit line voltages are shown in FIG. 3 in one embodiment of the invention as voltage versus time. The isolation gate voltage in this embodiment is varied from a first reference voltage, such as an array power supply voltage, Vcc to a higher, second reference voltage such as a pumped array power supply voltage Vccp. Vccp in one embodiment is Vcc plus an amount higher than the threshold voltage, Vt, of n-channel transistors formed on the DRAM. In one embodiment, Vcc is 2.0 volts, and Vccp is 3.1 volts or higher where the Vt is 1.0 volts. In a further embodiment, Vcc is 2.5 volts, and Vccp is 4.0 volts to provied a significant increase compared to a Vt of 1.0 volts. In FIG. 3, the isolation gate voltage provided by the
multilevel gate driver 210 is shown at 310. It is varied between Vcc and Vccp as data is accessed at a time interval 312, sensed at atime interval 314 and restored during atime interval 316. Digit line voltages are indicated at 318 and 320 where a positive charge is read onstorage capacitor 232. As seen in FIG. 3, the isolation gate voltage is at Vcc prior to read 312. During access 312, theisolation gate voltage 310 is raised to Vccp, and then lowered to Vcc during thesensing interval 314. Finally, during restore 316, the isolation gate voltage is again raised to Vccp. - With relatively high Vt, it becomes more difficult to differentiate between the high and low digit lines, especially where the digit lines are biased to Vcc/2, which is very common in high density DRAMs. Essentially, with the isolation gate held at Vcc, the isolation transistors tend to present a significant resistance between the storage cell and the sense amp, reducing the difference in voltage on the digit lines induced by the charge stored on the storage cell. In addition, with even lower Vcc in new DRAMs, the isolation transistor does not adequately turn on because of the relatively large Vt. When reading a “1” from a storage cell, the charge may be insufficient to overcome an increased resistance of the isolation transistor, further leading to unreliable sensing. By using a pumped power supply voltage, Vccp, the isolation transistors turn on better and become much more conductive and Vt becomes relatively small with respect to the pumped power supply voltage, allowing the difference in voltage on the digit lines to be reliably detected by the sense amplifiers. Since the isolation gates still present significant resistance at Vcc, it is not necessary to drop the gates down to zero volts as in the prior art during the sensing interval. In other words, there is sufficient gain in the sense amplifier to drive to full rails of Vcc and zero volts due to such resistance combined with the parasitic capacitance of the digit lines. Finally, during the restore interval, raising the isolation gate voltage to Vccp again turns on the isolation gate fully, reducing its resistance and allowing the
storage capacitor 232 to be properly written. - A further embodiment of the invention is illustrated in the voltage versus time diagram of FIG. 4. For simplicity, only the
isolation gate voltage 410 is shown. The same time intervals of access, 412, sense, 414 and restore 416 are also shown. In this embodiment, both the isolation gate voltage is held at a desired reference voltage, such as Vccp during access 412 and restore 416 intervals, but is brought to zero or near zero volts during the sensing operation to fully isolate the digit lines from the sense amplifier. This allows the sense amplifier to more quickly drive to full rail, which allows data to be transferred to I/O lines more quickly, improving the speed at which data is accessed. Similar benefits during the access and sense intervals are obtained as in the embodiment of FIG. 3, along with the benefits during the restoreinterval 416. - Yet a further embodiment of the present invention is illustrated in FIG. 5. Again, only the
isolation gate voltage 510 is shown, and the same time intervals of access, 512, sense, 514 and restore 516 are shown. In this embodiment, the isolation gate voltage is held fairly constant at the first reference voltage Vcc during the access 512 andsense 514 intervals. Then, during restore, the isolation gate voltage is rapidly ramped up to the second reference voltage Vccp to more quickly perform the restore operation by lowering the resistance provided by the isolation gates as in the previous embodiments. In this case, however, since the voltage during the sense interval is already at Vcc, less time is required to ramp up theisolation gate voltage 510 to Vccp. This allows the restore operation to complete more quickly. - A further embodiment of the invention is illustrated in the voltage versus time diagram of FIG. 6. For simplicity, only the
isolation gate voltage 610 is shown. The same time intervals of access, 612, sense, 614 and restore 616 are also shown. In this embodiment, the isolation gate voltage is held at the second reference voltage before and during access 612 and during restore 616 intervals, but is brought to the first reference voltage during the sensing operation to provide increased resistance between the sense amplifiers and the digit lines. This allows the sense amplifier to more quickly drive to full rail, improving the speed at which data is read. In addition, it takes less time to change the power supply voltage levels applied. Similar benefits during the access and sense intervals are obtained as in the embodiment of FIG. 3, along with the benefits during the restoreinterval 416. In further variations of FIG. 6, the first reference voltage during thesense interval 614 may be any voltage between Vcc and zero, or perhaps less than zero if desired. It should serve to increase the resistance or isolation provided by the isolation gates. - It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. While the power supply voltage and threshold voltages were described as explicit values, memory devices having other supply and threshold voltages will also benefit from the various embodiments of the present invention. One range of Vcc is between approximately 1.5 and 2.5 volts. The second reference voltage, Vccp, was described as a voltage higher than the first reference voltage by more than Vt. This need not be the case. The higher, second reference voltage could also be less than Vt above the supply voltage and at least some of the benefits of significantly affecting the resistance of the isolation gates as compared to their resistance at a gate voltage of Vcc will be obtained. Such variations will be obvious to one skilled in the art upon review of the present description.
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US09/293,027 US6275409B1 (en) | 1997-06-19 | 1999-04-16 | Methods of operating a dynamic random access memory |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060209604A1 (en) * | 2005-02-15 | 2006-09-21 | Micron Technology, Inc. | Negative voltage driving for the digit line isolation gates |
US20100290268A1 (en) * | 2005-05-05 | 2010-11-18 | Micron Technology, Inc. | Memory cell, pair of memory cells, and memory array |
TWI607434B (en) * | 2011-10-24 | 2017-12-01 | 半導體能源研究所股份有限公司 | Semiconductor memory device and driving method thereof |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5901078A (en) | 1997-06-19 | 1999-05-04 | Micron Technology, Inc. | Variable voltage isolation gate and method |
US6545904B2 (en) * | 2001-03-16 | 2003-04-08 | Micron Technology, Inc. | 6f2 dram array, a dram array formed on a semiconductive substrate, a method of forming memory cells in a 6f2 dram array and a method of isolating a single row of memory cells in a 6f2 dram array |
US7132696B2 (en) * | 2002-08-28 | 2006-11-07 | Micron Technology, Inc. | Intermeshed guard bands for multiple voltage supply structures on an integrated circuit, and methods of making same |
US6859408B2 (en) * | 2002-08-29 | 2005-02-22 | Micron Technology, Inc. | Current limiting antifuse programming path |
US6834019B2 (en) * | 2002-08-29 | 2004-12-21 | Micron Technology, Inc. | Isolation device over field in a memory device |
KR100571645B1 (en) * | 2003-05-29 | 2006-04-17 | 주식회사 하이닉스반도체 | The method to store rapidly data to the cell without voltage loss and the memory device therefor |
US6992939B2 (en) * | 2004-01-26 | 2006-01-31 | Micron Technology, Inc. | Method and apparatus for identifying short circuits in an integrated circuit device |
US8310859B2 (en) * | 2008-09-30 | 2012-11-13 | Samsung Electronics Co., Ltd. | Semiconductor memory device having balancing capacitors |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB9007789D0 (en) * | 1990-04-06 | 1990-06-06 | Foss Richard C | Method for dram sensing current control |
JPH0620465A (en) * | 1991-09-02 | 1994-01-28 | Mitsubishi Electric Corp | Semiconductor storage device |
JPH05159575A (en) * | 1991-12-04 | 1993-06-25 | Oki Electric Ind Co Ltd | Dynamic random-access memory |
US5301160A (en) * | 1992-02-24 | 1994-04-05 | Texas Instruments Incorporated | Computer including an integrated circuit having a low power selection control arrangement |
JP2795074B2 (en) * | 1992-07-16 | 1998-09-10 | 日本電気株式会社 | Dynamic RAM |
US5311478A (en) * | 1992-08-18 | 1994-05-10 | Micron Technology, Inc. | Integrated circuit memory with asymmetric row access topology |
US5339274A (en) * | 1992-10-30 | 1994-08-16 | International Business Machines Corporation | Variable bitline precharge voltage sensing technique for DRAM structures |
JPH06150646A (en) * | 1992-11-13 | 1994-05-31 | Nec Corp | Semiconductor memory |
US5369622A (en) * | 1993-04-20 | 1994-11-29 | Micron Semiconductor, Inc. | Memory with isolated digit lines |
US5367213A (en) * | 1993-06-09 | 1994-11-22 | Micron Semiconductor, Inc. | P-channel sense amplifier pull-up circuit incorporating a voltage comparator for use in DRAM memories having non-bootstrapped word lines |
JPH0757466A (en) * | 1993-08-12 | 1995-03-03 | Toshiba Corp | Semiconductor integrated circuit |
KR960009953B1 (en) * | 1994-01-27 | 1996-07-25 | 삼성전자 주식회사 | Sense-amp. control circuit of semiconductor memory device |
US5508958A (en) * | 1994-09-29 | 1996-04-16 | Intel Corporation | Method and apparatus for sensing the state of floating gate memory cells by applying a variable gate voltage |
US5532955A (en) * | 1994-12-30 | 1996-07-02 | Mosaid Technologies Incorporated | Method of multilevel dram sense and restore |
US5719813A (en) * | 1995-06-06 | 1998-02-17 | Micron Technology, Inc. | Cell plate referencing for DRAM sensing |
US5553028A (en) * | 1995-06-23 | 1996-09-03 | Micron Technology, Inc. | Single P-sense AMP circuit using depletion isolation devices |
KR0154755B1 (en) * | 1995-07-07 | 1998-12-01 | 김광호 | Semiconductor memory device having variable plate voltage generater circuit |
KR0172555B1 (en) * | 1995-12-29 | 1999-03-30 | 김주용 | High speed sense amplifier |
JP3862333B2 (en) * | 1996-12-10 | 2006-12-27 | 株式会社ルネサステクノロジ | Semiconductor memory device |
US5901078A (en) | 1997-06-19 | 1999-05-04 | Micron Technology, Inc. | Variable voltage isolation gate and method |
-
1997
- 1997-06-19 US US08/878,657 patent/US5901078A/en not_active Expired - Lifetime
-
1998
- 1998-06-18 JP JP11504818A patent/JP2000513479A/en active Pending
- 1998-06-18 AU AU79783/98A patent/AU7978398A/en not_active Abandoned
- 1998-06-18 WO PCT/US1998/012731 patent/WO1998058380A1/en active IP Right Grant
- 1998-06-18 KR KR10-1999-7012040A patent/KR100368705B1/en not_active IP Right Cessation
- 1998-06-19 TW TW087109841A patent/TW422978B/en not_active IP Right Cessation
-
1999
- 1999-04-16 US US09/293,027 patent/US6275409B1/en not_active Expired - Lifetime
-
2001
- 2001-08-14 US US09/929,611 patent/US6445610B1/en not_active Expired - Lifetime
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060209604A1 (en) * | 2005-02-15 | 2006-09-21 | Micron Technology, Inc. | Negative voltage driving for the digit line isolation gates |
US7697357B2 (en) | 2005-02-15 | 2010-04-13 | Micron Technology, Inc. | Negative voltage driving for the digit line isolation gates |
US20100290268A1 (en) * | 2005-05-05 | 2010-11-18 | Micron Technology, Inc. | Memory cell, pair of memory cells, and memory array |
US8207564B2 (en) * | 2005-05-05 | 2012-06-26 | Micron Technology, Inc. | Memory cell, pair of memory cells, and memory array |
TWI607434B (en) * | 2011-10-24 | 2017-12-01 | 半導體能源研究所股份有限公司 | Semiconductor memory device and driving method thereof |
Also Published As
Publication number | Publication date |
---|---|
US6275409B1 (en) | 2001-08-14 |
KR20010014011A (en) | 2001-02-26 |
WO1998058380A1 (en) | 1998-12-23 |
TW422978B (en) | 2001-02-21 |
US6445610B1 (en) | 2002-09-03 |
JP2000513479A (en) | 2000-10-10 |
US5901078A (en) | 1999-05-04 |
AU7978398A (en) | 1999-01-04 |
KR100368705B1 (en) | 2003-01-24 |
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