US20020042194A1 - Method for forming contact holes on conductors having a protective layer using selective etching - Google Patents
Method for forming contact holes on conductors having a protective layer using selective etching Download PDFInfo
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- US20020042194A1 US20020042194A1 US09/781,422 US78142201A US2002042194A1 US 20020042194 A1 US20020042194 A1 US 20020042194A1 US 78142201 A US78142201 A US 78142201A US 2002042194 A1 US2002042194 A1 US 2002042194A1
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- insulating film
- protective film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
Definitions
- the protective film serves to protect the gate electrodes from the etching gas during etching.
- the side-wall portions of the protective film which cover the side walls of the gate electrodes are exposed in the course of the etching process, the side-wall portions function as etching stoppers, and contact holes can be formed between the gate electrodes with high accuracy regardless of placement accuracy of the etching mask, so that specified conductive property can be obtained by a conductive material used to fill the contact holes.
- the contact hole can be formed by a single etching process in a specified position of the insulating film.
- the exposed protective film needs to be etched. Because the protective film has a different etching-resistant characteristic from that of the insulating film, their etching conditions differ to a large extent in the forming process of the two contact holes.
- the opening 20 is hindered from intruding into the substrate 10 , which would otherwise be caused by excessive removal of the insulating film 15 .
- those contact holes 21 to 23 including the first and second contact holes 21 and 22 can be formed collectively.
- the etched-away opening 20 is formed in conjunction with a specified gate electrode 11 d , during which process the protective film 14 related to the specified gate electrode 11 d is removed, and then the etched-away opening 20 is refilled with the same material as the material for the insulating film 15 .
- a single etching mask 24 which is made possible by those preparatory steps, such as refilling the opening 20 , it is possible to collectively form the contact holes, including the first contact hole 21 that opens to the active region of the substrate 10 and the second contact hole 22 that opens to the gate electrode 11 .
- a mixed etching gas of CHF 3 and CO for example, is used which is used in forming the etched-away opening 20 as mentioned above.
- This etching gas as described above, exhibits a higher etching rate with the protective film 14 of silicon nitride than with the insulating film 15 of silicon oxide. Therefore, in the etched-away opening 35 , the signal lines 25 d and 25 e are exposed without the insulating film 15 being removed excessively.
- the gate electrodes 11 are formed on the semiconductor substrate 10 in the same way as in FIG. 2( a ) showing the first embodiment.
- the protective film 14 of the gate electrode 11 d is partially removed by the formation of the etched-away opening 20 by etching using a mixed gas of CHF 3 and CO, which has been used for the insulating film 15 , thereby temporarily exposing the tungsten silicide portion of the gate electrode 11 d , and after this the etched-away opening 20 is refilled with a silicon oxide material.
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming contact holes for conductive strips passing through an insulating film, such as an interlayer insulating film.
- 2. Description of Related Art
- In semiconductor devices, including semiconductor elements, such as MOS transistors, when contact holes, which run through an insulating film, where the MOS transistors are buried, and which open to active regions on the semiconductor substrate, are formed between gate electrodes of a pair of MOS transistors on a semiconductor substrate, for example, they are generally formed by a self-aligned contact process.
- According to the self-aligned contact process, a protective film of silicon nitride, for example, is formed to cover gate electrodes for MOS transistors on a semiconductor substrate, for example. Moreover, an insulating film of silicon oxide is formed to bury the gate electrodes along with the protective film in it. On this insulating film, wiring for a multi-layered structure is formed when necessary, and prior to this wiring work, to form contact holes that open to the semiconductor substrate between the gate electrodes, those regions of the insulating film which are located between the gate electrodes are subjected to an etching process using an etching mask and an etching gas to expose the above-mentioned regions between the gate electrodes.
- Because the etching gas shows a notably low etching rate to the protective film than to the insulating film, the protective film serves to protect the gate electrodes from the etching gas during etching. When the side-wall portions of the protective film which cover the side walls of the gate electrodes are exposed in the course of the etching process, the side-wall portions function as etching stoppers, and contact holes can be formed between the gate electrodes with high accuracy regardless of placement accuracy of the etching mask, so that specified conductive property can be obtained by a conductive material used to fill the contact holes.
- Meanwhile, in conventional semiconductor devices such as have been mentioned above, it is often required to provide two contact holes: a contact hole that opens to the surface of the semiconductor substrate and another contact hole that opens to a conductor, such as a gate electrode under the protective film.
- In the former, the contact hole can be formed by a single etching process in a specified position of the insulating film. In the latter, however, after the insulating film has been etched, the exposed protective film needs to be etched. Because the protective film has a different etching-resistant characteristic from that of the insulating film, their etching conditions differ to a large extent in the forming process of the two contact holes.
- For this reason, in the conventional manufacturing method, it is necessary to separately carry out an etching process using a mask for the contact hole that opens to the surface of the semiconductor substrate, and an etching process using a mask for the contact hole that opens to the conductive line under the protective film. Therefore, it is necessary to set a relative position of the two masks for the different contact holes with accuracy.
- In this respect, there has been requirement for a method for forming two contact holes with high accuracy and with improved facility.
- To solve the above problem, the present invention adopts the following structure.
- <Structure>
- In manufacturing a semiconductor device having a semiconductor substrate, a conductor formed on the semiconductor substrate and covered with a protective film, and an insulating film deposited above the semiconductor substrate to cover the conductor, a method for forming a first contact hole running through the insulating film and opening to the surface of the semiconductor substrate or to an electric connection member buried in the insulating film, and a second contact hole running through both the insulating film and the protective film and opening to said conductor under the protective film, the contact-hole forming method comprises the steps of:
- forming an etched-away opening running from the upper surface of the insulating film to expose the top portion of the conductor corresponding to the opening by using an etching medium exhibiting a higher etching rate to the protective film than to the insulating film to partially remove by etching the protective film on the conductor where the second contact hole is to be formed;
- refilling the etched-away opening with a material of the same characteristic as the insulating film; and
- etching the layer of the insulating film that has been refilled with a single etching medium to thereby simultaneously form the first contact hole opening to the semiconductor substrate or the electric connection member buried in the insulating film, and the second contact hole opening to the conductor.
- According to the above method of the present invention, the protective film above the conductor, where the second contact hole is to be formed, is removed in advance, when the etched-away opening is formed to expose the top portion of the corresponding conductor from the surface of the insulating film, and the etched-away opening is refilled. Under this condition, it is possible to form the second contact hole substantially under the same condition as in etching of the first contact hole.
- Moreover, in the formation of the etched-away opening, because an etching medium is used which exhibits a greater etching rate to the protective film than to the insulating film, the etched-away opening does not have its circumferential wall become like a beer barrel or taper off nor does it incur an etching stoppage at the interface between the insulating film and the protective film caused by a change of the kind of etching medium, so that the protective film can be etched so as to have specified parts appropriately removed.
- Therefore, according to the above-mentioned method of the present invention, a final etching process to form the first and second contact holes after refilling of the etched-away opening can be carried out substantially under the same condition, and therefore both contact holes can be formed collectively by an etching process using a single etching mask having arranged therein two opening patterns for the first and second contact holes.
- The above-mentioned conductors include gate electrodes or signal lines of field-effect semiconductor devices formed on a semiconductor substrate and various kinds of conductive parts formed on the semiconductor substrate.
- The etching rate of the etching medium with respect to the protective film can be made 1.3-2.0 times that of the insulating film.
- When the insulating film is silicon oxide and the protective film is a silicon nitride film used as an etching stopper in a self-aligned contact process, a mixed gas of CHF3 and CO as the etching medium.
- FIGS.1(a) to 1(d) show a manufacturing process in a first embodiment of the method for forming contact holes according to the present invention (Part 1);
- FIGS.2(a) to 2(b) show a manufacturing process in the first embodiment of the method for forming contact holes according to the present invention (Part 2);
- FIGS.3(a) to 3(d) show a manufacturing process in a second embodiment of the method for forming contact holes according to the present invention (Part 1);
- FIGS.4(a) to 4(c) show a manufacturing process in the second embodiment of the method for forming contact holes according to the present invention (Part 2); and
- FIGS.5(a) to 5(b) show a manufacturing process in a third embodiment of the method for forming contact holes according to the present invention.
- The present invention will be described in detail by referring to preferred embodiments illustrated in the accompanying drawings.
- <Embodiment 1>
- FIGS. 1 and 2 show a first embodiment of a semiconductor device manufacturing process according to the present invention.
- As shown in FIG. (a), a plurality of gate electrodes11 (11 a to 11 e) for MOS transistors are formed in parallel and mutually spaced apart in an active region of a
silicon semiconductor substrate 10, for example. - In the illustrated example, each gate electrode11 has a well-known multi-layered structure including a
polysilicon layer 12 containing impurity atoms and a tungsten silicide layer 13 (provided for increased electric conductivity), and is covered at the top surface with aprotective film 14 of a silicon nitride, for example. Those gate electrodes 11 are provided by depositing polysilicon and silicide in this order on thesubstrate 10, for example, through an intermediary of a well-known gate electrode not shown, then forming aprotective film 14 of silicon nitride on the stacked structure by photolithography, and subsequently removing unwanted portions of the stacked structure and the gate oxide film by selective etching with the protective film used as the etching mask. - Though not illustrated, by using the gate electrodes11 each having a
protective film 14 at the top portion as a mask, impurity atoms to form the source and drain regions are injected into thesubstrate 10 on either side of the gate electrodes 11 by ion implantation, for example. - After the source and drain regions corresponding to the gate electrodes11 are formed, as shown in FIG. 1(b), a silicon nitride film of the same material as that of the above-mentioned
protective film 14 is deposited by CVD, for example, to cover each gate electrode 11. - By the deposition of the silicon nitride material of the side-
wall portions 14 b to cover the side walls of the gate electrodes 11 are formed in a manner continuous with thetop portions 14 a of theprotective films 14, andbottom portions 14 c with a thin thickness are formed between the gate electrodes 11 on thesubstrate 10 in a manner continuous with the side-wall portions 14 b. As a result, the thickness of thetop portions 14 a of theprotective film 14 increases by an amount corresponding to the thickness of thebottom portions 14 c. - After the silicon nitride film has been deposited, as shown in FIG. 1(c), to bury the silicon nitride film, an
interlayer insulating film 15, of a silicon oxide film, for example, is formed. The surface of theinterlayer insulating film 15 is subjected to a flattening process. To form contact holes, which open to the source and drain regions in the active region of thesubstrate 10 between desired gate electrodes 11, anetching mask 16 havingopenings 16 a that correspond to desired contact holes is formed on the flattened surface of theinsulating film 15 by a self-aligned contact process. In the example illustrated, self-aligned contact holes are formed respectively between thegate electrodes gate electrodes - The
insulating film 15 is etched by selective etching with theetching mask 16. As an etching medium, a CF-based etching gas, for example, is used. - This etching gas exhibits a sufficiently higher etching rate to the
insulating film 15 of silicon oxide than to theprotective film 14 of silicon nitride. Therefore, when those portions of theinsulating film 15 which correspond to theopenings etching mask 16 are removed and consequently some parts of thetop portions 14 a, the side-wall portions 14 b and the bottom portions of theprotective film 14 are exposed to the etching gas, thebottom portions 14 c of thin thickness are removed in a relatively short time, but thetop portions 14 a and side-wall portions 14 b except for thebottom portions 14 c remain after the portions between the side-wall portions 14 b of theinsulating film 15 have been removed. - As described above, the
top portions 14 a and the side-wall portions 14 b of theprotective film 14, which have been well known to function substantially as etching stoppers. Therefore, as shown in FIG. 1(d), desired self-alignedcontact holes protective film 14 provided in conjunction with the gate electrodes regardless of the placement accuracy with which theetching mask 16 is placed. -
Plugs 18 are formed to fill up thecontact holes plugs 18 are made of impurity-doped polysilicon, for example, and serve as conductors. After theplugs 18 are formed, theetching mask 16 is removed. - After this, a first contact hole21 (refer to FIG. 2(b)) that opens to the active region of the
substrate 10 and a second contact hole 22 (refer to FIG. 2(b)) that opens to the gate electrode 11 as a conductor are formed without using the above-mentioned self-aligned contact process. Before thecontact holes protective film 14 is removed which is on the desired gate electrode 11 where thesecond contact hole 22 is to be formed. - As shown in FIG. 1(d), when the above-mentioned
second contact hole 22 is formed on thegate electrode 11 d, for example, the surface of the insulatingfilm 15 is subjected to a flattening process, and anetching mask 19 having an opening 19 a to partially expose that portion of the insulating film which is located above and corresponds to a desiredgate electrode 11 d is formed on the flattened surface of the insulatingfilm 15. - The diameter of the opening19 a of the
etching mask 19 is preferably sufficiently larger than the width dimension of thegate electrode 11 d. - An etched-away
opening 20 is formed in the insulatingfilm 15 by removing that portion of the insulatingfilm 15 which is located above thegate electrode 11 d by etching with themask 19 mentioned above. - In the above etching, a mixed gas of CHF3 and CO, for example, is used as an etching medium. This etching gas exhibits a higher etching rate to the
protective film 14 of silicon nitride than to the insulatingfilm 15 of silicon oxide. Therefore, by suitably setting the composition of components of this etching gas, it is possible to obtain an etching gas which has an etching rate of 1.3, for example, with respect to theprotective film 14 when the etching rate to the insulatingfilm 15 is 1. - In etching using the above-mentioned etching gas, the insulating
film 15 is etched away partially, and when theprotective film 14 of thegate electrode 11 d is exposed as the etching process proceeds, theprotective film 14 is etched faster than the insulatingfilm 15. - Consequently, as shown in FIG. 1(d), an etched-away
opening 20 is formed as an extension of the opening 19 a of theetching mask 19, and thegate electrode 11 d can be exposed under the condition that the unwantedprotective film 14 has been removed from the etched-away opening. In the example in FIG. 1(d), theprotective film 14 has had removed itstop portion 14 a of thegate electrode 11 d as well as upper halves of its side-wall portions 14 b, which were continuous to the top portion. - In the forming process of the etched-away
opening 20, the insulatingfilm 15 and theprotective film 14 react to the etching gas at their etching rates mentioned above, and therefore the insulating film does not react so strongly as theprotective film 14. Accordingly, the etched-awayopening 20 does not become like a beer barrel with the circumferential wall swelling outward at its middle portion nor does it taper off downwardly as it has a relatively large diameter. Therefore, anadequate opening 20 aligned with the opening 19 a of theetching mask 19 can be formed by etching. - By using an etching gas which has a higher etching rate to the
protective film 14 than to the insulatingfilm 15, theopening 20 is hindered from intruding into thesubstrate 10, which would otherwise be caused by excessive removal of the insulatingfilm 15. - By this forming process of the etched-away
opening 20, the insulatingfilm 15 and theprotective film 14 can be removed by using a single kind of etching gas, so that it is not necessary to change over the etching gas. Therefore, a carbide film, which conventionally occurs by a changeover of the etching gas, is prevented from forming on the protective film. Thus, the etching stoppage caused by the carbide film, which is a commonplace phenomenon, is prevented, with the result that the etched-awayopening 20 can be formed suitably, and thegate electrode 11 d without theprotective film 14 can be exposed in theopening 20. - The ratio of components of this etching gas should preferably be selected suitably so that the etching rate of the
protective film 14 is in the range of 1.3 to 2.0 when the etching rate of the insulatingfilm 15 is 1. - After the etched-away
opening 20 is formed, theetching mask 19 is removed. Subsequently, as shown in FIG. 2(a), silicon oxide, which is the same material for the insulatingfilm 15, is deposited. By this deposition, theplugs 18 are buried and the etched-awayopening 20 is refilled. - After refilling the etched-away
opening 20, the surface of the insulatingfilm 15 is subjected to a flattening process. After this, as shown in FIG. 2(b), on the insulatingfilm 15, anetching mask 24 is formed, which hasopenings first contact hole 21 to open to the active region of thesubstrate 10 and thesecond contact hole 22 to open to the gate electrode 11, with theprotective film 14 eliminated. Thoseopenings gate electrodes - In the illustrated example, in the
etching mark 24, there are formed theopenings plugs - In the etching process of the insulating
film 15 using the above-mentionedetching mask 24, a CF-based etching gas, such as the one used in forming the contact holes 17. - In the etching process to form the contact holes21, 22, 23, 23 using the
etching mask 24, theprotective film 14 is not involved in the formation of the contact holes 22, 23, 23 with the exception of thefirst contact hole 21. In the formation of thefirst contact hole 21, thebottom portion 14 c of theprotective film 14 is involved in the process; however, as described above, thebottom portion 14 c of thin thickness can be removed easily by the CF-based etching gas mentioned above. - Therefore, as shown in FIG. 2(b), by the etching process using a
single etching mask 24 and a single etching gas, those contact holes 21 to 23, including the first and second contact holes 21 and 22 can be formed collectively. - Conductive lines, not shown, filling up the contact holes like the
plugs 18 are formed in the contact holes 21, 22 and 23, and conductors as components of multi-layer wiring are formed on the insulatingfilm 15 after theetching mask 24 is removed. - According to the method for forming the contact holes, as described above, the etched-away
opening 20 is formed in conjunction with a specifiedgate electrode 11 d, during which process theprotective film 14 related to the specifiedgate electrode 11 d is removed, and then the etched-awayopening 20 is refilled with the same material as the material for the insulatingfilm 15. By carrying out the final etching process using asingle etching mask 24, which is made possible by those preparatory steps, such as refilling theopening 20, it is possible to collectively form the contact holes, including thefirst contact hole 21 that opens to the active region of thesubstrate 10 and thesecond contact hole 22 that opens to the gate electrode 11. - In the above-mentioned method for forming the contact holes, the contact holes, including the first and second contact holes21 and 22 corresponding to the
openings etching mask 24 can be formed with high precision relatively easily as it becomes unnecessary to align the positions of the mask for thefirst contact hole 21 and the mask for thesecond contact hole 22. - As the material for refilling the etched-away
opening 20, instead of using the same material as with the insulatingfilm 15, it is possible to use an electrical insulating material with an etching-resistant characteristic almost the same as in the insulatingfilm 15. - In the first embodiment, description has been made of the method for forming contact holes according to the present invention. Description will next be made of an example in which the method for forming contact holes according to the present invention is applied to conductors such as bit lines by referring to FIGS. 3 and 4.
- <Embodiment 2>
- FIGS. 3 and 4 shows a second embodiment of the semiconductor device manufacturing process according to the present invention.
- As shown in FIG. 3(a), a plurality of signal lines 25 (25 a˜25 e) for transmitting electric signals are formed in parallel and mutually spaced apart on the
interlayer insulating film 15 covering thesilicon semiconductor substrate 10, for example. - The signal lines25 are bit lines of memory. In the insulating
film 15 under the bit lines, the gate electrodes 11 (11 a-11 e) are arranged in a direction at right angles with the signal lines. Those gate electrodes 11 are shown in FIGS. 1 and 2 but they are not illustrated here for simplicity of drawing. - The signal lines25 are formed by forming an impurity-doped
polysilicon layer 12 on the insulatingfilm 15, then forming aprotective film 14 of silicon nitride on the polysilicon layer by photolithographic etching and removing thepolysilicon layer 12 by selective etching with the protective film used as the mask. - As shown in FIG. 3(b), by deposition of the same material as that for the
protective films 14 formed over the top portions of the signal lines, thetop portions 14 a of theprotective film 14 and the side-wall portions 14 b, which are continuous to the top portions and covering the side portions of the signal lines 25, are formed, so that the signal lines 25 are covered with thetop portions 14 a and the side-wall portions 14 b of theprotective film 14. - After the tops and the sides of the signal lines25 are covered with the
protective film 14, the silicon oxide material of the insulating film 5 is additionally deposited. By this additional deposition of the material, as shown in FIG. 3(c), the signal lines 25 covered with theprotective film 14 are buried in the insulatingfilm 15. - After this, as shown in FIG. 3(d), on the insulating
film 15, which has been made flat by a flattening process, anetching mask 26 is formed, which hasopenings substrate 10 between desired signal lines 25. - In this illustrated example, self-aligned contact holes are formed respectively between the
signal lines signal lines - Then, the insulating
film 15 is etched by selective etching using theetching mask 26. As an etching medium for the etching process, a CF-based etching gas, which has been used in the preceding example, may be used. - With respect to this etching gas, as mentioned above, the
top portions 14 a and the side-wall portions 14 b of theprotective film 14 work substantially as etching stoppers. Therefore, as shown in FIG. 1(d), desired self-aligned contact holes 27 that extend to thesubstrate 10 are formed with high accuracy between the signal lines 25 by the etching stopper action of theprotective film 14 as described above the placement accuracy or inaccuracy with which theetching mask 26 is placed. - As shown in FIG. 4(a), plugs 28 like those provided in the contact holes 27 are formed, and
storage nodes 29, adielectric film 30 covering thestorage nodes 29, and aconductive layer 31, where thestorage nodes 29 covered with thedielectric film 30 are buried, are formed as the components of capacitors built in conjunction with theplugs 28. The capacitor of a memory cell is formed by astorage node 29 and theconductive layer 31 having thedielectric film 30 between them. - The
conductive layer 31 of the memory cell capacitor has anelectric connection member 31 a extending onto the insulatingfilm 15. Theconductive layer 31 is formed by a remainder of the deposited material for theconductive layer 31 after the unnecessary portions of theconductive layer 31 have been etched away by selective etching using themask 32. - After the
conductive layer 31 is patterned as mentioned above, before a first contact hole 33 (FIG. 4(c)) that opens to theconductive layer 31 and second contact holes (FIG. 4(c)) that open to thesignal lines protective layers 14 on thesecond signal lines mask 32 for patterning of theconductive layer 31. - In this removal of the
protective film 14, a mixed etching gas of CHF3 and CO, for example, is used which is used in forming the etched-awayopening 20 as mentioned above. This etching gas, as described above, exhibits a higher etching rate with theprotective film 14 of silicon nitride than with the insulatingfilm 15 of silicon oxide. Therefore, in the etched-awayopening 35, thesignal lines film 15 being removed excessively. - In the example shown in FIG. 4(a), after the
signal lines portions 14 b′ of the side-wall portions 14 b reduced in height exist on either side of the signal lines. In order to use remainingportions 14′ as etching stoppers in etching of the second contact holes 34, after themask 32 is removed,silicon nitride 14′ is deposited additionally on the exposedconductive layer 31 and on the insulatinglayer 15 including thesignal lines - This additional
silicon nitride film 14′ has a thin thickness as in thebottom portions 14 c of theprotective film 14 shown in FIG. 1(b), but by the deposition of additional silicon nitride, the thickness of the remaining side-wall portions 14 b′ left around thesignal lines silicon nitride film 14′ additionally deposited. - As shown in FIG. 4(c), the same depositing material as that for the insulating
film 15 is deposited on thesilicon nitride film 14′ , thereby refilling the etched-awayopening 35. Subsequently, after the surface of the refilled insulatingfilm 15 has been flattened, on the insulating film, anetching mask 37 is formed which hasopenings first contact hole 33 that opens to theelectric connection member 31 a and the second contact holes 34, 34 that open to thesignal lines - When etching the insulating
film 15 with theetching mask 37, a CF-based etching gas, for example, is used which has been used when etching the contact holes 17, 17. - In the etching process to form the contact holes33 and 34, 34 using the
etching mask 37, there is thesilicon nitride film 14′ of thin thickness, subjected to etching, on theelectric connection member 31 a and on thesignal lines silicon nitride film 14′ can be removed easily and does not function substantially as an etching stopper. - In contrast, the
remainder 14 b′ of the side-wall portions made of silicon nitride left behind on either side of thesignal lines film 15 on either side of thesignal lines etching mask 37 mentioned earlier. - According to the method for forming contact holes according to the present invention described with reference to the second embodiment, as mentioned above, the
first contact hole 33 that opens to theelectric connection member 31 a, and the second contact holes 34, 34 that open to thesignal lines opening 35 in conjunction with the specifiedsignal lines signal lines opening 35 with the same material as that for the insulatingfilm 15. - Therefore, the contact holes33 and 34 corresponding to the
openings etching mask 37 can be formed with high accuracy relatively easily. - Thus, it is unnecessary to deposit the
silicon nitride film 14′ , for which reason the involvement of a different kind of material in etching of the insulatingfilm 15 can be avoided, making is possible to carry out more easily the final etching process for thefirst contact hole 33 and the second contact holes 34, 34 using theetching mask 37. - <Embodiment 3>
- In the first and second embodiments, description has been made of examples in which the first and second contact holes are formed separately. However, as shown in FIG. 5, the first and second contact holes can be formed as a common contact hole.
- As shown in FIG. 5(a), the gate electrodes 11 (11 a to 11 e) are formed on the
semiconductor substrate 10 in the same way as in FIG. 2(a) showing the first embodiment. Theprotective film 14 of thegate electrode 11 d, out of those gate electrodes 11, is partially removed by the formation of the etched-awayopening 20 by etching using a mixed gas of CHF3 and CO, which has been used for the insulatingfilm 15, thereby temporarily exposing the tungsten silicide portion of thegate electrode 11 d, and after this the etched-awayopening 20 is refilled with a silicon oxide material. - In FIGS.5(a) and 5(b), the
isolation regions 10 a are shown, which delimit the active regions of thesubstrate 10, and the same reference numerals designate the same or like components as in FIG. 2(a), though theplugs 18 shown in FIG. 2(a) are not illustrated. - In FIGS.5(a) and 5(b), the
isolation regions 10 a are shown as located under the gate electrodes 11, but actually the gate electrodes 11 are formed so as to be located on the active regions in positions shifted below or above the plane of this paper. - After the etched-away
opening 20 has been refilled, the surface of the insulatingfilm 15 is made flat by a flattening process. After this, as shown in FIG. 5(b), on the insulatingfilm 15, anetching mask 24 is formed having anopening 24 d including thegate electrode 11 d and the left-half portion, as shown, of thegate electrode 11 c. - In etching of the insulating
film 15 using theetching mask 24, a CF-based etching gas, for example, is used which has been used in forming the contact holes 17, 17 in the first embodiment. - In the etching using the
etching mask 24, anenlarged contact hole 38, which corresponds to theopening 24 d of theetching mask 24, is formed in the insulatingfilm 15 so that theenlarged contact hole 38 includes thegate electrode 11 d and the region between thegate electrode 11 d and thegate electrode 11 e. - In the etching of the
enlarged contact hole 38, out of a pair of side-wall portions 14 b remaining around thegate electrode 11 d, one side-wall portion 14 b located at a lower end of the wall of thehole 38 prevents unaccptable damage to thesubstrate 10 caused by an inaccurate placement of theetching mask 24. Moreover, out of theprotective film 14 of thegate electrode 11 e, itstop portion 14 a and that part of the side-wall portion 14 b which is exposed in theetching mask 37 functions as etching stoppers and serves to give a self aligned contact. - On the other hand, that thin-
thickness bottom portion 14 c of theprotective film 14 which is located between thegate electrodes - Thus, the
enlarged contact hole 38 opens to thegate electrode 11 d, from which theprotective film 14 has been removed, and at the region between thegate electrode 11 d and thegate electrode 11 e and therefore functions as a common contact hole for the first and second contact holes (21 and 22). - A common contact hole such as this is advantageous in forming electrical short-circuit plugs.
- In the description made so far, an insulating material, a protective film and an etching gas of specific kinds have been used, but they have been shown not for restrictive but for illustrative purposes, and various materials may be selected without departing from the spirit and scope of the present invention.
- According to the present invention, as described above, by having the specified portions of the protective film removed in advance, it becomes possible to carry out a final etching process to form the first contact hole and the second contact hole under the same condition in such a way that the former is open to the semiconductor substrate and the latter passes through the protective film and is open to the gate electrode. Therefore, it is possible to form both contact holes using a single etching mask for the final etching process.
- For this reason, the relative position of the two contact holes is determined by the accuracy of the pattern of the mask, so that painful effort for positioning separate masks for forming the first and second contact holes becomes unnecessary. Thus, positioning work of the two masks with high accuracy can be done away with and the fist and second contact holes can be formed accurately with relative ease.
Claims (6)
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JP2000305675 | 2000-10-05 | ||
JP305675/2000 | 2000-10-05 | ||
JP12-305675 | 2000-10-05 |
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US20020042194A1 true US20020042194A1 (en) | 2002-04-11 |
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US09/781,422 Expired - Lifetime US6399470B1 (en) | 2000-10-05 | 2001-02-13 | Method for forming contact holes on conductors having a protective layer using selective etching |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040198039A1 (en) * | 2003-02-10 | 2004-10-07 | Infineon Technologies Ag | Method and arrangement for contacting terminals |
DE102004020935B3 (en) * | 2004-04-28 | 2005-09-01 | Infineon Technologies Ag | Production of a memory component, with a contact hole plane, uses a semiconductor substrate with prepared cell field and logic zones and surface gate electrode conductor paths |
US11049784B2 (en) * | 2018-06-15 | 2021-06-29 | Melexis Technologies Nv | Semiconductor device for use in harsh media |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR101345047B1 (en) * | 2011-03-30 | 2013-12-26 | 샤프 가부시키가이샤 | Active matrix substrate, display device, and active matrix substrate manufacturing method |
Family Cites Families (4)
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JPH09153545A (en) * | 1995-09-29 | 1997-06-10 | Toshiba Corp | Semiconductor device and is manufacture |
US5683922A (en) | 1996-10-04 | 1997-11-04 | United Microelectronics Corporation | Method of fabricating a self-aligned contact |
JPH11135779A (en) * | 1997-10-28 | 1999-05-21 | Toshiba Corp | Semiconductor device and manufacture thereof |
TW404009B (en) | 1999-01-27 | 2000-09-01 | United Microelectronics Corp | The method of manufacturing self-aligned contact (SAC) |
-
2001
- 2001-02-13 US US09/781,422 patent/US6399470B1/en not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040198039A1 (en) * | 2003-02-10 | 2004-10-07 | Infineon Technologies Ag | Method and arrangement for contacting terminals |
DE102004020935B3 (en) * | 2004-04-28 | 2005-09-01 | Infineon Technologies Ag | Production of a memory component, with a contact hole plane, uses a semiconductor substrate with prepared cell field and logic zones and surface gate electrode conductor paths |
US11049784B2 (en) * | 2018-06-15 | 2021-06-29 | Melexis Technologies Nv | Semiconductor device for use in harsh media |
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