US20020053316A1 - Method of deposition of a single-crystal silicon region - Google Patents

Method of deposition of a single-crystal silicon region Download PDF

Info

Publication number
US20020053316A1
US20020053316A1 US09/988,233 US98823301A US2002053316A1 US 20020053316 A1 US20020053316 A1 US 20020053316A1 US 98823301 A US98823301 A US 98823301A US 2002053316 A1 US2002053316 A1 US 2002053316A1
Authority
US
United States
Prior art keywords
implantation
silicon
deposition
layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US09/988,233
Inventor
Yvon Gris
Germaine Troillard
Jocelyne Mourier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US09/988,233 priority Critical patent/US20020053316A1/en
Publication of US20020053316A1 publication Critical patent/US20020053316A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H01L29/66287—Silicon vertical transistors with a single crystalline emitter, collector or base including extrinsic, link or graft base formed on the silicon substrate, e.g. by epitaxy, recrystallisation, after insulating device isolation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10S117/913—Graphoepitaxy or surface modification to enhance epitaxy

Definitions

  • the present invention generally relates to the manufacturing of semiconductor devices.
  • silicon has to be deposited on a single-crystal silicon substrate, or on an area of this substrate.
  • Several techniques are currently used.
  • a first, so-called epitaxial, type of deposition is performed under a reducing atmosphere and enables the crystal structure of the deposited layer to be in crystalline continuity with the substrate.
  • These techniques require a deposition at high temperature, typically ranging between 1000° C. and 1200° C. for a deposition under atmospheric pressure and between 900° C. and 1100° C. under reduced pressure.
  • the reducing atmosphere is obtained by using a mixture of reactive gases in hydrogen (H2).
  • CVD chemical vapor deposition
  • silicon is desired to be deposited on a portion of a single-crystal silicon substrate to form either a substrate doping source, or a contacting area between an underlying layer and the external environment, or to simultaneously ensure both functions. It is then essential that the temperatures involved do not exceed a value on the order of 600° C. to avoid undesirable dopant diffusions.
  • An object of the present invention is to provide a method of deposition at low temperature (lower than 750° C.) of silicon on a single-crystal silicon substrate, such that the deposited silicon has a single-crystal structure.
  • Another object of the present invention is to provide a method of low temperature deposition of silicon on a single-crystal silicon substrate, such that the deposited silicon has a single-crystal structure with crystallographic axes distinct from those of the substrate.
  • Another object of the present invention is to provide a specific application of this method to the manufacturing of emitters of bipolar transistors.
  • the present invention provides a method of deposition of a silicon layer on a single-crystal silicon substrate, so that the silicon layer is a single-crystal layer, but of different orientation than the substrate, including the steps of defining a window on the substrate; creating inside the window interstitial defects with an atomic proportion lower than one for one hundred; and performing a silicon deposition in conditions generally corresponding to those of an epitaxial deposition, but at a temperature lower than 900° C.
  • the deposition temperature ranges between 600° C. and 700° C.
  • the step of defect creation includes an implantation step.
  • the implantation is performed through a silicon oxide layer of a thickness lower than 10 nm and this implantation is followed by a step of removal of the silicon oxide layer.
  • the implantation is an implantation of an electrically neutral element.
  • the implantation is an implantation of an element chosen from the group containing fluorine, silicon, germanium, boron, indium, phosphorus, arsenic, and antimony.
  • the implantation of an electrically neutral element is a fluorine implantation at 12 keV, at 10 13 at./cm 2 .
  • the window opening is reduced to a width lower than 5 ⁇ m, preferably, on the order of 0.35 ⁇ m.
  • the reduction of the width of the window opening is performed by compound spacers.
  • the compound spacers are formed of silicon nitride regions, and of polysilicon spacers.
  • FIGS. 1A, 1B, and 1 C schematically illustrate successive steps of a method according to the present invention
  • FIGS. 2A, 2B, and 2 C illustrate an embodiment of some steps of the method according to the present invention.
  • FIGS. 3A to 3 D show an example of application of the method according to the present invention to the formation of a bipolar transistor emitter.
  • FIG. 1A shows a single-crystal silicon substrate 11 , above which is formed a layer 12 provided with a window 13 , of a width lower than 5 ⁇ m and, preferably, lower than 1 ⁇ m.
  • the aim of the present invention is to develop a single-crystal silicon area extending from the surface of substrate 11 apparent in opening 13 .
  • the surface of the region of layer 11 uncovered by window 13 is processed to create, in uncovered region 14 , interstitial defects in the crystal lattice which is thus slightly locally deformed.
  • the processing is applied to create defects with a proportion of about one atom for one hundred, down to a depth lower than 5 nm. Such a dose is too low to amorphize the silicon which remains single-crystal silicon.
  • any plasma or RIE-type etching, in which ions are directed to the surface to create an anisotropic chemical etch may be used. Any voluntary implantation of ions or neutral atoms will mechanically create interstitial defects. According to the present invention, these defects should, preferably, be located at the surface.
  • the implanters used in microelectronics are preferentially used since they enable a perfect control of the flow and energy of the implanted ions. According to the valence of the implanted atom, in addition to the mechanical effect, creation of interstitial defects, a second electric effect will occur when the added atom will substitute to an existing silicon atom.
  • boron ( 11 B) and indium ( 11 4In) implantations will be performed to provide a P-type doping
  • antimony ( 12 2Sb) implantations will be performed to provide an N-type doping
  • silicon ( 28 Si), germanium ( 7 3Ge), or fluorine ( 19 F) implantations will be performed to remain electrically neutral. Any other massive atom may be used.
  • an upper layer 15 is deposited in conditions close to those of an epitaxial deposition, that is, under a reducing atmosphere but at a temperature lower than the temperature generally used in an epitaxial deposition.
  • the temperature of the deposition according to the present invention typically is in a range between 600 and 700° C., for example, 630° C. under a reduced pressure of about 0.1.10 5 Pa (80 torr), the reactive gas being silane (SiH 4 ).
  • layer 15 In the window opening and substantially vertically thereabove, layer 15 , designated by reference 15 ′, hatched in FIG. 1C, takes a single-crystal structure, like substrate 11 , but along different crystallographic axes than those of substrate 11 . Outside the window, substantially above layer 12 , layer 15 , designated by reference 15 ′′, conventionally takes a polycrystal, or possibly amorphous, structure.
  • FIGS. 2A to 2 C illustrate a specific embodiment of the interstitial defects creation processing.
  • a layer 12 provided with a window 13 is formed above an initial single-crystal silicon substrate 11 .
  • the apparent surface of substrate 11 in window 13 is covered with a silicon oxide layer 16 .
  • Silicon oxide layer 16 which is very thin, of a thickness below 10 nm, is either a native oxide, or a voluntarily formed thermal oxide layer. This sacrificial oxide layer has an important function of cleaning and reorganizing the single-crystal silicon surface.
  • a low dose implantation 14 is then performed through oxide layer 16 . Outside the window, this implantation is masked by layer 12 .
  • oxide layer 16 is removed by wet etching.
  • the substrate structure then is identical to that already described in relation with FIG. 1B.
  • the silicon deposition according to the present invention is performed.
  • the direct contacting of an area of a single-crystal substrate 11 with a single-crystal silicon region 15 ′ of different crystallographic axes than substrate 11 is thus obtained, as previously described in relation with FIG. 1C.
  • Implanted body 14 is characterized by its mass, its energy, and possibly its electric effect.
  • the implantation is performed at low energy and low concentration, to create a defect density, for example, on the order of 10 19 at./cm 3 down to a depth on the order of 10 nm.
  • the applicant has successfully performed silicon, fluorine, and boron ( 11 B) implantations.
  • a fluorine implantation has been performed through a 5-nm oxide layer, under a 10-keV energy, and at a density of 4.10 12 at./cm 2 .
  • Layer 12 shown in FIGS. 1A to 1 C and 2 A to 2 C may be formed of any material currently used in the field of integrated circuit manufacturing, for example, silicon oxide (SiO 2 ) or silicon nitride (Si 3 N 4 ). It could also be a stacking of layers including, for example, one or several insulating layers and, possibly, one or several conductive layers.
  • FIGS. 3A to 3 D illustrate steps of formation of an NPN-type bipolar transistor emitter in a submicronic BICMOS technology developed by the applicant.
  • FIG. 3A shows a bipolar transistor before the formation of the emitter, such as described in U.S. patent application Ser. No. 08/968,598, which application is incorporated herein by reference.
  • the structure includes, in particular:
  • an N-type epitaxial layer 20 is provided.
  • a thick oxide layer 24 defining a base area
  • a P-type for example, boron-doped polysilicon base contact area 25 ;
  • An opening 21 is formed in layers 25 and 26 substantially at the center of the window defined by thick oxide 24 .
  • a thermal oxide 27 covers the lateral wall of polysilicon 25 and the silicon bottom 28 of opening 21 .
  • An extrinsic base region 28 having for example a junction depth on the order of 100 nm results from a diffusion of the dopant (for example, boron) contained in polysilicon layer 25 .
  • An intrinsic base region 29 results from an implantation (for example, of type P) delimited by opening 21 .
  • This intrinsic base is preferably boron implanted at low energy (for example, 2.10 13 atoms/cm 2 under 5 keV).
  • the lateral walls of the opening have been provided with compound spacers formed of silicon nitride regions 22 , and of polysilicon spacers 23 .
  • Nitride 22 and spacers 23 thus altogether define a smaller opening than the opening initially formed in layers 25 and 26 for the definition of intrinsic base 28 .
  • This smaller opening is the emitter opening and has a width lower than 5 ⁇ m, preferably on the order of 0.35 ⁇ m.
  • spacers 23 result from a reactive ionic etching of polysilicon and the opening in the bottom of nitride layer 22 results from a wet chemical etching.
  • the surface of base region 29 is free of defects which could result from a plasma etching of layer 23 .
  • an emitter contact region which could also be used as an emitter doping source is desired to be formed by diffusion in underlying intrinsic base region 29 .
  • this is done by polysilicon CVD.
  • an implantation 34 is performed through oxide layer 27 at the surface of intrinsic base region 29 .
  • Implantation 34 is performed to create interstitial defects, preferably, down to a depth on the order of 10 nm, with an electrically neutral body, in order not to alter the doping of the thin intrinsic base, for example, fluoride, at 12 keV, at 10 13 at./cm 2 , through a 5-nm oxide layer.
  • a silicon layer 35 is deposited according to the present invention.
  • This deposition is performed in the conditions generally used for an epitaxial deposition in a reducing atmosphere, for example, from a mixture of hydrogen and silane (SiH4), but at a temperature on the order of 650° C., and thus lower than the usual temperature of an epitaxy.
  • Layer 35 thus formed will exhibit in the opening, and substantially vertically thereabove, a single-crystal structure, but having different axes than the single-crystal structure of intrinsic base 29 .
  • a high doping for example, of type N
  • this layer 35 for example, from arsine AsH 3
  • An advantage of the present invention is that a single-crystal emitter is perfectly reproducible and has well determined characteristics, contrary to a conventional polycrystal emitter. Indeed, two polycrystal structures never are perfectly identical, which results in variations of operating characteristics from one transistor to another.
  • a conventional emitter that is, a polycrystal emitter
  • recombinations of minority carriers which decrease the gain of the device occur, upon operation of the transistor comprising this emitter.
  • Such recombinations are no longer possible, or are reduced, in the case of the single-crystal emitter according to the present invention in which the recombinations are located at the level of the grain boundary and of the metallization formed on the emitter contact recovery single-crystal silicon layer.
  • the base current characteristics according to the present invention are improved, and thus the gain of the associated transistor is increased.
  • Incoherent interfaces used to increase the emitter resistance, which would reduce the maximum possible current in the associated transistor and create parasitic passive elements.
  • Another advantage of the present invention is to make the base current relatively insensitive to the surface of the emitter-base interface and relatively insensitive to the emitter volume, the only element recombining minority carriers in this volume being the majority carriers and no longer the grain boundaries.
  • the base current will mainly depend on the only remaining recombining element: the surface of the metal contact.
  • Another advantage of the present invention is that the current injected by the emitter always is proportional to the emitter. Accordingly, the gain of the associated transistor can be adjusted according to the ratio between the contact surface and the emitter-base surface.
  • the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art, as concerns its implementation and its applications. It may in particular be applied to integrated circuit structures. Further, it enables definition of an area perfectly delimited at the top and on the sides by dielectrics, and at the bottom by a potential barrier.
  • the properties of this “box” and of the underlying monatomic interface are usable in many fields other than bipolar transistors. In particular, this principle may be applied to sensors, since the interface is very clean, to the manufacturing of fast diodes, to the modification of energy band structures in a limited field, by bringing down to a few nanometers the thickness of the upper layer deposition (15 or 35 in the above examples). By means of the present invention, supernetworks only made of silicon also become implementable.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

The present invention relates to a method of deposition of a silicon layer on a single-crystal silicon substrate, so that the silicon layer is a single-crystal layer, but of different orientation than the substrate, including the steps of defining a window on the substrate; creating inside the window interstitial defects with an atomic proportion lower than one for one hundred; and performing a silicon deposition in conditions generally corresponding to those of an epitaxial deposition, but at a temperature lower than 850° C.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of application Ser. No. 09/884,900, filed Jun. 19, 2001, which in turn is a continuation of application Ser. No. 09/703,266, filed Oct. 31, 2000, which in turn is a continuation of application Ser. No. 09/237,378, filed Jan. 26, 1999, entitled METHOD OF DEPOSITION OF A SINGLE-CRYSTAL SILICON REGION, which prior application is incorporated herein by reference.[0001]
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0002]
  • The present invention generally relates to the manufacturing of semiconductor devices. [0003]
  • 2. Discussion of the Related Art [0004]
  • In many semiconductor component manufacturing processes, silicon has to be deposited on a single-crystal silicon substrate, or on an area of this substrate. Several techniques are currently used. [0005]
  • A first, so-called epitaxial, type of deposition is performed under a reducing atmosphere and enables the crystal structure of the deposited layer to be in crystalline continuity with the substrate. These techniques require a deposition at high temperature, typically ranging between 1000° C. and 1200° C. for a deposition under atmospheric pressure and between 900° C. and 1100° C. under reduced pressure. The reducing atmosphere is obtained by using a mixture of reactive gases in hydrogen (H2). [0006]
  • Techniques, such as chemical vapor deposition (CVD), which enable silicon depositions at low temperature (500° C. to 700° C.) are also known. With these techniques, the deposited silicon is polycrystalline, or amorphous. More precisely, the size of the polysilicon grains decreases with temperature. At low pressure and at 550° C., the deposited silicon is amorphous. [0007]
  • In many cases, at the end of the manufacturing process of an integrated circuit, silicon is desired to be deposited on a portion of a single-crystal silicon substrate to form either a substrate doping source, or a contacting area between an underlying layer and the external environment, or to simultaneously ensure both functions. It is then essential that the temperatures involved do not exceed a value on the order of 600° C. to avoid undesirable dopant diffusions. [0008]
    • SUMMARY OF THE INVENTION
  • An object of the present invention is to provide a method of deposition at low temperature (lower than 750° C.) of silicon on a single-crystal silicon substrate, such that the deposited silicon has a single-crystal structure. [0009]
  • Another object of the present invention is to provide a method of low temperature deposition of silicon on a single-crystal silicon substrate, such that the deposited silicon has a single-crystal structure with crystallographic axes distinct from those of the substrate. [0010]
  • Another object of the present invention is to provide a specific application of this method to the manufacturing of emitters of bipolar transistors. [0011]
  • To achieve these and other objects, the present invention provides a method of deposition of a silicon layer on a single-crystal silicon substrate, so that the silicon layer is a single-crystal layer, but of different orientation than the substrate, including the steps of defining a window on the substrate; creating inside the window interstitial defects with an atomic proportion lower than one for one hundred; and performing a silicon deposition in conditions generally corresponding to those of an epitaxial deposition, but at a temperature lower than 900° C. [0012]
  • According to an embodiment of the present invention, the deposition temperature ranges between 600° C. and 700° C. [0013]
  • According to an embodiment of the present invention, the step of defect creation includes an implantation step. [0014]
  • According to an embodiment of the present invention, the implantation is performed through a silicon oxide layer of a thickness lower than 10 nm and this implantation is followed by a step of removal of the silicon oxide layer. [0015]
  • According to an embodiment of the present invention, the implantation is an implantation of an electrically neutral element. [0016]
  • According to an embodiment of the present invention, the implantation is an implantation of an element chosen from the group containing fluorine, silicon, germanium, boron, indium, phosphorus, arsenic, and antimony. [0017]
  • According to an embodiment of the present invention, the implantation of an electrically neutral element is a fluorine implantation at 12 keV, at 10[0018] 13 at./cm2.
  • According to an embodiment of the present invention, the window opening is reduced to a width lower than 5 μm, preferably, on the order of 0.35 μm. [0019]
  • According to an embodiment of the present invention, the reduction of the width of the window opening is performed by compound spacers. [0020]
  • According to an embodiment of the present invention, the compound spacers are formed of silicon nitride regions, and of polysilicon spacers. [0021]
  • The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.[0022]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1A, 1B, and [0023] 1C schematically illustrate successive steps of a method according to the present invention;
  • FIGS. 2A, 2B, and [0024] 2C illustrate an embodiment of some steps of the method according to the present invention; and
  • FIGS. 3A to [0025] 3D show an example of application of the method according to the present invention to the formation of a bipolar transistor emitter.
    • DETAILED DESCRIPTION
  • FIG. 1A shows a single-[0026] crystal silicon substrate 11, above which is formed a layer 12 provided with a window 13, of a width lower than 5 μm and, preferably, lower than 1 μm. The aim of the present invention is to develop a single-crystal silicon area extending from the surface of substrate 11 apparent in opening 13.
  • As shown in FIG. 1B, the surface of the region of [0027] layer 11 uncovered by window 13 is processed to create, in uncovered region 14, interstitial defects in the crystal lattice which is thus slightly locally deformed. The processing is applied to create defects with a proportion of about one atom for one hundred, down to a depth lower than 5 nm. Such a dose is too low to amorphize the silicon which remains single-crystal silicon. In particular, any plasma or RIE-type etching, in which ions are directed to the surface to create an anisotropic chemical etch, may be used. Any voluntary implantation of ions or neutral atoms will mechanically create interstitial defects. According to the present invention, these defects should, preferably, be located at the surface. For this reason, it is now preferred to use charged particles rather than neutral atoms. The implanters used in microelectronics are preferentially used since they enable a perfect control of the flow and energy of the implanted ions. According to the valence of the implanted atom, in addition to the mechanical effect, creation of interstitial defects, a second electric effect will occur when the added atom will substitute to an existing silicon atom. In practice, boron (11B) and indium (114In) implantations will be performed to provide a P-type doping, phosphorus (31P), arsenic (75As), or antimony (122Sb) implantations will be performed to provide an N-type doping, or silicon (28Si), germanium (73Ge), or fluorine (19F) implantations will be performed to remain electrically neutral. Any other massive atom may be used.
  • As shown in FIG. 1C, immediately after this processing, and without providing any anneal step, an [0028] upper layer 15 is deposited in conditions close to those of an epitaxial deposition, that is, under a reducing atmosphere but at a temperature lower than the temperature generally used in an epitaxial deposition. The temperature of the deposition according to the present invention typically is in a range between 600 and 700° C., for example, 630° C. under a reduced pressure of about 0.1.105 Pa (80 torr), the reactive gas being silane (SiH4).
  • In the window opening and substantially vertically thereabove, [0029] layer 15, designated by reference 15′, hatched in FIG. 1C, takes a single-crystal structure, like substrate 11, but along different crystallographic axes than those of substrate 11. Outside the window, substantially above layer 12, layer 15, designated by reference 15″, conventionally takes a polycrystal, or possibly amorphous, structure.
  • The contacting of an area of a single-[0030] crystal substrate 11 with a single-crystal silicon region 15′ having different crystallographic axes than substrate 11 is thus obtained.
  • FIGS. 2A to [0031] 2C illustrate a specific embodiment of the interstitial defects creation processing. A layer 12 provided with a window 13 is formed above an initial single-crystal silicon substrate 11. The apparent surface of substrate 11 in window 13 is covered with a silicon oxide layer 16. Silicon oxide layer 16, which is very thin, of a thickness below 10 nm, is either a native oxide, or a voluntarily formed thermal oxide layer. This sacrificial oxide layer has an important function of cleaning and reorganizing the single-crystal silicon surface.
  • As illustrated in FIG. 2B, a [0032] low dose implantation 14 is then performed through oxide layer 16. Outside the window, this implantation is masked by layer 12.
  • At the following step shown in FIG. 2C, [0033] oxide layer 16 is removed by wet etching. The substrate structure then is identical to that already described in relation with FIG. 1B.
  • Then, without performing any previous anneal, the silicon deposition according to the present invention is performed. The direct contacting of an area of a single-[0034] crystal substrate 11 with a single-crystal silicon region 15′ of different crystallographic axes than substrate 11 is thus obtained, as previously described in relation with FIG. 1C.
  • Implanted [0035] body 14 is characterized by its mass, its energy, and possibly its electric effect. The implantation is performed at low energy and low concentration, to create a defect density, for example, on the order of 1019 at./cm3 down to a depth on the order of 10 nm. As an example, the applicant has successfully performed silicon, fluorine, and boron (11B) implantations. For example, a fluorine implantation has been performed through a 5-nm oxide layer, under a 10-keV energy, and at a density of 4.1012 at./cm2.
  • [0036] Layer 12 shown in FIGS. 1A to 1C and 2A to 2C may be formed of any material currently used in the field of integrated circuit manufacturing, for example, silicon oxide (SiO2) or silicon nitride (Si3N4). It could also be a stacking of layers including, for example, one or several insulating layers and, possibly, one or several conductive layers.
  • As an example only, and without this forming a limitation of the present invention, for which those skilled in the art may provide many other applications, a specific application of the present invention to the formation of a bipolar transistor emitter will be described hereafter. [0037]
  • FIGS. 3A to [0038] 3D illustrate steps of formation of an NPN-type bipolar transistor emitter in a submicronic BICMOS technology developed by the applicant.
  • FIG. 3A shows a bipolar transistor before the formation of the emitter, such as described in U.S. patent application Ser. No. 08/968,598, which application is incorporated herein by reference. Before the emitter is formed, the structure includes, in particular: [0039]
  • an N-[0040] type epitaxial layer 20;
  • a [0041] thick oxide layer 24 defining a base area;
  • a P-type, for example, boron-doped polysilicon [0042] base contact area 25; and
  • an [0043] encapsulation oxide layer 26.
  • An [0044] opening 21 is formed in layers 25 and 26 substantially at the center of the window defined by thick oxide 24.
  • A [0045] thermal oxide 27 covers the lateral wall of polysilicon 25 and the silicon bottom 28 of opening 21. An extrinsic base region 28 having for example a junction depth on the order of 100 nm results from a diffusion of the dopant (for example, boron) contained in polysilicon layer 25. An intrinsic base region 29 results from an implantation (for example, of type P) delimited by opening 21. This intrinsic base is preferably boron implanted at low energy (for example, 2.1013 atoms/cm2 under 5 keV).
  • Then, the lateral walls of the opening have been provided with compound spacers formed of [0046] silicon nitride regions 22, and of polysilicon spacers 23. Nitride 22 and spacers 23 thus altogether define a smaller opening than the opening initially formed in layers 25 and 26 for the definition of intrinsic base 28. This smaller opening is the emitter opening and has a width lower than 5 μm, preferably on the order of 0.35 μm. Preferably, spacers 23 result from a reactive ionic etching of polysilicon and the opening in the bottom of nitride layer 22 results from a wet chemical etching. As a result, the surface of base region 29 is free of defects which could result from a plasma etching of layer 23.
  • From this structure, an emitter contact region which could also be used as an emitter doping source is desired to be formed by diffusion in underlying [0047] intrinsic base region 29. In the above-mentioned patent application, this is done by polysilicon CVD.
  • According to the present invention, as illustrated in FIG. 3B, an [0048] implantation 34 is performed through oxide layer 27 at the surface of intrinsic base region 29. Implantation 34 is performed to create interstitial defects, preferably, down to a depth on the order of 10 nm, with an electrically neutral body, in order not to alter the doping of the thin intrinsic base, for example, fluoride, at 12 keV, at 1013 at./cm2, through a 5-nm oxide layer.
  • At the following step, shown in FIG. 3C, without any intermediary anneal step, the region of [0049] oxide layer 27 which is apparent at the bottom of the opening is carefully cleaned, for example in a diluted hydrofluoric acid bath.
  • At the following step, shown in FIG. 3D, a [0050] silicon layer 35 is deposited according to the present invention. This deposition is performed in the conditions generally used for an epitaxial deposition in a reducing atmosphere, for example, from a mixture of hydrogen and silane (SiH4), but at a temperature on the order of 650° C., and thus lower than the usual temperature of an epitaxy. Layer 35 thus formed will exhibit in the opening, and substantially vertically thereabove, a single-crystal structure, but having different axes than the single-crystal structure of intrinsic base 29. Further, since the deposition is performed in an epitaxy reactor, a high doping (for example, of type N) of this layer 35 (for example, from arsine AsH3) can be simultaneously performed.
  • The application of the method according to the present invention results in a single-crystal [0051] emitter contact layer 35 on a single-crystal base layer. The interface between these layers of different crystallographic axes thus exhibits a single grain boundary.
  • Measurements performed by transmission microscopy that enable visualization of the atoms, and thus, the crystal structure, have shown that the area disturbed at the level of the grain boundary extends over a thickness of less than 3 to 5 atomic layers. [0052]
  • An advantage of the present invention is that a single-crystal emitter is perfectly reproducible and has well determined characteristics, contrary to a conventional polycrystal emitter. Indeed, two polycrystal structures never are perfectly identical, which results in variations of operating characteristics from one transistor to another. [0053]
  • In the presence of a conventional incoherent interface between a single-crystal base region and a polycrystal emitter contact layer, a “dopant pumping”, that is, an undesirable local concentration of the dopants of the underlying layer, appears and modifies the doping of the base region. The coherent interface of the method according to the present invention eliminates this problem. [0054]
  • Prior incoherent interfaces used to generate random noise due to the uncontrollability of the structure of the associated incoherent grain boundaries. This noise no longer appears in the case of the coherent interface of the method according to the present invention. [0055]
  • In a conventional emitter, that is, a polycrystal emitter, recombinations of minority carriers (holes, in the case of an NPN transistor) which decrease the gain of the device occur, upon operation of the transistor comprising this emitter. Such recombinations are no longer possible, or are reduced, in the case of the single-crystal emitter according to the present invention in which the recombinations are located at the level of the grain boundary and of the metallization formed on the emitter contact recovery single-crystal silicon layer. As a result, the base current characteristics according to the present invention are improved, and thus the gain of the associated transistor is increased. [0056]
  • Incoherent interfaces used to increase the emitter resistance, which would reduce the maximum possible current in the associated transistor and create parasitic passive elements. [0057]
  • Another advantage of the present invention is to make the base current relatively insensitive to the surface of the emitter-base interface and relatively insensitive to the emitter volume, the only element recombining minority carriers in this volume being the majority carriers and no longer the grain boundaries. Thus, according to the doping conditions, the base current will mainly depend on the only remaining recombining element: the surface of the metal contact. [0058]
  • Another advantage of the present invention is that the current injected by the emitter always is proportional to the emitter. Accordingly, the gain of the associated transistor can be adjusted according to the ratio between the contact surface and the emitter-base surface. [0059]
  • The present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art, as concerns its implementation and its applications. It may in particular be applied to integrated circuit structures. Further, it enables definition of an area perfectly delimited at the top and on the sides by dielectrics, and at the bottom by a potential barrier. The properties of this “box” and of the underlying monatomic interface are usable in many fields other than bipolar transistors. In particular, this principle may be applied to sensors, since the interface is very clean, to the manufacturing of fast diodes, to the modification of energy band structures in a limited field, by bringing down to a few nanometers the thickness of the upper layer deposition (15 or 35 in the above examples). By means of the present invention, supernetworks only made of silicon also become implementable. [0060]
  • Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.[0061]

Claims (10)

What is claimed is:
1. A method of deposition of a silicon layer on a single-crystal silicon substrate, so that the silicon layer is a single-crystal layer, but of different orientation than the substrate, including the steps of:
defining a window on the substrate;
creating inside the window interstitial defects with an atomic proportion lower than one for one hundred; and
performing a silicon deposition in conditions generally corresponding to those of an epitaxial deposition, but at a temperature lower than 900° C.
2. The method of claim 1, wherein the deposition temperature ranges between 600° C. and 700° C.
3. The method of claim 2, wherein the step of defect creation includes an implantation step.
4. The method of claim 3, wherein the implantation is performed through a silicon oxide layer of a thickness lower than 10 nm and wherein this implantation is followed by a step of removal of the silicon oxide layer.
5. The method of claim 3, wherein the implantation is an implantation of an electrically neutral element.
6. The method of claim 3, wherein the implantation is an implantation of an element chosen from the group containing fluorine, silicon, germanium, boron, indium, phosphorus, arsenic, and antimony.
7. The method of claim 6, wherein the implantation of an electrically neutral element is a fluorine implantation at 12 keV, at 1013 at./cm2.
8. The method of claim 1, wherein the window opening has a width lower than 5 μm, preferably, on the order of 0.35 μm.
9. The method of claim 8, wherein the width of the window opening is reduced by compound spacers.
10. The method of claim 9, wherein the compound spacers comprise silicon nitride regions, and polysilicon spacers.
US09/988,233 1998-01-30 2001-11-19 Method of deposition of a single-crystal silicon region Abandoned US20020053316A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/988,233 US20020053316A1 (en) 1998-01-30 2001-11-19 Method of deposition of a single-crystal silicon region

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
FR9801313A FR2774509B1 (en) 1998-01-30 1998-01-30 METHOD FOR DEPOSITING A REGION OF SINGLE CRYSTAL SILICON
FR98/01313 1998-01-30
US09/237,378 US6165265A (en) 1998-01-30 1999-01-26 Method of deposition of a single-crystal silicon region
US70326600A 2000-10-31 2000-10-31
US88490001A 2001-06-19 2001-06-19
US09/988,233 US20020053316A1 (en) 1998-01-30 2001-11-19 Method of deposition of a single-crystal silicon region

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US88490001A Continuation 1998-01-30 2001-06-19

Publications (1)

Publication Number Publication Date
US20020053316A1 true US20020053316A1 (en) 2002-05-09

Family

ID=9522603

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/237,378 Expired - Lifetime US6165265A (en) 1998-01-30 1999-01-26 Method of deposition of a single-crystal silicon region
US09/988,233 Abandoned US20020053316A1 (en) 1998-01-30 2001-11-19 Method of deposition of a single-crystal silicon region

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/237,378 Expired - Lifetime US6165265A (en) 1998-01-30 1999-01-26 Method of deposition of a single-crystal silicon region

Country Status (4)

Country Link
US (2) US6165265A (en)
EP (1) EP0933801A1 (en)
JP (1) JPH11274171A (en)
FR (1) FR2774509B1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090065820A1 (en) * 2007-09-06 2009-03-12 Lu-Yang Kao Method and structure for simultaneously fabricating selective film and spacer
US20100148271A1 (en) * 2008-12-17 2010-06-17 Chien-Liang Lin Method for gate leakage reduction and Vt shift control and complementary metal-oxide-semiconductor device
CN103145883A (en) * 2013-03-19 2013-06-12 中国海洋石油总公司 Experimental instrument for photo-initiated solution polymerization
CN105609406A (en) * 2014-11-19 2016-05-25 株式会社日立国际电气 Semiconductor device manufacturing method, substrate processing apparatus, gas supply system, three-dimensional flash memory, dynamic random access memory and semiconductor device
TWI672800B (en) * 2014-11-19 2019-09-21 日商國際電氣股份有限公司 Semiconductor device manufacturing method, substrate processing device, gas supply system, and recording medium

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1296361A1 (en) 2001-09-13 2003-03-26 STMicroelectronics S.r.l. A process of forming an interface free layer of silicon on a substrate of monocrystalline silicon
CN100358110C (en) * 2002-12-20 2007-12-26 皇家飞利浦电子股份有限公司 Method of manufacturing a semiconductor device
JP4643130B2 (en) * 2003-06-19 2011-03-02 株式会社日立製作所 Semiconductor device and manufacturing method thereof

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3897625A (en) * 1973-03-30 1975-08-05 Siemens Ag Method for the production of field effect transistors by the application of selective gettering
US4469527A (en) * 1981-06-19 1984-09-04 Tokyo University Method of making semiconductor MOSFET device by bombarding with radiation followed by beam-annealing
US4515755A (en) * 1981-05-11 1985-05-07 Toshiba Ceramics Co., Ltd. Apparatus for producing a silicon single crystal from a silicon melt
US4584026A (en) * 1984-07-25 1986-04-22 Rca Corporation Ion-implantation of phosphorus, arsenic or boron by pre-amorphizing with fluorine ions
US4637127A (en) * 1981-07-07 1987-01-20 Nippon Electric Co., Ltd. Method for manufacturing a semiconductor device
US5011789A (en) * 1985-09-06 1991-04-30 U.S. Philips Corporation Method of manufacturing a semiconductor device
US5024723A (en) * 1990-05-07 1991-06-18 Goesele Ulrich M Method of producing a thin silicon on insulator layer by wafer bonding and chemical thinning
US5221412A (en) * 1989-09-26 1993-06-22 Toagosei Chemical Industry Co., Ltd. Vapor-phase epitaxial growth process by a hydrogen pretreatment step followed by decomposition of disilane to form monocrystalline Si film
US5378651A (en) * 1991-10-31 1995-01-03 International Business Machines Corporation Comprehensive process for low temperature epitaxial growth
US5441901A (en) * 1993-10-05 1995-08-15 Motorola, Inc. Method for forming a carbon doped silicon semiconductor device having a narrowed bandgap characteristic
US5561076A (en) * 1992-04-02 1996-10-01 Nec Corporation Method of fabricating an isolation region for a semiconductor device using liquid phase deposition
US5734195A (en) * 1993-03-30 1998-03-31 Sony Corporation Semiconductor wafer for epitaxially grown devices having a sub-surface getter region
US5821158A (en) * 1995-08-28 1998-10-13 Nec Corporation Substrate surface treatment method capable of removing a spontaneous oxide film at a relatively low temperature

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0249019B2 (en) * 1982-01-29 1990-10-26 Fujitsu Ltd HANDOTAISOCHINOSEIZOHOHO
JPS6292364A (en) * 1985-10-18 1987-04-27 Fuji Photo Film Co Ltd Semiconductor device and manufacture thereof
JP2706441B2 (en) * 1986-02-18 1998-01-28 松下電子工業株式会社 Method of manufacturing complementary MIS integrated circuit
JPH01223765A (en) * 1988-03-02 1989-09-06 Nec Corp Manufacture of semiconductor device
US5010034A (en) * 1989-03-07 1991-04-23 National Semiconductor Corporation CMOS and bipolar fabrication process using selective epitaxial growth scalable to below 0.5 micron
JPH05175209A (en) * 1991-12-26 1993-07-13 Toshiba Corp Semiconductor device and its manufacture
JPH05217916A (en) * 1992-01-31 1993-08-27 Nec Corp Manufacture of semiconductor device
JPH06260427A (en) * 1993-03-05 1994-09-16 Nec Corp Selective growth method of semiconductor film
US5554561A (en) * 1993-04-30 1996-09-10 Texas Instruments Incorporated Epitaxial overgrowth method
JPH0794521A (en) * 1993-09-20 1995-04-07 Toshiba Corp Bipolar transistor
JPH07176742A (en) * 1993-12-20 1995-07-14 Nec Corp Manufacture of semiconductor device and semiconductor device
KR0158065B1 (en) * 1995-05-29 1998-12-01 스기야마 가즈히코 Semiconductor integrated circuit and its manufacture
JP2836576B2 (en) * 1996-05-15 1998-12-14 日本電気株式会社 Method for manufacturing semiconductor device

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3897625A (en) * 1973-03-30 1975-08-05 Siemens Ag Method for the production of field effect transistors by the application of selective gettering
US4515755A (en) * 1981-05-11 1985-05-07 Toshiba Ceramics Co., Ltd. Apparatus for producing a silicon single crystal from a silicon melt
US4469527A (en) * 1981-06-19 1984-09-04 Tokyo University Method of making semiconductor MOSFET device by bombarding with radiation followed by beam-annealing
US4637127A (en) * 1981-07-07 1987-01-20 Nippon Electric Co., Ltd. Method for manufacturing a semiconductor device
US4584026A (en) * 1984-07-25 1986-04-22 Rca Corporation Ion-implantation of phosphorus, arsenic or boron by pre-amorphizing with fluorine ions
US5011789A (en) * 1985-09-06 1991-04-30 U.S. Philips Corporation Method of manufacturing a semiconductor device
US5221412A (en) * 1989-09-26 1993-06-22 Toagosei Chemical Industry Co., Ltd. Vapor-phase epitaxial growth process by a hydrogen pretreatment step followed by decomposition of disilane to form monocrystalline Si film
US5024723A (en) * 1990-05-07 1991-06-18 Goesele Ulrich M Method of producing a thin silicon on insulator layer by wafer bonding and chemical thinning
US5378651A (en) * 1991-10-31 1995-01-03 International Business Machines Corporation Comprehensive process for low temperature epitaxial growth
US5561076A (en) * 1992-04-02 1996-10-01 Nec Corporation Method of fabricating an isolation region for a semiconductor device using liquid phase deposition
US5734195A (en) * 1993-03-30 1998-03-31 Sony Corporation Semiconductor wafer for epitaxially grown devices having a sub-surface getter region
US5441901A (en) * 1993-10-05 1995-08-15 Motorola, Inc. Method for forming a carbon doped silicon semiconductor device having a narrowed bandgap characteristic
US5821158A (en) * 1995-08-28 1998-10-13 Nec Corporation Substrate surface treatment method capable of removing a spontaneous oxide film at a relatively low temperature

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090065820A1 (en) * 2007-09-06 2009-03-12 Lu-Yang Kao Method and structure for simultaneously fabricating selective film and spacer
US20100148271A1 (en) * 2008-12-17 2010-06-17 Chien-Liang Lin Method for gate leakage reduction and Vt shift control and complementary metal-oxide-semiconductor device
US8232605B2 (en) 2008-12-17 2012-07-31 United Microelectronics Corp. Method for gate leakage reduction and Vt shift control and complementary metal-oxide-semiconductor device
CN103145883A (en) * 2013-03-19 2013-06-12 中国海洋石油总公司 Experimental instrument for photo-initiated solution polymerization
CN105609406A (en) * 2014-11-19 2016-05-25 株式会社日立国际电气 Semiconductor device manufacturing method, substrate processing apparatus, gas supply system, three-dimensional flash memory, dynamic random access memory and semiconductor device
US9691609B2 (en) 2014-11-19 2017-06-27 Hitachi Kokusai Electric Inc. Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
US9941119B2 (en) 2014-11-19 2018-04-10 Hitachi Kokusai Electric Inc. Method of forming silicon layer in manufacturing semiconductor device and recording medium
TWI672800B (en) * 2014-11-19 2019-09-21 日商國際電氣股份有限公司 Semiconductor device manufacturing method, substrate processing device, gas supply system, and recording medium

Also Published As

Publication number Publication date
JPH11274171A (en) 1999-10-08
US6165265A (en) 2000-12-26
FR2774509A1 (en) 1999-08-06
EP0933801A1 (en) 1999-08-04
FR2774509B1 (en) 2001-11-16

Similar Documents

Publication Publication Date Title
JP4414895B2 (en) Method for the fabrication of bipolar transistors with improved base-emitter junctions
US6316818B1 (en) Vertical bipolar transistor including an extrinsic base with reduced roughness, and fabrication process
US4717681A (en) Method of making a heterojunction bipolar transistor with SIPOS
US6265275B1 (en) Method of selectively doping the intrinsic collector of a vertical bipolar transistor with epitaxial base
EP0552671A2 (en) Isolation technique for silicon germanium devices
US20030157787A1 (en) Method of forming a germanium film on a semiconductor substrate that includes the formation of a graded silicon-germanium buffer layer prior to the formation of a germanium layer
JP2000031155A (en) Low noise vertical bipolar transistor and fabrication thereof
JPH04230037A (en) Vapor application method of n-type silicon layer, npn transistor
US6580104B1 (en) Elimination of contaminants prior to epitaxy and related structure
US9484430B2 (en) Back-end transistors with highly doped low-temperature contacts
US6551891B1 (en) Process for fabricating a self-aligned vertical bipolar transistor
JPH0785476B2 (en) Emitter-embedded bipolar transistor structure
JP3545503B2 (en) Method for manufacturing semiconductor integrated circuit device
US20060163625A1 (en) Semiconductor layer and forming method thereof, and semiconductor device and manufacturing method thereof technical field
US6165265A (en) Method of deposition of a single-crystal silicon region
US7719031B2 (en) Heterojunction biploar transistor and method for manufacturing same
JP2705344B2 (en) Semiconductor device and manufacturing method thereof
US6706583B1 (en) High speed low noise transistor
US8102052B2 (en) Process for the simultaneous deposition of crystalline and amorphous layers with doping
US6445043B1 (en) Isolated regions in an integrated circuit
JP3493175B2 (en) Manufacturing method of vertical bipolar transistor
GB2137019A (en) Semiconductor Device and Method for Manufacturing
JP2701793B2 (en) Method for manufacturing semiconductor device
JP3255423B2 (en) Method for forming germanium layer
JP2828127B2 (en) Selective polycrystalline silicon film growth method

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION