US20020058462A1 - Chemical mechanical polishing of dielectric materials - Google Patents
Chemical mechanical polishing of dielectric materials Download PDFInfo
- Publication number
- US20020058462A1 US20020058462A1 US09/963,317 US96331701A US2002058462A1 US 20020058462 A1 US20020058462 A1 US 20020058462A1 US 96331701 A US96331701 A US 96331701A US 2002058462 A1 US2002058462 A1 US 2002058462A1
- Authority
- US
- United States
- Prior art keywords
- dielectric layer
- planarity
- successive
- polishing
- topology
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31633—Deposition of carbon doped silicon oxide, e.g. SiOC
Definitions
- the invention relates to planarization of a semiconductor wafer to minimize cumulative non-planarity, caused by a topology of non-planar features on successive layers of the wafer being stacked one on another.
- a semiconductor wafer is provided with a dielectric layer having a damascene topology of surface imbedded, circuit interconnects, which are fabricated, for example, by a known damascene process.
- Each semiconductor wafer must have a smooth planar polished surface, which provides a base on which is to be fabricated, one or more than one, successive layers, each having imbedded circuit interconnections.
- the damascene topology contributes to a topology of non-planar features on the polished surface.
- Polishing by chemical mechanical planarization is known for polishing a semiconductor wafer to remove a top layer of excess metallization, which leaves behind metal in trenches to provide the circuit interconnections.
- a desired result of a CMP polishing operation is to provide a smooth planar polished surface that extends over the dielectric layer and the metal in trenches.
- CMP polishing leaves behind imperfections in the surface of a polished wafer. For example, CMP polishing leaves behind recessed dishing of the metal in the trenches. In the event that CMP polishing is allowed to continue for an extended duration, recessed erosion of the dielectric layer will occur from excessive polishing or overpolishing.
- the topology of non-planar features comprises, dishing of the metal in trenches, and further comprises, erosion of the dielectric layer, as caused by the polishing operation.
- Each successive dielectric layer with applied metallization is similarly polished by CMP, leaving behind a topology of non-planar features on each successive polished layer.
- a method for minimizing cumulative non-planarity caused by successive layers on a semiconductor wafer.
- An embodiment of the method includes the steps of;
- polishing a semiconductor wafer to remove excess metallization from the surface of an underlying dielectric layer, leaving the underlying dielectric layer with a topology of non-planarity features
- polishing the successive dielectric layer to provide on the successive dielectric layer a smooth planar polished surface that minimizes non-planarity due to the topology of non-planarity features on the underlying dielectric layer.
- An advantage of the invention resides in a method that provides a semiconductor wafer having a smooth planar polished surface on a dielectric layer that is without damascene topology, which minimizes variations in planarity due to the topology of non-planarity features on the underlying dielectric layer
- a semiconductor wafer comprises, an underlying dielectric layer with imbedded metallization providing circuit interconnections, the underlying dielectric layer having non-planarity features at its surface due to damascene topology, and a successive dielectric layer that is without damascene topology overlying the first dielectric layer, the successive dielectric layer having a smooth polished planar surface that minimizes cumulative non-planarity.
- FIG. 1 is a fragmentary enlarged view of a portion of a semiconductor wafer with an exemplary underlying dielectric layer and a layer of metallization;
- FIG. 2 is a view similar to FIG. 1, and discloses the wafer after a first step polishing operation
- FIG. 3 is a view similar to FIG. 2, and discloses the wafer after a second step polishing operation, having a topology of non-planar features, and a successive dielectric layer provided with a smooth planar polished surface that minimizes cumulative non-planarity;
- FIG. 4 is a view similar to FIG. 3, and discloses a successive dielectric layer and a thicker dielectric layer provided with a smooth planar polished surface that minimizes cumulative non-planarity.
- FIG. 1 discloses a semiconductor wafer 1 having a thinly sliced, silicon substrate 2 , on which is applied an underlying dielectric layer 3 having one of multiple trenches 4 in which metal 5 is imbedded to provide surface imbedded circuit interconnections. Further, the wafer 1 comprises, a thin barrier film 6 covering the underlying dielectric layer 3 .
- the underlying dielectric layer 3 is any one of a number of underlying dielectric layers with trenches 4 that are to be covered by a successive layer on the wafer 1 .
- FIG. 1 discloses the underlying dielectric layer 3 as being the first underlying dielectric layer on the wafer 1 .
- the underlying dielectric layer 3 has a surface to be used as a base on which multilevel layers are to be fabricated.
- the metal filled trenches 4 in the underlying dielectric layer 3 comprise a damascene topology.
- the thin barrier film 6 is between the metal 5 in the trenches 4 and the underlying dielectric layer 3 .
- the barrier film 6 provides a barrier to migration of the metal into the underlying dielectric layer 3 .
- Fabrication by a known damascene process includes, the barrier film 6 being deposited, for example, by chemical vapor deposition, to cover the surface of the underlying dielectric layer 3 , including each trench 4 .
- the barrier film 6 covering the underlying dielectric layer 3 of SiO 2 comprises, tantalum, meaning elemental Tantalum and/or a tantalum compound including tantalum nitride, or, alternatively, the barrier film 6 comprises, an silicon carbide, SiC, based material applied by chemical vapor deposition over an underlying dielectric layer 3 of organosilicate glass.
- Metallization 7 for example, copper metallization, is applied over the underlying barrier film 6 to fill each of the trenches 4 of the underlying dielectric layer 3 with metal 5 .
- the metallization 7 is applied as a thin film by chemical vapor deposition, followed by a thicker amount applied by a known electroplating process.
- the metallization 7 further comprises excess metallization covering the surface of the dielectric layer 3 .
- a first step polishing operation is performed to remove the copper metallization 7 to the level of the underlying barrier film 6 .
- the wafer 1 is polished according to a known CMP polishing system.
- the CMP polishing system operates to move the wafer 1 against a moving polishing pad of the known CMP polishing system, and uses a combination of the moving polishing pad with polishing fluid at an interface with the wafer 1 being polished, to remove the metallization 7 by polishing friction and chemical reaction of the metallization 7 to the polishing fluid.
- the wafer 1 disclosed in FIG. 2 was subjected to a first step CMP polishing operation that polishes the barrier film 6 to a planar surface, and that polishes the metal 5 in each trench 4 to the same height as that of the barrier film 6 .
- some of the metal 5 in each trench 4 is removed during polishing, by chemical reaction to the polishing fluid and by polishing friction, which causes concave dishing 8 of the metal 5 in each dished trench 4 .
- Dishing 8 of the damascene topology undesirably provides non-planarity features that contribute to variations in planarity of the wafer 1 .
- FIG. 1 As disclosed by FIG.
- CMP polishing of the surface of the wafer 1 accomplishes removal of the surface layer of copper metallization 7 to expose the surface of the barrier film 6 , and to leave metal 5 in the trenches 4 .
- FIG. 2 further discloses recessed dishing 8 of the metal 5 in each trench 4 that results from the first step polishing operation.
- the first step polishing operation is followed by a second step polishing operation.
- the second step polishing operation removes the barrier film 6 to the surface of the underlying dielectric layer 3 , and which further results in the underlying dielectric layer 3 being polished with a smooth planar polished surface that is suitable for subsequent fabrication of successive layers of material.
- the wafer 1 is left with metal 5 in the trenches 4 to provide circuit interconnections. Further recessed dishing 8 of the metal 5 in each trench 4 results from the second step polishing operation.
- CMP polishing is allowed to continue for an extended duration
- recessed erosion of the dielectric layer 3 of the damascene topology will occur from excessive polishing or overpolishing.
- the recessed erosion undesirably provides further non-planarity features that contribute to variations in planarity of the wafer 1 .
- a desired result of CMP polishing is for both the underlying dielectric layer 3 and the metal 5 in the trenches 4 to attain the same planarity with a smooth planar polished surface resulting from polishing.
- the CMP polishing operation would desirably result in a polished planar surface of the wafer 1 , without residual metal films on the polished surface of the dielectric layer 3 , and with all of the trenches 4 having metal 5 at heights that are even with the level of the polished surface.
- chemical reaction and mechanical friction, applied by the polishing operation results in undesired removal of metal 5 from the trenches 4 , referred to as dishing 8 of such metal 5 .
- dishing 8 is acceptable, as dishing 8 of the metal 5 is compensated for, by precisely controlling the dimensions of the width of each trench 4 .
- Known mathematical calculations indicate that the impedance of a circuit interconnection, as provided by the metal 5 in a trench 4 , is dependent to a greater extent upon controlling the dimensions of the width of each trench 4 , and is dependent to a lesser extent upon variations in the height of dished metal 5 .
- FIG. 3 discloses a semiconductor wafer 1 that comprises, a silicon substrate 2 , an underlying dielectric layer 3 with trenches 4 and with imbedded metal 5 providing circuit interconnections.
- the underlying dielectric layer 3 has non-planarity features at its surface due to dished metal 5 in the trenches 4 .
- the dished metal 5 would have contributed to cumulative non-planarity of the surface of the wafer 1 , when the underlying dielectric layer 3 was used as a base on which to apply a successive layer of material on the wafer 1 .
- an embodiment of the invention provides a wafer 1 of minimized cumulative non-planarity at its surface.
- the wafer 1 has a successive dielectric layer 9 without forms of damascene topology, such as trenches, overlying the first dielectric layer 3 .
- the successive dielectric layer 9 has a smooth polished planar surface 10 that minimizes cumulative non-planarity due to the presence of non-planarity features in the underlying dielectric layer 3 .
- the non-planarity features result from a process step of, polishing the semiconductor wafer 1 to remove excess metallization from the surface of the underlying dielectric layer 3 , leaving the underlying dielectric layer 3 with a topology of non-planarity features in the form of dished metal 5 in trenches 4 .
- the polished surface 10 of the successive dielectric layer 9 minimizes cumulative non-planarity of the wafer 1 , and provides a base for subsequently fabricated layers of materials.
- the successive dielectric layer 9 itself is of sufficient thickness for subsequent fabrication of metal receiving trenches 4 , as shown by broken outline.
- another embodiment of the successive dielectric layer 9 is of sufficient thickness to become reduced in thickness upon being polished.
- the successive dielectric layer 9 is polished to a smooth planar polished surface 10 , to minimize cumulative non-planarity of the wafer 1 .
- the successive dielectric layer 9 is without forms of damascene topology, such as trenches.
- the successive dielectric layer is first, polished to a smooth planar polished surface 10 , to minimize cumulative non-planarity of the wafer 1 .
- the polished surface 10 of the successive dielectric layer 9 minimizes cumulative non-planarity of the wafer 1 , and provides a base for subsequently fabricated layers of materials.
- the successive dielectric layer 9 is followed by fabrication of a thicker dielectric layer 9 a.
- the thicker dielectric layer 9 a has an unpolished surface 10 a that provides a base for subsequently fabricated layers of materials.
- the thicker dielectric layer 9 a and the dielectric layer 9 are of combined sufficient thickness to provide a base for subsequent fabrication of metal receiving trenches 4 therein, as shown by broken outline.
- a method for minimizing cumulative non-planarity of a surface of a semiconductor wafer 1 .
- An embodiment of the method includes the steps of; applying a successive dielectric layer 9 that is without forms of damascene topology that would contribute non-planarity features.
- the successive dielectric layer 9 is applied over both the underlying dielectric layer 3 and the topology of non-planarity features of the underlying dielectric layer 3 .
- the successive dielectric layer 9 has a sufficient thickness to become reduced in thickness upon being polished, and the method includes the step of polishing the successive dielectric layer 9 , for example, by CMP, chemical mechanical planarization, to provide on the successive dielectric layer 9 a smooth planar polished surface 10 that minimizes non-planarity due to the topology of non-planarity features on the underlying dielectric layer 3 .
- An advantage of the invention resides in a method that provides a semiconductor wafer 1 having a smooth planar polished surface 10 on a successive dielectric layer 9 that is without trenches, which minimizes variations in planarity due to the topology of non-planarity features on the underlying dielectric layer 3 .
- the successive dielectric layer 9 is fabricated from material alternatives that comprises, for example, SiO 2 , a fluorinated-silicate glass, a hydrogen silsequixane, an organic polymer, such as, a polyarylene and a poly-arylene-ether, or an organosiloxane polymer, or an organosilicate glass, such as carbon-doped SiO 2 with added methyl groups obtained by reaction of tetramethylsilane or trimethylsilane precursors, or a fluoropolymer, such as, polytetrafluoroethylene, which materials are applied, respectively, by spin-on or chemical-vapor deposition.
- the dielectric constant K is further reduced by increased porosity of the materials.
- the successive dielectric layer 9 is without damascene topology, and is polished with a smooth planar polished surface 10 suitable as base on which are fabricated one or more than one layer of a wafer 1 having multilevel, circuit interconnections.
- An etchant or, reactive liquid is borne by an aqueous polishing fluid during a CMP polishing operation to polish the successive dielectric layer 9 that is made of a material that forms soluble reaction products with the reactive liquid.
- a combination of polishing friction and chemical reaction of the successive dielectric layer 9 with the reaction liquid to produce soluble dissolution of the surface of the successive dielectric layer 9 will polish the successive dielectric layer 9 with a smooth planar polished surface 10 .
- CMP polishing of a successive dielectric layer 9 of carbon-doped SiO x is accomplished by polishing with dilute Hydrofluoric HF acid as a reactive liquid in an aqueous polishing fluid that is applied during the polishing operation at an interface between the successive dielectric layer 9 and a polishing pad of a known CMP polishing apparatus.
- a combination of polishing friction and chemical reaction of the silicates with the HF reaction liquid to produce soluble reaction products, will polish the successive dielectric layer 9 with a smooth planar polished surface 10 .
- a kit of parts having materials for application to a surface of a semiconductor wafer 1 includes: a low K dielectric of carbon-doped SiO x , where x ⁇ 2; and a chemical reagent for dissolution of the surface of the low K dielectric during CMP polishing, comprising; dilute Hydrofluoric HF acid as a reactive liquid in an aqueous polishing fluid for CMP polishing of the low K dielectric.
- a kit of parts having materials for polishing a surface of a semiconductor wafer includes: a low K dielectric material and a reactive liquid for soluble dissolution of the surface of the low K dielectric material during CMP polishing to be used as a reactive liquid borne by a polishing fluid for dissolution of the low K dielectric material during CMP polishing of the low K dielectric material to provide a smooth planar polished surface on the low K dielectric material.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
A semiconductor wafer has, an underlying dielectric layer with non-planarity features at its surface due to damascene topology, and a successive dielectric layer that is without damascene topology overlying the first dielectric layer, the successive dielectric layer having a smooth polished planar surface that minimizes cumulative non-planarity. The surface is polished by chemical-mechanical planarization with a reactive liquid borne by an aqueous polishing fluid applied at an interface of the successive dielectric layer and a polishing pad.
Description
- This application claims the benefit of U.S. Provisional Patent Application Serial No. 60/237,463 filed Oct. 2, 2000.
- The invention relates to planarization of a semiconductor wafer to minimize cumulative non-planarity, caused by a topology of non-planar features on successive layers of the wafer being stacked one on another.
- According to U.S. Pat. No. 5,676,587, a semiconductor wafer is provided with a dielectric layer having a damascene topology of surface imbedded, circuit interconnects, which are fabricated, for example, by a known damascene process. Each semiconductor wafer must have a smooth planar polished surface, which provides a base on which is to be fabricated, one or more than one, successive layers, each having imbedded circuit interconnections. However, the damascene topology contributes to a topology of non-planar features on the polished surface.
- As successive layers are fabricated, one on another, and are polished, the topology of non-planar features on respective layers are stacked one on another. Thereby, the non-planar features on the respective layers become cumulative, and contribute to cumulative non-planarity of the surface of the wafer. Cumulative non-planarity contributes to difficulty in controlling the dimensions of successive layers that are fabricated on the wafer. A need exists for a semiconductor wafer of such a construction that minimizes cumulative non-planarity caused by successive layers on the wafer. A further need exists for a process for fabricating a semiconductor wafer in a manner that minimizes cumulative non-planarity caused by successive layers on the wafer.
- Polishing by chemical mechanical planarization, CMP, is known for polishing a semiconductor wafer to remove a top layer of excess metallization, which leaves behind metal in trenches to provide the circuit interconnections. A desired result of a CMP polishing operation is to provide a smooth planar polished surface that extends over the dielectric layer and the metal in trenches. One of the problems to be overcome, is that CMP polishing leaves behind imperfections in the surface of a polished wafer. For example, CMP polishing leaves behind recessed dishing of the metal in the trenches. In the event that CMP polishing is allowed to continue for an extended duration, recessed erosion of the dielectric layer will occur from excessive polishing or overpolishing. The topology of non-planar features, as caused by the polishing operation, comprises, dishing of the metal in trenches, and further comprises, erosion of the dielectric layer, as caused by the polishing operation. Each successive dielectric layer with applied metallization is similarly polished by CMP, leaving behind a topology of non-planar features on each successive polished layer.
- According to an embodiment of the invention, a method is disclosed for minimizing cumulative non-planarity caused by successive layers on a semiconductor wafer. An embodiment of the method includes the steps of;
- polishing a semiconductor wafer to remove excess metallization from the surface of an underlying dielectric layer, leaving the underlying dielectric layer with a topology of non-planarity features;
- applying a successive dielectric layer that is without damascene topology over both the underlying dielectric layer and the topology of non-planarity features, the successive dielectric layer having a sufficient thickness to become reduced in thickness upon being polished, and
- polishing the successive dielectric layer to provide on the successive dielectric layer a smooth planar polished surface that minimizes non-planarity due to the topology of non-planarity features on the underlying dielectric layer.
- An advantage of the invention resides in a method that provides a semiconductor wafer having a smooth planar polished surface on a dielectric layer that is without damascene topology, which minimizes variations in planarity due to the topology of non-planarity features on the underlying dielectric layer
- According to a further embodiment of the invention, a semiconductor wafer comprises, an underlying dielectric layer with imbedded metallization providing circuit interconnections, the underlying dielectric layer having non-planarity features at its surface due to damascene topology, and a successive dielectric layer that is without damascene topology overlying the first dielectric layer, the successive dielectric layer having a smooth polished planar surface that minimizes cumulative non-planarity.
- Embodiments of the invention will now be described by way of example with reference to the accompanying drawings, according to which:
- FIG. 1 is a fragmentary enlarged view of a portion of a semiconductor wafer with an exemplary underlying dielectric layer and a layer of metallization;
- FIG. 2 is a view similar to FIG. 1, and discloses the wafer after a first step polishing operation;
- FIG. 3 is a view similar to FIG. 2, and discloses the wafer after a second step polishing operation, having a topology of non-planar features, and a successive dielectric layer provided with a smooth planar polished surface that minimizes cumulative non-planarity; and
- FIG. 4 is a view similar to FIG. 3, and discloses a successive dielectric layer and a thicker dielectric layer provided with a smooth planar polished surface that minimizes cumulative non-planarity.
- FIG. 1 discloses a
semiconductor wafer 1 having a thinly sliced,silicon substrate 2, on which is applied an underlyingdielectric layer 3 having one ofmultiple trenches 4 in whichmetal 5 is imbedded to provide surface imbedded circuit interconnections. Further, thewafer 1 comprises, athin barrier film 6 covering the underlyingdielectric layer 3. The underlyingdielectric layer 3 is any one of a number of underlying dielectric layers withtrenches 4 that are to be covered by a successive layer on thewafer 1. For the purpose of illustration, FIG. 1 discloses the underlyingdielectric layer 3 as being the first underlying dielectric layer on thewafer 1. - The underlying
dielectric layer 3 has a surface to be used as a base on which multilevel layers are to be fabricated. The metal filledtrenches 4 in the underlyingdielectric layer 3 comprise a damascene topology. Thethin barrier film 6 is between themetal 5 in thetrenches 4 and the underlyingdielectric layer 3. Thebarrier film 6 provides a barrier to migration of the metal into the underlyingdielectric layer 3. - Fabrication by a known damascene process, includes, the
barrier film 6 being deposited, for example, by chemical vapor deposition, to cover the surface of the underlyingdielectric layer 3, including eachtrench 4. For example, thebarrier film 6 covering the underlyingdielectric layer 3 of SiO2, comprises, tantalum, meaning elemental Tantalum and/or a tantalum compound including tantalum nitride, or, alternatively, thebarrier film 6 comprises, an silicon carbide, SiC, based material applied by chemical vapor deposition over an underlyingdielectric layer 3 of organosilicate glass.Metallization 7, for example, copper metallization, is applied over theunderlying barrier film 6 to fill each of thetrenches 4 of the underlyingdielectric layer 3 withmetal 5. For example, themetallization 7 is applied as a thin film by chemical vapor deposition, followed by a thicker amount applied by a known electroplating process. Themetallization 7 further comprises excess metallization covering the surface of thedielectric layer 3. - According to accepted practices, a first step polishing operation is performed to remove the
copper metallization 7 to the level of theunderlying barrier film 6. Thewafer 1 is polished according to a known CMP polishing system. The CMP polishing system operates to move thewafer 1 against a moving polishing pad of the known CMP polishing system, and uses a combination of the moving polishing pad with polishing fluid at an interface with thewafer 1 being polished, to remove themetallization 7 by polishing friction and chemical reaction of themetallization 7 to the polishing fluid. - The
wafer 1 disclosed in FIG. 2 was subjected to a first step CMP polishing operation that polishes thebarrier film 6 to a planar surface, and that polishes themetal 5 in eachtrench 4 to the same height as that of thebarrier film 6. However, as further disclosed by FIG. 2, some of themetal 5 in eachtrench 4 is removed during polishing, by chemical reaction to the polishing fluid and by polishing friction, which causesconcave dishing 8 of themetal 5 in each dishedtrench 4. Dishing 8 of the damascene topology undesirably provides non-planarity features that contribute to variations in planarity of thewafer 1. As disclosed by FIG. 2, CMP polishing of the surface of thewafer 1 accomplishes removal of the surface layer ofcopper metallization 7 to expose the surface of thebarrier film 6, and to leavemetal 5 in thetrenches 4. FIG. 2 further discloses recessed dishing 8 of themetal 5 in eachtrench 4 that results from the first step polishing operation. - The first step polishing operation is followed by a second step polishing operation. With reference to FIG. 3, the second step polishing operation removes the
barrier film 6 to the surface of the underlyingdielectric layer 3, and which further results in the underlyingdielectric layer 3 being polished with a smooth planar polished surface that is suitable for subsequent fabrication of successive layers of material. Thewafer 1 is left withmetal 5 in thetrenches 4 to provide circuit interconnections. Further recessed dishing 8 of themetal 5 in eachtrench 4 results from the second step polishing operation. In the event that CMP polishing is allowed to continue for an extended duration, recessed erosion of thedielectric layer 3 of the damascene topology will occur from excessive polishing or overpolishing. The recessed erosion undesirably provides further non-planarity features that contribute to variations in planarity of thewafer 1. - A desired result of CMP polishing is for both the underlying
dielectric layer 3 and themetal 5 in thetrenches 4 to attain the same planarity with a smooth planar polished surface resulting from polishing. The CMP polishing operation would desirably result in a polished planar surface of thewafer 1, without residual metal films on the polished surface of thedielectric layer 3, and with all of thetrenches 4 havingmetal 5 at heights that are even with the level of the polished surface. However, chemical reaction and mechanical friction, applied by the polishing operation, results in undesired removal ofmetal 5 from thetrenches 4, referred to as dishing 8 ofsuch metal 5. Some dishing 8 is acceptable, as dishing 8 of themetal 5 is compensated for, by precisely controlling the dimensions of the width of eachtrench 4. Known mathematical calculations indicate that the impedance of a circuit interconnection, as provided by themetal 5 in atrench 4, is dependent to a greater extent upon controlling the dimensions of the width of eachtrench 4, and is dependent to a lesser extent upon variations in the height of dishedmetal 5. - As dielectric layers are fabricated, one on another, and are polished, the topology of non-planar features on multiple dielectric layers become stacked one on another. Thereby, the non-planar features become cumulative and contribute to cumulative non-planarity of the surface of the
wafer 1. Cumulative non-planarity contributes to difficulty in controlling the dimensions of successive dielectric layers with imbedded metallization. - FIG. 3 discloses a
semiconductor wafer 1 that comprises, asilicon substrate 2, an underlyingdielectric layer 3 withtrenches 4 and with imbeddedmetal 5 providing circuit interconnections. The underlyingdielectric layer 3 has non-planarity features at its surface due to dishedmetal 5 in thetrenches 4. In the past, the dishedmetal 5 would have contributed to cumulative non-planarity of the surface of thewafer 1, when theunderlying dielectric layer 3 was used as a base on which to apply a successive layer of material on thewafer 1. - With further reference to FIG. 3, an embodiment of the invention provides a
wafer 1 of minimized cumulative non-planarity at its surface. Thewafer 1 has asuccessive dielectric layer 9 without forms of damascene topology, such as trenches, overlying the firstdielectric layer 3. Thesuccessive dielectric layer 9 has a smooth polishedplanar surface 10 that minimizes cumulative non-planarity due to the presence of non-planarity features in theunderlying dielectric layer 3. The non-planarity features result from a process step of, polishing thesemiconductor wafer 1 to remove excess metallization from the surface of theunderlying dielectric layer 3, leaving the underlyingdielectric layer 3 with a topology of non-planarity features in the form of dishedmetal 5 intrenches 4. Thepolished surface 10 of thesuccessive dielectric layer 9 minimizes cumulative non-planarity of thewafer 1, and provides a base for subsequently fabricated layers of materials. For example, thesuccessive dielectric layer 9 itself is of sufficient thickness for subsequent fabrication ofmetal receiving trenches 4, as shown by broken outline. - With further reference to FIG. 4, another embodiment of the
successive dielectric layer 9 is of sufficient thickness to become reduced in thickness upon being polished. Thesuccessive dielectric layer 9 is polished to a smooth planarpolished surface 10, to minimize cumulative non-planarity of thewafer 1. Thesuccessive dielectric layer 9 is without forms of damascene topology, such as trenches. The successive dielectric layer is first, polished to a smooth planarpolished surface 10, to minimize cumulative non-planarity of thewafer 1. Thepolished surface 10 of thesuccessive dielectric layer 9 minimizes cumulative non-planarity of thewafer 1, and provides a base for subsequently fabricated layers of materials. After being polished, to minimize cumulative non-planarity of thewafer 1, thesuccessive dielectric layer 9 is followed by fabrication of a thickerdielectric layer 9 a. The thickerdielectric layer 9 a has anunpolished surface 10 a that provides a base for subsequently fabricated layers of materials. For example, the thickerdielectric layer 9 a and thedielectric layer 9 are of combined sufficient thickness to provide a base for subsequent fabrication ofmetal receiving trenches 4 therein, as shown by broken outline. - According to an embodiment of the invention, a method is disclosed for minimizing cumulative non-planarity of a surface of a
semiconductor wafer 1. An embodiment of the method includes the steps of; applying asuccessive dielectric layer 9 that is without forms of damascene topology that would contribute non-planarity features. Thesuccessive dielectric layer 9 is applied over both theunderlying dielectric layer 3 and the topology of non-planarity features of theunderlying dielectric layer 3. Thesuccessive dielectric layer 9 has a sufficient thickness to become reduced in thickness upon being polished, and the method includes the step of polishing thesuccessive dielectric layer 9, for example, by CMP, chemical mechanical planarization, to provide on thesuccessive dielectric layer 9 a smooth planarpolished surface 10 that minimizes non-planarity due to the topology of non-planarity features on theunderlying dielectric layer 3. - An advantage of the invention resides in a method that provides a
semiconductor wafer 1 having a smooth planarpolished surface 10 on asuccessive dielectric layer 9 that is without trenches, which minimizes variations in planarity due to the topology of non-planarity features on theunderlying dielectric layer 3. - The
successive dielectric layer 9 is fabricated from material alternatives that comprises, for example, SiO2, a fluorinated-silicate glass, a hydrogen silsequixane, an organic polymer, such as, a polyarylene and a poly-arylene-ether, or an organosiloxane polymer, or an organosilicate glass, such as carbon-doped SiO2 with added methyl groups obtained by reaction of tetramethylsilane or trimethylsilane precursors, or a fluoropolymer, such as, polytetrafluoroethylene, which materials are applied, respectively, by spin-on or chemical-vapor deposition. The dielectric constant K is further reduced by increased porosity of the materials. Thesuccessive dielectric layer 9 is without damascene topology, and is polished with a smooth planarpolished surface 10 suitable as base on which are fabricated one or more than one layer of awafer 1 having multilevel, circuit interconnections. - An etchant or, reactive liquid, is borne by an aqueous polishing fluid during a CMP polishing operation to polish the
successive dielectric layer 9 that is made of a material that forms soluble reaction products with the reactive liquid. A combination of polishing friction and chemical reaction of thesuccessive dielectric layer 9 with the reaction liquid to produce soluble dissolution of the surface of thesuccessive dielectric layer 9, will polish thesuccessive dielectric layer 9 with a smooth planarpolished surface 10. - By way of example, CMP polishing of a
successive dielectric layer 9 of carbon-doped SiOx, where x<2, and polishing of silica and other silicates, is accomplished by polishing with dilute Hydrofluoric HF acid as a reactive liquid in an aqueous polishing fluid that is applied during the polishing operation at an interface between thesuccessive dielectric layer 9 and a polishing pad of a known CMP polishing apparatus. A combination of polishing friction and chemical reaction of the silicates with the HF reaction liquid to produce soluble reaction products, will polish thesuccessive dielectric layer 9 with a smooth planarpolished surface 10. According to a further embodiment of the invention, a kit of parts having materials for application to a surface of asemiconductor wafer 1, includes: a low K dielectric of carbon-doped SiOx, where x<2; and a chemical reagent for dissolution of the surface of the low K dielectric during CMP polishing, comprising; dilute Hydrofluoric HF acid as a reactive liquid in an aqueous polishing fluid for CMP polishing of the low K dielectric. - According to a further embodiment of the invention, a kit of parts having materials for polishing a surface of a semiconductor wafer, includes: a low K dielectric material and a reactive liquid for soluble dissolution of the surface of the low K dielectric material during CMP polishing to be used as a reactive liquid borne by a polishing fluid for dissolution of the low K dielectric material during CMP polishing of the low K dielectric material to provide a smooth planar polished surface on the low K dielectric material.
- Although embodiments of the invention are disclosed, other embodiments and modifications are intended to be covered by the spirit and scope of the appended claims.
Claims (7)
1. A method for minimizing cumulative non-planarity of a semiconductor wafer comprising the steps of;
applying a successive dielectric layer that is without damascene topology over both an underlying dielectric layer and a topology of non-planarity features on the underlying dielectric layer, the successive dielectric layer having a sufficient thickness to become reduced in thickness upon being polished, and polishing the successive dielectric layer to provide on the successive dielectric layer a smooth planar polished surface that minimizes non-planarity due to the topology of non-planarity features on the underlying dielectric layer.
2. The method as recited in claim 1 , further comprising the step of; polishing the semiconductor wafer prior to applying the successive dielectric layer, to remove excess metallization from the surface of the underlying dielectric layer, leaving the underlying dielectric layer with the topology of non-planarity features.
3. A semiconductor wafer comprises, an underlying dielectric layer with non-planarity features at its surface provided by damascene topology, and a successive dielectric layer that is without damascene topology overlying the underlying dielectric layer, the successive dielectric layer having a smooth polished planar surface that minimizes cumulative non-planarity.
4. The semiconductor wafer according to claim 3 , and further comprising: the underlying dielectric layer having non-planarity features at its surface due to dished metal in trenches in the underlying dielectric layer.
5. The semiconductor wafer according to claim 3 , and further comprising: the underlying dielectric layer having non-planarity features at its surface due to recessed erosion of the underlying dielectric layer.
6. A kit of parts having materials for application to a surface of a semiconductor wafer, comprises: a low K dielectric material, and a reactive liquid for soluble dissolution of the surface of the low K dielectric during CMP polishing using the reactive liquid in a polishing fluid during CMP polishing to provide a smooth planar polished surface on the low K dielectric material.
7. A kit of parts having materials for polishing a surface of a semiconductor wafer, comprises: a low K dielectric material and a reactive liquid for soluble dissolution of the surface of the low K dielectric material during CMP polishing to be used as a reactive liquid borne by a polishing fluid for dissolution of the low K dielectric material during CMP polishing of the low K dielectric material to provide a smooth planar polished surface on the low K dielectric material.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/963,317 US20020058462A1 (en) | 2000-10-02 | 2001-09-26 | Chemical mechanical polishing of dielectric materials |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US23746300P | 2000-10-02 | 2000-10-02 | |
US09/963,317 US20020058462A1 (en) | 2000-10-02 | 2001-09-26 | Chemical mechanical polishing of dielectric materials |
Publications (1)
Publication Number | Publication Date |
---|---|
US20020058462A1 true US20020058462A1 (en) | 2002-05-16 |
Family
ID=22893827
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/963,317 Abandoned US20020058462A1 (en) | 2000-10-02 | 2001-09-26 | Chemical mechanical polishing of dielectric materials |
Country Status (2)
Country | Link |
---|---|
US (1) | US20020058462A1 (en) |
WO (1) | WO2002029878A2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6566171B1 (en) * | 2001-06-12 | 2003-05-20 | Lsi Logic Corporation | Fuse construction for integrated circuit structure having low dielectric constant dielectric material |
US20140238725A1 (en) * | 2013-02-25 | 2014-08-28 | Industrial Technology Research Institute | Method of flattening surface of conductive structure and conductive structure with flattened surface |
US20170092794A1 (en) * | 2015-09-25 | 2017-03-30 | National Tsing Hua University | Method of transferring thin film |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8597531B2 (en) | 2009-04-02 | 2013-12-03 | Infineon Technologies Ag | Method for manufacturing a device on a substrate |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2226991A (en) * | 1989-01-13 | 1990-07-18 | Ibm | Etching organic polymeric materials |
US5599740A (en) * | 1995-11-16 | 1997-02-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Deposit-etch-deposit ozone/teos insulator layer method |
US5766803A (en) * | 1996-06-05 | 1998-06-16 | Advanced Micro Devices, Inc. | Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization |
US5721172A (en) * | 1996-12-02 | 1998-02-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned polish stop layer hard masking method for forming planarized aperture fill layers |
US6153933A (en) * | 1997-09-05 | 2000-11-28 | Advanced Micro Devices, Inc. | Elimination of residual materials in a multiple-layer interconnect structure |
JP3660799B2 (en) * | 1997-09-08 | 2005-06-15 | 株式会社ルネサステクノロジ | Manufacturing method of semiconductor integrated circuit device |
US6083850A (en) * | 1997-12-18 | 2000-07-04 | Advanced Micro Devices, Inc. | HSQ dielectric interlayer |
US6281114B1 (en) * | 2000-02-07 | 2001-08-28 | Infineon Technologies Ag | Planarization after metal chemical mechanical polishing in semiconductor wafer fabrication |
-
2001
- 2001-09-26 US US09/963,317 patent/US20020058462A1/en not_active Abandoned
- 2001-09-26 WO PCT/US2001/030109 patent/WO2002029878A2/en active Application Filing
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6566171B1 (en) * | 2001-06-12 | 2003-05-20 | Lsi Logic Corporation | Fuse construction for integrated circuit structure having low dielectric constant dielectric material |
US6806551B2 (en) | 2001-06-12 | 2004-10-19 | Lsi Logic Corporation | Fuse construction for integrated circuit structure having low dielectric constant dielectric material |
US20140238725A1 (en) * | 2013-02-25 | 2014-08-28 | Industrial Technology Research Institute | Method of flattening surface of conductive structure and conductive structure with flattened surface |
US20170092794A1 (en) * | 2015-09-25 | 2017-03-30 | National Tsing Hua University | Method of transferring thin film |
US10115848B2 (en) * | 2015-09-25 | 2018-10-30 | National Tsing Hua University | Method of transferring thin film |
Also Published As
Publication number | Publication date |
---|---|
WO2002029878A3 (en) | 2003-01-23 |
WO2002029878A2 (en) | 2002-04-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6071809A (en) | Methods for forming high-performing dual-damascene interconnect structures | |
US5920792A (en) | High density plasma enhanced chemical vapor deposition process in combination with chemical mechanical polishing process for preparation and planarization of intemetal dielectric layers | |
US5510652A (en) | Polishstop planarization structure | |
US5854140A (en) | Method of making an aluminum contact | |
US6051496A (en) | Use of stop layer for chemical mechanical polishing of CU damascene | |
US6191050B1 (en) | Interlayer dielectric with a composite dielectric stack | |
US6114243A (en) | Method to avoid copper contamination on the sidewall of a via or a dual damascene structure | |
JP5121348B2 (en) | Local area alloying to prevent copper dishing during chemical mechanical polishing (CMP) | |
US5302551A (en) | Method for planarizing the surface of an integrated circuit over a metal interconnect layer | |
US7208404B2 (en) | Method to reduce Rs pattern dependence effect | |
US6103625A (en) | Use of a polish stop layer in the formation of metal structures | |
US20040101667A1 (en) | Adhesion between dielectric materials | |
US6017803A (en) | Method to prevent dishing in chemical mechanical polishing | |
US6372632B1 (en) | Method to eliminate dishing of copper interconnects by the use of a sacrificial oxide layer | |
WO1999063591A1 (en) | Dual-damascene interconnect structures employing low-k dielectric materials | |
US20100267217A1 (en) | Backside Process for a Substrate | |
JP2003179135A (en) | Method for manufacturing copper interconnect having interlayer insulator of very low permittivity | |
US8367552B2 (en) | Method for fabrication of in-laid metal interconnects | |
EP1562228B1 (en) | Chemical mechanical polishing process for low dishing of metal lines in semiconductor wafer fabrication | |
US7348277B2 (en) | Methods of fabricating semiconductor device using sacrificial layer | |
WO2000002235A1 (en) | Method of planarizing integrated circuits | |
CN100530571C (en) | Methods for fabricating interconnect structures having low K dielectric properties | |
US20020058462A1 (en) | Chemical mechanical polishing of dielectric materials | |
US20020182853A1 (en) | Method for removing hard-mask layer after metal-CMP in dual-damascene interconnect structure | |
US6461230B1 (en) | Chemical-mechanical polishing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: RODEL HOLDINGS, INC., DELAWARE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OLIVER, MICHAEL R.;COOK, LEE MELBOURNE;REEL/FRAME:012579/0912 Effective date: 20011108 |
|
STCB | Information on status: application discontinuation |
Free format text: EXPRESSLY ABANDONED -- DURING EXAMINATION |