US20020058466A1

US20020058466A1 - Method and system for reducing thickness of spin-on glass on semiconductor wafers

Info

Publication number: US20020058466A1
Application number: US10/029,788
Authority: US
Inventors: David Curran; Richard Guldi; William Pressnall
Original assignee: Texas Instruments Inc
Current assignee: Texas Instruments Inc
Priority date: 2000-11-13
Filing date: 2001-10-26
Publication date: 2002-05-16

Abstract

A method for reducing thickness of spin-on glass on semiconductor wafers includes rotatably mounting a semiconductor wafer and positioning a grinding member proximate an outer edge of the semiconductor wafer. The method further includes rotating both the semiconductor wafer and the grinding member, and engaging the rotating grinding member with the outer edge of the rotating semiconductor wafer while applying a chemical to the outer edge.

Description

BACKGROUND OF THE INVENTION

In semiconductor fabrication, one process that sometimes follows layering operations is a process called planarization. Planarization results in a smooth, planar surface for the semiconductor wafer and combats the effects of a varied wafer topography. Generally, as a semiconductor device is constructed using multiple surface layers and etchings, the surface of a semiconductor device becomes uneven. One planarization technique applies a layer of material to establish a smoother, flatter surface. One example of creating a planarization layer involves applying a liquid mixture of silicon dioxide in a solvent that evaporates quickly leaving a planarized film. Such a layer is called spin-on-glass (“SOG”).

One drawback of using SOG is the added thickness that occurs near the outer edge of the semiconductor wafer. This added thickness frequently causes cracking when the SOG is hardened and/or densified. In addition, flaking occurs when a chemical mechanical polish is used on a wafer with SOG. The cracks and flakes can destroy integrated circuit dies built near the edge of the wafer thereby significantly reducing die yield. Advances in integrated circuit die fabrication have produced larger dies in recent years, thereby exacerbating this reduced die yield problem.

Few approaches have been attempted to solve the problems presented by the use of SOG. Some semiconductor manufacturers just live with these problems and scrap the defective dies. Others have tried to eliminate the problems by improving or altering the SOG process, such as changing the speed at which the liquid oxide is spun-on. But these approaches have not solved the problems. Another potential alternative is to use a solvent to dissolve the added thickness of the SOG. Semiconductor manufacturers use solvent to dissolve the outer two to three millimeters of the wafers so that the wafers can be handled by handling machinery. However, this dissolving process can not be extended to reduce the full width of the added thickness of the SOG near the outer edge because the process would disturb the SOG thickness needed at the wafer edge. An additional approach could be to use a dry etch process, but this would be very expensive and not cost-effective.

SUMMARY OF THE INVENTION

The challenges in the field of semiconductor fabrication continue to increase with demands for more and better techniques having greater flexibility and adaptability. Therefore, a need has arisen for a new method and system for reducing thickness of spin-on glass on semiconductor wafers.

In accordance with the present invention, a method and system for reducing thickness of spin-on glass on semiconductor wafers is provided that addresses disadvantages and problems associated with previously developed methods and systems.

According to one embodiment of the invention, a method for reducing thickness of spin-on glass on semiconductor wafers includes rotatably mounting a semiconductor wafer and positioning a grinding member proximate an outer edge of the semiconductor wafer. The method further includes rotating both the semiconductor wafer and the grinding member, and engaging the rotating grinding member with the outer edge of the rotating semiconductor wafer while applying a chemical to the outer edge.

According to another embodiment of the invention, a method for reducing thickness of spin-on glass on semiconductor wafers includes rotatably mounting a semiconductor wafer and positioning a grinding member proximate an outer edge of the semiconductor wafer. The method further includes rotating both the semiconductor wafer and the grinding member, and engaging the rotating grinding member with the outer edge of the rotating semiconductor wafer while applying deionized water to approximately the center of the rotating semiconductor wafer.

According to an additional embodiment of the invention, a method for reducing thickness of spin-on glass on semiconductor wafers includes providing a chemical in a container, rotatably mounting a semiconductor wafer, and bearing a grinding member against a portion of an outer edge of the semiconductor wafer. The method further includes rotating the semiconductor wafer while the semiconductor wafer is in contact with the grinding member and while the portion of the outer edge of the semiconductor wafer is immersed in the chemical.

Embodiments of the invention provide numerous technical advantages. For example, integrated circuit die yield is improved according to one embodiment of the present invention. According to that embodiment, useable dies may be fabricated on locations at the wafer within approximately 3 mm of the semiconductor wafer edge, thereby resulting in significant savings and cost-effectiveness. Other technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the invention, and for further features and advantages, reference is now made to the following description, taken in conjunction with the accompanying drawings, in which: [0010]
FIG. 1 is a cross-sectional view of a semiconductor wafer having various layers including a spin-on glass (“SOG”) layer with a SOG protuberance; [0011]
FIG. 2A is a schematic diagram illustrating one method of reducing thickness of spin-on glass on semiconductor wafers in accordance with one embodiment of the present invention; [0012]
FIG. 2B is a flowchart generally outlining the method shown in FIG. 2A; [0013]
FIG. 3A is a schematic diagram illustrating another method of reducing thickness of SOG on semiconductor wafers in accordance with one embodiment of the present invention; [0014]
FIG. 3B is a flowchart generally outlining the method shown in FIG. 3A; [0015]
FIG. 4A is a schematic diagram illustrating an additional method of reducing thickness of SOG on semiconductor wafers in accordance with one embodiment of the present invention; and [0016]
FIG. 4B is a flowchart generally outlining the method shown in FIG. 4A. [0017]

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Embodiments of the present invention and their advantages are best understood by referring now to FIGS. 1 through 4B of the drawings, in which like numerals refer to like parts. [0018]
FIG. 1 is a cross-sectional view of one embodiment of a [0019] semiconductor wafer 100 having a substrate 102, a spin-on glass (“SOG”) layer 104 disposed outwardly from substrate 102, and a SOG protuberance 106 disposed outwardly from, and near a side edge 118 of, substrate 102. Semiconductor wafer 100 is used in the fabrication of integrated circuit dies for use in, for example, electronic and telecommunications devices. Therefore, semiconductor wafer 100 may have many different types of layers or regions, such as a transistor circuitry region 108, a metal oxide layer 110, and a metallization region 112 as shown in FIG. 1. The number and type of layers and regions depends on the type of integrated circuit fabricated on substrate 102.
[0020] Substrate 102 can be any suitable material used in semiconductor fabrication, such as a silicon wafer or a germanium wafer. SOG layer 104 is a planarization layer well known in the art of semiconductor fabrication. The application of SOG layer 104 to semiconductor wafer 100 is one of many planarization techniques used in semiconductor wafer fabrication. In one embodiment, the application of SOG layer 104 involves applying a liquid mixture of silicon dioxide, or other silicate, in a solvent while the associated wafer is spun. The solvent evaporates quickly leaving a planarized film. One drawback of using SOG layer 104 is that SOG protuberance 106 forms on outer edge 116 of semiconductor wafer 100 due to the centrifugal force acting on the liquid mixture as a result of the spinning of semiconductor wafer 100.
[0021] SOG protuberance 106 frequently causes cracks 114 when the SOG is hardened and/or densified, or if a solvent is used to dissolve a portion of outer edge 116 for handling purposes. In addition, flaking can occur if a chemical mechanical polish (“CMP”) is used on semiconductor wafer 100. Cracks 114 and flakes can destroy integrated circuit dies that are built in close proximity to side edge 118 of semiconductor wafer 100, thereby significantly hurting die yield.
[0022] SOG protuberance 106 forms on an outer edge 116 on semiconductor wafer 100, and is usually no more than approximately ten millimeters from side edge 118, as illustrated. Semiconductor manufacturers strive to build integrated circuit dies as close to side edge 118 as possible to maximize the number of dies produced on each wafer. Currently, the only restraint on the proximity of dies to side edge 118 are those imposed by wafer handling equipment. As a result, manufacturers desire to build integrated circuit dies up to approximately three millimeters from side edge 118. The present invention addresses reducing the thickness of SOG protuberance 106 on semiconductor wafer 100. One such method is illustrated in FIGS. 2A and 2B.
FIGS. 2A and 2B illustrate one method of reducing the thickness of [0023] SOG protuberance 106 on semiconductor wafer 100 in accordance with the present invention. A chemical 212 is provided in a container 210 at step 200. In one embodiment, chemical 212 is a hydrofluoric acid; however, chemical 212 may be other types of chemicals suitable for etching SOG protuberance 106, such as an aluminum oxide or silicon dioxide. Container 210 may be any type or size of container suitable to hold chemical 212.
[0024] Semiconductor wafer 100 is rotatably mounted at step 202. In one embodiment, semiconductor wafer 100 is secured in a substantially vertical position; however, semiconductor wafer 100 may be secured in other suitable positions. In one embodiment, semiconductor wafer 100 is secured to a spindle 214 with a vacuum chuck, which is well known in the art of semiconductor fabrication; however, semiconductor wafer 100 may be secured to spindle 214 using other suitable methods.
A grinding [0025] member 218 is disposed against a portion 216 of an outer edge 220 of semiconductor wafer 100, at step 204. Outer edge 220 typically corresponds to a portion of semiconductor wafer 100 having SOG protuberance 106. In one embodiment, grinding member 218 is a scrubber mechanism used in the CMP process; however, grinding member 218 may be other types of members with abrasive materials for abrading SOG protuberance 106. Grinding member 218 is mounted in any suitable manner. For example, grinding member 218 may be spring-loaded so that a substantially constant force is applied to SOG protuberance 106, or grinding member 218 may be pneumatically, hydraulically, or electrically controlled so that grinding member 218 reduces a predetermined amount of SOG thickness per unit time. Grinding member 218 may also be angled as desired, such that the depth of grinding is controlled by stopping grinding member 118 when it reaches substrate 102.
At [0026] step 206, semiconductor wafer 100 is rotated while semiconductor wafer 100 is in contact with grinding member 118 and while portion 216 of outer edge 220 is immersed in chemical 212. As a result, grinding member 218, in conjunction with chemical 212, reduces the thickness of SOG protuberance 106 to a desired level. SOG layer 104 may then be densified knowing that cracking and flaking will be significantly reduced. This allows die yield to be improved, thereby significantly enhancing cost-effectiveness.
FIGS. 3A and 3B illustrate another method of reducing the thickness of [0027] SOG protuberance 106 on semiconductor wafer 100 in accordance with the present invention. Semiconductor wafer 100 is rotatably mounted at step 300. In one embodiment, semiconductor wafer 100 is secured in a substantially horizontal position; however, semiconductor wafer 100 may be secured in other suitable positions, such as a substantially vertical position. In one embodiment, semiconductor wafer 100 is secured to a spindle 320 with a vacuum chuck, which is well known in the art of semiconductor fabrication; however, semiconductor wafer 100 may be secured to spindle 320 using other suitable methods.
A grinding [0028] member 322 is positioned proximate an outer edge 328 of semiconductor wafer 100, at step 302. In one embodiment, grinding member 322 is an ultra-fine grit grinding wheel; however, grinding member 322 may be other types of rotatable mechanisms with abrasive materials used for reducing the thickness of SOG protuberance 106. Grinding member 322 is mounted in any suitable manner. As described above with grinding member 218, grinding member 322 may be spring-loaded so that a substantially constant force is applied to SOG protuberance 106, or grinding member 322 may be pneumatically, hydraulically or electrically controlled so that grinding member 322 reduces a predetermined amount of SOG thickness per unit time. Alternatively, grinding member 322 may be manually controlled.
[0029] Semiconductor wafer 100 is rotated, at step 304, and grinding member 322 is rotated, at step 306. Both semiconductor wafer 100 and grinding member 322 may be rotated in either a clockwise or counterclockwise direction. A chemical 324 is applied to outer edge 328 of semiconductor wafer 100, at step 308. In one embodiment, chemical 324 is a hydrofluoric acid; however, chemical 212 may be other types of chemicals suitable for etching SOG protuberance 106, such as an aluminum oxide or silicon dioxide. In one embodiment, chemical 324 is applied to outer edge 328 with a syringe 326; however, chemical 324 may be applied to outer edge 328 using other suitable methods that allow localized application.
Rotating grinding [0030] member 322 is engaged with outer edge 328 of rotating semiconductor wafer 100, at step 310, such that grinding member 322, in conjunction with chemical 324, reduces the thickness of SOG protuberance 106 to a desired level. Rotating grinding member 322 is then disengaged so that rotating semiconductor wafer 100 may be rinsed, at step 312. SOG layer 104 may then be densified knowing that cracking and flaking will be significantly reduced. This allows die yield to be improved, thereby significantly enhancing cost-effectiveness.
FIGS. 4A and 4B illustrate another method of reducing the thickness of [0031] SOG protuberance 106 on semiconductor wafer 100 in accordance with the present invention. Semiconductor wafer 100 is rotatably mounted at step 400. In one embodiment, semiconductor wafer 100 is secured in a substantially horizontal position; however, semiconductor wafer 100 may be secured in other suitable positions, such as a substantially vertical position. In one embodiment, semiconductor wafer 100 is secured to a spindle 420 with a vacuum chuck, which is well known in the art of semiconductor fabrication; however, semiconductor wafer 100 may be secured to spindle 420 using other suitable methods.
A grinding [0032] member 422 is positioned proximate an outer edge 428 of semiconductor wafer 100, at step 402. In one embodiment, grinding member 422 is an ultra-fine grit grinding wheel; however, grinding member 422 may be other types of rotatable mechanisms with abrasive materials used for reducing the thickness of SOG protuberance 106. Grinding member 422 is mounted in any suitable manner. As described above in conjunction with grinding members 218 and 322, grinding member 422 may be spring-loaded so that a substantially constant force is applied to SOG protuberance 106, or grinding member 422 may be pneumatically, hydraulically or electrically controlled so that grinding member 422 reduces a predetermined amount of SOG thickness per unit time. Alternatively, grinding member 422 may be manually controlled.
[0033] Semiconductor wafer 100 is rotated, at step 404, and grinding member 322 is rotated, at step 406. Both semiconductor wafer 100 and grinding member 422 may be rotated in either a clockwise or counterclockwise direction. A deionized water 424 is applied to approximately the center of rotating semiconductor wafer 100, at step 408. Deionized water 424 is used to rinse semiconductor wafer 100, thereby facilitating particle and chemical removal. The present invention contemplates the use of other deionized liquids to rinse semiconductor wafer 100. In one embodiment, deionized water 424 is applied to approximately the center of rotating semiconductor wafer 100 with a syringe 426; however, deionized water 424 can be applied to approximately the center of rotating semiconductor wafer 100 using other suitable methods that allow localized application.
Rotating grinding [0034] member 422 is engaged with outer edge 428 of rotating semiconductor wafer 100, at step 410, such that grinding member 422 reduces the thickness of SOG protuberance 106 to a desired level. Rotating grinding member 322 is then disengaged, at step 412, so that rotating semiconductor wafer 100 may be rinsed. SOG layer 104 may then be densified knowing that cracking and flaking will be significantly reduced. This allows die yield to be improved, thereby significantly enhancing cost-effectiveness.
Although embodiments of the invention and their advantages are described in detail, a person skilled in the art could make various alternations, additions, and omissions without departing from the spirit and scope of the present invention as defined by the appended claims. [0035]

Claims

What is claimed is:

1. A method for reducing thickness of spin-on glass on semiconductor wafers, the method comprising:

rotatably mounting a semiconductor wafer;

positioning a grinding member proximate an outer edge of the semiconductor wafer;

rotating the semiconductor wafer;

rotating the grinding member;

applying a chemical to the outer edge; and

engaging the rotating grinding member with the outer edge of the rotating semiconductor wafer.

2. The method of claim 1, further comprising:

disengaging the rotating grinding member; and

rinsing the semiconductor wafer with deionized water.

3. The method of claim 1, wherein rotatably mounting the semiconductor wafer comprises securing the semiconductor wafer in a substantially horizontal position to a spindle with a vacuum chuck.

4. The method of claim 1, wherein positioning the grinding member comprises orientating the grinding member in a substantially horizontal position.

5. The method of claim 1, wherein positioning the grinding member comprises orientating the grinding member in a substantially vertical position.

6. The method of claim 1, wherein applying the chemical comprises using a syringe to apply a hydrofluoric acid to approximately a portion of the outer edge that is engaged with the grinding member.

7. The method of claim 1, wherein engaging the rotating grinding member with the outer edge of the rotating semiconductor wafer comprises pneumatically controlling the grinding member.

8. The method of claim 1, wherein engaging the rotating grinding member with the outer edge of the rotating semiconductor wafer comprises spring-loading the grinding member.

9. A method for reducing thickness of spin-on glass on semiconductor wafers, the method comprising:

rotatably mounting a semiconductor wafer;

rotating the semiconductor wafer;

rotating the grinding member;

applying deionized water to approximately the center of the rotating semiconductor wafer; and

10. The method of claim 9, wherein rotatably mounting the semiconductor wafer comprises securing the semiconductor wafer in a substantially horizontal position to a spindle with a vacuum chuck.

11. The method of claim 9, wherein positioning the grinding member comprises orientating the grinding member in a substantially horizontal position.

12. The method of claim 9, wherein positioning the grinding member comprises orientating the grinding member in a substantially vertical position.

13. The method of claim 9, wherein engaging the rotating grinding member with the outer edge of the rotating semiconductor wafer comprises pneumatically controlling the grinding member.

14. The method of claim 9, wherein engaging the rotating grinding member with the outer edge of the rotating semiconductor wafer comprises spring-loading the grinding member.

15. A method for reducing thickness of spin-on glass on semiconductor wafers, the method comprising:

providing a chemical in a container;

rotatably mounting a semiconductor wafer;

bearing a grinding member against a portion of an outer edge of the semiconductor wafer; and

rotating the semiconductor wafer while the semiconductor wafer is in contact with the grinding member and while the portion of the outer edge of the semiconductor wafer is immersed in the chemical.

16. The method of claim 15, further comprising rinsing the semiconductor wafer with deionized water.

17. The method of claim 15, wherein rotatably mounting the semiconductor wafer comprises securing the semiconductor wafer in a substantially vertical position to a spindle with a vacuum chuck.

18. The method of claim 15, wherein positioning the grinding member comprises orientating the grinding member in a substantially horizontal position.

19. The method of claim 15, wherein bearing the grinding member against the portion of the outer edge comprises pneumatically controlling the grinding member.

20. The method of claim 15, wherein bearing the grinding member against the portion of the outer edge comprises spring-loading the grinding member.