US20020090779A1 - Method for forming lower electrode of cylinder-shaped capacitor preventing twin bit failure - Google Patents
Method for forming lower electrode of cylinder-shaped capacitor preventing twin bit failure Download PDFInfo
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- US20020090779A1 US20020090779A1 US10/040,866 US4086601A US2002090779A1 US 20020090779 A1 US20020090779 A1 US 20020090779A1 US 4086601 A US4086601 A US 4086601A US 2002090779 A1 US2002090779 A1 US 2002090779A1
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000003990 capacitor Substances 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 106
- 238000005498 polishing Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 2
- 239000005368 silicate glass Substances 0.000 claims description 2
- 239000002356 single layer Substances 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000006227 byproduct Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
Definitions
- the present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming lower electrodes of a cylinder-shaped capacitor of a memory device or a merged DRAM logic (MDL) device.
- MDL merged DRAM logic
- Three-dimensional capacitors include pin-shaped capacitors, trench-shaped capacitors, stack-shaped capacitors, and cylinder-shaped capacitors, and among these, the cylinder-shaped capacitor is most widely used.
- FIGS. 1 and 2 are sectional views showing a conventional method for forming lower electrodes of a cylinder-shaped capacitor
- FIG. 3 is a plan view illustrating a conventional method for forming lower electrodes of a cylinder-shaped capacitor.
- a lower structure such as a transistor and a bit line, is formed on a semiconductor substrate 10 , and an interlevel dielectric (ILD) film 12 is deposited on the semiconductor substrate 10 .
- ILD interlevel dielectric
- Buried contacts (BC) 14 as a conductive region connected to the cylinder-shaped capacitor are formed on the semiconductor substrate 10 .
- a buffer layer 16 and an etch stopper 18 are sequentially formed on the resultant structure.
- a sacrificial oxide layer 20 for forming the cylinder-shaped capacitor is formed on the etch stopper 18 .
- an etching process using a photoresist pattern 22 is performed on the sacrificial oxide layer 20 to form a first opening 24 therein as a region where the cylinder-shaped capacitor is formed.
- etch skew (a dotted part of A) in which anisotropic dry etching forms a first opening 24 that is curved instead of straight occurs.
- the etch stopper 18 and the buffer layer 16 are further etched on the semiconductor substrate 10 where the etch skew occurs, and the first opening 24 further extends downwards, thereby exposing an upper part of the BC 14 as a conductive region to be electrically connected to the cylinder-shaped capacitor.
- a conductive layer for forming cylinder-shaped lower electrodes 28 is deposited on the semiconductor substrate 10 .
- a chemical-mechanical polishing (CMP) process is performed on the resultant structure to remove a portion of the conductive layer for forming the cylinder-shaped lower electrodes 28 that is disposed on the sacrificial oxide layer 20 , thereby separating the cylinder-shaped lower electrode 28 .
- the sacrificial oxide layer 20 is removed by wet etching to complete the lower electrodes 28 of the cylinder-shaped capacitor.
- FIG. 3 is a plan view illustrating the cylinder-shaped lower electrodes 28 formed in accordance with the processing steps described above.
- the left side of FIG. 3 shows four cylinder-shaped lower electrodes 28 formed on a predetermined region of the semiconductor substrate 10 before integration density increases.
- the right side of FIG. 3, which has the same area as the left side, shows five cylinder-shaped lower electrodes 28 formed on the semiconductor substrate 10 after the integration density has increased.
- the pitch between cylinder-shaped lower electrodes is reduced from t 1 to t 2 , and the probability of twin bit failure increases. In twin bit failure, a bridge between neighboring cylinder-shaped lower electrodes at the top of the cylinder-shaped lower electrodes occurs in proportion to the reduced degree.
- the present invention contemplates a method for forming a lower electrode of a cylinder-shaped capacitor in which etch skew or twin bit failure can be prevented by applying a slope-improving layer for improving sidewall slope before the formation of the lower electrodes of the capacitor.
- a buffer layer and an etch stopper are sequentially formed on a semiconductor substrate including a conductive region.
- a sacrificial dielectric layer is formed on the etch stopper.
- a first opening is formed within the sacrificial oxide layer by etching a portion thereof using the etch stopper.
- a slope-improving layer for improving sidewall slope of the first opening is formed on the resultant structure.
- a second opening is then formed by etching a portion of the slope-improving layer, the etch stopper and the buffer layer under the first opening. The second opening exposes the conductive region to which the cylinder-shaped capacitor is electrically connected.
- a conductive layer for forming cylinder-shaped lower electrodes is deposited on the resultant structure including the second opening. The cylinder-shaped lower electrodes are then formed separated from each other.
- the slope-improving layer for improving sidewall slope having excellent gap-fill characteristics is further formed after the first opening for forming a cylinder-shaped capacitor is formed and improves etch slope of the first opening. Also, the etch profile for a region in which etch skew occurs is improved, and the space between cylinder-shaped lower electrodes is increased, thereby preventing twin bit failure.
- FIGS. 1 and 3 are diagrams illustrating a method for forming a lower electrode of a cylinder-shaped capacitor according to the prior art and problems thereof;
- FIGS. 4 through 13 are diagrams illustrating a method for forming a lower electrode of a cylinder-shaped capacitor according to the present invention.
- FIGS. 4 through 13 are diagrams illustrating a method for forming a lower electrode of a cylinder-shaped capacitor according to the present invention.
- a lower structure such as a transistor or a bit line is formed on a semiconductor substrate 100 by a conventional method.
- an interlevel dielectric (ILD) film 102 formed of a dielectric material such as oxide is formed on the semiconductor substrate 100 .
- a buried contact (BC) opening is formed through the ILD film 102 using conventional techniques such as photolithography and etching.
- a conductive material for example, doped-polysilicon or tungsten, is deposited over the ILD film 102 and within the BC opening.
- a planarization process such as a chemical mechanical polishing (CMP) process is performed thereon to complete a BC 104 .
- CMP chemical mechanical polishing
- a buffer layer 106 comprising a dielectric material such as plasma enhanced tetraethylorthosilicate (PE-TEOS), and an etch stopper 108 having an etch selectivity to a sacrificial dielectric layer to be formed thereon such as a sacrificial oxide layer 110 are sequentially formed overlying the BC 104 .
- the etch stopper 108 comprises a silicon nitride layer (SiN) if the sacrificial oxide layer 110 comprises PE-TEOS.
- the sacrificial oxide layer 110 for example, a single layer of PE-TEOS or a multilayer including the PE-TEOS layer, is formed on the etch stopper 108 .
- a polysilicon layer is preferably formed on the sacrificial oxide layer 110 as an etching mask 112 .
- An anti-reflection layer comprising a silicon oxynitride layer (SiON) or another anti-reflection layer is additionally formed on the polysilicon etching mask 112 .
- a first opening 114 for forming a cylinder-shaped capacitor is then formed within the sacrificial oxide layer by photolithography and etching.
- the sacrificial oxide layer 110 is etched by a dry etching method using the polysilicon etching mask 112 .
- a slope-improving layer 116 for improving sidewall slope is deposited to a thickness of about 50-500 ⁇ , for example, 300 ⁇ , over the resultant structure including the first opening 114 .
- the layer 116 for improving sidewall slope is preferably an undoped silicate glass (USG) layer formed by a chemical vapor deposition (CVD) method to have excellent gap-fill characteristics and improves the etch slope of dry etching to form the first opening 114 .
- the layer 116 improves the etch profile for a region in which etch skew occurs, and thus prevents twin bit failure caused between cylinder-shaped lower electrodes to be formed. It is desired that the layer 116 for improving sidewall slope have excellent gap-fill characteristics.
- the layer 116 can be formed of any material having excellent gap-fill characteristics.
- Other layers such as a high-density plasma (HDP) oxide layer also can be used instead of the USG layer as the layer 116 for improving sidewall slope.
- Reference numeral 115 denotes a first opening after the formation of the layer 116 for improving sidewall slope.
- FIG. 7 is a plan view of the semiconductor substrate 100 before and after the formation of the layer 116 for improving sidewall slope according to an embodiment of the present invention.
- the outer line 117 of the first opening 114 shows the edge of the first opening 114 before the formation of the layer 116
- the inner line 113 shows the edge of the first opening 115 after the deposition of the layer 116 for improving sidewall slope.
- FIG. 8 is an enlarged sectional view of 8 of FIG. 6.
- the layer 116 for improving sidewall slope deposited by the CVD method has excellent gap-fill characteristics when it is deposited in the first opening 114 .
- the layer 116 for improving sidewall slope is not necessarily deposited to a uniform thickness in the first opening, instead its thickness varies, for example, from u 1 at the top, u 2 at the middle, and u 3 at the bottom of the first opening.
- the thickness of the layer 116 for improving sidewall slope deposited at the middle u 2 of the first opening is 70-80 ⁇
- the thickness of the layer 116 for improving sidewall slope deposited at the bottom u 3 of the first opening is less than 30 ⁇ .
- the thickness to which the layer 116 for improving sidewall slope is deposited in the first opening 114 varies depending in which area it is deposited. With this feature of the layer 116 , the etch slope of the first opening is improved.
- FIG. 9 is a sectional view illustrating the layer 116 for improving sidewall slope when etch skew occurs in FIG. 6.
- the layer 116 for improving sidewall slope having excellent gap-fill characteristics compensates a region in which the etch skew occurs. This feature improves the profile of the region of the first opening in which the etch skew occurs.
- the layer 116 for improving sidewall slope according to the present invention can prevent twin bit failure or a micro-bridge.
- a portion of the layer 116 at the bottom u 3 of the first opening 114 , the etch stopper 108 , and the buffer layer 106 adjacent to the first opening are removed by etching.
- a second opening 118 is formed to expose the buried contact (BC) 104 (a conductive region) to which the cylinder-shaped lower electrode is electrically connected.
- the conductive region exposed by the second opening 118 may be the top surface of the BC 104 .
- the conductive region may be a source region of a transistor of a lower structure instead of the buried contact (BC).
- a polysilicon layer or other suitable conductive layer 121 to form the cylinder-shaped lower electrodes 122 is deposited over the resultant structure including the second opening 118 to a predetermined thickness.
- the slope of the layer 121 for forming cylinder-shaped lower electrodes is steeper than the slope before the layer 116 for improving sidewall slope is formed. As a result, the probability of twin bit failure can be reduced.
- portions of the layer 121 to form cylinder-shaped lower electrodes 122 over the sacrificial oxide layer 110 are removed by planarization techniques such as a chemical mechanical polishing (CMP) or an etch back process.
- CMP chemical mechanical polishing
- etch back process etch back process
- wet etching is performed on the semiconductor substrate 100 on which the separated cylinder-shaped lower electrodes 122 are formed, thereby substantially completely removing the sacrificial oxide layer 110 .
- An etching solution such as a buffered oxide etchant (BOE) can be used during the wet etching.
- BOE buffered oxide etchant
- the etch stopper 108 and the buffer layer 106 are removed, thereby completing the cylinder-shaped lower electrodes 122 connected to the BC 104 .
- lower electrodes 122 of a cylinder-shaped capacitor preventing twin bit failure is completed according to a preferred embodiment of the present invention.
- the cylinder-shaped lower electrodes 122 according to the present invention can be widely applied to a semiconductor memory device such as a DRAM and a semiconductor device such as a merged DRAM logic (MDL) device.
- MDL merged DRAM logic
- the layer for improving sidewall slope having excellent gap-fill characteristics is additionally formed after the first opening for forming a cylinder-shaped capacitor is etched, thereby improving the etch slope of the first opening. Also, the etch profile for a region in which etch skew occurs is improved, and the space between cylinder-shaped lower electrodes is increased, thereby preventing twin bit failure.
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming lower electrodes of a cylinder-shaped capacitor of a memory device or a merged DRAM logic (MDL) device.
- 2. Description of the Related Art
- As the integration density of semiconductor devices increases, design rule decreases. In particular, as a memory device such as a dynamic random access memory (DRAM) rapidly becomes highly-integrated and as its pattern becomes increasingly fine, the pitch between lower electrodes of a capacitor decreases. However, the capacitance required to drive the DRAM does not decrease at the same rate as the pitch decreases because of problems such as soft error.
- Consequently, in most DRAMs, a method for making capacitors applied in DRAMs three-dimensional is used to increase the capacitance. Three-dimensional capacitors include pin-shaped capacitors, trench-shaped capacitors, stack-shaped capacitors, and cylinder-shaped capacitors, and among these, the cylinder-shaped capacitor is most widely used.
- FIGS. 1 and 2 are sectional views showing a conventional method for forming lower electrodes of a cylinder-shaped capacitor, and FIG. 3 is a plan view illustrating a conventional method for forming lower electrodes of a cylinder-shaped capacitor.
- Referring to FIG. 1, a lower structure (not shown for simplicity), such as a transistor and a bit line, is formed on a
semiconductor substrate 10, and an interlevel dielectric (ILD)film 12 is deposited on thesemiconductor substrate 10. Buried contacts (BC) 14 as a conductive region connected to the cylinder-shaped capacitor are formed on thesemiconductor substrate 10. Next, abuffer layer 16 and anetch stopper 18 are sequentially formed on the resultant structure. - Next, a
sacrificial oxide layer 20 for forming the cylinder-shaped capacitor is formed on theetch stopper 18. Subsequently, an etching process using aphotoresist pattern 22 is performed on thesacrificial oxide layer 20 to form afirst opening 24 therein as a region where the cylinder-shaped capacitor is formed. - However, during etching of the
sacrificial oxide layer 20 to form thefirst opening 24, because etch by-products 26 are formed at the top of the first opening 24, etch skew (a dotted part of A) in which anisotropic dry etching forms afirst opening 24 that is curved instead of straight occurs. - Referring to FIG. 2, the
etch stopper 18 and thebuffer layer 16 are further etched on thesemiconductor substrate 10 where the etch skew occurs, and thefirst opening 24 further extends downwards, thereby exposing an upper part of theBC 14 as a conductive region to be electrically connected to the cylinder-shaped capacitor. - Subsequently, a conductive layer for forming cylinder-shaped
lower electrodes 28 is deposited on thesemiconductor substrate 10. Subsequently, a chemical-mechanical polishing (CMP) process is performed on the resultant structure to remove a portion of the conductive layer for forming the cylinder-shapedlower electrodes 28 that is disposed on thesacrificial oxide layer 20, thereby separating the cylinder-shapedlower electrode 28. Lastly, thesacrificial oxide layer 20 is removed by wet etching to complete thelower electrodes 28 of the cylinder-shaped capacitor. - FIG. 3 is a plan view illustrating the cylinder-shaped
lower electrodes 28 formed in accordance with the processing steps described above. The left side of FIG. 3 shows four cylinder-shapedlower electrodes 28 formed on a predetermined region of thesemiconductor substrate 10 before integration density increases. The right side of FIG. 3, which has the same area as the left side, shows five cylinder-shapedlower electrodes 28 formed on thesemiconductor substrate 10 after the integration density has increased. As the integration density increases, the pitch between cylinder-shaped lower electrodes is reduced from t1 to t2, and the probability of twin bit failure increases. In twin bit failure, a bridge between neighboring cylinder-shaped lower electrodes at the top of the cylinder-shaped lower electrodes occurs in proportion to the reduced degree. - The conventional methods for forming a cylinder-shaped capacitor have the following problems.
- First, as a memory device such as a DRAM becomes highly-integrated, the number of capacitors formed in a certain area increases. Thus, the spacing between cylinder-shaped lower electrodes decreases, and the probability of twin bit failure increases.
- Second, the probability of a bridge occurring between neighboring cylinder-shaped lower electrodes, even at the middle of the cylinder-shaped lower electrodes, increases due to etch skew. Furthermore, as the integration density of a DRAM increases, the height of the cylinder-shaped lower electrodes becomes greater. Thus, the probability of the cylinder-shaped lower electrodes falling down, twin bit failure, or micro-bridge formation, increases.
- To solve the above problems, the present invention contemplates a method for forming a lower electrode of a cylinder-shaped capacitor in which etch skew or twin bit failure can be prevented by applying a slope-improving layer for improving sidewall slope before the formation of the lower electrodes of the capacitor.
- Accordingly, according to one embodiment of the present invention, a buffer layer and an etch stopper are sequentially formed on a semiconductor substrate including a conductive region. A sacrificial dielectric layer is formed on the etch stopper. A first opening is formed within the sacrificial oxide layer by etching a portion thereof using the etch stopper. A slope-improving layer for improving sidewall slope of the first opening is formed on the resultant structure. A second opening is then formed by etching a portion of the slope-improving layer, the etch stopper and the buffer layer under the first opening. The second opening exposes the conductive region to which the cylinder-shaped capacitor is electrically connected. A conductive layer for forming cylinder-shaped lower electrodes is deposited on the resultant structure including the second opening. The cylinder-shaped lower electrodes are then formed separated from each other.
- According to the present invention, the slope-improving layer for improving sidewall slope having excellent gap-fill characteristics is further formed after the first opening for forming a cylinder-shaped capacitor is formed and improves etch slope of the first opening. Also, the etch profile for a region in which etch skew occurs is improved, and the space between cylinder-shaped lower electrodes is increased, thereby preventing twin bit failure.
- The above object and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which:
- FIGS. 1 and 3 are diagrams illustrating a method for forming a lower electrode of a cylinder-shaped capacitor according to the prior art and problems thereof; and
- FIGS. 4 through 13 are diagrams illustrating a method for forming a lower electrode of a cylinder-shaped capacitor according to the present invention.
- FIGS. 4 through 13 are diagrams illustrating a method for forming a lower electrode of a cylinder-shaped capacitor according to the present invention.
- Referring FIG. 4, a lower structure such as a transistor or a bit line is formed on a
semiconductor substrate 100 by a conventional method. Subsequently, an interlevel dielectric (ILD)film 102 formed of a dielectric material such as oxide is formed on thesemiconductor substrate 100. Next, a buried contact (BC) opening is formed through the ILDfilm 102 using conventional techniques such as photolithography and etching. A conductive material, for example, doped-polysilicon or tungsten, is deposited over the ILDfilm 102 and within the BC opening. Then, a planarization process such as a chemical mechanical polishing (CMP) process is performed thereon to complete aBC 104. - Subsequently, a
buffer layer 106 comprising a dielectric material such as plasma enhanced tetraethylorthosilicate (PE-TEOS), and anetch stopper 108 having an etch selectivity to a sacrificial dielectric layer to be formed thereon such as asacrificial oxide layer 110 are sequentially formed overlying theBC 104. Preferably, theetch stopper 108 comprises a silicon nitride layer (SiN) if thesacrificial oxide layer 110 comprises PE-TEOS. - Next, the
sacrificial oxide layer 110, for example, a single layer of PE-TEOS or a multilayer including the PE-TEOS layer, is formed on theetch stopper 108. A polysilicon layer is preferably formed on thesacrificial oxide layer 110 as anetching mask 112. An anti-reflection layer comprising a silicon oxynitride layer (SiON) or another anti-reflection layer is additionally formed on thepolysilicon etching mask 112. - Referring to FIG. 5, a
first opening 114 for forming a cylinder-shaped capacitor is then formed within the sacrificial oxide layer by photolithography and etching. Preferably, thesacrificial oxide layer 110 is etched by a dry etching method using thepolysilicon etching mask 112. In order to prevent over etch, it is desirable that the etching stop at theetch stopper 108. - Referring to FIG. 6, a slope-improving
layer 116 for improving sidewall slope is deposited to a thickness of about 50-500 Å, for example, 300 Å, over the resultant structure including thefirst opening 114. - The
layer 116 for improving sidewall slope is preferably an undoped silicate glass (USG) layer formed by a chemical vapor deposition (CVD) method to have excellent gap-fill characteristics and improves the etch slope of dry etching to form thefirst opening 114. Thelayer 116 improves the etch profile for a region in which etch skew occurs, and thus prevents twin bit failure caused between cylinder-shaped lower electrodes to be formed. It is desired that thelayer 116 for improving sidewall slope have excellent gap-fill characteristics. Thus, thelayer 116 can be formed of any material having excellent gap-fill characteristics. Other layers such as a high-density plasma (HDP) oxide layer also can be used instead of the USG layer as thelayer 116 for improving sidewall slope.Reference numeral 115 denotes a first opening after the formation of thelayer 116 for improving sidewall slope. - FIG. 7 is a plan view of the
semiconductor substrate 100 before and after the formation of thelayer 116 for improving sidewall slope according to an embodiment of the present invention. In detail, theouter line 117 of thefirst opening 114 shows the edge of thefirst opening 114 before the formation of thelayer 116, and theinner line 113 shows the edge of thefirst opening 115 after the deposition of thelayer 116 for improving sidewall slope. - That is, before the deposition of the
layer 116 for improving sidewall slope, the pitch between cylinder-shaped lower electrodes (122 of FIG. 12) is t2, but after the deposition of thelayer 116 for improving sidewall slope, the pitch between cylinder-shapedlower electrodes 122 is increased to t3. If the thickness of thelayer 116 for improving sidewall slope at the top of the first opening is β, then t3=t2+2β. Twin bit failure can be prevented by the pitch between cylinder-shaped lower electrodes having a value of 2β when more cylinder-shaped lower electrodes are formed within a limited area. - FIG. 8 is an enlarged sectional view of8 of FIG. 6. In detail, the
layer 116 for improving sidewall slope deposited by the CVD method has excellent gap-fill characteristics when it is deposited in thefirst opening 114. Thelayer 116 for improving sidewall slope is not necessarily deposited to a uniform thickness in the first opening, instead its thickness varies, for example, from u1 at the top, u2 at the middle, and u3 at the bottom of the first opening. - As one example, if the
layer 116 for improving sidewall slope having a thickness of 300 Å is deposited at the top u1 of the first opening, the thickness of thelayer 116 for improving sidewall slope deposited at the middle u2 of the first opening is 70-80 Å, and the thickness of thelayer 116 for improving sidewall slope deposited at the bottom u3 of the first opening is less than 30 Å. As a result, the thickness to which thelayer 116 for improving sidewall slope is deposited in thefirst opening 114 varies depending in which area it is deposited. With this feature of thelayer 116, the etch slope of the first opening is improved. - FIG. 9 is a sectional view illustrating the
layer 116 for improving sidewall slope when etch skew occurs in FIG. 6. In detail, even though etch by-products 120 caused by dry etching are formed at the top of the first opening and etch skew occurs, thelayer 116 for improving sidewall slope having excellent gap-fill characteristics compensates a region in which the etch skew occurs. This feature improves the profile of the region of the first opening in which the etch skew occurs. Thus, at the middle of the cylinder-shaped lower electrode, thelayer 116 for improving sidewall slope according to the present invention can prevent twin bit failure or a micro-bridge. - Referring to FIG. 10, a portion of the
layer 116 at the bottom u3 of thefirst opening 114, theetch stopper 108, and thebuffer layer 106 adjacent to the first opening are removed by etching. Thus, asecond opening 118 is formed to expose the buried contact (BC) 104 (a conductive region) to which the cylinder-shaped lower electrode is electrically connected. - The conductive region exposed by the
second opening 118 may be the top surface of theBC 104. The conductive region may be a source region of a transistor of a lower structure instead of the buried contact (BC). - Referring to FIG. 11, a polysilicon layer or other suitable
conductive layer 121 to form the cylinder-shaped lower electrodes 122 (See FIG. 12) is deposited over the resultant structure including thesecond opening 118 to a predetermined thickness. Thus, the slope of thelayer 121 for forming cylinder-shaped lower electrodes is steeper than the slope before thelayer 116 for improving sidewall slope is formed. As a result, the probability of twin bit failure can be reduced. - Referring to FIG. 12, portions of the
layer 121 to form cylinder-shapedlower electrodes 122 over thesacrificial oxide layer 110 are removed by planarization techniques such as a chemical mechanical polishing (CMP) or an etch back process. Thus, cylinder-shapedlower electrodes 122 are formed separated from each other. Here, if the cylinder-shapedlower electrodes 122 are separated by the CMP process, the CMP process can be performed using thesacrificial oxide layer 110 as a polishing stop layer. - Referring to FIG. 13, wet etching is performed on the
semiconductor substrate 100 on which the separated cylinder-shapedlower electrodes 122 are formed, thereby substantially completely removing thesacrificial oxide layer 110. An etching solution such as a buffered oxide etchant (BOE) can be used during the wet etching. Subsequently, theetch stopper 108 and thebuffer layer 106 are removed, thereby completing the cylinder-shapedlower electrodes 122 connected to theBC 104. Thus,lower electrodes 122 of a cylinder-shaped capacitor preventing twin bit failure is completed according to a preferred embodiment of the present invention. The cylinder-shapedlower electrodes 122 according to the present invention can be widely applied to a semiconductor memory device such as a DRAM and a semiconductor device such as a merged DRAM logic (MDL) device. - Thus, with an embodiment of the present invention, the layer for improving sidewall slope having excellent gap-fill characteristics is additionally formed after the first opening for forming a cylinder-shaped capacitor is etched, thereby improving the etch slope of the first opening. Also, the etch profile for a region in which etch skew occurs is improved, and the space between cylinder-shaped lower electrodes is increased, thereby preventing twin bit failure.
- While this invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made thereto without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (20)
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KR2001-674 | 2001-01-05 | ||
KR1020010000674A KR100360414B1 (en) | 2001-01-05 | 2001-01-05 | Method for forming a lower electrode of cylinder type capacitor preventing a twin bit failure |
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US20020090779A1 true US20020090779A1 (en) | 2002-07-11 |
US6458653B1 US6458653B1 (en) | 2002-10-01 |
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US (1) | US6458653B1 (en) |
KR (1) | KR100360414B1 (en) |
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KR100360414B1 (en) | 2002-11-13 |
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