US20020110973A1 - Fabrication method and structure of a flash memory - Google Patents

Fabrication method and structure of a flash memory Download PDF

Info

Publication number
US20020110973A1
US20020110973A1 US09/784,229 US78422901A US2002110973A1 US 20020110973 A1 US20020110973 A1 US 20020110973A1 US 78422901 A US78422901 A US 78422901A US 2002110973 A1 US2002110973 A1 US 2002110973A1
Authority
US
United States
Prior art keywords
shallow trench
trench isolations
trenches
circuit region
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/784,229
Other versions
US6436751B1 (en
Inventor
Jih-Wei Liou
Hwi-Huang Chen
Yen-Chang Chen
Pao-Chuan Lin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to US09/784,229 priority Critical patent/US6436751B1/en
Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, HWI-HUANG, CHEN, YEN-CHANG, LIN, PAO-CHUAN, LIOU, JIH-WEI
Publication of US20020110973A1 publication Critical patent/US20020110973A1/en
Application granted granted Critical
Publication of US6436751B1 publication Critical patent/US6436751B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42Simultaneous manufacture of periphery and memory cells

Definitions

  • the invention relates in general to a method of fabricating a memory. More particularly, this invention relates to a method of fabricating a flash memory.
  • a flash memory is a kind of non-volatile memory (NVM) with the characteristics of a small dimension, fast access speed and low power consumption. Since the data erasing is performed in a “block by block” fashion, the operation speed is faster than other memory.
  • NVM non-volatile memory
  • the basic structure of the flash memory comprises a stacked gate structure assembled by a tunnel oxide layer, a floating gate, a dielectric layer and a control gate, and a source/drain region in the substrate at two sides of the stacked gate structure.
  • the flash memory further comprises a peripheral circuit memory around the memory circuit region to integrate the peripheral devices for data writing/erasing/reading.
  • Flash memories use an intercrossing control gate line and a bit line that connect to the drain region to control the write operation of an individual memory cell, and the source regions at the other side of the control gate are connected to each other.
  • the shallow trench isolations between the gates are removed.
  • An ion implantation step is then performed to form a common source, also referred to as a buried source line.
  • a self-aligned source (SAS) process is performed. That is, the shallow trench isolation between every other pair of gates has to be removed.
  • SAS self-aligned source
  • the shallow trench isolations in both the memory circuit region and the peripheral circuit region are formed in the same photolithography and etching process. Therefore, the depth and topography for the shallow trench isolations in both regions are the same.
  • a high voltage is typically required for the write/erase operation of a flash memory.
  • the depth for the shallow trench isolation in the peripheral circuit region that controls the write/erase function has to be deeper than 0.4 microns to provide a sufficient isolation effect.
  • the invention provides a method of fabricating a flash memory.
  • a plurality of first shallow trench isolations is formed in a memory circuit region on a substrate, and a plurality of second shallow trenches is formed in a peripheral circuit region on the substrate.
  • the second shallow trench isolations are deeper than the first shallow trench isolations.
  • a plurality of stacked gates is formed on the substrate in the memory circuit region along a direction perpendicular to the shallow trench isolations.
  • Each stacked gate comprises a tunneling oxide layer, a floating gate, a dielectric layer and a control gate.
  • the first shallow trench isolations located between every other pair of the stacked gates are removed.
  • a self-aligned source process is performed to form a common source region between every other pair of the stacked gates, while a column of separate drain regions is also formed between every alternate pair of the stacked gates.
  • the drain regions in the same column are separated from each other by the first shallow trench isolations.
  • the invention further provides a structure of a flash memory.
  • a substrate comprises a memory circuit region and a peripheral circuit region comprises a plurality of second shallow trench isolations.
  • the memory circuit region comprises a plurality of stacked gates, preferably parallel to each other on the substrate.
  • a common source and a column of drain regions are formed in the substrate between every alternate pair of the stacked gates.
  • the drain regions in the same column are separated from each other by a plurality of first shallow trench isolations.
  • the peripheral circuit region comprises a plurality of second shallow trench isolations deeper than the first shallow trench isolations.
  • the first shallow trench isolations formed in the memory circuit region are shallower than the shallow trench isolations formed in the peripheral circuit region. Therefore, the damage to the gate during the removal step of the shallow trench isolations in the memory circuit region is minimized, or even prevented.
  • the required width is also reduced, so that the integration of the flash memory is increased.
  • the shallow trench isolations formed in the peripheral circuit are maintained at a required depth, so that the operation speed is not affected while the integration is enhanced.
  • the common source formed after removing the shallow trench isolation region is formed with a less uneven profile, so that the electrical performance is enhanced.
  • FIGS. 1 - 5 are three-dimensional graphs showing the flash memory during different fabrication process stage according to the invention.
  • FIG. 6 and FIG. 7A are top views showing the fabrication process following FIG. 5;
  • FIG. 7B is a cross sectional view along the cutting I-I in FIG. 7A.
  • a substrate 100 having a memory circuit region 113 and a peripheral circuit region 123 is provided.
  • a pad oxide layer 101 and a mask layer 102 for example, a silicon nitride layer, are formed on the substrate 100 .
  • a photoresist layer 104 is formed on the mask layer 102 .
  • the photoresist layer 104 comprises a pattern that expose a portion of the mask layer 102 in the memory circuit region 113 , while the peripheral circuit region 123 is completely covered.
  • the pattern of the photoresist layer 104 expose a plurality of parallel strips of the mask layer 102 as shown in FIG. 1.
  • the exposed mask layer 102 , the pad oxide layer 101 and the substrate 100 under the exposed mask layer 102 are etched to form a plurality of trenches 110 in the memory circuit regions 113 .
  • the trenches 110 are formed as a plurality of parallel strips in the substrate 100 .
  • the trenches 110 have a depth between about 0.1 micron to about 0.3 micron and a width less than about 0.25 micron.
  • the profiles of the trenches 110 are rounded to release stress.
  • the photoresist layer 104 is removed, and a photoresist layer 114 is formed to completely cover the memory circuit region 113 and a portion of the peripheral circuit region 123 .
  • the photoresist layer 114 has a pattern to expose a portion of the mask layer 102 in the peripheral circuit region 123 .
  • the exposed mask layer 102 , the pad oxide layer 101 and the substrate 100 under the exposed mask layer 102 are etched to form at least a trench 120 in the peripheral circuit region 123 .
  • the trench 120 has an inclined sidewall and a rounded surface to release stress.
  • the depth of the trench 120 is larger than about 0.4 micron, and the width thereof is larger than about 0.35 micron.
  • the high operation voltage devices in the peripheral circuit region 123 can thus have a better isolation effect.
  • the photoresist layer 114 is removed to expose the surfaces of the trenches 110 and 120 .
  • a liner oxide layer 125 is formed along the surfaces of the trenches 110 and 120 .
  • the trenches 110 and 120 are then filled with an insulating material as the shallow trench isolations 130 and 140 .
  • the steps of filling the trenches 110 and 120 include forming the insulating material layer on the mask layer 102 to fill the trenches 110 and 120 , followed by a step of chemical mechanical polishing (CMP).
  • the insulating material includes a silicon oxide formed by chemical vapor deposition (CVD). After filling the insulating material, a step of annealing is performed to density the insulating material.
  • the mask layer 102 and the pad oxide layer 101 are then removed to expose the substrate 100 .
  • a plurality of stacked gates 150 are formed in the memory circuit region 113 along a direction perpendicular to the shallow trench isolations 130 .
  • Each of the stacked gates 150 comprises a tunneling oxide layer 152 , a floating gate 154 , a dielectric layer 156 and a control gate 158 .
  • the tunneling oxide layer 152 is formed across each of the shallow trench isolations 130 .
  • the floating gates 154 formed on the tunneling oxide layers 152 comprise polysilicon layers.
  • the dielectric layers 156 for example, a composite layer of oxide/nitride/oxide, are formed on the floating gates 154 .
  • the control gates 158 are formed on the dielectric layers 156 with a material, for example, polysilicon.
  • a photoresist layer 159 (the frames drawn with bold lines) is formed to cover the central portion of the stacked gates 150 .
  • the photoresist layer 159 has an opening over each of the shallow trench isolations 130 between every other pair of the stacked gates 150 .
  • the openings of the photoresist layer 159 are wider than the shallow trench isolations 130 between every pair of the stacked gates 150 to ensure that the shallow trench isolations 130 are completely exposed.
  • an edge portion of the control gates 158 is exposed.
  • the exposed shallow trench isolations 130 are then removed to expose the substrate 100 in the trench 110 at which the shallow trench isolations 130 are removed.
  • the photoresist layer 159 is removed.
  • the exposed substrate 100 is doped using the stacked gates 150 as a mask.
  • a common source region 170 is formed in the substrate 100 between every other pair of the stacked gates 150 .
  • a column of a plurality of drain regions 180 is formed in the substrate 100 between every alternate pair of the stacked gates 158 .
  • the drain regions 180 in the same column are separated from each other by the remaining shallow trench isolations 130 .
  • the shallow trench isolations formed in the memory circuit region are shallower and narrower than the shallow trench isolations formed in the peripheral circuit region; therefore, the integration is enhanced without affecting the operation of the high voltage devices formed in the peripheral circuit region.
  • the smaller shallow trench isolations to be removed can prevent damage of the control gates of the stacked gates.

Abstract

A fabrication method and a structure of a flash memory. Several first shallow trench isolations and second shallow trench isolations are formed in a memory circuit region and a peripheral circuit region of a substrate, respectively. The first shallow trench isolations are shallower than the second shallow trench isolations. Several gates are formed along a direction perpendicular to the substrate in the memory circuit region. A self-aligned source region process is performed to remove the isolation layer within every other first shallow trench isolations between the gates. A common source region and a column of separate drain regions are thus alternatively formed between the gates. The drain regions in the same column are isolated by the first shallow trench isolations.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The invention relates in general to a method of fabricating a memory. More particularly, this invention relates to a method of fabricating a flash memory. [0002]
  • 2. Description of the Related Art [0003]
  • A flash memory is a kind of non-volatile memory (NVM) with the characteristics of a small dimension, fast access speed and low power consumption. Since the data erasing is performed in a “block by block” fashion, the operation speed is faster than other memory. [0004]
  • The basic structure of the flash memory comprises a stacked gate structure assembled by a tunnel oxide layer, a floating gate, a dielectric layer and a control gate, and a source/drain region in the substrate at two sides of the stacked gate structure. In addition, the flash memory further comprises a peripheral circuit memory around the memory circuit region to integrate the peripheral devices for data writing/erasing/reading. [0005]
  • Many flash memories use an intercrossing control gate line and a bit line that connect to the drain region to control the write operation of an individual memory cell, and the source regions at the other side of the control gate are connected to each other. In this kind of flash memory, in order to save the volume occupied by the interconnect structure between the source region, the shallow trench isolations between the gates are removed. An ion implantation step is then performed to form a common source, also referred to as a buried source line. In this method, a self-aligned source (SAS) process is performed. That is, the shallow trench isolation between every other pair of gates has to be removed. [0006]
  • In the conventional fabrication process of a flash memory, the shallow trench isolations in both the memory circuit region and the peripheral circuit region are formed in the same photolithography and etching process. Therefore, the depth and topography for the shallow trench isolations in both regions are the same. A high voltage is typically required for the write/erase operation of a flash memory. Thus, for a process under 0.25 micron, the depth for the shallow trench isolation in the peripheral circuit region that controls the write/erase function has to be deeper than 0.4 microns to provide a sufficient isolation effect. [0007]
  • In the self-aligned source process, as the photoresist layer covering the gates is always narrower than the width of the gate, a portion of the gate is exposed. In order to remove a shallow trench isolation deeper than 0.4 micron, the exposed gate is inevitably damaged. In addition, as the shallow trench isolation is typically formed with an inclined sidewall and a rounded bottom surface to release stress, an isolation structure having a width of about 0.35 micron is required to have a depth larger than 0.4 micron. The above features decrease the integration of the flash memory. [0008]
  • SUMMARY OF THE INVENTION
  • The invention provides a method of fabricating a flash memory. A plurality of first shallow trench isolations is formed in a memory circuit region on a substrate, and a plurality of second shallow trenches is formed in a peripheral circuit region on the substrate. The second shallow trench isolations are deeper than the first shallow trench isolations. A plurality of stacked gates is formed on the substrate in the memory circuit region along a direction perpendicular to the shallow trench isolations. Each stacked gate comprises a tunneling oxide layer, a floating gate, a dielectric layer and a control gate. The first shallow trench isolations located between every other pair of the stacked gates are removed. A self-aligned source process is performed to form a common source region between every other pair of the stacked gates, while a column of separate drain regions is also formed between every alternate pair of the stacked gates. The drain regions in the same column are separated from each other by the first shallow trench isolations. [0009]
  • The invention further provides a structure of a flash memory. A substrate comprises a memory circuit region and a peripheral circuit region comprises a plurality of second shallow trench isolations. The memory circuit region comprises a plurality of stacked gates, preferably parallel to each other on the substrate. A common source and a column of drain regions are formed in the substrate between every alternate pair of the stacked gates. The drain regions in the same column are separated from each other by a plurality of first shallow trench isolations. The peripheral circuit region comprises a plurality of second shallow trench isolations deeper than the first shallow trench isolations. [0010]
  • As mentioned above, the first shallow trench isolations formed in the memory circuit region are shallower than the shallow trench isolations formed in the peripheral circuit region. Therefore, the damage to the gate during the removal step of the shallow trench isolations in the memory circuit region is minimized, or even prevented. In addition, as the shallow trench isolations formed in the memory circuit region are shallower, the required width is also reduced, so that the integration of the flash memory is increased. The shallow trench isolations formed in the peripheral circuit are maintained at a required depth, so that the operation speed is not affected while the integration is enhanced. Furthermore, as the shallow trench isolations are shallower in the memory circuit region, the common source formed after removing the shallow trench isolation region is formed with a less uneven profile, so that the electrical performance is enhanced. [0011]
  • Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.[0012]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. [0013] 1-5 are three-dimensional graphs showing the flash memory during different fabrication process stage according to the invention;
  • FIG. 6 and FIG. 7A are top views showing the fabrication process following FIG. 5; and [0014]
  • FIG. 7B is a cross sectional view along the cutting I-I in FIG. 7A.[0015]
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • In FIG. 1, a [0016] substrate 100 having a memory circuit region 113 and a peripheral circuit region 123 is provided. A pad oxide layer 101 and a mask layer 102, for example, a silicon nitride layer, are formed on the substrate 100. A photoresist layer 104 is formed on the mask layer 102. The photoresist layer 104 comprises a pattern that expose a portion of the mask layer 102 in the memory circuit region 113, while the peripheral circuit region 123 is completely covered. Preferably, the pattern of the photoresist layer 104 expose a plurality of parallel strips of the mask layer 102 as shown in FIG. 1. The exposed mask layer 102, the pad oxide layer 101 and the substrate 100 under the exposed mask layer 102 are etched to form a plurality of trenches 110 in the memory circuit regions 113. Again, the trenches 110 are formed as a plurality of parallel strips in the substrate 100. Preferably, the trenches 110 have a depth between about 0.1 micron to about 0.3 micron and a width less than about 0.25 micron. The profiles of the trenches 110 are rounded to release stress.
  • In FIG. 2, the [0017] photoresist layer 104 is removed, and a photoresist layer 114 is formed to completely cover the memory circuit region 113 and a portion of the peripheral circuit region 123. The photoresist layer 114 has a pattern to expose a portion of the mask layer 102 in the peripheral circuit region 123. Using the photoresist layer 114 as a mask, the exposed mask layer 102, the pad oxide layer 101 and the substrate 100 under the exposed mask layer 102 are etched to form at least a trench 120 in the peripheral circuit region 123. The trench 120 has an inclined sidewall and a rounded surface to release stress. The depth of the trench 120 is larger than about 0.4 micron, and the width thereof is larger than about 0.35 micron. The high operation voltage devices in the peripheral circuit region 123 can thus have a better isolation effect.
  • In FIG. 3, the [0018] photoresist layer 114 is removed to expose the surfaces of the trenches 110 and 120. In FIG. 4, a liner oxide layer 125 is formed along the surfaces of the trenches 110 and 120. The trenches 110 and 120 are then filled with an insulating material as the shallow trench isolations 130 and 140. The steps of filling the trenches 110 and 120 include forming the insulating material layer on the mask layer 102 to fill the trenches 110 and 120, followed by a step of chemical mechanical polishing (CMP). The insulating material includes a silicon oxide formed by chemical vapor deposition (CVD). After filling the insulating material, a step of annealing is performed to density the insulating material. The mask layer 102 and the pad oxide layer 101 are then removed to expose the substrate 100.
  • In FIG. 5, a plurality of stacked [0019] gates 150 are formed in the memory circuit region 113 along a direction perpendicular to the shallow trench isolations 130. Each of the stacked gates 150 comprises a tunneling oxide layer 152, a floating gate 154, a dielectric layer 156 and a control gate 158. The tunneling oxide layer 152 is formed across each of the shallow trench isolations 130. The floating gates 154 formed on the tunneling oxide layers 152 comprise polysilicon layers. The dielectric layers 156, for example, a composite layer of oxide/nitride/oxide, are formed on the floating gates 154. The control gates 158 are formed on the dielectric layers 156 with a material, for example, polysilicon.
  • In FIG. 6, a self-aligned source process is performed. A photoresist layer [0020] 159 (the frames drawn with bold lines) is formed to cover the central portion of the stacked gates 150. The photoresist layer 159 has an opening over each of the shallow trench isolations 130 between every other pair of the stacked gates 150. The openings of the photoresist layer 159 are wider than the shallow trench isolations 130 between every pair of the stacked gates 150 to ensure that the shallow trench isolations 130 are completely exposed. As a result, an edge portion of the control gates 158 is exposed. The exposed shallow trench isolations 130 are then removed to expose the substrate 100 in the trench 110 at which the shallow trench isolations 130 are removed.
  • In FIG. 7A, the [0021] photoresist layer 159 is removed. The exposed substrate 100 is doped using the stacked gates 150 as a mask. As a result, a common source region 170 is formed in the substrate 100 between every other pair of the stacked gates 150. Simultaneously, a column of a plurality of drain regions 180 is formed in the substrate 100 between every alternate pair of the stacked gates 158. The drain regions 180 in the same column are separated from each other by the remaining shallow trench isolations 130.
  • In the invention, the shallow trench isolations formed in the memory circuit region are shallower and narrower than the shallow trench isolations formed in the peripheral circuit region; therefore, the integration is enhanced without affecting the operation of the high voltage devices formed in the peripheral circuit region. [0022]
  • In addition to the enhancement of the integration, the smaller shallow trench isolations to be removed can prevent damage of the control gates of the stacked gates. [0023]
  • Other embodiments of the invention will appear to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples to be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims. [0024]

Claims (20)

What is claimed is:
1. A method of fabricating a flash memory, comprising:
providing a substrate having a memory circuit region and a peripheral circuit region;
forming a plurality of first shallow trench isolations and a plurality of second shallow trench isolations in the memory circuit region and the peripheral circuit region, respectively, wherein the first shallow trench isolations are shallower than the second shallow trench isolations;
forming a plurality of stacked gates on the substrate in the memory circuit region, wherein each stack gate is formed by stacking a plurality of tunnel oxide layers, a plurality of floating gates, a dielectric layer, and a control gate, with the control gate being stacked along a direction perpendicular to the first shallow trench isolations;
removing the first shallow trench isolations between every other pair of the stacked gates; and
performing a self-aligned source process to form a common source region and a column of a plurality of drain regions in the substrate between alternate pairs of the stacked gates.
2. The method according to claim 1, wherein the step of forming the first and second shallow trench isolations comprises a step of forming the first and second shallow trench isolations with rounded surfaces.
3. The method according to claim 1, wherein the step of forming the first and second shallow trench isolations further comprises:
forming a mask layer on the substrate;
performing two photolithography and etching processes to form a plurality of first trenches in the memory circuit region and at least a second trench in the peripheral circuit region, wherein the first trenches are shallower than the second trench;
filling the first and second trenches with an insulating material; and
removing the mask layer.
4. The method according to claim 3, comprising further forming a pad oxide layer between the substrate and the mask layer.
5. The method according to claim 3, comprising further forming a liner oxide layer along the surfaces of the first and second trenches before filling the first and the second trenches.
6. The method according to claim 3, wherein filling the first and second trenches further comprises:
forming an insulating material over the substrate to fill the first and the second trenches; and
performing chemical mechanical polishing to remove the insulating material overfilling the first and the second trenches.
7. The method according to claim 3, wherein forming the insulating material includes forming a silicon oxide layer.
8. The method according to claim 3, comprising further annealing to density the insulating material.
9. The method according to claim 1, wherein forming the first shallow trench isolations comprises forming the first shallow trench isolation with a depth of about 0.1 micron to about 0.3 micron.
10. The method according to claim 1, wherein the step of forming the first shallow trench isolations comprises forming the first shallow trench isolation with a width smaller than about 0.25 micron.
11. The method according to claim 1, wherein the floating gate and the control gate include polysilicon.
12. A structure of a flash memory, comprising:
a substrate having a memory circuit region and a peripheral circuit region, wherein the memory cell region of the substrate having a plurality of first trenches, the peripheral circuit region of the substrate having a plurality of second trenches, the first trenches being shallower than the second trenches;
a plurality of first trench isolation layers, wherein each of the first isolation layers is located in a part of each of the first trenches; a plurality of second shallow trench isolation layers, wherein the second shallow trench isolation layers are located in the second trenches;
a plurality of stacked gates on the substrate in the memory circuit region along a direction perpendicular to the first shallow trench isolations; and
a plurality of common source regions and drain regions in the substrate between every alternate pair of the stacked gates;
wherein each of the first shallow trench isolation layers is formed on a side where the drain regions are formed.
13. The structure according to claim 12, wherein the first and second shallow trench isolations have rounded surfaces.
14. The structure according to claim 12, wherein the first shallow trench isolations have a depth of about 0.1 micron to about 0.3 micron.
15. The structure according to claim 12, wherein the first shallow trench isolations each have a width less than about 0.25 micron.
16. The structure according to claim 12, wherein the first and second shallow trench isolations comprise silicon oxide.
17. The structure according to claim 12, wherein the first and second shallow trench isolations further comprise a liner oxide layer.
18. The structure according to claim 12, wherein each of the stacked gates further comprises a tunneling oxide layer, a floating gate, a dielectric layer and a control gate.
19. The structure according to claim 18, wherein the floating and control gates comprise polysilicon.
20. The structure according to claim 18, wherein the dielectric layers comprise a composite layer of oxide/nitride/oxide.
US09/784,229 2001-02-13 2001-02-13 Fabrication method and structure of a flash memory Expired - Lifetime US6436751B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/784,229 US6436751B1 (en) 2001-02-13 2001-02-13 Fabrication method and structure of a flash memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/784,229 US6436751B1 (en) 2001-02-13 2001-02-13 Fabrication method and structure of a flash memory

Publications (2)

Publication Number Publication Date
US20020110973A1 true US20020110973A1 (en) 2002-08-15
US6436751B1 US6436751B1 (en) 2002-08-20

Family

ID=25131759

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/784,229 Expired - Lifetime US6436751B1 (en) 2001-02-13 2001-02-13 Fabrication method and structure of a flash memory

Country Status (1)

Country Link
US (1) US6436751B1 (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050023603A1 (en) * 2001-08-30 2005-02-03 Micron Technology, Inc. Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators
US20050029599A1 (en) * 1999-09-01 2005-02-10 Tran Luan C. Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry
US20050180215A1 (en) * 2003-06-27 2005-08-18 Danny Shum One transistor flash memory cell
EP1770772A1 (en) * 2005-09-30 2007-04-04 STMicroelectronics S.r.l. Process for manufacturing a non-volatile memory device
US20070170492A1 (en) * 2005-02-23 2007-07-26 Micron Technology, Inc. Germanium-silicon-carbide floating gates in memories
US20080293197A1 (en) * 2007-05-25 2008-11-27 Young-Sun Ko Method of manufacturing semiconductor memory device
KR100959716B1 (en) * 2002-12-30 2010-05-25 동부일렉트로닉스 주식회사 Manufacturing method of Flash memory
US7759724B2 (en) 2001-08-30 2010-07-20 Micron Technology, Inc. Memory cells having gate structure with multiple gates and multiple materials between the gates
US20110079871A1 (en) * 2009-10-05 2011-04-07 Hynix Semiconductor Inc. Semiconductor device and method of fabricating the same
US20120094450A1 (en) * 2010-10-19 2012-04-19 Eon Silicon Solution Inc. Manufacturing method of multi-level cell nor flash memory
US20120319231A1 (en) * 2007-07-13 2012-12-20 Marvell Wold Trade Ltd. Microelectronic Device Including Shallow Trench Isolation Structures Having Rounded Bottom Surfaces
CN112331611A (en) * 2020-11-30 2021-02-05 上海华力微电子有限公司 Preparation method of shallow trench isolation
CN113192960A (en) * 2021-04-27 2021-07-30 上海华虹宏力半导体制造有限公司 Forming method of flash memory

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6624022B1 (en) 2000-08-29 2003-09-23 Micron Technology, Inc. Method of forming FLASH memory
JP2003037193A (en) * 2001-07-25 2003-02-07 Mitsubishi Electric Corp Non-volatile semiconductor storage device and manufacturing method therefor
KR100402392B1 (en) * 2001-11-06 2003-10-17 삼성전자주식회사 Semiconductor device having trench isolation structure and method of fabricating the same
TW588413B (en) * 2002-11-07 2004-05-21 Winbond Electronics Corp Manufacturing method and device of memory with different depths of isolation trench
DE10260185B4 (en) * 2002-12-20 2007-04-12 Infineon Technologies Ag Semiconductor memory with vertical charge trapping memory cells and method for its production
US7074682B2 (en) * 2003-10-01 2006-07-11 Dongbuanam Semiconductor Inc. Method for fabricating a semiconductor device having self aligned source (SAS) crossing trench
KR100655435B1 (en) * 2005-08-04 2006-12-08 삼성전자주식회사 Nonvolatile memory device and method of fabricating the same
KR100723767B1 (en) * 2005-11-10 2007-05-30 주식회사 하이닉스반도체 Flash memory device and manufacturing method thereof
KR100900301B1 (en) 2007-04-27 2009-06-02 삼성전자주식회사 Memory Semiconductor Devices With Buried Bit Line And Methods Of Fabricating The Same
KR100940644B1 (en) * 2007-12-27 2010-02-05 주식회사 동부하이텍 Semiconductor device and method for fabricating the same
CN103579247B (en) * 2012-07-31 2016-08-03 宜扬科技股份有限公司 A kind of Nonvolatile memory and operational approach, manufacture method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5175122A (en) * 1991-06-28 1992-12-29 Digital Equipment Corporation Planarization process for trench isolation in integrated circuit manufacture
JPH0513566A (en) * 1991-07-01 1993-01-22 Toshiba Corp Manufacture of semiconductor device
US6265292B1 (en) * 1999-07-12 2001-07-24 Intel Corporation Method of fabrication of a novel flash integrated circuit
US6261905B1 (en) * 2000-04-28 2001-07-17 Taiwan Semiconductor Manufacturing Company Flash memory structure with stacking gate formed using damascene-like structure

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050029599A1 (en) * 1999-09-01 2005-02-10 Tran Luan C. Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry
US6914287B2 (en) * 1999-09-01 2005-07-05 Micron Technology, Inc Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry
US7759724B2 (en) 2001-08-30 2010-07-20 Micron Technology, Inc. Memory cells having gate structure with multiple gates and multiple materials between the gates
US20050023603A1 (en) * 2001-08-30 2005-02-03 Micron Technology, Inc. Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators
US7504687B2 (en) * 2001-08-30 2009-03-17 Micron Technology, Inc. Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators
KR100959716B1 (en) * 2002-12-30 2010-05-25 동부일렉트로닉스 주식회사 Manufacturing method of Flash memory
US20050180215A1 (en) * 2003-06-27 2005-08-18 Danny Shum One transistor flash memory cell
US7190022B2 (en) * 2003-06-27 2007-03-13 Infineon Technologies Ag One transistor flash memory cell
US20070170492A1 (en) * 2005-02-23 2007-07-26 Micron Technology, Inc. Germanium-silicon-carbide floating gates in memories
US7879674B2 (en) 2005-02-23 2011-02-01 Micron Technology, Inc. Germanium-silicon-carbide floating gates in memories
EP1770772A1 (en) * 2005-09-30 2007-04-04 STMicroelectronics S.r.l. Process for manufacturing a non-volatile memory device
US7871879B2 (en) * 2007-05-25 2011-01-18 Dongbu Hitek Co., Ltd. Method of manufacturing semiconductor memory device
US20080293197A1 (en) * 2007-05-25 2008-11-27 Young-Sun Ko Method of manufacturing semiconductor memory device
US20120319231A1 (en) * 2007-07-13 2012-12-20 Marvell Wold Trade Ltd. Microelectronic Device Including Shallow Trench Isolation Structures Having Rounded Bottom Surfaces
US9142445B2 (en) 2007-07-13 2015-09-22 Marvell World Trade Ltd. Method and apparatus for forming shallow trench isolation structures having rounded corners
US20110079871A1 (en) * 2009-10-05 2011-04-07 Hynix Semiconductor Inc. Semiconductor device and method of fabricating the same
US8741734B2 (en) * 2009-10-05 2014-06-03 Hynix Semiconductor Inc. Semiconductor device and method of fabricating the same
US20120094450A1 (en) * 2010-10-19 2012-04-19 Eon Silicon Solution Inc. Manufacturing method of multi-level cell nor flash memory
CN112331611A (en) * 2020-11-30 2021-02-05 上海华力微电子有限公司 Preparation method of shallow trench isolation
CN113192960A (en) * 2021-04-27 2021-07-30 上海华虹宏力半导体制造有限公司 Forming method of flash memory

Also Published As

Publication number Publication date
US6436751B1 (en) 2002-08-20

Similar Documents

Publication Publication Date Title
US6436751B1 (en) Fabrication method and structure of a flash memory
KR100350055B1 (en) Semiconductor device having multi-gate dielectric layers and method of fabricating the same
US7160780B2 (en) Method of manufacturing a fin field effect transistor
US8048737B2 (en) Semiconductor device and method of fabricating the same
US7384843B2 (en) Method of fabricating flash memory device including control gate extensions
US6153472A (en) Method for fabricating a flash memory
US7371638B2 (en) Nonvolatile memory cells having high control gate coupling ratios using grooved floating gates and methods of forming same
US6570215B2 (en) Nonvolatile memories with floating gate spacers, and methods of fabrication
KR100684886B1 (en) Flash memory device and method of fabricating the same
US20040061165A1 (en) Floating gate memory fabrication methods comprising a field dielectric etch with a horizontal etch component
US7585724B2 (en) FLASH memory device and method of manufacture
US20040145020A1 (en) Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby
US7510934B2 (en) Methods of fabricating nonvolatile memory devices
US20060258092A1 (en) Semiconductor integrated circuit device and manufacturing method thereof
US20060011971A1 (en) Nonvolatile semiconductor memory device and method of manufacturing the same
US20070128797A1 (en) Flash memory device and method for fabricating the same
US7335940B2 (en) Flash memory and manufacturing method thereof
JP2003289114A (en) Semiconductor storage device and method for manufacturing the same
KR100655283B1 (en) Electrically Erasable Programmable Read-Only MemoryEEPROM Device And Method Of Fabricating The Same
US7205208B2 (en) Method of manufacturing a semiconductor device
KR100602126B1 (en) Flash memory cell and method for manufacturing the same
US7820504B2 (en) Method for manufacturing differential isolation structures in a semiconductor electronic device and corresponding structure
US20070262476A1 (en) Method for providing STI structures with high coupling ratio in integrated circuit manufacturing
CN115732397A (en) Semiconductor structure and forming method thereof
KR100943482B1 (en) Method for fabricating semiconductor device having flash memory cell

Legal Events

Date Code Title Description
AS Assignment

Owner name: UNITED MICROELECTRONICS CORP., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIOU, JIH-WEI;CHEN, HWI-HUANG;CHEN, YEN-CHANG;AND OTHERS;REEL/FRAME:011558/0027

Effective date: 20010205

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12