US20020110973A1 - Fabrication method and structure of a flash memory - Google Patents
Fabrication method and structure of a flash memory Download PDFInfo
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- US20020110973A1 US20020110973A1 US09/784,229 US78422901A US2002110973A1 US 20020110973 A1 US20020110973 A1 US 20020110973A1 US 78422901 A US78422901 A US 78422901A US 2002110973 A1 US2002110973 A1 US 2002110973A1
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- trench isolations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
Definitions
- the invention relates in general to a method of fabricating a memory. More particularly, this invention relates to a method of fabricating a flash memory.
- a flash memory is a kind of non-volatile memory (NVM) with the characteristics of a small dimension, fast access speed and low power consumption. Since the data erasing is performed in a “block by block” fashion, the operation speed is faster than other memory.
- NVM non-volatile memory
- the basic structure of the flash memory comprises a stacked gate structure assembled by a tunnel oxide layer, a floating gate, a dielectric layer and a control gate, and a source/drain region in the substrate at two sides of the stacked gate structure.
- the flash memory further comprises a peripheral circuit memory around the memory circuit region to integrate the peripheral devices for data writing/erasing/reading.
- Flash memories use an intercrossing control gate line and a bit line that connect to the drain region to control the write operation of an individual memory cell, and the source regions at the other side of the control gate are connected to each other.
- the shallow trench isolations between the gates are removed.
- An ion implantation step is then performed to form a common source, also referred to as a buried source line.
- a self-aligned source (SAS) process is performed. That is, the shallow trench isolation between every other pair of gates has to be removed.
- SAS self-aligned source
- the shallow trench isolations in both the memory circuit region and the peripheral circuit region are formed in the same photolithography and etching process. Therefore, the depth and topography for the shallow trench isolations in both regions are the same.
- a high voltage is typically required for the write/erase operation of a flash memory.
- the depth for the shallow trench isolation in the peripheral circuit region that controls the write/erase function has to be deeper than 0.4 microns to provide a sufficient isolation effect.
- the invention provides a method of fabricating a flash memory.
- a plurality of first shallow trench isolations is formed in a memory circuit region on a substrate, and a plurality of second shallow trenches is formed in a peripheral circuit region on the substrate.
- the second shallow trench isolations are deeper than the first shallow trench isolations.
- a plurality of stacked gates is formed on the substrate in the memory circuit region along a direction perpendicular to the shallow trench isolations.
- Each stacked gate comprises a tunneling oxide layer, a floating gate, a dielectric layer and a control gate.
- the first shallow trench isolations located between every other pair of the stacked gates are removed.
- a self-aligned source process is performed to form a common source region between every other pair of the stacked gates, while a column of separate drain regions is also formed between every alternate pair of the stacked gates.
- the drain regions in the same column are separated from each other by the first shallow trench isolations.
- the invention further provides a structure of a flash memory.
- a substrate comprises a memory circuit region and a peripheral circuit region comprises a plurality of second shallow trench isolations.
- the memory circuit region comprises a plurality of stacked gates, preferably parallel to each other on the substrate.
- a common source and a column of drain regions are formed in the substrate between every alternate pair of the stacked gates.
- the drain regions in the same column are separated from each other by a plurality of first shallow trench isolations.
- the peripheral circuit region comprises a plurality of second shallow trench isolations deeper than the first shallow trench isolations.
- the first shallow trench isolations formed in the memory circuit region are shallower than the shallow trench isolations formed in the peripheral circuit region. Therefore, the damage to the gate during the removal step of the shallow trench isolations in the memory circuit region is minimized, or even prevented.
- the required width is also reduced, so that the integration of the flash memory is increased.
- the shallow trench isolations formed in the peripheral circuit are maintained at a required depth, so that the operation speed is not affected while the integration is enhanced.
- the common source formed after removing the shallow trench isolation region is formed with a less uneven profile, so that the electrical performance is enhanced.
- FIGS. 1 - 5 are three-dimensional graphs showing the flash memory during different fabrication process stage according to the invention.
- FIG. 6 and FIG. 7A are top views showing the fabrication process following FIG. 5;
- FIG. 7B is a cross sectional view along the cutting I-I in FIG. 7A.
- a substrate 100 having a memory circuit region 113 and a peripheral circuit region 123 is provided.
- a pad oxide layer 101 and a mask layer 102 for example, a silicon nitride layer, are formed on the substrate 100 .
- a photoresist layer 104 is formed on the mask layer 102 .
- the photoresist layer 104 comprises a pattern that expose a portion of the mask layer 102 in the memory circuit region 113 , while the peripheral circuit region 123 is completely covered.
- the pattern of the photoresist layer 104 expose a plurality of parallel strips of the mask layer 102 as shown in FIG. 1.
- the exposed mask layer 102 , the pad oxide layer 101 and the substrate 100 under the exposed mask layer 102 are etched to form a plurality of trenches 110 in the memory circuit regions 113 .
- the trenches 110 are formed as a plurality of parallel strips in the substrate 100 .
- the trenches 110 have a depth between about 0.1 micron to about 0.3 micron and a width less than about 0.25 micron.
- the profiles of the trenches 110 are rounded to release stress.
- the photoresist layer 104 is removed, and a photoresist layer 114 is formed to completely cover the memory circuit region 113 and a portion of the peripheral circuit region 123 .
- the photoresist layer 114 has a pattern to expose a portion of the mask layer 102 in the peripheral circuit region 123 .
- the exposed mask layer 102 , the pad oxide layer 101 and the substrate 100 under the exposed mask layer 102 are etched to form at least a trench 120 in the peripheral circuit region 123 .
- the trench 120 has an inclined sidewall and a rounded surface to release stress.
- the depth of the trench 120 is larger than about 0.4 micron, and the width thereof is larger than about 0.35 micron.
- the high operation voltage devices in the peripheral circuit region 123 can thus have a better isolation effect.
- the photoresist layer 114 is removed to expose the surfaces of the trenches 110 and 120 .
- a liner oxide layer 125 is formed along the surfaces of the trenches 110 and 120 .
- the trenches 110 and 120 are then filled with an insulating material as the shallow trench isolations 130 and 140 .
- the steps of filling the trenches 110 and 120 include forming the insulating material layer on the mask layer 102 to fill the trenches 110 and 120 , followed by a step of chemical mechanical polishing (CMP).
- the insulating material includes a silicon oxide formed by chemical vapor deposition (CVD). After filling the insulating material, a step of annealing is performed to density the insulating material.
- the mask layer 102 and the pad oxide layer 101 are then removed to expose the substrate 100 .
- a plurality of stacked gates 150 are formed in the memory circuit region 113 along a direction perpendicular to the shallow trench isolations 130 .
- Each of the stacked gates 150 comprises a tunneling oxide layer 152 , a floating gate 154 , a dielectric layer 156 and a control gate 158 .
- the tunneling oxide layer 152 is formed across each of the shallow trench isolations 130 .
- the floating gates 154 formed on the tunneling oxide layers 152 comprise polysilicon layers.
- the dielectric layers 156 for example, a composite layer of oxide/nitride/oxide, are formed on the floating gates 154 .
- the control gates 158 are formed on the dielectric layers 156 with a material, for example, polysilicon.
- a photoresist layer 159 (the frames drawn with bold lines) is formed to cover the central portion of the stacked gates 150 .
- the photoresist layer 159 has an opening over each of the shallow trench isolations 130 between every other pair of the stacked gates 150 .
- the openings of the photoresist layer 159 are wider than the shallow trench isolations 130 between every pair of the stacked gates 150 to ensure that the shallow trench isolations 130 are completely exposed.
- an edge portion of the control gates 158 is exposed.
- the exposed shallow trench isolations 130 are then removed to expose the substrate 100 in the trench 110 at which the shallow trench isolations 130 are removed.
- the photoresist layer 159 is removed.
- the exposed substrate 100 is doped using the stacked gates 150 as a mask.
- a common source region 170 is formed in the substrate 100 between every other pair of the stacked gates 150 .
- a column of a plurality of drain regions 180 is formed in the substrate 100 between every alternate pair of the stacked gates 158 .
- the drain regions 180 in the same column are separated from each other by the remaining shallow trench isolations 130 .
- the shallow trench isolations formed in the memory circuit region are shallower and narrower than the shallow trench isolations formed in the peripheral circuit region; therefore, the integration is enhanced without affecting the operation of the high voltage devices formed in the peripheral circuit region.
- the smaller shallow trench isolations to be removed can prevent damage of the control gates of the stacked gates.
Abstract
A fabrication method and a structure of a flash memory. Several first shallow trench isolations and second shallow trench isolations are formed in a memory circuit region and a peripheral circuit region of a substrate, respectively. The first shallow trench isolations are shallower than the second shallow trench isolations. Several gates are formed along a direction perpendicular to the substrate in the memory circuit region. A self-aligned source region process is performed to remove the isolation layer within every other first shallow trench isolations between the gates. A common source region and a column of separate drain regions are thus alternatively formed between the gates. The drain regions in the same column are isolated by the first shallow trench isolations.
Description
- 1. Field of the Invention
- The invention relates in general to a method of fabricating a memory. More particularly, this invention relates to a method of fabricating a flash memory.
- 2. Description of the Related Art
- A flash memory is a kind of non-volatile memory (NVM) with the characteristics of a small dimension, fast access speed and low power consumption. Since the data erasing is performed in a “block by block” fashion, the operation speed is faster than other memory.
- The basic structure of the flash memory comprises a stacked gate structure assembled by a tunnel oxide layer, a floating gate, a dielectric layer and a control gate, and a source/drain region in the substrate at two sides of the stacked gate structure. In addition, the flash memory further comprises a peripheral circuit memory around the memory circuit region to integrate the peripheral devices for data writing/erasing/reading.
- Many flash memories use an intercrossing control gate line and a bit line that connect to the drain region to control the write operation of an individual memory cell, and the source regions at the other side of the control gate are connected to each other. In this kind of flash memory, in order to save the volume occupied by the interconnect structure between the source region, the shallow trench isolations between the gates are removed. An ion implantation step is then performed to form a common source, also referred to as a buried source line. In this method, a self-aligned source (SAS) process is performed. That is, the shallow trench isolation between every other pair of gates has to be removed.
- In the conventional fabrication process of a flash memory, the shallow trench isolations in both the memory circuit region and the peripheral circuit region are formed in the same photolithography and etching process. Therefore, the depth and topography for the shallow trench isolations in both regions are the same. A high voltage is typically required for the write/erase operation of a flash memory. Thus, for a process under 0.25 micron, the depth for the shallow trench isolation in the peripheral circuit region that controls the write/erase function has to be deeper than 0.4 microns to provide a sufficient isolation effect.
- In the self-aligned source process, as the photoresist layer covering the gates is always narrower than the width of the gate, a portion of the gate is exposed. In order to remove a shallow trench isolation deeper than 0.4 micron, the exposed gate is inevitably damaged. In addition, as the shallow trench isolation is typically formed with an inclined sidewall and a rounded bottom surface to release stress, an isolation structure having a width of about 0.35 micron is required to have a depth larger than 0.4 micron. The above features decrease the integration of the flash memory.
- The invention provides a method of fabricating a flash memory. A plurality of first shallow trench isolations is formed in a memory circuit region on a substrate, and a plurality of second shallow trenches is formed in a peripheral circuit region on the substrate. The second shallow trench isolations are deeper than the first shallow trench isolations. A plurality of stacked gates is formed on the substrate in the memory circuit region along a direction perpendicular to the shallow trench isolations. Each stacked gate comprises a tunneling oxide layer, a floating gate, a dielectric layer and a control gate. The first shallow trench isolations located between every other pair of the stacked gates are removed. A self-aligned source process is performed to form a common source region between every other pair of the stacked gates, while a column of separate drain regions is also formed between every alternate pair of the stacked gates. The drain regions in the same column are separated from each other by the first shallow trench isolations.
- The invention further provides a structure of a flash memory. A substrate comprises a memory circuit region and a peripheral circuit region comprises a plurality of second shallow trench isolations. The memory circuit region comprises a plurality of stacked gates, preferably parallel to each other on the substrate. A common source and a column of drain regions are formed in the substrate between every alternate pair of the stacked gates. The drain regions in the same column are separated from each other by a plurality of first shallow trench isolations. The peripheral circuit region comprises a plurality of second shallow trench isolations deeper than the first shallow trench isolations.
- As mentioned above, the first shallow trench isolations formed in the memory circuit region are shallower than the shallow trench isolations formed in the peripheral circuit region. Therefore, the damage to the gate during the removal step of the shallow trench isolations in the memory circuit region is minimized, or even prevented. In addition, as the shallow trench isolations formed in the memory circuit region are shallower, the required width is also reduced, so that the integration of the flash memory is increased. The shallow trench isolations formed in the peripheral circuit are maintained at a required depth, so that the operation speed is not affected while the integration is enhanced. Furthermore, as the shallow trench isolations are shallower in the memory circuit region, the common source formed after removing the shallow trench isolation region is formed with a less uneven profile, so that the electrical performance is enhanced.
- Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
- FIGS.1-5 are three-dimensional graphs showing the flash memory during different fabrication process stage according to the invention;
- FIG. 6 and FIG. 7A are top views showing the fabrication process following FIG. 5; and
- FIG. 7B is a cross sectional view along the cutting I-I in FIG. 7A.
- In FIG. 1, a
substrate 100 having amemory circuit region 113 and aperipheral circuit region 123 is provided. Apad oxide layer 101 and amask layer 102, for example, a silicon nitride layer, are formed on thesubstrate 100. Aphotoresist layer 104 is formed on themask layer 102. Thephotoresist layer 104 comprises a pattern that expose a portion of themask layer 102 in thememory circuit region 113, while theperipheral circuit region 123 is completely covered. Preferably, the pattern of thephotoresist layer 104 expose a plurality of parallel strips of themask layer 102 as shown in FIG. 1. The exposedmask layer 102, thepad oxide layer 101 and thesubstrate 100 under the exposedmask layer 102 are etched to form a plurality oftrenches 110 in thememory circuit regions 113. Again, thetrenches 110 are formed as a plurality of parallel strips in thesubstrate 100. Preferably, thetrenches 110 have a depth between about 0.1 micron to about 0.3 micron and a width less than about 0.25 micron. The profiles of thetrenches 110 are rounded to release stress. - In FIG. 2, the
photoresist layer 104 is removed, and aphotoresist layer 114 is formed to completely cover thememory circuit region 113 and a portion of theperipheral circuit region 123. Thephotoresist layer 114 has a pattern to expose a portion of themask layer 102 in theperipheral circuit region 123. Using thephotoresist layer 114 as a mask, the exposedmask layer 102, thepad oxide layer 101 and thesubstrate 100 under the exposedmask layer 102 are etched to form at least atrench 120 in theperipheral circuit region 123. Thetrench 120 has an inclined sidewall and a rounded surface to release stress. The depth of thetrench 120 is larger than about 0.4 micron, and the width thereof is larger than about 0.35 micron. The high operation voltage devices in theperipheral circuit region 123 can thus have a better isolation effect. - In FIG. 3, the
photoresist layer 114 is removed to expose the surfaces of thetrenches liner oxide layer 125 is formed along the surfaces of thetrenches trenches shallow trench isolations 130 and 140. The steps of filling thetrenches mask layer 102 to fill thetrenches mask layer 102 and thepad oxide layer 101 are then removed to expose thesubstrate 100. - In FIG. 5, a plurality of stacked
gates 150 are formed in thememory circuit region 113 along a direction perpendicular to theshallow trench isolations 130. Each of the stackedgates 150 comprises atunneling oxide layer 152, a floatinggate 154, adielectric layer 156 and acontrol gate 158. Thetunneling oxide layer 152 is formed across each of theshallow trench isolations 130. The floatinggates 154 formed on thetunneling oxide layers 152 comprise polysilicon layers. Thedielectric layers 156, for example, a composite layer of oxide/nitride/oxide, are formed on the floatinggates 154. Thecontrol gates 158 are formed on thedielectric layers 156 with a material, for example, polysilicon. - In FIG. 6, a self-aligned source process is performed. A photoresist layer159 (the frames drawn with bold lines) is formed to cover the central portion of the stacked
gates 150. Thephotoresist layer 159 has an opening over each of theshallow trench isolations 130 between every other pair of the stackedgates 150. The openings of thephotoresist layer 159 are wider than theshallow trench isolations 130 between every pair of the stackedgates 150 to ensure that theshallow trench isolations 130 are completely exposed. As a result, an edge portion of thecontrol gates 158 is exposed. The exposedshallow trench isolations 130 are then removed to expose thesubstrate 100 in thetrench 110 at which theshallow trench isolations 130 are removed. - In FIG. 7A, the
photoresist layer 159 is removed. The exposedsubstrate 100 is doped using the stackedgates 150 as a mask. As a result, acommon source region 170 is formed in thesubstrate 100 between every other pair of the stackedgates 150. Simultaneously, a column of a plurality ofdrain regions 180 is formed in thesubstrate 100 between every alternate pair of the stackedgates 158. Thedrain regions 180 in the same column are separated from each other by the remainingshallow trench isolations 130. - In the invention, the shallow trench isolations formed in the memory circuit region are shallower and narrower than the shallow trench isolations formed in the peripheral circuit region; therefore, the integration is enhanced without affecting the operation of the high voltage devices formed in the peripheral circuit region.
- In addition to the enhancement of the integration, the smaller shallow trench isolations to be removed can prevent damage of the control gates of the stacked gates.
- Other embodiments of the invention will appear to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples to be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
Claims (20)
1. A method of fabricating a flash memory, comprising:
providing a substrate having a memory circuit region and a peripheral circuit region;
forming a plurality of first shallow trench isolations and a plurality of second shallow trench isolations in the memory circuit region and the peripheral circuit region, respectively, wherein the first shallow trench isolations are shallower than the second shallow trench isolations;
forming a plurality of stacked gates on the substrate in the memory circuit region, wherein each stack gate is formed by stacking a plurality of tunnel oxide layers, a plurality of floating gates, a dielectric layer, and a control gate, with the control gate being stacked along a direction perpendicular to the first shallow trench isolations;
removing the first shallow trench isolations between every other pair of the stacked gates; and
performing a self-aligned source process to form a common source region and a column of a plurality of drain regions in the substrate between alternate pairs of the stacked gates.
2. The method according to claim 1 , wherein the step of forming the first and second shallow trench isolations comprises a step of forming the first and second shallow trench isolations with rounded surfaces.
3. The method according to claim 1 , wherein the step of forming the first and second shallow trench isolations further comprises:
forming a mask layer on the substrate;
performing two photolithography and etching processes to form a plurality of first trenches in the memory circuit region and at least a second trench in the peripheral circuit region, wherein the first trenches are shallower than the second trench;
filling the first and second trenches with an insulating material; and
removing the mask layer.
4. The method according to claim 3 , comprising further forming a pad oxide layer between the substrate and the mask layer.
5. The method according to claim 3 , comprising further forming a liner oxide layer along the surfaces of the first and second trenches before filling the first and the second trenches.
6. The method according to claim 3 , wherein filling the first and second trenches further comprises:
forming an insulating material over the substrate to fill the first and the second trenches; and
performing chemical mechanical polishing to remove the insulating material overfilling the first and the second trenches.
7. The method according to claim 3 , wherein forming the insulating material includes forming a silicon oxide layer.
8. The method according to claim 3 , comprising further annealing to density the insulating material.
9. The method according to claim 1 , wherein forming the first shallow trench isolations comprises forming the first shallow trench isolation with a depth of about 0.1 micron to about 0.3 micron.
10. The method according to claim 1 , wherein the step of forming the first shallow trench isolations comprises forming the first shallow trench isolation with a width smaller than about 0.25 micron.
11. The method according to claim 1 , wherein the floating gate and the control gate include polysilicon.
12. A structure of a flash memory, comprising:
a substrate having a memory circuit region and a peripheral circuit region, wherein the memory cell region of the substrate having a plurality of first trenches, the peripheral circuit region of the substrate having a plurality of second trenches, the first trenches being shallower than the second trenches;
a plurality of first trench isolation layers, wherein each of the first isolation layers is located in a part of each of the first trenches; a plurality of second shallow trench isolation layers, wherein the second shallow trench isolation layers are located in the second trenches;
a plurality of stacked gates on the substrate in the memory circuit region along a direction perpendicular to the first shallow trench isolations; and
a plurality of common source regions and drain regions in the substrate between every alternate pair of the stacked gates;
wherein each of the first shallow trench isolation layers is formed on a side where the drain regions are formed.
13. The structure according to claim 12 , wherein the first and second shallow trench isolations have rounded surfaces.
14. The structure according to claim 12 , wherein the first shallow trench isolations have a depth of about 0.1 micron to about 0.3 micron.
15. The structure according to claim 12 , wherein the first shallow trench isolations each have a width less than about 0.25 micron.
16. The structure according to claim 12 , wherein the first and second shallow trench isolations comprise silicon oxide.
17. The structure according to claim 12 , wherein the first and second shallow trench isolations further comprise a liner oxide layer.
18. The structure according to claim 12 , wherein each of the stacked gates further comprises a tunneling oxide layer, a floating gate, a dielectric layer and a control gate.
19. The structure according to claim 18 , wherein the floating and control gates comprise polysilicon.
20. The structure according to claim 18 , wherein the dielectric layers comprise a composite layer of oxide/nitride/oxide.
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