US20030027415A1 - Ball grid assembly with solder columns - Google Patents
Ball grid assembly with solder columns Download PDFInfo
- Publication number
- US20030027415A1 US20030027415A1 US10/255,694 US25569402A US2003027415A1 US 20030027415 A1 US20030027415 A1 US 20030027415A1 US 25569402 A US25569402 A US 25569402A US 2003027415 A1 US2003027415 A1 US 2003027415A1
- Authority
- US
- United States
- Prior art keywords
- pins
- solder
- solderable
- coated
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1182—Applying permanent coating, e.g. in-situ coating
- H01L2224/11822—Applying permanent coating, e.g. in-situ coating by dipping, e.g. in a solder bath
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
- H01L2224/742—Apparatus for manufacturing bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/1031—Surface mounted metallic connector elements
- H05K2201/10318—Surface mounted metallic pins
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0338—Transferring metal or conductive material other than a circuit pattern, e.g. bump, solder, printed component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
- H05K2203/104—Using magnetic force, e.g. to align particles or for a temporary connection during processing
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
- H05K3/3426—Leaded components characterised by the leads
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
A method of making a ball grid assembly and the assembly wherein a mask (1) is provided which is not wettable by solder and through which a pattern of parallel holes (3) is provided extending to at least one of a pair of opposing surfaces. A magnet (5), preferably an electromagnet, is disposed at the other one of the opposing surfaces. Solderable magnetic pins (7) are caused to enter the holes by magnetic attraction by positioning the one surface of the mask over the pins with a portion of each of the pins extending out of the hole into which it has entered. A layer of solder (11) is formed on the portion of each of the pins extending out of a hole in the mask and this layer of solder is reflowed over the pins and over a grid of solder adherable elements (13) on the package (15) and then allowed to set. The mask is removed from the pins when the solder is again set.
Description
- 1. Field of the Invention
- This invention relates to an automated solder ball grid assembly array and to a method of providing solder columns therein and the assembly.
- 2. Brief Description of the Prior Art
- Typically, in accordance with the prior art, surface mounted electronic packages which are mounted on circuit boards have leads around the periphery of a surface of the package with the leads later being soldered to the board. Another type of packaging uses a pin grid array where the pins can be anywhere on a surface of the package rather than only at the perimeter, thereby permitting many more pins to be available in the same area as compared with the above described arrangement. A further type of prior art packaging is a ball grid array wherein an electronic package is provided with interconnect traces and solder balls thereon which are the means for connection. There is mismatch in such types of packaging between the printed circuit board which is typically FR-4 and the integrated circuit package which is ceramic, BT resin or filled epoxy novalac resin. Whereas leaded SMT packages have leads which can flex and absorb the mismatch, in ball grid array (BGA) the leads are rigid and the solder is subject to fatigue cracking. As the distance between mismatching materials (i.e., package and board) is increased, stress concentration is decreased within the material which connects the dissimilar materials. In order to compensate for some mismatch in thermal expansion between the electronic package, the printed circuit board and the solder ball connection of a package, it is desirable to make the connections as tall as possible to absorb some of the mismatch and stresses. Accordingly, the solder balls are sometimes replaced with solder columns to provide such tall connections as a column grid. Attachment of solder balls and/or solder columns is cumbersome and relatively costly with automation thereof being highly desirable.
- In accordance with the present invention, there is provided an automated solder ball grid assembly array having solder columns and a method of providing the solder columns therein and the assembly itself which materially speeds up the prior art procedures and materially lowers the fabrication costs. The solder connections are made taller and the procedure for making the connections is improved relative to the prior art.
- Briefly, the improvements are accomplished by providing an electromagnet whose surface is not a solderable material, this surface being covered by a mask with a pattern of holes. The mask is formed using the technology and materials for solder masks found in standard printed circuit board technology. The pattern of holes mirrors the pads on the ball grid assembly (BGA) package. The mask is affixed onto the magnet, preferably an electromagnet, with the holes extending in the direction of the electromagnet. Solderable or solder plated magnetic pins, preferably of a steel alloy, such as, for example, A-42 coated with a solderable metal, such as, for example, copper, gold or palladium and the like are then provided, for example, in a box or deposited on a surface in some random manner. The mask with electromagnet on a side of the mask away from the pins is then brought into the vicinity of the pins so that the pins are attracted to the mask by the magnet and enter the holes in the mask. The mask is preferably designed relative to the length and diameter of the pins so that the hole diameter is larger than the pin but only one pin can fit into each hole of the mask and the pins will extend out of the holes in the mask. It is known that solder will coat a material with which it is compatible and make a thicker layer thereon. Accordingly, at least a portion of each of the pins extending out of the mask is dipped into molten solder and removed from the solder, the solder forming a coating over the pins at least at some or all of the portion of the pins extending out of the mask. Preferably the pins have been preplated with solder. This solder is then reflowed and travels along the associated pin as well as onto the pads of a package with contact pads thereon. This is accomplished by aligning the solder coated pins with the pads and heating the pads on the package sufficiently so that the pads will supply sufficient heat to cause some of the solder to reflow along the associated pin and onto the pads. The electromagnet is then turned off and removed along with the mask when the solder has hardened or set. The result is an electronic package having pins with solder coated on the exterior of the pins.
- FIG. 1 is a front view of a mask as used in accordance with the present invention;
- FIG. 2 is a side view of the mask of FIG. 1 secured to an electromagnet;
- FIG. 3 is a side view of the mask and electromagnet of FIG. 2 with pins loaded in the mask;
- FIG. 4 is a front view of the mask, electromagnet and pins of FIG. 3 prior to coating of the pins with solder from a solder pot;
- FIG. 5 is a front view as in FIG. 4 with the pins coated with solder and the pins aligned with solder balls of an electronic package having a solder ball grid array thereon; and
- FIG. 6 is a front view of the electronic package of FIG. 5 after attachment of the pins in FIG. 5 to the ball grid and removal of the mask and electromagnet.
- Referring first to FIG. 1, there is shown a mask1 typically photo-formed of an acrylic or other
polymer having holes 3 extending entirely therethrough. The pattern of the mask mirrors the pads in a BGA type electronic package. Theholes 3 have a diameter such that only one pin, as described hereinbelow, can fit in ahole 3 at one time. The mask 1 is affixed onto anelectromagnet 5 with theholes 3 extending to the electromagnet as shown in FIG. 2 (it is not essential that these holes extend entirely through the mask to the electromagnet). Solderable or solder coatedmagnetic pins 7 of, for example, alloy 42 are then provided in a box or container in some random manner and the mask 1 withelectromagnet 5 on the side of the mask away from thepins 7 is then brought into the vicinity of the pins so that the pins are attracted to the mask by the magnet and enter theholes 3 in the mask as shown in FIG. 3. Thepins 7 are sized so that only one pin can fit in each hole of the mask 1 at one time and the pins will extend out of theholes 3 in the mask. A portion of each of thepins 7 extends out of the mask 1 and all or a part of these portions of the pins that extend out of the mask are dipped into molten solder in asolder pot 9 as shown in FIG. 4 and removed from the solder pot. Alternately, the pins could be solder coated or plated before pick up by the magnet to eliminate this step. The solder forms asolder coating 11 over thepins 7 as shown in FIG. 5. Thesolder 11 coatedpins 7 are then aligned with the solder pads orlands 13 of anelectronic package 15 as shown in FIG. 5.pins 7 is then reflowed along the associated pin and onto thesolder pads 13 of thepackage 15 by aligning the solder coatedpins pads balls 13 and heating thepackage 15 to supply sufficient heat to cause some of thesolder 11 to reflow onto the solder pads as shown in FIG. 6. The temperature of the package is then reduced to allow the solder to set. Theelectromagnet 5 is then turned off and removed along with the mask 1 when thesolder 11 has hardened or set. The result is an electronic package having pins with solder coated on the exterior of the pins in the form of columns as shown in FIG. 6. - Though the invention has been described with reference to a specific preferred embodiment thereof, many variations and modifications will immediately become apparent to those skilled in the art. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.
Claims (19)
1. A method of making a ball grid assembly comprising the steps of:
(a) providing a mask which is not wettable by a solder to be used in conjunction therewith and through which a pattern of parallel holes is provided extending to at least one of a pair of opposing surfaces with a magnet disposed at the other of said opposing surfaces;
(b) providing one of solderable or solder-coated magnetic pins;
(c) causing said pins to enter said holes by magnetic attraction by positioning said one surface over said pins with a portion of each of said pins extending out of the hole into which it has entered;
(d) forming a layer of solder on the portion of each of said pins extending out of a said hole;
(e) causing said layer of solder to reflow over said pins and over a grid of solder adherable elements and then set; and
(f) removing said pins from said mask.
2. The method of claim 1 wherein said grid is a plurality of solder pads disposed on a package.
3. The method of claim 1 wherein said magnet is an electromagnet.
4. The method of claim 2 wherein said magnet is an electromagnet.
5. The method of claim 1 wherein said solderable magnetic pins have a magnetizable core which is coated with a solderable metal.
6. The method of claim 4 wherein said solderable magnetic pins have a magnetizable core which is coated with a solderable metal.
7. The method of claim 1 wherein said solderable magnetic pins are a core of an alloy of steel coated with a material taken from the class consisting of copper, gold or palladium.
8. The method of claim 4 wherein said solderable magnetic pins are taken from the class consisting of an alloy of steel coated with a material taken from the class consisting of copper, gold or palladium.
9. A package which comprises:
(a) a surface having a plurality of electrically conductive pads thereon; and
(b) a solder-coated solderable magnetic pin secured to each of said pads.
10. The package of claim 9 wherein said pads are one of solder pads or lands.
11. The package of claim 9 wherein each said solder-coated magnetic pin is secured to said pad by solder coated on said pin.
12. The package of claim 10 wherein each said solder-coated magnetic pin is secured to said pad by solder coated on said pin.
13. The package of claim 9 wherein each said pin is disposed normal to said surface.
14. The package of claim 10 wherein each said pin is disposed with its major axis normal to said surface.
15. The package of claim 11 wherein each said pin is disposed with its major axis normal to said surface.
16. The package of claim 12 wherein each said pin is disposed with its major axis normal to said surface.
17. A method of making a ball grid assembly comprising the steps of:
(a) providing a mask which is not wettable by a solder to be used in conjunction therewith and through which a pattern of parallel holes is provided extending to at least one of a pair of opposing surfaces with a magnet disposed at the other of said opposing surfaces;
(b) providing solderable pins;
(c) causing said pins to enter said holes with a portion of each of said pins extending out of the hole into which it has entered;
(d) forming a layer of solder on the portion of each of said pins extending out of a said hole;
(e) causing said layer of solder to reflow over said pins and over a grid of solder adherable elements and then set; and
(f) removing said pins from said mask.
18. The method of claim 17 wherein said solderable pins are taken from the class consisting of a magnetizable core coated with a solderable metal.
19. The method of claim 17 wherein said solderable pins are taken from the class consisting of a core of an alloy of steel coated with a solderable metal taken from the class consisting of gold, copper or palladium.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/255,694 US20030027415A1 (en) | 1996-01-16 | 2002-09-27 | Ball grid assembly with solder columns |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US1004496P | 1996-01-16 | 1996-01-16 | |
US08/782,872 US6528873B1 (en) | 1996-01-16 | 1997-01-14 | Ball grid assembly with solder columns |
US10/255,694 US20030027415A1 (en) | 1996-01-16 | 2002-09-27 | Ball grid assembly with solder columns |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/782,872 Division US6528873B1 (en) | 1996-01-16 | 1997-01-14 | Ball grid assembly with solder columns |
Publications (1)
Publication Number | Publication Date |
---|---|
US20030027415A1 true US20030027415A1 (en) | 2003-02-06 |
Family
ID=39383330
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/782,872 Expired - Lifetime US6528873B1 (en) | 1996-01-16 | 1997-01-14 | Ball grid assembly with solder columns |
US10/255,694 Abandoned US20030027415A1 (en) | 1996-01-16 | 2002-09-27 | Ball grid assembly with solder columns |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/782,872 Expired - Lifetime US6528873B1 (en) | 1996-01-16 | 1997-01-14 | Ball grid assembly with solder columns |
Country Status (1)
Country | Link |
---|---|
US (2) | US6528873B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020046208A1 (en) * | 2018-08-29 | 2020-03-05 | Thales Solutions Asia Pte Ltd | Nanostructure transfer method |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6528873B1 (en) * | 1996-01-16 | 2003-03-04 | Texas Instruments Incorporated | Ball grid assembly with solder columns |
JP4744689B2 (en) * | 2000-12-11 | 2011-08-10 | パナソニック株式会社 | Viscous fluid transfer device and electronic component mounting device |
US8093722B2 (en) * | 2008-05-27 | 2012-01-10 | Mediatek Inc. | System-in-package with fan-out WLCSP |
US8310051B2 (en) | 2008-05-27 | 2012-11-13 | Mediatek Inc. | Package-on-package with fan-out WLCSP |
US20100213589A1 (en) * | 2009-02-20 | 2010-08-26 | Tung-Hsien Hsieh | Multi-chip package |
US20100213588A1 (en) * | 2009-02-20 | 2010-08-26 | Tung-Hsien Hsieh | Wire bond chip package |
US8864536B2 (en) | 2012-05-03 | 2014-10-21 | International Business Machines Corporation | Implementing hybrid molded solder-embedded pin contacts and connectors |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5147084A (en) * | 1990-07-18 | 1992-09-15 | International Business Machines Corporation | Interconnection structure and test method |
US5311402A (en) * | 1992-02-14 | 1994-05-10 | Nec Corporation | Semiconductor device package having locating mechanism for properly positioning semiconductor device within package |
US5349495A (en) * | 1989-06-23 | 1994-09-20 | Vlsi Technology, Inc. | System for securing and electrically connecting a semiconductor chip to a substrate |
US5484964A (en) * | 1995-02-06 | 1996-01-16 | Dawson, Deceased; Peter F. | Surface mounting pin grid arrays |
US5486723A (en) * | 1993-05-27 | 1996-01-23 | Ma Laboratories, Inc. | Packaged integrated circuit add-on card |
US5512786A (en) * | 1994-08-10 | 1996-04-30 | Kyocera Corporation | Package for housing semiconductor elements |
US5521438A (en) * | 1993-09-24 | 1996-05-28 | Ngk Spark Plug Co., Ltd. | Ceramic base and metallic member assembly |
US6251767B1 (en) * | 1997-01-14 | 2001-06-26 | Texas Instruments Incorporated | Ball grid assembly with solder columns |
US6528873B1 (en) * | 1996-01-16 | 2003-03-04 | Texas Instruments Incorporated | Ball grid assembly with solder columns |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6292352A (en) * | 1985-10-17 | 1987-04-27 | Tanaka Denshi Kogyo Kk | Lead pin for chip-on-board |
JPS648649A (en) * | 1987-06-30 | 1989-01-12 | Ibiden Co Ltd | Semiconductor device |
JPS6471159A (en) * | 1987-09-10 | 1989-03-16 | Fujitsu Ltd | Semiconductor device |
JPH0235764A (en) * | 1988-07-26 | 1990-02-06 | Matsushita Electric Works Ltd | Terminal pin for semiconductor package |
JP2674788B2 (en) * | 1988-07-26 | 1997-11-12 | 松下電工株式会社 | Semiconductor package terminal pins |
US5468681A (en) * | 1989-08-28 | 1995-11-21 | Lsi Logic Corporation | Process for interconnecting conductive substrates using an interposer having conductive plastic filled vias |
JPH04186660A (en) * | 1990-11-16 | 1992-07-03 | Nec Kyushu Ltd | Package for semiconductor device |
US5177670A (en) * | 1991-02-08 | 1993-01-05 | Hitachi, Ltd. | Capacitor-carrying semiconductor module |
US5550403A (en) * | 1994-06-02 | 1996-08-27 | Lsi Logic Corporation | Improved laminate package for an integrated circuit and integrated circuit having such a package |
US5608264A (en) * | 1995-06-05 | 1997-03-04 | Harris Corporation | Surface mountable integrated circuit with conductive vias |
-
1997
- 1997-01-14 US US08/782,872 patent/US6528873B1/en not_active Expired - Lifetime
-
2002
- 2002-09-27 US US10/255,694 patent/US20030027415A1/en not_active Abandoned
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5349495A (en) * | 1989-06-23 | 1994-09-20 | Vlsi Technology, Inc. | System for securing and electrically connecting a semiconductor chip to a substrate |
US5147084A (en) * | 1990-07-18 | 1992-09-15 | International Business Machines Corporation | Interconnection structure and test method |
US5311402A (en) * | 1992-02-14 | 1994-05-10 | Nec Corporation | Semiconductor device package having locating mechanism for properly positioning semiconductor device within package |
US5486723A (en) * | 1993-05-27 | 1996-01-23 | Ma Laboratories, Inc. | Packaged integrated circuit add-on card |
US5521438A (en) * | 1993-09-24 | 1996-05-28 | Ngk Spark Plug Co., Ltd. | Ceramic base and metallic member assembly |
US5512786A (en) * | 1994-08-10 | 1996-04-30 | Kyocera Corporation | Package for housing semiconductor elements |
US5484964A (en) * | 1995-02-06 | 1996-01-16 | Dawson, Deceased; Peter F. | Surface mounting pin grid arrays |
US6528873B1 (en) * | 1996-01-16 | 2003-03-04 | Texas Instruments Incorporated | Ball grid assembly with solder columns |
US6251767B1 (en) * | 1997-01-14 | 2001-06-26 | Texas Instruments Incorporated | Ball grid assembly with solder columns |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020046208A1 (en) * | 2018-08-29 | 2020-03-05 | Thales Solutions Asia Pte Ltd | Nanostructure transfer method |
Also Published As
Publication number | Publication date |
---|---|
US6528873B1 (en) | 2003-03-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5660321A (en) | Method for controlling solder bump height and volume for substrates containing both pad-on and pad-off via contacts | |
US6259039B1 (en) | Surface mount connector with pins in vias | |
KR100287393B1 (en) | Substrate structure and method for improving attachment reliability of semiconductor chips and modules | |
EP0263222B1 (en) | Method of forming solder terminals for a pinless ceramic module | |
JP3846554B2 (en) | Mask for printing, printing method, mounting structure, and manufacturing method of the mounting structure | |
US5459287A (en) | Socketed printed circuit board BGA connection apparatus and associated methods | |
KR0157284B1 (en) | Printed circuit board of solder ball take-on groove furnished and this use of package ball grid array | |
US6514845B1 (en) | Solder ball contact and method | |
US6066551A (en) | Method for forming bump of semiconductor device | |
US6029882A (en) | Plastic solder array using injection molded solder | |
JP2004207232A (en) | Solder storage transferring device and step | |
EP0947125B1 (en) | Method of making a printed circuit board having a tin/lead coating | |
KR100404275B1 (en) | Electrically conductive wire | |
US6251767B1 (en) | Ball grid assembly with solder columns | |
US6528873B1 (en) | Ball grid assembly with solder columns | |
US6272741B1 (en) | Hybrid solder ball and pin grid array circuit board interconnect system and method | |
JPH06124953A (en) | Bump forming method of semiconductor device | |
CN112703825A (en) | Method for producing a circuit board assembly and circuit board assembly | |
EP0817550A1 (en) | Circuit board with improved positioning means | |
KR20060073648A (en) | Vertical removal of excess solder from a circuit substrate | |
US20050235488A1 (en) | Selective area solder placement | |
JP2008091557A (en) | Electronic component mounting method and apparatus | |
JPH01144698A (en) | Method and apparatus for manufacturing hybrid integrated circuit | |
JPH05283587A (en) | Soldering method of multiple-lead element | |
JPH06326451A (en) | Soldering method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |