US20030045033A1 - Method of manufacturing a semiconductor device - Google Patents

Method of manufacturing a semiconductor device Download PDF

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Publication number
US20030045033A1
US20030045033A1 US09/941,146 US94114601A US2003045033A1 US 20030045033 A1 US20030045033 A1 US 20030045033A1 US 94114601 A US94114601 A US 94114601A US 2003045033 A1 US2003045033 A1 US 2003045033A1
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Prior art keywords
substrate
resin
semiconductor chips
manufacturing
semiconductor device
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Granted
Application number
US09/941,146
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US6528354B1 (en
Inventor
Takashi Hosaka
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Seiko Instruments Inc
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Seiko Instruments Inc
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Priority to JP2000080753A priority Critical patent/JP2001267342A/en
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to US09/941,146 priority patent/US6528354B1/en
Assigned to SEIKO INSTRUMENTS INC. reassignment SEIKO INSTRUMENTS INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HOSAKA, TAKASHI
Application granted granted Critical
Publication of US6528354B1 publication Critical patent/US6528354B1/en
Publication of US20030045033A1 publication Critical patent/US20030045033A1/en
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Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • the present invention relates generally to a method of forming IC packages in which a number of semiconductor chips are mounted on a substrate.
  • FIGS. 1A to 1 F show a manufacturing method of a semiconductor device according to the present invention.
  • FIG. 2 shows a conventional semiconductor device.
  • the present invention relates to a technique for preventing a substrate from warping in a method of manufacturing a semiconductor device including mounting of a number of semiconductor chips on the substrate, covering the semiconductor chips with resin, and dividing the whole into semiconductor packages.
  • An example of the present invention is described with reference to the drawing as follows.
  • FIG. 1 shows a manufacturing method of the present invention.
  • FIG. 1A is a cross-sectional view illustrating a state where semiconductor chips 12 are mounted on a substrate 11 and wires inside the substrate 11 and the semiconductor chips 12 are connected with metal lines 14 .
  • the substrate include a glass epoxy substrate, a ceramic substrate, a polyimide substrate, and the like.
  • the substrate 11 is placed inside a mold 17 and resins 15 a and 15 b are poured thereinto and then are solidified.
  • resin was allowed to adhere onto the only side on which the semiconductor chips 12 were provided.
  • the resins 15 a and 15 b are poured on both front and back sides of the substrate 11 , respectively.
  • a tape 16 is interposed between the substrate 11 and the resin 15 b on the side on which the semiconductor chips 12 are not provided.
  • the mold 17 is removed after the resins 15 a and 15 b are solidified.
  • FIG. 1C shows a state where the front and back sides of the substrate 11 are covered with the resins 15 a and 15 b , respectively.
  • the face of the resin 15 a on the side on which the semiconductor chips are provided is stuck onto a dicing tape 18 . Since the substrate 11 is not warped, it sticks to the dicing tape 18 easily.
  • the tape 16 is peeled off from the substrate 11 .
  • the resin 15 b on the tape side is also peeled off together. This state after the peeling off is shown in FIG. 1E.
  • the substrate is cut by dicing.
  • a semiconductor package is obtained that is composed of the substrate 11 , the resin 15 a , and external electrodes 20 .

Abstract

It is intended to provide high quality IC packages with the same size as that of IC chips. In a step of covering semiconductor chips with a resin for protection thereof, the resin is also allowed to adhere onto an opposite side of the substrate on which the semiconductor chips are mounted.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates generally to a method of forming IC packages in which a number of semiconductor chips are mounted on a substrate. [0002]
  • 2. Related Background Art [0003]
  • When a number of semiconductor chips are mounted on a substrate and are covered with a resin to be protected, which then is divided into individual semiconductor packages, conventionally, the substrate warps due to the resin which is adhered onto only one side of the substrate as shown in FIG. 2. [0004]
  • As shown in FIG. 2, since the resin is allowed to adhere onto only one side of the substrate, the substrate warps to one side. Hence, in the steps thereafter, it is necessary to work with consideration given to this warp. For instance, sufficient space should be provided so as to prevent upper-side and lower-side substrates from coming to contact with each other when a substrate is to be mounted on a magazine, or the focus of a microscope should be readjusted continuously in inspecting a substrate, which has required extra time and energy. In addition, when a substrate is cut and thereby semiconductor packages are obtained, such warp should be taken into account and the substrate cannot be cut with high precision. [0005]
    • SUMMARY OF THE INVENTION
  • In order to solve the above-mentioned problems, in the present invention, when semiconductor chips mounted on a substrate are to be covered with resin, resin is also allowed to adhere onto the opposite side of the substrate on which the semiconductor chips are mounted. According to this, comparable levels of resin stress are exerted on respective sides of the substrate. Hence, the stresses exerted on the respective sides cancel each other out and thus the substrate does not warp. The resin that has adhered onto the opposite side of the substrate on which the semiconductor chips are mounted is removed before the substrate is cut.[0006]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • In the accompanying drawings: [0007]
  • FIGS. 1A to [0008] 1F show a manufacturing method of a semiconductor device according to the present invention; and
  • FIG. 2 shows a conventional semiconductor device.[0009]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The present invention relates to a technique for preventing a substrate from warping in a method of manufacturing a semiconductor device including mounting of a number of semiconductor chips on the substrate, covering the semiconductor chips with resin, and dividing the whole into semiconductor packages. An example of the present invention is described with reference to the drawing as follows. [0010]
  • FIG. 1 shows a manufacturing method of the present invention. FIG. 1A is a cross-sectional view illustrating a state where [0011] semiconductor chips 12 are mounted on a substrate 11 and wires inside the substrate 11 and the semiconductor chips 12 are connected with metal lines 14. Examples of the substrate include a glass epoxy substrate, a ceramic substrate, a polyimide substrate, and the like.
  • Next, as shown in FIG. 1B, the [0012] substrate 11 is placed inside a mold 17 and resins 15 a and 15 b are poured thereinto and then are solidified. Conventionally, resin was allowed to adhere onto the only side on which the semiconductor chips 12 were provided. In the present invention, however, the resins 15 a and 15 b are poured on both front and back sides of the substrate 11, respectively. At this time, a tape 16 is interposed between the substrate 11 and the resin 15 b on the side on which the semiconductor chips 12 are not provided. The mold 17 is removed after the resins 15 a and 15 b are solidified.
  • FIG. 1C shows a state where the front and back sides of the [0013] substrate 11 are covered with the resins 15 a and 15 b, respectively.
  • Next, as shown in FIG. 1D, the face of the [0014] resin 15 a on the side on which the semiconductor chips are provided is stuck onto a dicing tape 18. Since the substrate 11 is not warped, it sticks to the dicing tape 18 easily.
  • Next, the [0015] tape 16 is peeled off from the substrate 11. At this time, the resin 15 b on the tape side is also peeled off together. This state after the peeling off is shown in FIG. 1E.
  • Afterward, the substrate is cut by dicing. Thus, as shown in FIG. 1F, a semiconductor package is obtained that is composed of the [0016] substrate 11, the resin 15 a, and external electrodes 20.
  • As described above, since resin is allowed to adhere not only to the side on which the semiconductor chips are mounted but also to the opposite side thereto, the substrate does not warp and thus processes in the steps carried out thereafter can be proceeded easily with no problem being caused. Particularly, it is easy to stick the substrate to the dicing tape before the substrate is cut, and thus the substrate is allowed to adhere completely to the dicing tape to be stuck thereto. In addition, since a tape is interposed between the lower-side face of the substrate and resin on the lower side of the substrate, the resin on the lower side can be removed from the substrate relatively easily after the substrate is stuck to the dicing tape. It is also possible to peel off the tape and resin on the lower side of the substrate after individual semiconductor packages are obtained. [0017]
  • The invention may be embodied in other forms without departing from the spirit or essential characteristics thereof. The embodiments disclosed in this application are to be considered in all respects as illustrative and not limiting. The scope of the invention is indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein. [0018]

Claims (2)

What is claimed is:
1. A method of manufacturing a semiconductor device, comprising mounting a number of semiconductor chips on a substrate and covering the semiconductor chips with a resin for protection thereof, wherein the step of covering the semiconductor chips with the resin for protection thereof includes a step of allowing the resin to adhere onto an opposite side of the substrate on which the semiconductor chips are mounted.
2. A method of manufacturing a semiconductor device, comprising mounting a number of semiconductor chips on a substrate and covering the semiconductor chips with a resin for protection thereof, wherein, before and after a step of covering the semiconductor chips with the resin for protection thereof, a step of allowing the resin to adhere onto an opposite side of the substrate on which the semiconductor chips are mounted, is provided.
US09/941,146 2000-03-22 2001-08-28 Method of manufacturing a semiconductor device Expired - Fee Related US6528354B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000080753A JP2001267342A (en) 2000-03-22 2000-03-22 Method of manufacturing semiconductor device
US09/941,146 US6528354B1 (en) 2000-03-22 2001-08-28 Method of manufacturing a semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000080753A JP2001267342A (en) 2000-03-22 2000-03-22 Method of manufacturing semiconductor device
US09/941,146 US6528354B1 (en) 2000-03-22 2001-08-28 Method of manufacturing a semiconductor device

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US6528354B1 US6528354B1 (en) 2003-03-04
US20030045033A1 true US20030045033A1 (en) 2003-03-06

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10334576B4 (en) * 2003-07-28 2007-04-05 Infineon Technologies Ag Method for producing a semiconductor component with a plastic housing
JP2008072156A (en) * 2004-12-02 2008-03-27 Murata Mfg Co Ltd Composite material vibrator
CN111583795B (en) * 2020-05-12 2022-03-08 Tcl华星光电技术有限公司 Preparation method of display panel and display device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6066514A (en) * 1996-10-18 2000-05-23 Micron Technology, Inc. Adhesion enhanced semiconductor die for mold compound packaging
JP3199963B2 (en) * 1994-10-06 2001-08-20 株式会社東芝 Method for manufacturing semiconductor device
NL1003315C2 (en) * 1996-06-11 1997-12-17 Europ Semiconductor Assembly E Method for encapsulating an integrated semiconductor circuit.
US6228688B1 (en) * 1997-02-03 2001-05-08 Kabushiki Kaisha Toshiba Flip-chip resin-encapsulated semiconductor device
US5914529A (en) * 1998-02-20 1999-06-22 Micron Technology, Inc. Bus bar structure on lead frame of semiconductor device package
US5933713A (en) * 1998-04-06 1999-08-03 Micron Technology, Inc. Method of forming overmolded chip scale package and resulting product
JP2002074985A (en) * 2000-08-29 2002-03-15 Mitsubishi Electric Corp Memory module, its manufacturing method, and test connector using it

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US6528354B1 (en) 2003-03-04

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