US20030082900A1 - Method of forming contact plugs - Google Patents
Method of forming contact plugs Download PDFInfo
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- US20030082900A1 US20030082900A1 US10/061,646 US6164602A US2003082900A1 US 20030082900 A1 US20030082900 A1 US 20030082900A1 US 6164602 A US6164602 A US 6164602A US 2003082900 A1 US2003082900 A1 US 2003082900A1
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- conducting structure
- gate conducting
- conductive layer
- contact hole
- layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/906—Dram with capacitor electrodes used for accessing, e.g. bit line is capacitor plate
Definitions
- the present invention relates to a semiconductor process and, more particularly, to a method of forming a bitline contact plug.
- FIGS. 1A to 1 H are sectional diagrams showing a conventional method of forming contact plugs using SAC process.
- a P-type silicon substrate 10 is provided with a plurality of shallow trench isolation (STI) regions 12 in the substrate 10 for isolating adjacent active areas (AA), a gate insulating layer 14 formed on the substrate 10 , a plurality of gate conducting structures 161 , 162 , 163 and 164 patterned on the gate insulating layer 14 , and a plurality of N ⁇ - type ion implantation regions 20 formed in the substrate 10 and at lateral regions of the gate conducting structures 161 ⁇ 164 .
- STI shallow trench isolation
- Each of the gate conducting structures 161 ⁇ 164 is stacked by a polysilicon layer 17 , a tungsten silicide layer 18 , and a silicon nitride cap layer 19 .
- a silicon oxide spacer 22 is grown on the sidewalls of the polysilicon layer 17 and the tungsten silicide layer 18 , and then a silicon nitride spacer 24 is formed on the sidewalls of the gate conducting structures 161 ⁇ 164 .
- an N + -type ion implantation region 26 is formed in the exposed N ⁇ -type ion implantation region 20 .
- the N + -type ion implantation region 26 serves as a source/drain region
- the remaining N ⁇ -type ion implantation region 20 serves as a lightly doped drain (LDD) structure.
- LDD lightly doped drain
- a SiON liner 28 is deposited on the entire surface of the substrate 10 , and then an inter-layered dielectric (ILD) layer 30 with a planarized surface is formed on the SiON liner 28 to fill the gaps between adjacent gate conducting structures 161 ⁇ 164 by deposition and chemical mechanical polishing (CMP).
- the ILD layer 30 is BPSG, HDP oxide, TEOS.
- bitline contact hole 32 using a first photoresist layer 31 with a pattern of the bitline contact plug formed as the mask, the ILD layer 30 and the SiON liner 28 formed between the two gate conducting structures 162 and 163 are removed to expose the N + -type ion implantation region 26 , thus forms a bitline contact hole 32 .
- a first conductive layer is deposited to fill the bitline contact hole 32 and then etched back to a predetermined height within the bitline contact hole 32 , thus the first conductive layer remaining in the bitline contact hole 32 serves as a bitline contact plug 34 .
- first interconnection contact hole 36 is formed over the first gate conducting structure 161 to expose the top of the tungsten silicide layer 18 .
- the second interconnection contact hole 38 is formed outside the gate conducting structure 164 to expose the N + -type ion implantation region 26 .
- a third photoresist layer 39 with a pattern of interconnections is employed as a mask to etch predetermined regions of the ILD layer 30 .
- a second conductive layer 40 is deposited on the entire surface of the substrate 10 to fill the first interconnection contact hole 36 and the second interconnection contact hole 38 .
- CMP is employed to level off the top of the second conductive layer 40 and the top of the ILD layer 30 . Therefore, the second conductive layer 40 formed on the ILD layer 30 serves as an interconnection structure 40 a , and the second conductive layer 40 formed in the first/second interconnection contact hole 36 / 38 serves as a first/second interconnection contact plug 40 b.
- the silicon nitride cap layer 19 requires a thick thickness in the SAC process, thus thermal budget is increased and electrical properties, such as V t , I dsat , I off , are worsened.
- the SAC process is applied to manufacture a device of a further reduced size, the problems encountered in photolithography becomes more difficult.
- the materials used for the cap layer 19 and the spacer 24 are limited to SiN or SiON, resulting in worsening the leakage problem in the polysilicon layer 17 .
- the present invention is a method of forming contact plugs to solve the above-mentioned problems.
- the method of forming contact plugs is used on a semiconductor substrate with at least four adjacent gate conducting structures, wherein a second gate conducting structure and a third gate conducting structure are formed within an active area.
- a second gate conducting structure and a third gate conducting structure are formed within an active area.
- the gap between the second gate conducting structure and the third gate conducting structure is filled with a first conductive layer.
- an inter-layered dielectric (ILD) layer with a planarized surface is formed on the entire surface of the substrate to cover the first conductive layer.
- a bitline contact hole is formed in the ILD layer to expose the first conductive layer.
- the bitline contact hole is filled with a second conductive layer to serve as a bitline contact plug.
- Yet another object of the invention is to provide a stable contact resistance between the bitline contact plug and the substrate.
- Still another object of the invention is to be applied to manufacture a device of a further reduced size without encountering problems in photolithography.
- Another object of the invention is to increases the selectiveness of using materials.
- FIGS. 1A to 1 H are sectional diagrams showing a conventional method of forming contact plugs using SAC process.
- FIGS. 2A to 2 J are sectional diagrams showing a method of forming contact plugs according to the present invention.
- FIGS. 2A to 2 J are sectional diagrams showing a method of forming contact plugs according to the present invention.
- a P-type silicon substrate 50 is provided with a plurality of STI regions 52 for isolating active areas, a gate insulating layer 54 formed on the substrate 50 , a plurality of gate conducting structures 561 , 562 , 563 and 564 patterned on the gate insulating layer 54 , and a plurality of N ⁇ -type ion implantation regions 60 formed in the substrate 50 and at lateral regions of the gate conducting structures 561 ⁇ 564 .
- Each of the gate conducting structures 561 ⁇ 564 is stacked by a polysilicon layer 57 , a tungsten silicide layer 58 and a cap layer 59 .
- the material used to formed cap layer 59 is selected from SiN, SiON or silicon oxide.
- a first spacer 62 is formed on the exposed sidewalls of the polysilicon layer 57 and the tungsten silicide layer 58 , and then a second spacer 64 is formed on the exposed sidewalls of the gate conducting structures 561 ⁇ 564 .
- the first spacer 62 is silicon oxide
- the second spacer 64 is selected from SiN, SiON or silicon oxide.
- N + -type ion implantation regions 66 are respectively formed in the exposed N ⁇ -type ion implantation regions 60 . Therefore, the N + -type ion implantation region 66 serves as a source/drain region, and the N ⁇ -type ion implantation region 60 serves as a lightly doped drain (LDD) structure.
- LDD lightly doped drain
- a liner 68 of SiON, SiN or silicon oxide is deposited on the entire surface of the substrate 50 .
- the liner 68 disposed on a part of the top of the second/third gate conducting structures 562 / 563 and disposed on the N + -type ion implantation region 66 between the second gate conducting structure 562 and the third gate conducting structure 563 is removed.
- FIG. 2D using photolithography and etching with a first photoresist layer 69 as the mask, the liner 68 disposed on a part of the top of the second/third gate conducting structures 562 / 563 and disposed on the N + -type ion implantation region 66 between the second gate conducting structure 562 and the third gate conducting structure 563 is removed.
- a first conductive layer 70 with a planarized surface is formed on the entire surface of the substrate 50 by deposition and CMP.
- the top of the first conductive layer 70 is equal to or higher than the top of the liner 68 remaining on the top of the gate conducting structures 561 ⁇ 564 .
- the material used to form the first conductive layer 70 is polysilicon or any other conductive materials.
- an ILD layer 72 with a planarized surface is formed on the entire surface of the substrate 50 to fill the gaps between adjacent gate conducting structures 561 ⁇ 564 by deposition and CMP.
- the ILD layer 72 is BPSG, HDP oxide, TEOS oxide or the combination of those.
- part of the ILD layer 72 , the SiON liner 68 and the cap layer 59 is removed to form a bitline contact hole 741 , a first interconnection contact hole 742 and a second interconnection contact hole 743 .
- the bitline contact hole 741 exposes the landing pad 70 a between the second gate conducting structure 562 and the third gate conducting structure 563 .
- the first interconnection contact hole 742 is over the first gate conducting structure 561 to expose the top of the tungsten silicide layer 58 .
- the second interconnection contact hole 743 is outside the fourth gate conducting structure 564 to expose the N + -type ion implantation region 66 .
- a fourth photoresist layer 75 with a pattern of interconnections is employed as the mask to remove part of the ILD layer 72 .
- a second conductive layer 76 is deposited on the entire surface of the substrate 50 to fill the bitline contact hole 741 , the first interconnection contact hole 742 and the second interconnection contact hole 743 , and then CMP is used to level off the surfaces of the second conductive layer 76 and the ILD layer 72 .
- the second conductive layer 76 is polysilicon, tungsten or other conductive materials.
- the second conductive layer 76 b remaining in the contact holes 741 , 742 and 743 respectively serves as a bitline contact plug, a first interconnection contact plug and a second interconnection contact plug.
- the second conductive layer 76 a remaining on the contact plugs serves as a bitline/interconnection structure.
- the present invention has advantages as listed below.
- the cap layer 59 of a thinner thickness is employed to reduce thermal budget and promote electrical properties of the product.
- the present invention can be applied to manufacture a device of a further reduced size without encountering problems in photolithography.
- the materials used for the cap layer 59 and the second spacer 64 are not only SiN and SiON, but also silicon oxide. This increases the selectiveness of using materials to form the cap layer 59 and the second spacer 64 .
- the liner 68 is silicon nitride
- the ILD layer 72 is BPSG.
- the material used to form the ILD layer 72 is selected from dielectric materials not containing boron and phosphorous. This prevents the boron ions or phosphorous ions from diffusing into the substrate 50 so as to ensure the device stability.
Abstract
A method of forming contact plugs is used on a semiconductor substrate with at least four adjacent gate conducting structures, wherein a second gate conducting structure and a third gate conducting structure are formed within an active area. First, the gap between the second gate conducting structure and the third gate conducting structure is filled with a first conductive layer. Then, an inter-layered dielectric (ILD) layer with a planarized surface is formed on the entire surface of the substrate to cover the first conductive layer. Next, a bitline contact hole is formed in the ILD layer to expose the first conductive layer. Thereafter, the bitline contact hole is filled with a second conductive layer to serve as a bitline contact plug.
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor process and, more particularly, to a method of forming a bitline contact plug.
- 2. Description of the Related Art
- When manufacturing memory products such as trench-type DRAM, stacked-type DRAM and FLASH memory, in order to reduce the size of a chip, the conventional semiconductor process uses self-aligned contact (SAC) technology to define a reduced distance between two adjacent gate conducting structures.
- FIGS. 1A to1H are sectional diagrams showing a conventional method of forming contact plugs using SAC process. As shown in FIG. 1A, a P-
type silicon substrate 10 is provided with a plurality of shallow trench isolation (STI)regions 12 in thesubstrate 10 for isolating adjacent active areas (AA), agate insulating layer 14 formed on thesubstrate 10, a plurality ofgate conducting structures gate insulating layer 14, and a plurality of N−- typeion implantation regions 20 formed in thesubstrate 10 and at lateral regions of thegate conducting structures 161˜164. Each of thegate conducting structures 161˜164 is stacked by apolysilicon layer 17, atungsten silicide layer 18, and a siliconnitride cap layer 19. As shown in FIG. 1B, asilicon oxide spacer 22 is grown on the sidewalls of thepolysilicon layer 17 and thetungsten silicide layer 18, and then asilicon nitride spacer 24 is formed on the sidewalls of thegate conducting structures 161˜164. Next, using ion implantation with thegate conducting structures 161˜164 and thesilicon nitride spacer 24 as the mask, an N+-typeion implantation region 26 is formed in the exposed N−-typeion implantation region 20. Thereby, the N+-typeion implantation region 26 serves as a source/drain region, and the remaining N−-typeion implantation region 20 serves as a lightly doped drain (LDD) structure. - As shown in FIG. 1C, a
SiON liner 28 is deposited on the entire surface of thesubstrate 10, and then an inter-layered dielectric (ILD)layer 30 with a planarized surface is formed on theSiON liner 28 to fill the gaps between adjacentgate conducting structures 161˜164 by deposition and chemical mechanical polishing (CMP). Preferably, theILD layer 30 is BPSG, HDP oxide, TEOS. Next, as shown in FIG. 1D, using a firstphotoresist layer 31 with a pattern of the bitline contact plug formed as the mask, theILD layer 30 and theSiON liner 28 formed between the twogate conducting structures ion implantation region 26, thus forms abitline contact hole 32. Thereafter, as shown in FIG. 1E, after removing the firstphotoresist layer 31, a first conductive layer is deposited to fill thebitline contact hole 32 and then etched back to a predetermined height within thebitline contact hole 32, thus the first conductive layer remaining in thebitline contact hole 32 serves as abitline contact plug 34. - As shown in FIG. 1F, using a second
photoresist layer 35 with a pattern of interconnection contact plugs as the mask, part of theILD layer 30, the SiONliner 28 and the siliconnitride cap layer 19 is removed to form a firstinterconnection contact hole 36 and a secondinterconnection contact hole 38. The firstinterconnection contact hole 36 is formed over the firstgate conducting structure 161 to expose the top of thetungsten silicide layer 18. The secondinterconnection contact hole 38 is formed outside thegate conducting structure 164 to expose the N+-typeion implantation region 26. Next, as shown in FIG. 1G, after removing the secondphotoresist layer 35, a thirdphotoresist layer 39 with a pattern of interconnections is employed as a mask to etch predetermined regions of theILD layer 30. Finally, as shown in FIG. 1H, a second conductive layer 40 is deposited on the entire surface of thesubstrate 10 to fill the firstinterconnection contact hole 36 and the secondinterconnection contact hole 38. Then, CMP is employed to level off the top of the second conductive layer 40 and the top of theILD layer 30. Therefore, the second conductive layer 40 formed on theILD layer 30 serves as aninterconnection structure 40 a, and the second conductive layer 40 formed in the first/secondinterconnection contact hole 36/38 serves as a first/secondinterconnection contact plug 40 b. - However, the above-described SAC process has disadvantages as listed below. First, when the
STI region 12 is very large or a problem of step height between AA and STI causes misalignment during photolithography or CMP cannot provide theILD layer 30 with an appropriate thickness and superior flatness, the etched profile of the contact hole would be affected, and it would cause problems of the interconnection structure, such as a short circuit between bitline and wordline or a blind window in thebitline contact hole 32. Second, since the etching selectivity from theILD layer 30 to theSiON liner 28 is not large enough to provide etching stop capability during the formation of thebitline contact hole 32, seams are probably formed in theSTI region 12 to cause junction leakage between thebitline contact plug 34 and thesubstrate 10. Third, the siliconnitride cap layer 19 requires a thick thickness in the SAC process, thus thermal budget is increased and electrical properties, such as Vt, Idsat, Ioff, are worsened. Fourth, if the SAC process is applied to manufacture a device of a further reduced size, the problems encountered in photolithography becomes more difficult. Fifth, the materials used for thecap layer 19 and thespacer 24 are limited to SiN or SiON, resulting in worsening the leakage problem in thepolysilicon layer 17. - The present invention is a method of forming contact plugs to solve the above-mentioned problems.
- The method of forming contact plugs is used on a semiconductor substrate with at least four adjacent gate conducting structures, wherein a second gate conducting structure and a third gate conducting structure are formed within an active area. First, the gap between the second gate conducting structure and the third gate conducting structure is filled with a first conductive layer. Then, an inter-layered dielectric (ILD) layer with a planarized surface is formed on the entire surface of the substrate to cover the first conductive layer. Next, a bitline contact hole is formed in the ILD layer to expose the first conductive layer. Thereafter, the bitline contact hole is filled with a second conductive layer to serve as a bitline contact plug.
- Accordingly, it is a principle object of the invention to prevent the formation of the bitline contact hole from poor etching profile, short circuits in the interconnection structure and blind window.
- It is another object of the invention to prevent the formation of seams in the STI region.
- Yet another object of the invention is to provide a stable contact resistance between the bitline contact plug and the substrate.
- It is a further object of the invention to reduce thermal budget and promote electrical properties of the product.
- Still another object of the invention is to be applied to manufacture a device of a further reduced size without encountering problems in photolithography.
- Another object of the invention is to increases the selectiveness of using materials.
- These and other objects of the present invention will become readily apparent upon further review of the following specification and drawings.
- FIGS. 1A to1H are sectional diagrams showing a conventional method of forming contact plugs using SAC process.
- FIGS. 2A to2J are sectional diagrams showing a method of forming contact plugs according to the present invention.
- Similar reference characters denote corresponding features consistently throughout the attached drawings.
- FIGS. 2A to2J are sectional diagrams showing a method of forming contact plugs according to the present invention. As shown in FIG. 2A, a P-
type silicon substrate 50 is provided with a plurality ofSTI regions 52 for isolating active areas, agate insulating layer 54 formed on thesubstrate 50, a plurality ofgate conducting structures gate insulating layer 54, and a plurality of N−-typeion implantation regions 60 formed in thesubstrate 50 and at lateral regions of thegate conducting structures 561˜564. Each of thegate conducting structures 561˜564 is stacked by apolysilicon layer 57, atungsten silicide layer 58 and acap layer 59. Preferably, the material used to formedcap layer 59 is selected from SiN, SiON or silicon oxide. - As shown in FIG. 2B, a
first spacer 62 is formed on the exposed sidewalls of thepolysilicon layer 57 and thetungsten silicide layer 58, and then asecond spacer 64 is formed on the exposed sidewalls of thegate conducting structures 561˜564. Preferably, thefirst spacer 62 is silicon oxide, and thesecond spacer 64 is selected from SiN, SiON or silicon oxide. Next, using thegate conducting structures 561˜564 and thesecond spacer 64 as the mask, N+-typeion implantation regions 66 are respectively formed in the exposed N−-typeion implantation regions 60. Therefore, the N+-typeion implantation region 66 serves as a source/drain region, and the N−-typeion implantation region 60 serves as a lightly doped drain (LDD) structure. - As shown in FIG. 2C, a
liner 68 of SiON, SiN or silicon oxide is deposited on the entire surface of thesubstrate 50. Then, as shown in FIG. 2D, using photolithography and etching with afirst photoresist layer 69 as the mask, theliner 68 disposed on a part of the top of the second/thirdgate conducting structures 562/563 and disposed on the N+-typeion implantation region 66 between the secondgate conducting structure 562 and the thirdgate conducting structure 563 is removed. Next, as shown in FIG. 2E, after removing thefirst photoresist layer 69, a firstconductive layer 70 with a planarized surface is formed on the entire surface of thesubstrate 50 by deposition and CMP. Preferably, the top of the firstconductive layer 70 is equal to or higher than the top of theliner 68 remaining on the top of thegate conducting structures 561˜564. The material used to form the firstconductive layer 70 is polysilicon or any other conductive materials. Thereafter, as shown in FIG. 2F, using asecond photoresist layer 71 as the mask and using theliner 68 as the etching stop layer, most of the firstconductive layer 70 is removed, thus the firstconductive layer 70 only remains in the gap between the secondgate conducting structure 562 and the thirdgate conducting structure 563 to serve as alanding pad 70 a. - As shown in FIG. 2G, after removing the
second photoresist layer 71, anILD layer 72 with a planarized surface is formed on the entire surface of thesubstrate 50 to fill the gaps between adjacentgate conducting structures 561˜564 by deposition and CMP. Preferably, theILD layer 72 is BPSG, HDP oxide, TEOS oxide or the combination of those. Then, as shown in FIG. 2H, using athird photoresist layer 73 with a pattern of contact holes as the mask, part of theILD layer 72, theSiON liner 68 and thecap layer 59 is removed to form abitline contact hole 741, a firstinterconnection contact hole 742 and a secondinterconnection contact hole 743. Thebitline contact hole 741 exposes thelanding pad 70 a between the secondgate conducting structure 562 and the thirdgate conducting structure 563. The firstinterconnection contact hole 742 is over the firstgate conducting structure 561 to expose the top of thetungsten silicide layer 58. The secondinterconnection contact hole 743 is outside the fourthgate conducting structure 564 to expose the N+-typeion implantation region 66. - As shown in FIG. 2I, after removing the
third photoresist layer 73, afourth photoresist layer 75 with a pattern of interconnections is employed as the mask to remove part of theILD layer 72. Finally, as shown in FIG. 2J, after removing thefourth photoresist layer 75, a second conductive layer 76 is deposited on the entire surface of thesubstrate 50 to fill thebitline contact hole 741, the firstinterconnection contact hole 742 and the secondinterconnection contact hole 743, and then CMP is used to level off the surfaces of the second conductive layer 76 and theILD layer 72. Preferably, the second conductive layer 76 is polysilicon, tungsten or other conductive materials. The secondconductive layer 76 b remaining in the contact holes 741, 742 and 743 respectively serves as a bitline contact plug, a first interconnection contact plug and a second interconnection contact plug. The secondconductive layer 76 a remaining on the contact plugs serves as a bitline/interconnection structure. - Compared with the prior art of forming the bitline contact hole, the present invention has advantages as listed below. First, since the etching selectivity from polysilicon to silicon oxide is high, the formation of the
bitline contact hole 741 over thelanding pad 70 a avoids the problems of poor etching profile, short circuits in the interconnection structure and blind window caused by conventional SAC process. Second, thefirst photoresist layer 69 is used as the mask to remove theliner 68 between the secondgate conducting layer 562 and thethird conducting layer 563, thus the recess depth of the exposed silicon cannot be large to prevent the formation of seams in theSTI region 52. This prevents junction leakage between thesubstrate 50 and thecontact plug 76 b. Third, a good ohmic contact is formed between the bitline contact plug 76 b, thelanding pad 70 a and thesubstrate 50 to provide a stable contact resistance. Fourth, thecap layer 59 of a thinner thickness is employed to reduce thermal budget and promote electrical properties of the product. Fifth, the present invention can be applied to manufacture a device of a further reduced size without encountering problems in photolithography. Sixth, the materials used for thecap layer 59 and thesecond spacer 64 are not only SiN and SiON, but also silicon oxide. This increases the selectiveness of using materials to form thecap layer 59 and thesecond spacer 64. In a preferred embodiment, when theliner 68 is silicon nitride, theILD layer 72 is BPSG. In another preferred embodiment, when theliner 68 is silicon oxide, the material used to form theILD layer 72 is selected from dielectric materials not containing boron and phosphorous. This prevents the boron ions or phosphorous ions from diffusing into thesubstrate 50 so as to ensure the device stability. - It is to be understood that the present invention is not limited to the embodiments described above, but encompasses any and all embodiments within the scope of the following claims.
Claims (27)
1. A method of forming contact plugs, comprising steps of:
(a) providing a semiconductor substrate having a first gate conducting structure, a second gate conducting structure, a third gate conducting structure and a fourth gate conducting structure arranging in sequence, wherein the second gate conducting structure and the third gate conducting structure are formed within an active area;
(b) filling the gap between the second gate conducting structure and the third gate conducting structure with a first conductive layer;
(c) forming an inter-layered dielectric (ILD) layer with a planarized surface on the entire surface of the substrate to cover the first conductive layer and fill the gap between the first gate conducting structure and the second gate conducting structure and the gap between the third gate conducting structure and the fourth gate conducting structure;
(d) forming a bitline contact hole in the ILD layer to expose the first conductive layer;
(e) filling the bitline contact hole with a second conductive layer to serve as a bitline contact plug.
2. The method according to claim 1 , wherein the first conductive layer is polysilicon.
3. The method according to claim 1 , wherein the formation of the first conductive layer comprises steps of:
(b1) depositing the first conductive layer on the entire surface of the substrate;
(b2) using chemical mechanical polishing (CMP) to planarize the surface of the first conductive layer until the top of the first conductive layer reaches a height equal to or slightly higher than the top of each gate conducting structure; and
(b3) using photolithography and etching to remove most of the first conductive layer, wherein the first conductive layer only remains between the second conductive structure and the third conductive structure.
4. The method according to claim 1 , wherein each of the gate conducting structures comprises a gate electrode layer and a cap layer.
5. The method according to claim 4 , wherein the material used to form the cap layer is selected from the group consisting of SiN, SiON and silicon oxide.
6. The method according to claim 1 , wherein the material used to form the ILD layer is selected from the group consisting of BPSG, HDP oxide and TEOS oxide.
7. The method according to claim 1 , wherein the step (d) forms a first interconnection contact hole and a second interconnection contact hole in the ILD layer at the same time that the bitline contact hole is formed, wherein the first interconnection contact hole exposes the top of the first gate conducting structure and the second interconnection contact hole exposes the substrate outside the fourth gate conducting structure.
8. The method according to claim 7 , wherein the step (e) fills the first interconnection contact hole and the second interconnection contact hole with the second conductive layer to serve as a first interconnection contact plug and a second interconnection contact plug.
9. The method according to claim 1 , wherein the substrate comprises a first shallow trench isolation (STI) region between the first gate conducting structure and the second gate conducting structure, and a second STI region between the third gate conducting structure and the fourth gate conducting structure, wherein the first STI region and the second STI region defines the active area.
10. A method of forming contact plugs, comprising steps of:
(a) providing a semiconductor substrate having a first gate conducting structure, a second gate conducting structure, a third gate conducting structure and a fourth gate conducting structure arranging in sequence, wherein the second gate conducting structure and the third gate conducting structure are formed within an active area;
(b) filling the gap between the second gate conducting structure and the third gate conducting structure with a first conductive layer;
(c) forming an inter-layered dielectric (ILD) layer with a planarized surface on the entire surface of the substrate to cover the first conductive layer and fill the gap between the first gate conducting structure and the second gate conducting structure and the gap between the third gate conducting structure and the fourth gate conducting structure;
(d) forming a first contact hole, a second contact hole and a third contact hole in the ILD layer, wherein the first contact hole exposes the top of the first gate conducting structure, the second contact hole exposes the first conductive layer, and the third contact hole exposes the substrate outside the fourth gate conducting structure;
(e) filling the first contact hole, the second contact hole and the third contact hole with a second conductive layer, wherein the second conductive layer in the second contact hole serves as a bitline contact plug.
11. The method according to claim 10 , wherein the first conductive layer is polysilicon.
12. The method according to claim 10 , wherein the formation of the first conductive layer comprises steps of:
(b1) depositing the first conductive layer on the entire surface of the substrate;
(b2) using chemical mechanical polishing (CMP) to planarize the surface of the first conductive layer until the top of the first conductive layer reaches a height equal to or slightly higher than the top of each gate conducting structure; and
(b3) using photolithography and etching to remove most of the first conductive layer, wherein the first conductive layer only remains between the second conductive structure and the third conductive structure.
13. The method according to claim 10 , wherein each of the gate conducting structures comprises a gate electrode layer and a cap layer.
14. The method according to claim 13 , wherein the material used to form the cap layer is selected from the group consisting of SiN, SiON and silicon oxide.
15. The method according to claim 10 , wherein the material used to form the ILD layer is selected from the group consisting of BPSG, HDP oxide and TEOS oxide.
16. The method according to claim 10 , wherein the second conductive layer in the second contact hole and the third contact hole serves as interconnection contact plugs.
17. The method according to claim 10 , wherein the substrate comprises a first shallow trench isolation (STI) region between the first gate conducting structure and the second gate conducting structure, and a second STI region between the third gate conducting structure and the fourth gate conducting structure, wherein the first STI region and the second STI region defines the active area.
18. A method of forming contact plugs, comprising steps of:
(a) providing a semiconductor substrate having a first gate conducting structure, a second gate conducting structure, a third gate conducting structure and a fourth gate conducting structure arranged in sequence, wherein the second gate conducting structure and the third gate conducting structure are formed within an active area;
(b) forming a liner on the entire surface of the substrate;
(c) removing the liner disposed on the top of the second gate conducting structure and the third gate conducting structure and the liner disposed on the substrate between the second gate conducting structure and the third gate conducting structure;
(d) filling the gap between the second gate conducting structure and the third gate conducting structure with a first conductive layer;
(e) forming an inter-layered dielectric (ILD) layer with a planarized surface on the entire surface of the substrate to cover the first conductive layer and filling the gap between the first gate conducting structure and the second gate conducting structure and the gap between the third gate conducting structure and the fourth gate conducting structure;
(f) forming a first contact hole, a second contact hole and a third contact hole in the ILD layer, wherein the first contact hole exposes the top of the first gate conducting structure, the second contact hole exposes the first conductive layer, and the third contact hole exposes the substrate outside the fourth gate conducting structure;
(g) filling the first contact hole, the second contact hole and the third contact hole with a second conductive layer, wherein the second conductive layer in the second contact hole serves as a bitline contact plug.
19. The method according to claim 18 , wherein the first conductive layer is polysilicon.
20. The method according to claim 18 , wherein the formation of the first conductive layer comprises steps of:
(d1) depositing the first conductive layer on the entire surface of the substrate;
(d2) using chemical mechanical polishing (CMP) to planarize the surface of the first conductive layer until the top of the first conductive layer reaches a height equal to or slightly higher than the top of each gate conducting structure; and
(d3) using photolithography and etching to remove most of the first conductive layer, wherein the first conductive layer only remains between the second conductive structure and the third conductive structure.
21. The method according to claim 18 , wherein the material used to form the liner is selected from the group consisting of SiN, SiON and silicon oxide.
22. The method according to claim 18 , wherein each of the gate conducting structures comprises a gate electrode layer and a cap layer.
23. The method according to claim 22 , wherein the material used to form the cap layer is selected from the group consisting of SiN, SiON and silicon oxide.
24. The method according to claim 18 , wherein the material used to form the ILD layer is selected from the group consisting of BPSG, HDP oxide and TEOS oxide.
25. The method according to claim 18 , wherein each gate conducting structure comprises a spacer formed on its sidewalls.
26. The method according to claim 25 , wherein the material used to form the spacer is at least one of the group consisting of SiN, SiON and silicon oxide.
27. The method according to claim 18 , wherein the substrate comprises a first shallow trench isolation (STI) region between the first gate conducting structure and the second gate conducting structure, and a second STI region between the third gate conducting structure and the fourth gate conducting structure, wherein the first STI region and the second STI region define the active area.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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TW90126528 | 2001-10-26 | ||
TW090126528A TW518719B (en) | 2001-10-26 | 2001-10-26 | Manufacturing method of contact plug |
DE10206149A DE10206149C1 (en) | 2001-10-26 | 2002-02-14 | Bitline contact plug formation method for flash memory manufacture, involves forming contact hole in inter-layered dielectric layer that covers conductive layer and fills gap between respective gate conducting structures |
Publications (2)
Publication Number | Publication Date |
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US6548394B1 US6548394B1 (en) | 2003-04-15 |
US20030082900A1 true US20030082900A1 (en) | 2003-05-01 |
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US10/061,646 Expired - Lifetime US6548394B1 (en) | 2001-10-26 | 2002-02-01 | Method of forming contact plugs |
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DE (1) | DE10206149C1 (en) |
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US7098141B1 (en) * | 2003-03-03 | 2006-08-29 | Lam Research Corporation | Use of silicon containing gas for CD and profile feature enhancements of gate and shallow trench structures |
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US20090176365A1 (en) * | 2006-02-27 | 2009-07-09 | Micron Technology, Inc. | Contact formation |
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US6573132B1 (en) * | 1999-03-25 | 2003-06-03 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating a semiconductor device having contacts self-aligned with a gate electrode thereof |
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2001
- 2001-10-26 TW TW090126528A patent/TW518719B/en not_active IP Right Cessation
-
2002
- 2002-02-01 US US10/061,646 patent/US6548394B1/en not_active Expired - Lifetime
- 2002-02-14 DE DE10206149A patent/DE10206149C1/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
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TW518719B (en) | 2003-01-21 |
DE10206149C1 (en) | 2003-09-25 |
US6548394B1 (en) | 2003-04-15 |
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