US20030102491A1 - Bilayer silicon carbide based barrier - Google Patents

Bilayer silicon carbide based barrier Download PDF

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US20030102491A1
US20030102491A1 US09/683,245 US68324501A US2003102491A1 US 20030102491 A1 US20030102491 A1 US 20030102491A1 US 68324501 A US68324501 A US 68324501A US 2003102491 A1 US2003102491 A1 US 2003102491A1
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Neng-Hui Yang
Cheng-Yuan Tsai
Hsin-Chang Wu
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United Microelectronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3148—Silicon Carbide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to an integrated circuit, and more particularly, to a bilayer silicon carbide (SiC) barrier for interconnect metallization applications.
  • SiC silicon carbide
  • the speed of an interconnect structure is characterized in terms of RC (resistance/capacitance) delays.
  • the lower dielectric constant materials help in reducing inter-metal capacitance, and therefore, reduce RC delays and improve device speeds.
  • Dual damascene processes are world widely used interconnect metallization techniques applying in high-speed logic devices of design rules below 0.25 micrometers.
  • interconnect metallization lines are formed in trenches of dielectric layers and are formed of copper (Cu).
  • the dual-damascene structures further comprises via plugs to electrically connect the metallization lines with other conductive layers.
  • the conventional dual damascene techniques include: (1) a via-first process, (2) a self-aligned process, and (3) a trench-first process.
  • a barrier layer is finally deposited on the metal layer filling in the trench.
  • the barrier layer is used to prevent outward migration of metals and prevent oxidation of metals.
  • silicon nitride is used to form the barrier layer.
  • silicon nitride has a great dielectric constant (>6.5) and thus reduces operating speeds of the interconnect metallization lines.
  • Furumura et al. U.S. Pat. No.
  • SiC silicon carbide
  • a-SiC amorphous SiC
  • the SiC barrier layer has a lower dielectric constant compared to the conventional silicon nitride barrier layer, however, the SiC barrier layer still has some disadvantages, such as (1) low breakdown voltages, (2) high leakage currents, and (3) unstable film properties. Therefore, using low dielectric constant materials to form a barrier layer and simultaneously prevent the above-mentioned problems has become an important issue.
  • An integrated circuit of the present invention substantially includes at least one metallic wiring layer damascened on a first dielectric layer, a bilayer SiC-based barrier deposited over the metallic wiring layer and the first dielectric layer, and a second dielectric layer formed over the bilayer SiC-based barrier.
  • the bilayer SiC-based barrier has a nitrogen-doped SiC bottom layer and an oxygen-doped SiC top layer formed by an in-situ deposition over the nitrogen-doped SiC bottom layer.
  • the nitrogen-doped SiC bottom layer has a minimum thickness to prevent metal atoms of the metallic wiring layer from diffusing to the second dielectric layer and, at the same time, avoid oxygen atoms of the oxygen-doped SiC top layer from diffusing into the metallic wiring layer.
  • FIG. 1 is a cross-sectional diagram of an interconnect metallization according to the present invention.
  • Table. 1 illustrates electrical properties of a bilayer SiC-based barrier (120 ⁇ SiN x C y +380 ⁇ SiO x C y ) compared to a single-layer SiC barrier (500 ⁇ SiC).
  • the present invention utilizes a bilayer SiC-based film as a barrier of an interconnect metallization.
  • the bilayer SiC-based film consists of a nitrogen-doped SiC (SiN x C y ) bottom layer and an oxygen-doped SiC (SiO x C y ) top layer.
  • the nitrogen-doped SiC bottom layer has perfect electrical properties, such as high breakdown voltages and low leakage currents.
  • the oxygen-doped SiC top layer has high breakdown voltages and perfect film stability.
  • the bilayer barrier of the present invention has the combining advantages of these two layers of high breakdown voltages, low leakage currents, and film stability.
  • the bilayer SiC has better mechanical properties.
  • Using the nitrogen-doped SiC layer only or using the oxygen-doped SiC layer only to form the barrier has some disadvantages.
  • nitrogen atoms of the barrier form amine to react with deep UV photo resist to cause photo resist footing.
  • oxygen atoms of the barrier diffuse into the metallic wiring layer to oxide metallic wiring lines.
  • the present invention utilizes the nitrogen-doped SiC layer as the bottom layer of the barrier and utilizes the oxygen-doped SiC layer as the top layer of the barrier, thus forming the bilayer barrier to improve film stability of the oxygen-doped SiC layer and prevent metal atoms of the metallic wiring layer from diffusing out to the dielectric layer and, at the same time, avoid oxygen atoms of the oxygen-doped SiC layer from diffusing into the metallic wiring layer.
  • FIG. 1 Please refer to FIG. 1 of a cross-sectional of an interconnect metallization 10 according to the present invention.
  • the interconnect metallization 10 has a first dielectric layer 11 .
  • a metallic wiring layer 12 is formed in the first dielectric layer 11 .
  • a bilayer SiC-based barrier 13 is deposited over the metallic wiring layer 12 and the first dielectric layer 11 .
  • a second dielectric layer 14 is formed over the bilayer SiC-based barrier 13 .
  • the bilayer SiC-based barrier 13 consists of a nitrogen-doped SiC bottom layer 13 a and an oxygen-doped SiC top layer 13 b.
  • the nitrogen-doped SiC bottom layer 13 a has a minimum thickness to prevent diffusion of metal atoms from the metallic wiring layer 12 to the second dielectric layer 14 and prevent diffusion of oxygen atoms from the oxygen-doped SiC top layer 13 b to the metallic wiring layer 12 as well.
  • the second dielectric layer 14 further comprises a metallic wiring layer (not shown), functioning as a via plug, penetrating through the bilayer SiC-based barrier 13 to electrically connect to the bottom metallic wiring layer 12 .
  • a method of forming the metallic wiring layer 12 in the first dielectric layer 11 includes a via-first fabrication process, a partial-via fabrication process, a self-aligned fabrication process, a trench-first fabrication or other interconnect metallization damascene fabrication process.
  • the techniques of forming the damascene metallic wiring layer are introduced in U.S. Pat. No. 6,1 97,681, Forming copper interconnects in dielectric materials with low constant dielectrics, by Liu et al., and in U.S. Pat. No. 6,004,1 88,Method for forming copper damascene structure by using a dual CMP barrier layer, by Roy et al.
  • the first dielectric layer 11 and the second dielectric layer 14 are made of fluorinated silicon glass (FSG), hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), black diamond materials, Coral, porous silica, amorphous fluorocarcon polymers, fluorinated polyimide, PTFE, poly(arylene ether), benzocyclobutene, SiLKTM or FLARETM.
  • a dielectric constant of the first dielectric layer 11 and the second dielectric layer 14 is less than 3.2.
  • the metallic wiring layer 12 is made of copper using a physical vapor deposition (PVD), an electroplating, a sputtering or an electron beam evaporation.
  • both the nitrogen-doped SiC bottom layer 13 a and the oxygen-doped SiC top layer 13 b of the bilayer SiC-based barrier 13 are deposited by using a plasma-enhanced chemical vapor deposition (PECVD) process.
  • PECVD plasma-enhanced chemical vapor deposition
  • the nitrogen-doped SiC bottom layer 13 a and the oxygen-doped SiC top layer 13 b are formed in the same PECVD chamber by an in-situ deposition. Parameters of the CVD process, such as gases, operating pressure, temperature and reacting time can be adjusted according to machine types or process designs.
  • a NH 3 flow rate ranging from 1000 to 1300 standard cubic centimeters per minute (sccm), the NH 3 flow rate having a preferred value of 1200 sccm; a nitrogen gas flow rate ranging from 1000 to 1300 sccm, the nitrogen gas flow rate having a preferred value of 1200 sccm; a 4-methylsilane (Si(CH 3 ) 4 ) flow rate ranging from 1200 to 1600 sccm, the (Si(CH 3 ) 4 ) flow rate having a preferred value of 1400 sccm; a high frequency radio frequency (HFRF) of about 1450 watts; a low frequency radio frequency (LFRF) of about 300 watts; an operating pressure of about 4 torr and an temperature of about 400° C.
  • HFRF high frequency radio frequency
  • LFRF low frequency radio frequency
  • the nitrogen-doped SiC bottom layer 13 a has the minimum thickness of about 100 angstroms ( ⁇ ), and 120 ⁇ is a preferred thickness of the bottom layer 13 a.
  • methylsilane (Si(CH 3 )H 3 ), 2-methylsilane (Si(CH 3 ) 2 H 2 ), or 3-methylsilane (Si(CH 3 ) 3 H) can be used as a precursor gas to form the bottom layer 13 a.
  • the nitrogen-doped SiC bottom layer 13 a and the oxygen-doped SiC top layer 13 b are formed in the same PECVD chamber. In other words, after depositing the nitrogen-doped SiC bottom layer 13 a, the oxygen-doped SiC top layer 13 b is in-situ deposited over the nitrogen-doped SiC bottom layer 13 a.
  • Parameter ranges of depositing the oxygen-doped SiC top layer 13 b are listed below:a Si(CH 3 ) 3 H flow rate of about 600 sccm; an oxygen gas flow rate of about 30 sccm; a HFRF of about 150 watts; an operating pressure ranging from 0.5 to 5 torr, the operating pressure having a preferred value of 2 torr; a temperature ranging from 350 to 450° C., the temperature having a preferred value of 400° C.
  • Si(CH 3 )H 3 , Si(CH 3 ) 2 H 2 or Si(CH 3 ) 3 H can be used as the precursor gas to form the top layer 13 b.
  • Table. 1 of electrical properties a bilayer SiC-based barrier with components of 120 ⁇ SiN x C y and 380 ⁇ SiO x C y .
  • the bilayer SiC-based barrier is compared with a single layer SiC-based barrier having a thickness the same as the thickness of the bilayer SiC-based barrier.
  • the bilayer SiC-based barrier has a dielectric constant of about 4.2, a breakdown voltage of about 4.0 MV/cm and a leakage current of about 1.7E-9 A/cm 2 .
  • the single layer SiC-based barrier has a dielectric constant of about 4.5, a breakdown voltage of about 5.5 MV/cm and a leakage current of about 2.0E-8 A/cm 2 . Therefore, the bilayer SiC-based barrier has better electrical properties than the single layer SiC-based barrier.

Abstract

A bilayer SiC-based barrier is formed over a metallic wiring layer and a first dielectric layer. The bilayer SiC-based barrier consists of a nitrogen-doped SiC bottom layer and an oxygen-doped SiC top layer. The nitrogen-doped SiC bottom layer has a minimum thickness to prevent metal atoms of the metallic wiring layer from diffusing out to a second dielectric layer and, at the same time, avoid oxygen atoms of the oxygen-doped SiC top layer from diffusing into the metallic wiring layer.

Description

    BACKGROUND OF THE INVENTION 1. Field of the Invention
  • The present invention relates to an integrated circuit, and more particularly, to a bilayer silicon carbide (SiC) barrier for interconnect metallization applications. [0001]
  • 2. Description of the Prior Art [0002]
  • As a demand for faster device speeds continues to increase, fabrication and design engineers have been implementing lower dielectric constant materials. Typically, the speed of an interconnect structure is characterized in terms of RC (resistance/capacitance) delays. The lower dielectric constant materials help in reducing inter-metal capacitance, and therefore, reduce RC delays and improve device speeds. [0003]
  • Dual damascene processes are world widely used interconnect metallization techniques applying in high-speed logic devices of design rules below 0.25 micrometers. In dual-damascene applications, interconnect metallization lines are formed in trenches of dielectric layers and are formed of copper (Cu). In addition to the interconnect metallization lines, the dual-damascene structures further comprises via plugs to electrically connect the metallization lines with other conductive layers. As known to those skilled in the art, the conventional dual damascene techniques include: (1) a via-first process, (2) a self-aligned process, and (3) a trench-first process. [0004]
  • No matter which fabrication process of the above-mentioned dual damascene techniques is chosen, a barrier layer is finally deposited on the metal layer filling in the trench. The barrier layer is used to prevent outward migration of metals and prevent oxidation of metals. Normally, silicon nitride is used to form the barrier layer. However, silicon nitride has a great dielectric constant (>6.5) and thus reduces operating speeds of the interconnect metallization lines. In order to improve the operating speeds of the interconnection metallization lines, Furumura et al. (U.S. Pat. No. 5,103,285) use silicon carbide (SiC) to form a barrier layer between a silicon substrate and a metal wire, the SiC barrier layer having a low dielectric constant of about 4-5. Mark et al. (U.S. Pat. No. 5,818,071) use amorphous SiC (a-SiC) to form a barrier layer between a metal wire and a dielectric layer, preventing diffusion of metal atoms from the metal wire to the dielectric layer. [0005]
  • The SiC barrier layer has a lower dielectric constant compared to the conventional silicon nitride barrier layer, however, the SiC barrier layer still has some disadvantages, such as (1) low breakdown voltages, (2) high leakage currents, and (3) unstable film properties. Therefore, using low dielectric constant materials to form a barrier layer and simultaneously prevent the above-mentioned problems has become an important issue. [0006]
    • SUMMARY OF THE INVENTION
  • It is therefore an objective of the present invention to provide an interconnect metallization line with high performance and high reliability. [0007]
  • It is another objective of the present invention to provide a bilayer SiC-based barrier layer to prevent the above-mentioned problems. [0008]
  • An integrated circuit of the present invention substantially includes at least one metallic wiring layer damascened on a first dielectric layer, a bilayer SiC-based barrier deposited over the metallic wiring layer and the first dielectric layer, and a second dielectric layer formed over the bilayer SiC-based barrier. [0009]
  • The bilayer SiC-based barrier has a nitrogen-doped SiC bottom layer and an oxygen-doped SiC top layer formed by an in-situ deposition over the nitrogen-doped SiC bottom layer. The nitrogen-doped SiC bottom layer has a minimum thickness to prevent metal atoms of the metallic wiring layer from diffusing to the second dielectric layer and, at the same time, avoid oxygen atoms of the oxygen-doped SiC top layer from diffusing into the metallic wiring layer. [0010]
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the multiple figures and drawings.[0011]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional diagram of an interconnect metallization according to the present invention.[0012]
  • Table. 1 illustrates electrical properties of a bilayer SiC-based barrier (120 Å SiN[0013] x Cy+380 Å SiOxCy) compared to a single-layer SiC barrier (500 Å SiC).
    • DETAILED DESCRIPTION
  • The present invention utilizes a bilayer SiC-based film as a barrier of an interconnect metallization. The bilayer SiC-based film consists of a nitrogen-doped SiC (SiN[0014] xCy) bottom layer and an oxygen-doped SiC (SiOxCy) top layer. The nitrogen-doped SiC bottom layer has perfect electrical properties, such as high breakdown voltages and low leakage currents. The oxygen-doped SiC top layer has high breakdown voltages and perfect film stability. Thus, the bilayer barrier of the present invention has the combining advantages of these two layers of high breakdown voltages, low leakage currents, and film stability. In addition, while comparing the bilayer barrier of the present invention to the conventional single-layer SiC barrier, the bilayer SiC has better mechanical properties.
  • Using the nitrogen-doped SiC layer only or using the oxygen-doped SiC layer only to form the barrier has some disadvantages. When the barrier is composed of the nitrogen-doped SiC layer only, nitrogen atoms of the barrier form amine to react with deep UV photo resist to cause photo resist footing. When the barrier is composed of oxygen-doped SiC layer only, oxygen atoms of the barrier diffuse into the metallic wiring layer to oxide metallic wiring lines. Therefore, the present invention utilizes the nitrogen-doped SiC layer as the bottom layer of the barrier and utilizes the oxygen-doped SiC layer as the top layer of the barrier, thus forming the bilayer barrier to improve film stability of the oxygen-doped SiC layer and prevent metal atoms of the metallic wiring layer from diffusing out to the dielectric layer and, at the same time, avoid oxygen atoms of the oxygen-doped SiC layer from diffusing into the metallic wiring layer. [0015]
  • Please refer to FIG. 1 of a cross-sectional of an [0016] interconnect metallization 10 according to the present invention. As shown in FIG. 1, the interconnect metallization 10 has a first dielectric layer 11. A metallic wiring layer 12 is formed in the first dielectric layer 11. A bilayer SiC-based barrier 13 is deposited over the metallic wiring layer 12 and the first dielectric layer 11. Finally, a second dielectric layer 14 is formed over the bilayer SiC-based barrier 13. The bilayer SiC-based barrier 13 consists of a nitrogen-doped SiC bottom layer 13 a and an oxygen-doped SiC top layer 13 b. Wherein, the nitrogen-doped SiC bottom layer 13 a has a minimum thickness to prevent diffusion of metal atoms from the metallic wiring layer 12 to the second dielectric layer 14 and prevent diffusion of oxygen atoms from the oxygen-doped SiC top layer 13 b to the metallic wiring layer 12 as well. In other embodiments of the present invention, the second dielectric layer 14 further comprises a metallic wiring layer (not shown), functioning as a via plug, penetrating through the bilayer SiC-based barrier 13 to electrically connect to the bottom metallic wiring layer 12.
  • A method of forming the [0017] metallic wiring layer 12 in the first dielectric layer 11 includes a via-first fabrication process, a partial-via fabrication process, a self-aligned fabrication process, a trench-first fabrication or other interconnect metallization damascene fabrication process. The techniques of forming the damascene metallic wiring layer are introduced in U.S. Pat. No. 6,1 97,681, Forming copper interconnects in dielectric materials with low constant dielectrics, by Liu et al., and in U.S. Pat. No. 6,004,1 88,Method for forming copper damascene structure by using a dual CMP barrier layer, by Roy et al.
  • The first [0018] dielectric layer 11 and the second dielectric layer 14 are made of fluorinated silicon glass (FSG), hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), black diamond materials, Coral, porous silica, amorphous fluorocarcon polymers, fluorinated polyimide, PTFE, poly(arylene ether), benzocyclobutene, SiLK™ or FLARE™. In the preferred embodiment of the present invention, a dielectric constant of the first dielectric layer 11 and the second dielectric layer 14 is less than 3.2. The metallic wiring layer 12 is made of copper using a physical vapor deposition (PVD), an electroplating, a sputtering or an electron beam evaporation.
  • In the preferred embodiment, both the nitrogen-doped [0019] SiC bottom layer 13 a and the oxygen-doped SiC top layer 13 b of the bilayer SiC-based barrier 13 are deposited by using a plasma-enhanced chemical vapor deposition (PECVD) process. Wherein, the nitrogen-doped SiC bottom layer 13 a and the oxygen-doped SiC top layer 13 b are formed in the same PECVD chamber by an in-situ deposition. Parameters of the CVD process, such as gases, operating pressure, temperature and reacting time can be adjusted according to machine types or process designs.
  • Some examples of the parameter ranges for depositing the nitrogen-doped [0020] SiC bottom layer 13 a are listed below: a NH3 flow rate ranging from 1000 to 1300 standard cubic centimeters per minute (sccm), the NH3 flow rate having a preferred value of 1200 sccm; a nitrogen gas flow rate ranging from 1000 to 1300 sccm, the nitrogen gas flow rate having a preferred value of 1200 sccm; a 4-methylsilane (Si(CH3)4) flow rate ranging from 1200 to 1600 sccm, the (Si(CH3)4) flow rate having a preferred value of 1400 sccm; a high frequency radio frequency (HFRF) of about 1450 watts; a low frequency radio frequency (LFRF) of about 300 watts; an operating pressure of about 4 torr and an temperature of about 400° C.
  • In order to avoid the metal atoms of the [0021] metallic wiring layer 12 from diffusing out to the second dielectric layer 14 and, at the same time, avoid oxygen atoms of the oxygen-doped SiC top layer 13 b from diffusing into the metallic wiring layer 12, the nitrogen-doped SiC bottom layer 13 a has the minimum thickness of about 100 angstroms (Å), and 120 Å is a preferred thickness of the bottom layer 13 a. In other embodiments of the present invention, methylsilane (Si(CH3)H3), 2-methylsilane (Si(CH3)2H2), or 3-methylsilane (Si(CH3)3H) can be used as a precursor gas to form the bottom layer 13 a.
  • The nitrogen-doped [0022] SiC bottom layer 13 a and the oxygen-doped SiC top layer 13 b are formed in the same PECVD chamber. In other words, after depositing the nitrogen-doped SiC bottom layer 13 a, the oxygen-doped SiC top layer 13 b is in-situ deposited over the nitrogen-doped SiC bottom layer 13 a. Parameter ranges of depositing the oxygen-doped SiC top layer 13 b are listed below:a Si(CH3)3H flow rate of about 600 sccm; an oxygen gas flow rate of about 30 sccm; a HFRF of about 150 watts; an operating pressure ranging from 0.5 to 5 torr, the operating pressure having a preferred value of 2 torr; a temperature ranging from 350 to 450° C., the temperature having a preferred value of 400° C. In other embodiments of the present invention, Si(CH3)H3, Si(CH3)2H2 or Si(CH3)3H can be used as the precursor gas to form the top layer 13 b.
    TABLE 1
    Bilayer SiC
    barrier (120 Å SiN Single layer SiC
    xCy + 380 Å SiO xCy) barrier (500 Å SiC)
    Dielectric constant 4.2 4.5
    (k)
    Breakdown voltage 4.0 2.5
    (MV/cm)
    Current leakage 1.7E−9 2E−8
    (@ 1MV/cm)
  • Please refer to Table. 1 of electrical properties a bilayer SiC-based barrier with components of 120 Å SiN[0023] xCy and 380 Å SiOxCy. In Table. 1, the bilayer SiC-based barrier is compared with a single layer SiC-based barrier having a thickness the same as the thickness of the bilayer SiC-based barrier. As shown in Table. 1, the bilayer SiC-based barrier has a dielectric constant of about 4.2, a breakdown voltage of about 4.0 MV/cm and a leakage current of about 1.7E-9 A/cm2. The single layer SiC-based barrier has a dielectric constant of about 4.5, a breakdown voltage of about 5.5 MV/cm and a leakage current of about 2.0E-8 A/cm2. Therefore, the bilayer SiC-based barrier has better electrical properties than the single layer SiC-based barrier.
  • Those skilled in the art will readily observe that numerous modification and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. [0024]

Claims (19)

What is claimed is:
1. An integrated circuit comprising:
at least one metallic wiring layer damascened on a first dielectric layer;
a multi-layer SiC-based barrier deposited over the metallic wiring layer and the first dielectric layer; and
a second dielectric layer formed over the bilayer SiC-based barrier.
2. The integrated circuit according to claim 1 wherein the metallic wiring layer is made of copper.
3. The integrated circuit according to claim 1 wherein the multi-layer SiC-based barrier is a bilayer SiC-based barrier.
4. The integrated circuit according to claim 1 wherein the multi-layer SiC-based barrier comprises a nitrogen-doped SiC layer and an oxygen-doped SiC layer.
5. The integrated circuit according to claim 4 wherein the oxygen-doped SiC layer is deposited over the nitrogen-doped SiC layer.
6. The integrated circuit according to claim 4 wherein a thickness of the nitrogen-doped SiC layer is greater than or equal to 100 angstroms.
7. The integrated circuit according to claim 4 wherein the multi-layer SiC-based barrier is deposited by using a plasma-enhanced chemical vapor deposition (PECVD) process.
8. The integrated circuit according to claim 4 wherein the nitrogen-doped SiC layer and the oxygen-doped SiC layer are formed in one PECVD chamber.
9. The integrated circuit according to claim 1 wherein both of the first dielectric layer and the second dielectric layer have a dielectric constant of less than about 3.2.
10. The integrated circuit according to claim 1 wherein the first dielectric layer is formed by using a chemical vapor deposition (CVD) process.
11. The integrated circuit according to claim 10 wherein the first dielectric layer is made from a methylsilane precursor.
12. The integrated circuit according to claim 11 wherein the methylsilane precursor is selected from a group consisting of methylsilane (Si(CH3)H3), 2-methylsilane (Si(CH3)2H2), and 3-methylsilane (Si(CH3)3H).
13. An integrated circuit comprising:
at least one metallic wiring layer damascened on a first dielectric layer;
a bilayer SiC-based barrier deposited over the metallic wiring layer and the first dielectric layer; and
a second dielectric layer formed over the bilayer SiC-based barrier;
wherein the bilayer SiC-based barrier consists of a nitrogen-doped SiC bottom layer having a minimum thickness and an oxygen-doped SiC top layer that is in-situ deposited over the bottom undoped SiC layer, and wherein the nitrogen-doped SiC bottom layer can prevent atoms of the metallic wiring layer from diffusing out to the second dielectric layer and, at the same time, avoid oxygen of the oxygen-doped SiC top layer from diffusing into the metallic wiring layer.
14. The integrated circuit according to claim 13 wherein the metallic wiring layer is made of copper.
15. The integrated circuit according to claim 13 wherein the minimum thickness of the nitrogen-doped SiC bottom layer is 100 angstoms.
16. The integrated circuit according to claim 13 wherein the bilayer SiC-based barrier is deposited by using a plasma-enhanced chemical vapor deposition (PECVD) process.
17. The integrated circuit according to claim 13 wherein the first dielectric layer is formed by using a chemical vapor deposition (CVD) process.
18. The integrated circuit according to claim 17 wherein the first dielectric layer is made from a methylsilane precursor.
19. The integrated circuit according to claim 18 wherein the methylsilane precursor is selected from a group consisting of methylsilane (Si(CH3)H3), 2-methylsilane (Si(CH3)2H2) and 3-methylsilane (Si(CH3)3H).
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