US20030146089A1 - Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence - Google Patents
Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence Download PDFInfo
- Publication number
- US20030146089A1 US20030146089A1 US10/358,925 US35892503A US2003146089A1 US 20030146089 A1 US20030146089 A1 US 20030146089A1 US 35892503 A US35892503 A US 35892503A US 2003146089 A1 US2003146089 A1 US 2003146089A1
- Authority
- US
- United States
- Prior art keywords
- mask
- workpiece
- plating
- electrolyte
- top portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
- C25D17/001—Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
- C25D17/008—Current shielding devices
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/38—Electroplating: Baths therefor from solutions of copper
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
- C25D5/022—Electroplating of selected surface areas using masking means
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/18—Electroplating using modulated, pulsed or reversing current
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/22—Electroplating combined with mechanical treatment during the deposition
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/34—Pretreatment of metallic surfaces to be electroplated
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
Abstract
The present invention relates to methods and apparatus for plating a conductive material on a substrate surface in a highly desirable manner. The invention removes at least one additive adsorbed on the top portion of the workpiece more than at least one additive disposed on a cavity portion, thereby allowing plating of the conductive material take place before the additive fully re-adsorbs onto the top portion and causing greater plating of the cavity portion relative to the top portion.
Description
- This application is a divisional of Ser. No. 09/740,701, filed Dec. 18, 2000 which claims priority to Application Ser. No. 60/224,739 filed Aug. 10, 2000 all incorporated herein by reference.
- The present invention relates generally to a semiconductor plating method and apparatus. More particularly, the present invention is directed to a method and apparatus that creates a differential between additive adsorbed on a top surface of a workpiece and additive adsorbed within a cavity portion of the workpiece using an external influence to enhance plating of a conductive material in the cavity portion of the workpiece.
- There are many steps required in manufacturing multi-level integrated circuits (IC). Such steps include depositing conductive and insulator materials on a semiconductor wafer or substrate followed by full or partly removal of these materials using photo-resist patterning, etching, and the like. After photolithography, patterning and etching steps, the resulting surface is generally non-planar as it contains many cavities or features such as vias, lines, trenches, channels, bond-pads, and the like that come in a wide variety of dimensions and shapes. These features are typically filled with a highly conductive metal material before additional processing steps such as etching and/or chemical mechanical polishing (CMP) is/are performed. Accordingly, a low resistance interconnection structure is formed between the various levels/sections of the IC.
- Copper (Cu) is quickly becoming the preferred material for interconnections in ICs because of its low electrical resistively and high resistance to electro-migration. Electrodeposition is one of the most popular methods for depositing Cu into the features on the substrate surface.
- As can be expected, there are many different designs of Cu plating systems that have been used in this industry. For example, U.S. Pat. No. 5,516,412 issued on May 14, 1996, to Andricacos et al. discloses a vertical paddle plating cell that is designed to electrodeposit a film on a flat article. Next, U.S. Pat. No. 5,985,123 issued on Nov. 16, 1999, to Koon discloses yet another vertical electroplating apparatus, which purports to overcome the non-uniform deposition problems associated with varying substrate sizes. Further, U.S. Pat. No. 5,853,559 issued on Dec. 29, 1998, to Tamaki et al. discloses an electroplating apparatus that minimizes waste of the plating electrolyte and accomplishes high recovery of the electrolyte.
- During the Cu electrodeposition process, specially formulated plating solutions or electrolyte are used. These solutions or electrolyte contain ionic species of Cu and additives to control the texture, morphology, and the plating behavior of the deposited material. Additives are needed to make the deposited layers smooth and somewhat shiny.
- There are many types of Cu plating solution formulations, some of which are commercially available. One such formulation includes Cu-sulfate (CuSO4) as the copper source (see James Kelly et al., Journal of The Electrochemical Society, Vol. 146, pages 2540-2545, (1999)) and includes water, sulfuric acid (H2SO4), and a small amount of chloride ions. As is well known, other chemicals can be added to the Cu plating solution to achieve desired properties of the deposited material.
- The additives in the Cu plating solution can be classified under several categories such as suppressors, levelers, brighteners, grain refiners, wetting agents, stress-reducing agents, accelerators, etc. In many instances, different classifications are often used to describe similar functions of these additives. Today, solutions used in electronic applications, particularly in manufacturing ICs, contain simpler additives consisting of two-component two-ingredient packages (e.g., see Robert Mikkola and Linlin Chen, “Investigation of the Roles of the Additive Components for Second Generation Copper Electroplating Chemistries used for Advanced Interconnect Metallization”, Proceedings of the International Interconnect Technology Conference, pages 117-119, Jun. 5-7, 2000). These formulations are generically known as suppressors and accelerators.
- Suppressors are typically polymer formulated from polyethylene glycol-PEG or polypropylene glycol-PPG and is believed to attach themselves to the substrate surface at high current density regions, thereby forming a high resistance film and suppressing the material deposited thereon. Accelerators are typically organic disulfides that enhance Cu deposition on portions of the substrate surface where they are adsorbed. The interplay between these two additives and possibly the chloride ions determines the nature of the Cu deposit.
- The following figures are used to more fully describe the conventional electrodeposition method and apparatus. FIG. I illustrates a perspective view of a cross-section of a
substrate 3 having aninsulator 2 formed thereon. Using conventional etching techniques, features such as a row ofsmall vias 4 a and awide trench 4 b are formed on theinsulator 2 and thesubstrate 3. In this example, thevias 4 a are narrow and deep; in other words, they have high aspect ratios (i.e., their depth to width ratio is large). Typically, the widths of thevias 4 a are sub-micron. Thetrench 4 b, on the other hand, is typically wide and has a small aspect ratio. In other words, the width of thetrench 4 b may be five to fifty times or more greater than its depth. - FIGS. 2a-2 c illustrate a conventional method for filling the features with Cu. FIG. 2a illustrates a cross sectional view of the
substrate 3 in FIG. 1 having various layers disposed thereon. For example, this figure illustrates thesubstrate 3 and theinsulator 2 having deposited thereon a barrier/glue oradhesion layer 5 and aseed layer 6. Thebarrier layer 5 may be tantalum, nitrides of tantalum, titanium, tungsten, or TiW, etc., or combinations of any other materials that are commonly used in this field. Thebarrier layer 5 is generally deposited using any of the various sputtering methods, by chemical vapor deposition (CVD), or by electroless plating methods. Thereafter, theseed layer 6 is deposited over thebarrier layer 5. Theseed layer 6 material may be copper or copper substitutes and may be deposited on thebarrier layer 5 using various sputtering methods, CVD, or electroless deposition or combinations thereof. - In FIG. 2b, after depositing the
seed layer 6, a conductive material 7 (e.g., copper layer) is generally electrodeposited thereon from a suitable acidic or non-acidic plating bath or bath formulation. During this step, an electrical contact is made to theCu seed layer 6 and/or thebarrier layer 5 so that a cathodic (negative) voltage can be applied thereto with respect to an anode (not shown). Thereafter, the Cu material 7 is electrodeposited over the substrate surface using the specially formulated plating solutions, as discussed above. By adjusting the amounts of the additives, such as the chloride ions, suppressor/inhibitor, and the accelerator, it is possible to obtain bottom-up Cu film growth in the small features. - The Cu material7 completely fills the
via 4 a and is generally uniform in thelarge trench 4 b, but does not completely fill thetrench 4 b because the additives that are used are not operative in large features. For example, it is believed that the bottom up deposition into thevia 4 a occurs because the suppressor/inhibitor molecules attach themselves to the top of thevia 4 a to suppress the material growth thereabouts. These molecules can not effectively diffuse to the bottom surface of thevia 4 a through the narrow opening. Preferential adsorption of the accelerator on the bottom surface of thevia 4 a results in faster growth in that region, resulting in bottom-up growth and the Cu deposit profile as shown in FIG. 2b. Without the appropriate additives, Cu can grow on the vertical walls as well as the bottom surface of thevia 4 a at the same rate, thereby causing defects such as seams and/or voids. - Adsorption characteristics of the suppressor and accelerator additives on the bottom surface of the
large trench 4 b is not expected to be any different than the adsorption characteristics on the top surface of thefield regions 8 of the substrate. Therefore, the Cu thickness t1 at the bottom surface of thetrench 4 b is about the same as the Cu thickness t2 over thefield regions 8. - As can be expected, to completely fill the
trench 4 b with the Cu material 7, further plating is required. FIG. 2c illustrates the resulting structure after additional Cu plating. In this case, the Cu thickness t3 over thefield regions 8 is relatively large and there is a step S1 from thefield regions 8 to the top of the Cu material 7 in thetrench 4 b. For IC applications, the Cu material 7 needs to be subjected to CMP or other material removal process so that the Cu material 7 as well as thebarrier layer 5 in thefield regions 8 are removed, thereby leaving the Cu material 7 only within the features. These removal processes are known to be quite costly. - Thus far, much attention has been focused on the development of Cu plating chemistries and plating techniques that yield bottom-up filling of small features on substrates. This is necessary because, as mentioned above, lack of bottom-up filling can cause defects in the small features. As part of these development efforts, it was discovered that the filling behavior of the small features could be affected not only by the solution chemistry, but also by the type of the power supply used for electrodeposition.
- Recent studies suggest that it might be preferable to use pulse or pulse-reverse plating methods to deposit defect free Cu into the small vias (e.g., U.S. Pat. No. 5,972,192 issued to Dubin et al. on Oct. 26, 1999, and Gandikota et al. “Extension of Copper Plating to 0.13 um Nodes by Pulse-Modulated Plating”, Proceedings of the International Interconnect Technology Conference, pages 239-241, Jun. 5-7, 2000). In the pulse-reverse plating process, a cathodic voltage pulse rather than a cathodic DC voltage is applied to the substrate surface. After a short period of plating during the cathodic pulse, the polarity of the voltage is reversed for a brief period causing electrochemical etching from the deposited material. Plating and etching cycles are then repeated until the small features are filled with high quality Cu. A recent study (e.g., C. H. Hsieh et al., “Film Properties and Surface Profile after Gap Fill of Electrochemically Deposited Cu Films by DC and Pulse Reverse Processes”, Proceedings of the International Interconnect Technology Conference, pages 182-184, Jun. 5-7, 2000), shows that the filling of the vias is controlled mainly by the additive diffusion when the DC process is used, whereas it is mainly controlled by additive adsorption when a pulse-reverse process is used.
- As described above, the attention in the semiconductor industry has mainly been concentrated on filling the various features on semiconductor wafers with Cu. Both DC and pulsed power supplies have been used in the deposition of these Cu films. Filling properties of Cu into small features was found to be a strong function of the type of the power supply used. Although the exact roles of the plating solution additives and their interaction with the applied voltage waveforms are not well understood, it is clear that the kinetics of the additive adsorption and diffusion processes influence the way metals deposit on non-planar substrate surfaces.
- As mentioned above, special bath formulations and pulse plating processes have been developed to obtain bottom-up filling of the small features. However, these techniques have not been found effective in filling the large features. In large features, the additives can freely diffuse in and out of them. The use of standard pulse plating techniques in conjunction with the commonly used additive systems containing chloride ions, accelerators and suppressors/inhibitors do not yield accelerated growth from the bottom surface of the features where the width of the feature is considerably larger than its depth. The growth of Cu in such features is conformal and the film thickness deposited on the bottom surface of the large features is approximately the same as that deposited on the field regions.
- Methods and apparatus to achieve accelerated bottom-up plating in small as well as large features on a substrate would be invaluable in terms of process efficiency and cost since such a process would yield a Cu deposit that is generally planar as illustrated in FIG. 3. The Cu thickness t5 over the
field regions 8 in this example is smaller than the traditional case as shown in FIG. 2c, and the step height S2 would also be much smaller. Removal of the thinner Cu layer in FIG. 3 by CMP or other methods would be easier, providing important cost savings. - Others have previously recognized attractive features of a plated Cu structure such as the one shown in FIG. 3. For example, in a PCT application (“Electroplated Interconnection Structures on Integrated Circuit Chips”, WO 98/27585, Jun. 25, 1998) researchers from International Business Machines Corporation state that the plating processes described therein produce super-filling of only the sub-micron size cavities when plating was carried out in a conventional plating cell. However, it also states that a further benefit could be realized when a cup plating cell is used as described in U.S. Pat. No. 4,339,319 issued on Jul. 13, 1982, to Aigo. In addition, when the substrate surface was held in contact with the meniscus of the electrolyte during plating in a cup plating cell, cavities of greatly different widths could be filled rapidly at the same rate yielding a structure similar to that shown in FIG. 3. The PCT application also mentions that superior performance of the meniscus plating approach was due to the higher concentration of the surface active additive molecules at the air-liquid interface.
- In U.S. Letters Patent 6,176,922 entitled “Method and apparatus for electrochemical mechanical deposition”, commonly owned by the assignee of the present invention, a technique is disclosed that achieves deposition of the conductive material into the cavities on the substrate surface while minimizing deposition on the field regions by polishing the field regions with a pad as the conductive material is deposited. The plating electrolyte in this application is supplied to the small gap between the pad and the substrate surface through a porous pad or through asparities in the pad.
- FIG. 4 shows a schematic depiction of an electrochemical mechanical deposition apparatus that can be used for planar or near-planar Cu deposition on a semiconductor wafer. A
carrier head 10 holds asemiconductor wafer 16 and provides anelectrical lead 17 connected to the conductive portion of thewafer 16. Thehead 10 can be rotated clockwise or counter-clockwise about afirst axis 10 b and can be moved in x, y, and z directions. Apad 18 is provided on top of ananode assembly 19, whichpad 18 faces thewafer 16. Anelectrolyte 20 containing the plating material is applied to thewafer 16 surface using theanode assembly 19. Theelectrolyte 20 can be flowed through the holes/openings in thepad 18, which makes physical contact with thewafer 16 surface. Theelectrolyte 20 then flows in the narrow gap between thewafer 16 and thepad 18, eventually flowing over the edges of thepad 18 into achamber 22 to be re-circulated (not shown) after cleaning/filtering/refurbishing. A secondelectrical lead 24 is connected to theanode assembly 19. Any other known method for providing the electric potentials to theanode assembly 19 andcathode wafer 16 can be used herein. - The
anode assembly 19 can also be rotated around asecond axis 10 c at controlled speeds in both the clockwise and counter-clockwise directions. It is also understood thataxes wafer 16 and thepad 18 is adjustable by moving thecarrier head 10 in the z direction. When thewafer 16 surface and thepad 18 are in contact, the pressure that is exerted on the two surfaces can also be adjusted. The co-pending U.S. Application Ser. No. 09/511,278, entitled “Pad Designs and Structures for a Versatile Materials Processing Apparatus”, filed Feb. 23, 2000, describes various shapes and forms of the holes in thepad 8, through which the electrolyte flows to the wafer surface. - During operation, a potential is applied between the
electrical lead 17 to thewafer 16 and theelectrical lead 24 to theanode assembly 19, making thewafer 16 surface more negative than theanode assembly 19. Theelectrolyte 20 can be introduced to thepad 18 from a reservoir (not shown) located in proximity to theanode assembly 19. Theanode assembly 19 can have an in-channel and holes that are made therein, which together provide a path for theelectrolyte 20 to be fed to the gap between thepad 18 and thewafer 16. - Under applied potential, Cu plates out of the
electrolyte 20 onto thewafer 16 surface. The movingpad 18 that is pushed against thewafer 16 surface at a controlled pressure minimizes accumulation of Cu over certain portions of thewafer 16 surface by polishing the same. - The
pad 18 is preferably nonconductive, hard, porous, or perforated type material so that an electric field can pass through it, while preventing shorting between theanode assembly 19 and thecathode wafer 16. The spacing or gap between thepad 18 and thecathode wafer 16 may range from less than 1 micron up to 2 millimeter. The diameter or cross sectional length of thepad 18 and thewafer 16 may range from about 5 millimeter to over 300 millimeter. The larger thewafer 16 diameter, the larger thepad 18 diameter. - It is an object of the present invention to provide a method and apparatus that plates a conductive material on a substrate surface in a highly desirable manner.
- It is another object of the present invention to provide a method and apparatus that plates a conductive material in both small and large features of a substrate surface with greater efficiency, cost-savings, and superior quality than prior art methods and apparatus.
- It is a further object of the present invention to provide a method and apparatus that plates a conductive material in small and large features on a substrate surface using a mask having one or more opening therein.
- It is yet another object of the present invention to provide a method and apparatus that plates a conductive material in small and large features while electrical power is locally pulsed on the substrate surface due to the movement of the opening(s) in the mask with respect to the substrate surface.
- It is a further object of the present invention to provide a method and apparatus that removes additive that has been previously adsorbed onto the top surface portion of a workpiece in order to enhance the plating of a conductive material on a cavity feature surface portion of the workpiece that did not have previously adsorbed additive removed.
- It is yet another object of the present invention to create a differential between additive adsorbed on a top surface of a workpiece and additive adsorbed within a cavity portion of the workpiece to enhance plating of a conductive material in the cavity portion of the workpiece.
- The above objects of the invention, among others, taken alone or in combination, are achieved by the present invention, which provides an apparatus for, and a method of, plating a conductive material on the surface of a workpiece.
- In one aspect of the method, an electrolyte solution with at least one additive disposed therein is applied over the workpiece, such that the additive becomes adsorbed onto the top portion and the cavity portion of the workpiece. An external influence is applied so that the additive adsorbed onto the top surface is removed, and plating of the conductive material take place before the additive fully re-adsorbs onto the top portion, thereby causing greater plating of the cavity portion relative to the top portion.
- In another aspect of the method, an electrolyte solution with at least one additive disposed therein is applied over the workpiece, such that the additive becomes adsorbed onto the top portion and the cavity portion of the workpiece. An external influence is applied so that a differential in the amount of additive that is adsorbed on the top portion relative to the cavity portion is achieved. Plating takes place while the differential still exists, thereby causing greater plating of the cavity portion relative to the top portion.
- In one aspect of the apparatus, a mask disposed between an anode and the workpiece and is movable with respect to the workpiece physically sweeps a top portion of the workpiece, thereby reducing additive adsorbed thereon, while additive adsorbed on a cavity portion remains. An anode that assists in creating an electric field between it and the workpiece is used to promote plating of the conductor within the electrolyte that is disposed over the workpiece.
- In another aspect of the apparatus, the mask contains an open area that is used to help define where the electric field will exist, thus allowing greater control over where plating will occur on the workpiece.
- These and other objects and advantages of the present invention will become apparent and more readily appreciated from the following detailed description of the presently preferred exemplary embodiments of the invention taken in conjunction with the accompanying drawings, of which:
- FIG. 1 illustrates a perspective view of a cross section of a substrate having an insulator layer and various features formed thereon;
- FIGS. 2a-2 c illustrate cross sectional views of a conventional method for depositing a conductive material on the substrate of FIG. 1;
- FIG. 3 illustrates a cross sectional view of a substrate having a conductive material deposited thereon in accordance with another conventional method;
- FIG. 4 illustrates an example of an electrochemical mechanical deposition apparatus;
- FIG. 5 illustrates a conventional plating cell having an anode, cathode, and electrolyte disposed therein;
- FIG. 6 illustrates a partial view of an apparatus in accordance with the preferred embodiment of the present invention;
- FIGS. 7a-7 d illustrate a mask pulsed plating method in accordance with the preferred embodiment of the present invention;
- FIG. 7e illustrates a graph corresponding to FIGS. 7a-7 d in accordance with the preferred embodiment of the present invention;
- FIG. 8 illustrates a perspective view of an apparatus in accordance with the first preferred embodiment of the present invention;
- FIG. 9 illustrates a perspective view of an apparatus in accordance with the second preferred embodiment of the present invention; and
- FIG. 10 illustrates a side view of an apparatus in accordance with the third preferred embodiment of the present invention.
- The preferred embodiments of the present invention will now be described with reference to the following figures. The inventors of the present invention have found that by mask-pulse plating the conductive material on the substrate surface, a more desirable and high quality conductive material can be deposited in the various features therein.
- The present invention can be used with any substrate such as a semiconductor wafer, flat panel, magnetic film head, packaging substrate, and the like. Further, specific processing parameters such as time, pressure, mask designs, and the like are provided herein, which specific parameters are intended to be explanatory rather than limiting.
- The plating method described herein is called “mask-pulsed” plating. The present invention describes a method and apparatus for mask-pulse plating the conductive material onto the substrate by intermittently moving the mask to make contact with the substrate surface and applying power between an anode and the substrate, the mask being positioned in between the anode and the substrate. Furthermore, the present invention is directed to novel plating method and apparatus that provide enhanced electrodeposition of conductive materials into the various features on the substrate surface.
- FIG. 5 illustrates a plating
cell 30 having therein ananode 31, acathode 32, and anelectrolyte 33. It should be noted that the platingcell 30 is a conventional cell and the exact geometry of the plating cell used in the present invention can vary. Theelectrolyte 33 is in contact with the top surface of thecathode 32. Thecathode 32 in the examples provided herein is a wafer (substrate) having various features on its top surface. When a DC or pulsed voltage is applied between thewafer 32 and theanode 31, Cu from theelectrolyte 33 is deposited on thewafer 32 as described above. The differences between the DC or pulsed power determines the quality of the Cu that is filled in the small features. - FIG. 6 illustrates a preferred embodiment of the present invention. In the present invention, a
mask 40 is positioned in close proximity to thecathode wafer 32, where themask 40 includes anopening 42 through which theelectrolyte 33 makes physical contact with a section of thewafer 32. For ease of understanding and explanation, FIG. 6 does not illustrate the electrical connections, the anode, and the plating cell containing theelectrolyte 33. When an appropriate voltage is applied between thecathode wafer 32 and the anode, theopening 42 allows the Cu from theelectrolyte 33 to be plated onto the surface of thesubstrate 32 directly below theopening 42. If themask 40 makes physical contact with thecathode wafer 32, then the plating would largely be limited to the area of the substrate directly underneath theopening 42. When themask 40 is moved in a side to side motion as indicated byarrow 43, the electrical current passing through a section on the wafer surface will vary. This is discussed in greater detail later herein. - FIGS. 7a-7 d illustrate a mask pulsed plating method in accordance with the preferred embodiment of the present invention. The
mask 40 is moved to the left with respect to the cathode wafer 32 (or alternatively, thewafer 32 may be moved to the right, or both themask 40 and thewafer 32 may be moved relative to each other). In FIG. 7a, at time t=t1, asection 45 on thewafer 32 surface is positioned under the electrically insulatingmask 40 and is not directly exposed to the electrolyte. Accordingly, the plating current at thesection 45 at t=t1 is very small or near zero as depicted in the graph of FIG. 7e. FIG. 7e illustrates a graph depicting the deposition/plating current in relation to time at thesection 45. - In FIG. 7b, as the
mask 40 and/or thewafer 32 is moved such that theopening 42 is above thesection 45, the plating current at thesection 45 at time t=t2 increases sharply as theopening 42 aligns with thesection 45. In FIG. 7c, the high current remains steady until t=t3. Thereafter, when thesection 45 is again positioned underneath the non-opened portion of themask 40 as shown in FIG. 7d, the current density is again very small or near zero. - Referring back to FIG. 7e, the time interval Δt (time between t2 and t3) is a function of the speed of the
mask 40 as well as the size of theopening 42. In addition, Δt will be a small value if themask 40 is moved rapidly in relation to thewafer 32. Also, if there are multiple openings in themask 40 or if the movement of themask 40 is back and forth, then the corresponding current vs. time plots would consist of multiple pulses. By controlling the size of the opening(s) on themask 40 and the relative speed of the substrate and the mask, the shape, duration and repetition rate of the current pulses at any section on the substrate can be controlled. - As can be seen from the above example, a DC power supply can be used for this plating technique. By moving the solid insulating
mask 40 that makes physical contact with thewafer 32, any section on the wafer surface can be suddenly and briefly exposed to the electrolyte and to the applied plating current. This is quite different from the prior art techniques defined above. For instance, in the present invention, certain sections of the wafer surface are substantially free from the electrolyte. The electrolyte is applied to a section of the wafer only when that section is exposed to the electrolyte and a pulse of current is simultaneously applied. - If the current mask-pulsed plating method is used with simple metal deposition electrolytes with no additives (i.e., inhibitors and accelerators), it would not be expected to be much different than conventional plating. This is because the size of the
openings 42 in themask 40 is much larger than the feature size on thewafer 32 surface. Therefore, when a section is exposed through theopening 42 to the electrolyte, regular plating would commence. However, if additives are added that influence polarization, then the mask-pulsed plating method can offer advantages that is not existent in conventional pulsed plating techniques. - For example, consider a Cu plating bath containing conventional solutions/chemicals (Cu sulfate, water, sulfuric acid and chloride ions) and an additive A. The additive A enhances deposition when it is adsorbed on the wafer surface. When this electrolyte is used in a conventional plating cell such as the one depicted in FIG. 5, the entire surface of the
wafer 32 will be exposed to the electrolyte and the additive A. The field regions on the wafer surface, as well as the bottom surface of the large features would likewise adsorb the additive A and plating begins on these surfaces at comparable rates. - If, however, the mask-pulsed plating technique is used with the same electrolyte, the mask would clear away the additive A from the field regions since it makes physical contact with these regions. Both the small and large features, however, will still contain the adsorbed additive A since these features are not in direct physical contact with the mask. When a section of the wafer is suddenly exposed to the electrolyte, the bottom and side surfaces of the features with the previously adsorbed additive A would immediately start plating at a higher rate than the field regions. If the time period Δt is less than the adsorption period required for the additive A to attach itself to the substrate surface, the applied plating current preferentially flows through the features to be filled, thereby yielding an enhanced deposition rate within the features in relation to the deposition rate on the field regions.
- The mask-pulsed plating method of the present invention utilizes the differences between response times of various additives to achieve enhanced plating into the various features of the substrate surface. The mechanism involves “sweeping” of the top surface of the substrate (field regions) by the mask, which does not make physical contact with the regions inside the features. The sweeping on the field regions establishes a differential between the concentration of the adsorbed species in those regions that are swept away and the regions that are within the features. When the surface is then suddenly exposed to the electrolyte and the electric field, the features with the adsorbed species attracts most of the plating current from the field regions.
- This present method works equally well using multiple additives. For example, if the plating solution contains an inhibitor B and an accelerator C with the adsorption kinetics of the inhibitor being much faster than that of accelerator, the following mechanism can be used by the mask-pulsed plating method. Both the inhibitor B and the accelerator C would be partially or wholly swept off the field regions of the substrate by the mask. However, both species would still be present in the features. When the substrate is exposed to the electrolyte and the electric field, the inhibitor B would readily adsorb onto the field regions introducing a high resistance path for the plating current. The accelerator C, which is already present within the features, compensates for the action of the inhibitor in those regions and the current can easily flow through these features. Therefore, until the accelerator C is properly adsorbed onto the field regions, the film growth rate within the features will be higher.
- This same result can also be expected from yet another chemistry where an inhibitor D has the property of strong adsorption and the accelerator E is weakly bonded to the field regions. In this case, the mask can readily remove the weakly bonded accelerator E from the field regions whereas, the accelerator E remains attached to the surfaces within the features. Upon exposure to the electrolyte and electric field, the plating current flows through the features preferentially until the accelerator E begins to get adsorbed again onto the field regions.
- It should be noted that the above descriptions are just some examples of the mechanisms involved in the present invention and are not meant to be limiting. The present invention utilizes differences between adsorption/de-sorption kinetic of various electrolyte additives. The present invention accomplishes this by applying a solution and power suddenly and simultaneously to a specific section of the substrate surface that has been previously cleared off, partially or wholly, of one or more of the additive species.
- The geometry of the plating system shown in FIG. 6 is quite simplistic. There are many possible designs that can be used to practice this invention. Some important aspects of the present invention are as follows.
- (1) The mask needs to be flat when using a wafer that is also flat. The mask should be made of an insulating rigid material and the surface facing the wafer may be hard and even contain abrasives to help “sweep” away the additives more efficiently.
- (2) There should be a relative movement between the wafer and the mask. The wafer, mask, or both may be moved in linear or orbital manner or combination thereof.
- (3) There should be substantially no electrolyte between the mask and the wafer surface. The wafer surface should be exposed to electrolyte only through the opening(s) in the mask.
- (4) The size of the opening(s) in the mask and the speed of the relative motion between the mask and the wafer should be such that any section on the wafer should be exposed to the electrolyte only briefly, typically for less than two seconds, preferably less than one second, e.g., 10-500 msec. This time interval should be adjusted with respect to the adsorption characteristics of the additives being used.
- FIG. 8 illustrates a perspective view of an apparatus in accordance with the first preferred embodiment of the present invention. In FIG. 8, a
mask 80 and anelectrolyte channel plate 300 are mounted on ananode assembly 90. Theelectrolyte 100 is supplied to theanode assembly 90 by a pumping conventional system (not shown). Theelectrolyte 100 is pumped through theholes 210 into thechannels 310 in thechannel plate 300. In operation, the substrate/cathode is positioned facing the top surface of themask 80 and the substrate and/or themask 80 is/are rotated. The substrate may be pushed against themask 80 at a pressure in the range of 0.01 psi and 0.5 psi. Higher pressures may be used, but may not be necessary. If themask 80 is rotated, theentire anode assembly 90 may likewise be rotated. A cathodic voltage is applied to the substrate (not shown) with respect to an anode (not shown) placed within theanode assembly 90. Theelectrolyte 100 flowing through thechannels 310 make physical contact with the wafer surface through theopenings 250 in themask 80. Theelectrolyte 100 is continuously discharged from the small bleedingholes 320 to be filtered and re-circulated. Very little, if any electrolyte actually get into the interface between themask 80 and the wafer surface, which are in intimate contact during operation. - FIG. 9 illustrates a perspective view of an apparatus in accordance with the second preferred embodiment of the present invention. The apparatus in FIG. 9 is similar to that shown in FIG. 8, except for the
holes 510 and thechannel plate 600. Thechannel plate 600 includes different shapedchannels 610, which are used to distribute theelectrolyte 100 in a serial manner to theopenings 250 of themask 80. - FIG. 10 illustrates a side view of an apparatus in accordance with the third preferred embodiment of the present invention. In yet another embodiment, FIG. 10 shows the
electrolyte 100 coming into areservoir 1 10 that resides on the top portion of theanode assembly 90. Theelectrolyte 100 makes contact with the surface of thewafer 350 throughholes 250 in themask 80. The electrolyte can be discharged from thereservoir 100 through bleedingholes 200. - The power supply used in the present invention may be pulsed or DC power supply, but preferably it is a DC power supply. The power supply can be used in the current controlled or voltage controlled mode, i.e., it either keeps the applied current constant or applied voltage constant. For the case of using a current controlled mode, it is important that the size of the opening(s) in the mask be large enough to cover portions of the field regions as well as portions of the features simultaneously. In other words, when the wafer surface is exposed to the electrolyte through the opening(s), there should not be just the field regions that are exposed to the electrolyte at any given time. For example, if the opening is very small or the number of features on the wafer surface is low (low density features), the field regions are exposed to the electrolyte. In this case, since the power supply pushes through a fixed current, all the current would flow through the field regions and the Cu will be plated on the field region without discrimination. But if both field regions and features are exposed simultaneously, then the current would preferentially flow through the features and more Cu would be plated into the features and less on the field regions. This situation can be assured by increasing the number of openings in the mask so that there are always portions of the both regions (field and feature) exposed through some of the holes simultaneously.
- If a constant voltage power supply is used, then the current automatically adjusts itself depending upon the resistance on the wafer surface. Therefore, if the mask hole exposes only the field regions of the wafer, less current is supplied to that surface and the plating amount is smaller. When features are exposed to the solution, more current flows into the feature and thus preferential plating takes place into the features. Therefore, it is more appropriate to use voltage controlled mode of the power supply if wafers with low feature density is coated and/or the number of holes in the mask is limited.
- This invention can be used to fill both small and large features. However, a serial process can also be utilized. In that approach, there are two processing steps. During the first step the mask is pulled away from the wafer surface allowing substantial amount of plating solution between the mask and the wafer surface. In this position, the system acts just like a traditional plating cell. With the help of the additives in the plating solution, the small features are filled during this step and the situation as shown in FIG. 2b occurs. During this first step, the mask and the substrate are moved with respect to each other for uniform deposition. Then the mask is brought in contact with the surface squeezing out the solution from the wafer/mask interface except at the holes/openings on the mask. Mask-pulsed plating then commences to preferentially fill the larger features as described earlier. It is important to note that in the mask-pulsed plating technique, there is substantially no plating solution between the mask and the wafer surface except where the mask holes/openings are positioned.
- Along with using copper and its alloys as the conductive material, other conductive materials such as copper alloys, iron, nickel, chromium, indium, lead, tin, lead-tin alloys, nonleaded solderable alloys, silver, zinc, cadmium, ruthenium, their respective alloys may be used in the present invention. The present invention is especially suited for the fabrication of high performance and highly reliable chip interconnect, packaging, magnetic, flat panel and opto-electronic applications.
- In the previous descriptions, numerous specific details are set forth, such as specific materials, mask designs, pressures, chemicals, processes, etc., to provide a thorough understanding of the present invention. However, as one having ordinary skill in the art would recognize, the present invention can be practiced without resorting to the details specifically set forth.
- Although various preferred embodiments have been described in detail above, those skilled in the art will readily appreciate that many modifications of the exemplary embodiment are possible without materially departing from the novel teachings and advantages of this invention.
Claims (28)
1. An apparatus for plating a conductive top surface of a workpiece with a conductor disposed in an electrolyte that exists on the top surface of the workpiece, the conductive top surface of the workpiece including a top portion and a cavity portion, and having at least one additive adsorbed thereon the apparatus comprising:
an anode used to which power can be applied, thereby creating an electric field between the anode and the top surface of the workpiece and allowing plating of the top surface to occur;
a mask disposed in proximity to the top surface of the workpiece between the anode and the workpiece and capable of causing physical sweeping of a first portion of the at least one additive adsorbed on the top portion of the workpiece due to relative movement between the mask and the workpiece, thereby reducing an amount of the first portion of the additive adsorbed on the top portion, and thereby the amount of conductor plated onto the top portion of the workpiece, for a period of time.
2. The apparatus according to claim 1 , wherein the mask is positioned to make physical contact with the top portion of the workpiece.
3. The apparatus according to claim 1 wherein the mask in made of an insulator.
4. The apparatus according to claim 1 wherein the mask includes an open area through which the electrolyte and a plating current can pass to an area of the workpiece corresponding to the open area of mask during application of power.
5. The apparatus according to claim 4 further including a DC power source that provides DC power during plating.
6. The apparatus according to claim 5 wherein a current pulse with a first current density is formed within the open area of the movable mask between the anode and the area of the workpiece, the first current density being greater than a second current density that exists in another area of the workpiece that is not covered by the moveable mask.
7. The apparatus according to claim 6 wherein, over a period of time, a plurality of current pulses are formed between the anode and different areas of the workpiece.
8. The apparatus according to claim 7 wherein the plurality of current pulses, summed together, equal a DC current provided by the DC power source.
9. The apparatus according to claim 4 , wherein the mask is positioned to make physical contact with the top portion of the workpiece.
10. The apparatus according to claim 9 wherein the mask comprises an insulator.
11. The apparatus according to claim 10 wherein the mask includes an abrasive that can assist in reducing an amount of the first portion of the additive adsorbed on the top portion.
12. The apparatus according to claim 1 wherein the relative movement between the mask and the workpiece results in a linear motion.
13. The apparatus according to claim 1 wherein the relative movement between the mask and the workpiece results in a reciprocating linear motion.
14. The apparatus according to claim 1 wherein the relative movement between the mask and the workpiece results in an orbital motion.
15. The apparatus according to claim 1 wherein the relative movement between the mask and the workpiece results in a reciprocating orbital motion.
16. The apparatus according to claim 1 wherein the mask comprises an insulator.
17. The apparatus according to claim 16 wherein the mask includes an abrasive that can assist in reducing an amount of the first portion of the additive adsorbed on the top portion.
18. The apparatus according to claim 17 wherein the mask includes an open area through which the electrolyte and a plating current can pass to an area of the workpiece corresponding to the open area of mask during application of power.
19. The apparatus according to claim 18 , wherein the mask is positioned to make physical contact with the top portion of the workpiece.
20. The apparatus according to claim 19 wherein the relative movement between the mask and the workpiece results in a linear motion.
21. The apparatus according to claim 19 wherein the relative movement between the mask and the workpiece results in a reciprocating linear motion.
22. The apparatus according to claim 19 wherein the relative movement between the mask and the workpiece results in an orbital motion.
23. The apparatus according to claim 19 wherein the relative movement between the mask and the workpiece results in a reciprocating orbital motion.
24. The apparatus according to claim 19 , wherein the mask is positioned to make physical contact with the top portion of the workpiece.
25. The apparatus according to claim 1 further including a pulsed power source that provides pulsed power during plating.
26. The apparatus according to claim 1 further including a DC power source.
27. The apparatus according to claim 26 wherein the DC power source operates in a current controlled mode in which the plating current is held substantially constant.
28. The apparatus according to claim 26 wherein the DC power operates in a voltage controlled mode in which a plating voltage is held substantially constant.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/358,925 US20030146089A1 (en) | 2000-08-10 | 2003-02-04 | Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence |
US10/705,360 US20040170753A1 (en) | 2000-12-18 | 2003-11-10 | Electrochemical mechanical processing using low temperature process environment |
US11/200,767 US20050279641A1 (en) | 2000-08-10 | 2005-08-09 | Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence |
US11/237,991 US20060081477A1 (en) | 2000-12-18 | 2005-09-26 | Method and apparatus for establishing additive differential on surfaces for preferential plating |
US11/436,857 US7404886B2 (en) | 2000-08-10 | 2006-05-17 | Plating by creating a differential between additives disposed on a surface portion and a cavity portion of a workpiece |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US22473900P | 2000-08-10 | 2000-08-10 | |
US09/740,701 US6534116B2 (en) | 2000-08-10 | 2000-12-18 | Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence |
US10/358,925 US20030146089A1 (en) | 2000-08-10 | 2003-02-04 | Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/740,701 Division US6534116B2 (en) | 1998-12-01 | 2000-12-18 | Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence |
Related Child Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/705,360 Continuation-In-Part US20040170753A1 (en) | 2000-12-18 | 2003-11-10 | Electrochemical mechanical processing using low temperature process environment |
US11/200,767 Continuation US20050279641A1 (en) | 2000-08-10 | 2005-08-09 | Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence |
US11/237,991 Continuation-In-Part US20060081477A1 (en) | 2000-12-18 | 2005-09-26 | Method and apparatus for establishing additive differential on surfaces for preferential plating |
US11/436,857 Continuation US7404886B2 (en) | 2000-08-10 | 2006-05-17 | Plating by creating a differential between additives disposed on a surface portion and a cavity portion of a workpiece |
Publications (1)
Publication Number | Publication Date |
---|---|
US20030146089A1 true US20030146089A1 (en) | 2003-08-07 |
Family
ID=46149914
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/740,701 Expired - Lifetime US6534116B2 (en) | 1998-12-01 | 2000-12-18 | Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence |
US10/358,925 Abandoned US20030146089A1 (en) | 2000-08-10 | 2003-02-04 | Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence |
US11/200,767 Abandoned US20050279641A1 (en) | 2000-08-10 | 2005-08-09 | Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence |
US11/436,857 Expired - Fee Related US7404886B2 (en) | 2000-08-10 | 2006-05-17 | Plating by creating a differential between additives disposed on a surface portion and a cavity portion of a workpiece |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/740,701 Expired - Lifetime US6534116B2 (en) | 1998-12-01 | 2000-12-18 | Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/200,767 Abandoned US20050279641A1 (en) | 2000-08-10 | 2005-08-09 | Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence |
US11/436,857 Expired - Fee Related US7404886B2 (en) | 2000-08-10 | 2006-05-17 | Plating by creating a differential between additives disposed on a surface portion and a cavity portion of a workpiece |
Country Status (1)
Country | Link |
---|---|
US (4) | US6534116B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7811424B1 (en) * | 2004-06-30 | 2010-10-12 | Lam Research Corporation | Reducing mechanical resonance and improved distribution of fluids in small volume processing of semiconductor materials |
US20110054397A1 (en) * | 2006-03-31 | 2011-03-03 | Menot Sebastien | Medical liquid injection device |
US7947163B2 (en) | 2006-07-21 | 2011-05-24 | Novellus Systems, Inc. | Photoresist-free metal deposition |
US8236160B2 (en) | 2000-08-10 | 2012-08-07 | Novellus Systems, Inc. | Plating methods for low aspect ratio cavities |
Families Citing this family (79)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7449098B1 (en) | 1999-10-05 | 2008-11-11 | Novellus Systems, Inc. | Method for planar electroplating |
US7686935B2 (en) * | 1998-10-26 | 2010-03-30 | Novellus Systems, Inc. | Pad-assisted electropolishing |
US7531079B1 (en) | 1998-10-26 | 2009-05-12 | Novellus Systems, Inc. | Method and apparatus for uniform electropolishing of damascene IC structures by selective agitation |
US7204917B2 (en) | 1998-12-01 | 2007-04-17 | Novellus Systems, Inc. | Workpiece surface influencing device designs for electrochemical mechanical processing and method of using the same |
US6413388B1 (en) * | 2000-02-23 | 2002-07-02 | Nutool Inc. | Pad designs and structures for a versatile materials processing apparatus |
US6534116B2 (en) * | 2000-08-10 | 2003-03-18 | Nutool, Inc. | Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence |
US6610190B2 (en) * | 2000-11-03 | 2003-08-26 | Nutool, Inc. | Method and apparatus for electrodeposition of uniform film with minimal edge exclusion on substrate |
US6251235B1 (en) | 1999-03-30 | 2001-06-26 | Nutool, Inc. | Apparatus for forming an electrical contact with a semiconductor substrate |
US6497800B1 (en) * | 2000-03-17 | 2002-12-24 | Nutool Inc. | Device providing electrical contact to the surface of a semiconductor workpiece during metal plating |
US6902659B2 (en) * | 1998-12-01 | 2005-06-07 | Asm Nutool, Inc. | Method and apparatus for electro-chemical mechanical deposition |
US6355153B1 (en) * | 1999-09-17 | 2002-03-12 | Nutool, Inc. | Chip interconnect and packaging deposition methods and structures |
JP3594894B2 (en) * | 2000-02-01 | 2004-12-02 | 新光電気工業株式会社 | Via filling plating method |
US6852208B2 (en) | 2000-03-17 | 2005-02-08 | Nutool, Inc. | Method and apparatus for full surface electrotreating of a wafer |
US7754061B2 (en) * | 2000-08-10 | 2010-07-13 | Novellus Systems, Inc. | Method for controlling conductor deposition on predetermined portions of a wafer |
US6858121B2 (en) * | 2000-08-10 | 2005-02-22 | Nutool, Inc. | Method and apparatus for filling low aspect ratio cavities with conductive material at high rate |
US20040170753A1 (en) * | 2000-12-18 | 2004-09-02 | Basol Bulent M. | Electrochemical mechanical processing using low temperature process environment |
US7172497B2 (en) * | 2001-01-05 | 2007-02-06 | Asm Nutool, Inc. | Fabrication of semiconductor interconnect structures |
IL141118A0 (en) * | 2001-01-25 | 2002-02-10 | Cerel Ceramics Technologies Lt | A method for the implementation of electronic components in via-holes of a multi-layer multi-chip module |
US7232514B2 (en) * | 2001-03-14 | 2007-06-19 | Applied Materials, Inc. | Method and composition for polishing a substrate |
US7160432B2 (en) * | 2001-03-14 | 2007-01-09 | Applied Materials, Inc. | Method and composition for polishing a substrate |
US6811680B2 (en) | 2001-03-14 | 2004-11-02 | Applied Materials Inc. | Planarization of substrates using electrochemical mechanical polishing |
US6899804B2 (en) * | 2001-12-21 | 2005-05-31 | Applied Materials, Inc. | Electrolyte composition and treatment for electrolytic chemical mechanical polishing |
US7582564B2 (en) * | 2001-03-14 | 2009-09-01 | Applied Materials, Inc. | Process and composition for conductive material removal by electrochemical mechanical polishing |
US6863795B2 (en) * | 2001-03-23 | 2005-03-08 | Interuniversitair Microelektronica Centrum (Imec) | Multi-step method for metal deposition |
US6869515B2 (en) * | 2001-03-30 | 2005-03-22 | Uri Cohen | Enhanced electrochemical deposition (ECD) filling of high aspect ratio openings |
JP4368543B2 (en) * | 2001-07-25 | 2009-11-18 | シャープ株式会社 | Plating method and plating apparatus |
JP3961377B2 (en) * | 2001-09-20 | 2007-08-22 | 株式会社リコー | Optical scanning apparatus and image forming apparatus |
US20070295611A1 (en) * | 2001-12-21 | 2007-12-27 | Liu Feng Q | Method and composition for polishing a substrate |
US20030146102A1 (en) * | 2002-02-05 | 2003-08-07 | Applied Materials, Inc. | Method for forming copper interconnects |
US20040000488A1 (en) * | 2002-06-28 | 2004-01-01 | Applied Materials, Inc. | CU ECP planarization by insertion of polymer treatment step between gap fill and bulk fill steps |
US7449099B1 (en) * | 2004-04-13 | 2008-11-11 | Novellus Systems, Inc. | Selectively accelerated plating of metal features |
US7799200B1 (en) | 2002-07-29 | 2010-09-21 | Novellus Systems, Inc. | Selective electrochemical accelerator removal |
US7405163B1 (en) | 2003-12-17 | 2008-07-29 | Novellus Systems, Inc. | Selectively accelerated plating of metal features |
US6974531B2 (en) * | 2002-10-15 | 2005-12-13 | International Business Machines Corporation | Method for electroplating on resistive substrates |
US20040084318A1 (en) * | 2002-11-05 | 2004-05-06 | Uri Cohen | Methods and apparatus for activating openings and for jets plating |
US7138039B2 (en) * | 2003-01-21 | 2006-11-21 | Applied Materials, Inc. | Liquid isolation of contact rings |
US7087144B2 (en) * | 2003-01-31 | 2006-08-08 | Applied Materials, Inc. | Contact ring with embedded flexible contacts |
US7025861B2 (en) | 2003-02-06 | 2006-04-11 | Applied Materials | Contact plating apparatus |
DK1620568T3 (en) * | 2003-04-24 | 2009-03-30 | Afshin Ahmadian | Analysis for allele-specific mutation detection |
US7429401B2 (en) * | 2003-05-23 | 2008-09-30 | The United States of America as represented by the Secretary of Commerce, the National Insitiute of Standards & Technology | Superconformal metal deposition using derivatized substrates |
US7390429B2 (en) * | 2003-06-06 | 2008-06-24 | Applied Materials, Inc. | Method and composition for electrochemical mechanical polishing processing |
JP2005029830A (en) * | 2003-07-10 | 2005-02-03 | Ebara Corp | Plating device and plating method |
US7250104B2 (en) * | 2003-08-08 | 2007-07-31 | Novellus Systems, Inc. | Method and system for optically enhanced metal planarization |
JP4423356B2 (en) * | 2003-09-02 | 2010-03-03 | 株式会社荏原製作所 | Substrate plating equipment |
US20050092620A1 (en) * | 2003-10-01 | 2005-05-05 | Applied Materials, Inc. | Methods and apparatus for polishing a substrate |
US7208404B2 (en) * | 2003-10-16 | 2007-04-24 | Taiwan Semiconductor Manufacturing Company | Method to reduce Rs pattern dependence effect |
US8158532B2 (en) * | 2003-10-20 | 2012-04-17 | Novellus Systems, Inc. | Topography reduction and control by selective accelerator removal |
US8530359B2 (en) | 2003-10-20 | 2013-09-10 | Novellus Systems, Inc. | Modulated metal removal using localized wet etching |
US7064057B2 (en) * | 2003-11-21 | 2006-06-20 | Asm Nutool, Inc. | Method and apparatus for localized material removal by electrochemical polishing |
US20050218000A1 (en) * | 2004-04-06 | 2005-10-06 | Applied Materials, Inc. | Conditioning of contact leads for metal plating systems |
US7285195B2 (en) * | 2004-06-24 | 2007-10-23 | Applied Materials, Inc. | Electric field reducing thrust plate |
JP4992428B2 (en) * | 2004-09-24 | 2012-08-08 | イビデン株式会社 | Plating method and plating apparatus |
US20060183321A1 (en) * | 2004-09-27 | 2006-08-17 | Basol Bulent M | Method for reduction of gap fill defects |
US20060249394A1 (en) * | 2005-05-05 | 2006-11-09 | Applied Materials, Inc. | Process and composition for electrochemical mechanical polishing |
US20060249395A1 (en) * | 2005-05-05 | 2006-11-09 | Applied Material, Inc. | Process and composition for electrochemical mechanical polishing |
US20060252254A1 (en) * | 2005-05-06 | 2006-11-09 | Basol Bulent M | Filling deep and wide openings with defect-free conductor |
US20070014958A1 (en) * | 2005-07-08 | 2007-01-18 | Chaplin Ernest R | Hanger labels, label assemblies and methods for forming the same |
US20070170066A1 (en) * | 2006-01-06 | 2007-07-26 | Beaudry Christopher L | Method for planarization during plating |
TW200741037A (en) | 2006-01-30 | 2007-11-01 | Ibiden Co Ltd | Plating apparatus and plating method |
US7550070B2 (en) * | 2006-02-03 | 2009-06-23 | Novellus Systems, Inc. | Electrode and pad assembly for processing conductive layers |
JP4878866B2 (en) * | 2006-02-22 | 2012-02-15 | イビデン株式会社 | Plating apparatus and plating method |
US7485561B2 (en) * | 2006-03-29 | 2009-02-03 | Asm Nutool, Inc. | Filling deep features with conductors in semiconductor manufacturing |
US7625814B2 (en) * | 2006-03-29 | 2009-12-01 | Asm Nutool, Inc. | Filling deep features with conductors in semiconductor manufacturing |
US20070254485A1 (en) * | 2006-04-28 | 2007-11-01 | Daxin Mao | Abrasive composition for electrochemical mechanical polishing |
US7732329B2 (en) * | 2006-08-30 | 2010-06-08 | Ipgrip, Llc | Method and apparatus for workpiece surface modification for selective material deposition |
US20080092947A1 (en) * | 2006-10-24 | 2008-04-24 | Applied Materials, Inc. | Pulse plating of a low stress film on a solar cell substrate |
US7799182B2 (en) | 2006-12-01 | 2010-09-21 | Applied Materials, Inc. | Electroplating on roll-to-roll flexible solar cell substrates |
US7704352B2 (en) * | 2006-12-01 | 2010-04-27 | Applied Materials, Inc. | High-aspect ratio anode and apparatus for high-speed electroplating on a solar cell substrate |
US20080128019A1 (en) * | 2006-12-01 | 2008-06-05 | Applied Materials, Inc. | Method of metallizing a solar cell substrate |
US7736928B2 (en) * | 2006-12-01 | 2010-06-15 | Applied Materials, Inc. | Precision printing electroplating through plating mask on a solar cell substrate |
US20080217182A1 (en) * | 2007-03-08 | 2008-09-11 | E. I. Dupont De Nemours And Company | Electroplating process |
US20080237048A1 (en) * | 2007-03-30 | 2008-10-02 | Ismail Emesh | Method and apparatus for selective electrofilling of through-wafer vias |
US8580090B2 (en) * | 2007-08-01 | 2013-11-12 | Intermolecular, Inc. | Combinatorial electrochemical deposition |
US20090065365A1 (en) * | 2007-09-11 | 2009-03-12 | Asm Nutool, Inc. | Method and apparatus for copper electroplating |
US20100126849A1 (en) * | 2008-11-24 | 2010-05-27 | Applied Materials, Inc. | Apparatus and method for forming 3d nanostructure electrode for electrochemical battery and capacitor |
US7884016B2 (en) * | 2009-02-12 | 2011-02-08 | Asm International, N.V. | Liner materials and related processes for 3-D integration |
US8168540B1 (en) | 2009-12-29 | 2012-05-01 | Novellus Systems, Inc. | Methods and apparatus for depositing copper on tungsten |
US10526719B2 (en) * | 2013-08-21 | 2020-01-07 | Taiwan Semiconductor Manufacturing Company Limited | Magnetic structure for metal plating control |
US9859124B2 (en) * | 2015-04-17 | 2018-01-02 | Taiwan Semiconductor Manufacturing Company Ltd | Method of manufacturing semiconductor device with recess |
Citations (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5567300A (en) * | 1994-09-02 | 1996-10-22 | Ibm Corporation | Electrochemical metal removal technique for planarization of surfaces |
US5862605A (en) * | 1996-05-24 | 1999-01-26 | Ebara Corporation | Vaporizer apparatus |
US6004880A (en) * | 1998-02-20 | 1999-12-21 | Lsi Logic Corporation | Method of single step damascene process for deposition and global planarization |
US6074546A (en) * | 1997-08-21 | 2000-06-13 | Rodel Holdings, Inc. | Method for photoelectrochemical polishing of silicon wafers |
US6176992B1 (en) * | 1998-11-03 | 2001-01-23 | Nutool, Inc. | Method and apparatus for electro-chemical mechanical deposition |
US6224737B1 (en) * | 1999-08-19 | 2001-05-01 | Taiwan Semiconductor Manufacturing Company | Method for improvement of gap filling capability of electrochemical deposition of copper |
US6245676B1 (en) * | 1998-02-20 | 2001-06-12 | Nec Corporation | Method of electroplating copper interconnects |
US6251235B1 (en) * | 1999-03-30 | 2001-06-26 | Nutool, Inc. | Apparatus for forming an electrical contact with a semiconductor substrate |
US6270647B1 (en) * | 1997-09-30 | 2001-08-07 | Semitool, Inc. | Electroplating system having auxiliary electrode exterior to main reactor chamber for contact cleaning operations |
US6284121B1 (en) * | 1997-10-08 | 2001-09-04 | Novellus Systems, Inc. | Electroplating system including additive for filling sub-micron features |
US6303014B1 (en) * | 1998-10-14 | 2001-10-16 | Faraday Technology Marketing Group, Llc | Electrodeposition of metals in small recesses using modulated electric fields |
US6346479B1 (en) * | 2000-06-14 | 2002-02-12 | Advanced Micro Devices, Inc. | Method of manufacturing a semiconductor device having copper interconnects |
US6352623B1 (en) * | 1999-12-17 | 2002-03-05 | Nutool, Inc. | Vertically configured chamber used for multiple processes |
US6375823B1 (en) * | 1999-02-10 | 2002-04-23 | Kabushiki Kaisha Toshiba | Plating method and plating apparatus |
US6413388B1 (en) * | 2000-02-23 | 2002-07-02 | Nutool Inc. | Pad designs and structures for a versatile materials processing apparatus |
US6482656B1 (en) * | 2001-06-04 | 2002-11-19 | Advanced Micro Devices, Inc. | Method of electrochemical formation of high Tc superconducting damascene interconnect for integrated circuit |
US6497800B1 (en) * | 2000-03-17 | 2002-12-24 | Nutool Inc. | Device providing electrical contact to the surface of a semiconductor workpiece during metal plating |
US6506103B1 (en) * | 1999-07-23 | 2003-01-14 | Riken | ELID centerless grinding apparatus |
US6534116B2 (en) * | 2000-08-10 | 2003-03-18 | Nutool, Inc. | Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence |
US20030054729A1 (en) * | 2000-08-30 | 2003-03-20 | Whonchee Lee | Methods and apparatus for electromechanically and/or electrochemically-mechanically removing conductive material from a microelectronic substrate |
US6600229B2 (en) * | 2001-01-23 | 2003-07-29 | Honeywell International Inc. | Planarizers for spin etch planarization of electronic components |
US6610190B2 (en) * | 2000-11-03 | 2003-08-26 | Nutool, Inc. | Method and apparatus for electrodeposition of uniform film with minimal edge exclusion on substrate |
US6653226B1 (en) * | 2001-01-09 | 2003-11-25 | Novellus Systems, Inc. | Method for electrochemical planarization of metal surfaces |
US6833063B2 (en) * | 2001-12-21 | 2004-12-21 | Nutool, Inc. | Electrochemical edge and bevel cleaning process and system |
US6848970B2 (en) * | 2002-09-16 | 2005-02-01 | Applied Materials, Inc. | Process control in electrochemically assisted planarization |
US6867136B2 (en) * | 2001-07-20 | 2005-03-15 | Nutool, Inc. | Method for electrochemically processing a workpiece |
US6902659B2 (en) * | 1998-12-01 | 2005-06-07 | Asm Nutool, Inc. | Method and apparatus for electro-chemical mechanical deposition |
US6936154B2 (en) * | 2000-12-15 | 2005-08-30 | Asm Nutool, Inc. | Planarity detection methods and apparatus for electrochemical mechanical processing systems |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2288389A1 (en) * | 1974-10-17 | 1976-05-14 | Nat Res Dev | METAL ELECTRODEPOSITION PROCESS ON SEMICONDUCTOR SUBSTRATES |
IT1046971B (en) * | 1975-03-11 | 1980-09-10 | Oxy Metal Industries Corp | Baths for electrodeposition of copper - contg soluble prod prepd by reacting alkoxylated polyalkylene-imine with alkylating agent |
US5516412A (en) * | 1995-05-16 | 1996-05-14 | International Business Machines Corporation | Vertical paddle plating cell |
US5807165A (en) * | 1997-03-26 | 1998-09-15 | International Business Machines Corporation | Method of electrochemical mechanical planarization |
JP2000208443A (en) | 1999-01-13 | 2000-07-28 | Sony Corp | Method and apparatus for manufacturing electronic device |
US6444110B2 (en) * | 1999-05-17 | 2002-09-03 | Shipley Company, L.L.C. | Electrolytic copper plating method |
EP1063696B1 (en) | 1999-06-22 | 2007-08-22 | Interuniversitair Micro-Elektronica Centrum Vzw | A method for improving the quality of a metal-containing layer deposited from a plating bath |
US6341998B1 (en) | 1999-11-04 | 2002-01-29 | Vlsi Technology, Inc. | Integrated circuit (IC) plating deposition system and method |
JP3594894B2 (en) | 2000-02-01 | 2004-12-02 | 新光電気工業株式会社 | Via filling plating method |
US6354916B1 (en) * | 2000-02-11 | 2002-03-12 | Nu Tool Inc. | Modified plating solution for plating and planarization and process utilizing same |
US6436267B1 (en) * | 2000-08-29 | 2002-08-20 | Applied Materials, Inc. | Method for achieving copper fill of high aspect ratio interconnect features |
-
2000
- 2000-12-18 US US09/740,701 patent/US6534116B2/en not_active Expired - Lifetime
-
2003
- 2003-02-04 US US10/358,925 patent/US20030146089A1/en not_active Abandoned
-
2005
- 2005-08-09 US US11/200,767 patent/US20050279641A1/en not_active Abandoned
-
2006
- 2006-05-17 US US11/436,857 patent/US7404886B2/en not_active Expired - Fee Related
Patent Citations (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5567300A (en) * | 1994-09-02 | 1996-10-22 | Ibm Corporation | Electrochemical metal removal technique for planarization of surfaces |
US5862605A (en) * | 1996-05-24 | 1999-01-26 | Ebara Corporation | Vaporizer apparatus |
US6074546A (en) * | 1997-08-21 | 2000-06-13 | Rodel Holdings, Inc. | Method for photoelectrochemical polishing of silicon wafers |
US6270647B1 (en) * | 1997-09-30 | 2001-08-07 | Semitool, Inc. | Electroplating system having auxiliary electrode exterior to main reactor chamber for contact cleaning operations |
US6284121B1 (en) * | 1997-10-08 | 2001-09-04 | Novellus Systems, Inc. | Electroplating system including additive for filling sub-micron features |
US6004880A (en) * | 1998-02-20 | 1999-12-21 | Lsi Logic Corporation | Method of single step damascene process for deposition and global planarization |
US6090239A (en) * | 1998-02-20 | 2000-07-18 | Lsi Logic Corporation | Method of single step damascene process for deposition and global planarization |
US6245676B1 (en) * | 1998-02-20 | 2001-06-12 | Nec Corporation | Method of electroplating copper interconnects |
US6303014B1 (en) * | 1998-10-14 | 2001-10-16 | Faraday Technology Marketing Group, Llc | Electrodeposition of metals in small recesses using modulated electric fields |
US6176992B1 (en) * | 1998-11-03 | 2001-01-23 | Nutool, Inc. | Method and apparatus for electro-chemical mechanical deposition |
US6402925B2 (en) * | 1998-11-03 | 2002-06-11 | Nutool, Inc. | Method and apparatus for electrochemical mechanical deposition |
US6676822B1 (en) * | 1998-11-03 | 2004-01-13 | Nutool, Inc. | Method for electro chemical mechanical deposition |
US6902659B2 (en) * | 1998-12-01 | 2005-06-07 | Asm Nutool, Inc. | Method and apparatus for electro-chemical mechanical deposition |
US6375823B1 (en) * | 1999-02-10 | 2002-04-23 | Kabushiki Kaisha Toshiba | Plating method and plating apparatus |
US6251235B1 (en) * | 1999-03-30 | 2001-06-26 | Nutool, Inc. | Apparatus for forming an electrical contact with a semiconductor substrate |
US6958114B2 (en) * | 1999-03-30 | 2005-10-25 | Asm Nutool, Inc. | Method and apparatus for forming an electrical contact with a semiconductor substrate |
US6471847B2 (en) * | 1999-03-30 | 2002-10-29 | Nutool, Inc. | Method for forming an electrical contact with a semiconductor substrate |
US6506103B1 (en) * | 1999-07-23 | 2003-01-14 | Riken | ELID centerless grinding apparatus |
US6224737B1 (en) * | 1999-08-19 | 2001-05-01 | Taiwan Semiconductor Manufacturing Company | Method for improvement of gap filling capability of electrochemical deposition of copper |
US6352623B1 (en) * | 1999-12-17 | 2002-03-05 | Nutool, Inc. | Vertically configured chamber used for multiple processes |
US6413388B1 (en) * | 2000-02-23 | 2002-07-02 | Nutool Inc. | Pad designs and structures for a versatile materials processing apparatus |
US6497800B1 (en) * | 2000-03-17 | 2002-12-24 | Nutool Inc. | Device providing electrical contact to the surface of a semiconductor workpiece during metal plating |
US6346479B1 (en) * | 2000-06-14 | 2002-02-12 | Advanced Micro Devices, Inc. | Method of manufacturing a semiconductor device having copper interconnects |
US6534116B2 (en) * | 2000-08-10 | 2003-03-18 | Nutool, Inc. | Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence |
US20030054729A1 (en) * | 2000-08-30 | 2003-03-20 | Whonchee Lee | Methods and apparatus for electromechanically and/or electrochemically-mechanically removing conductive material from a microelectronic substrate |
US6610190B2 (en) * | 2000-11-03 | 2003-08-26 | Nutool, Inc. | Method and apparatus for electrodeposition of uniform film with minimal edge exclusion on substrate |
US6942780B2 (en) * | 2000-11-03 | 2005-09-13 | Asm Nutool, Inc. | Method and apparatus for processing a substrate with minimal edge exclusion |
US6936154B2 (en) * | 2000-12-15 | 2005-08-30 | Asm Nutool, Inc. | Planarity detection methods and apparatus for electrochemical mechanical processing systems |
US6653226B1 (en) * | 2001-01-09 | 2003-11-25 | Novellus Systems, Inc. | Method for electrochemical planarization of metal surfaces |
US6600229B2 (en) * | 2001-01-23 | 2003-07-29 | Honeywell International Inc. | Planarizers for spin etch planarization of electronic components |
US6482656B1 (en) * | 2001-06-04 | 2002-11-19 | Advanced Micro Devices, Inc. | Method of electrochemical formation of high Tc superconducting damascene interconnect for integrated circuit |
US6867136B2 (en) * | 2001-07-20 | 2005-03-15 | Nutool, Inc. | Method for electrochemically processing a workpiece |
US6833063B2 (en) * | 2001-12-21 | 2004-12-21 | Nutool, Inc. | Electrochemical edge and bevel cleaning process and system |
US6848970B2 (en) * | 2002-09-16 | 2005-02-01 | Applied Materials, Inc. | Process control in electrochemically assisted planarization |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8236160B2 (en) | 2000-08-10 | 2012-08-07 | Novellus Systems, Inc. | Plating methods for low aspect ratio cavities |
US7811424B1 (en) * | 2004-06-30 | 2010-10-12 | Lam Research Corporation | Reducing mechanical resonance and improved distribution of fluids in small volume processing of semiconductor materials |
US20110054397A1 (en) * | 2006-03-31 | 2011-03-03 | Menot Sebastien | Medical liquid injection device |
US7947163B2 (en) | 2006-07-21 | 2011-05-24 | Novellus Systems, Inc. | Photoresist-free metal deposition |
US8500985B2 (en) | 2006-07-21 | 2013-08-06 | Novellus Systems, Inc. | Photoresist-free metal deposition |
Also Published As
Publication number | Publication date |
---|---|
US20050279641A1 (en) | 2005-12-22 |
US20060207885A1 (en) | 2006-09-21 |
US20020074230A1 (en) | 2002-06-20 |
US6534116B2 (en) | 2003-03-18 |
US7404886B2 (en) | 2008-07-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7404886B2 (en) | Plating by creating a differential between additives disposed on a surface portion and a cavity portion of a workpiece | |
US6858121B2 (en) | Method and apparatus for filling low aspect ratio cavities with conductive material at high rate | |
US6303014B1 (en) | Electrodeposition of metals in small recesses using modulated electric fields | |
US7517444B2 (en) | Plating method and apparatus for controlling deposition on predetermined portions of a workpiece | |
US6524461B2 (en) | Electrodeposition of metals in small recesses using modulated electric fields | |
US6867136B2 (en) | Method for electrochemically processing a workpiece | |
US7435323B2 (en) | Method for controlling thickness uniformity of electroplated layers | |
US6943112B2 (en) | Defect-free thin and planar film processing | |
US20060081477A1 (en) | Method and apparatus for establishing additive differential on surfaces for preferential plating | |
US7754061B2 (en) | Method for controlling conductor deposition on predetermined portions of a wafer | |
WO2002015245A2 (en) | Plating method and apparatus that creates a differential between additive disposed on a top surface and a cavity surface of a workpiece using an external influence | |
US20050092616A1 (en) | Baths, methods, and tools for superconformal deposition of conductive materials other than copper | |
US6797144B2 (en) | Method for reducing surface defects in an electrodeposition process | |
US20070151859A1 (en) | Method of forming copper interconnections in semiconductor devices | |
WO2001021294A2 (en) | Pattern dependent surface profile evolution of electrochemically deposited metal | |
Ritzdorf | Challenges and Opportunities for Electrochemical Processing in Microelectronics |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: NU TOOL, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BASOL, BULENT;REEL/FRAME:013733/0568 Effective date: 20010323 |
|
AS | Assignment |
Owner name: ASM NUTOOL, INC., CALIFORNIA Free format text: CHANGE OF NAME;ASSIGNOR:NUTOOL, INC.;REEL/FRAME:016002/0935 Effective date: 20040729 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |