US20030146504A1 - Chip-size semiconductor package - Google Patents

Chip-size semiconductor package Download PDF

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Publication number
US20030146504A1
US20030146504A1 US10/062,426 US6242602A US2003146504A1 US 20030146504 A1 US20030146504 A1 US 20030146504A1 US 6242602 A US6242602 A US 6242602A US 2003146504 A1 US2003146504 A1 US 2003146504A1
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Prior art keywords
conductive
chip
wiring pattern
conductive wiring
semiconductor package
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US10/062,426
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US6987323B2 (en
Inventor
Tae Yamane
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Lapis Semiconductor Co Ltd
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Oki Electric Industry Co Ltd
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Publication of US20030146504A1 publication Critical patent/US20030146504A1/en
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Assigned to OKI SEMICONDUCTOR CO., LTD. reassignment OKI SEMICONDUCTOR CO., LTD. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: OKI ELECTRIC INDUSTRY CO., LTD.
Assigned to Lapis Semiconductor Co., Ltd. reassignment Lapis Semiconductor Co., Ltd. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: OKI SEMICONDUCTOR CO., LTD
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body

Definitions

  • the present invention generally relates to a chip-size semiconductor package, and more particularly to a chip-size semiconductor package having a wiring layer in which stress applied thereto is effectively relaxed.
  • a chip-size semiconductor package includes a Si chip; metal pads formed on the Si chip; a wafer coating formed over the Si chip; conductive wiring patterns formed on the wafer coating; a molding resin formed over the wafer coating; conductive posts formed in the molding resin; and terminals formed on the molding resin.
  • the conductive wiring patterns are electrically connected to the metal pads through the wafer coating.
  • the terminals are connected to the conductive posts one by one.
  • a connecting portion (boundary portion) between the conductive post and wiring pattern is extremely narrow and weak. Therefore, the connecting portion may be broken by stress, which is generated when the molding resin is expanded or contracted.
  • the connecting portion is shaped to decrease in area gradually from the conductive post to conductive wiring pattern.
  • the area to be in contact with the molding resin is increased, so that the molding resin may be easily removed from the conductive post and conductive wiring pattern. As a result, the connecting portion may be broken later.
  • an object of the present invention is to provide a chip-size semiconductor package in which a connecting portion between a conductive post and a wiring pattern is not easily broken.
  • a chip-size semiconductor package includes a semiconductor chip; a metal pad formed on the semiconductor chip; a wafer coat formed over the semiconductor chip; a conductive wiring pattern formed on the wafer coat, in which the metal pad is electrically connected to the conductive pattern; a molding resin formed over the conductive wiring pattern; a conductive post which is formed in the molding resin and is connected to the conductive wiring pattern; and a terminal which is formed on the molding resin and is connected to the conductive post.
  • a connecting portion (boundary portion) of the conductive wiring pattern and conductive post is provided with a slit to disperse stress to be applied to the connecting portion.
  • the connecting portion is provided with a plurality of slits, which are separated from each other.
  • the slits may be shaped to be rectangular and arranged to extend radially.
  • the connecting portion is shaped to decrease in area gradually from the conductive post to the conductive wiring pattern.
  • a chip-size semiconductor package includes a semiconductor chip; a metal pad formed on the semiconductor chip; a wafer coat formed over the semiconductor chip; a conductive wiring pattern formed on the wafer coat, in which the metal pad is electrically connected to the conductive pattern; a molding resin formed over the conductive wiring pattern; a conductive post which is formed in the molding resin and is connected to the conductive wiring pattern; a terminal which is formed on the molding resin and is connected to the conductive post; and a dummy pattern arranged adjacent a connecting portion (boundary portion) of the conductive post and wiring pattern.
  • the dummy pattern is a conductive pattern which is formed in the same process as the conductive wiring pattern and is arranged parallel to the conductive wiring pattern.
  • the dummy pattern may include two parts arranged at the both side of the conductive pattern.
  • the connecting portion is shaped to decrease in area gradually from the conductive post to the conductive wiring pattern, and the two parts of the dummy pattern are arranged along the conductive post and conductive wiring pattern.
  • a chip-size semiconductor package includes a semiconductor chip; a metal pad formed on the semiconductor chip; a wafer coat formed over the semiconductor chip; a conductive wiring pattern formed on the wafer coat, in which the metal pad is electrically connected to the conductive pattern; a molding resin formed over the conductive wiring pattern; a conductive post which is formed in the molding resin and is connected to the conductive wiring pattern; and a terminal which is formed on the molding resin and is connected to the conductive post. At least one of the conductive wiring pattern and conductive post is provided with a dent around a connecting portion (boundary portion) of the conductive wiring pattern and conductive post.
  • the dent may be shaped to be square.
  • the connecting portion is shaped to decrease in area gradually from the conductive post to the conductive wiring pattern.
  • a chip-size semiconductor package includes a semiconductor chip; a metal pad formed on the semiconductor chip; a wafer coat formed over the semiconductor chip; a conductive wiring pattern formed on the wafer coat, in which the metal pad is electrically connected to the conductive pattern; a molding resin formed over the conductive wiring pattern; a conductive post which is formed in the molding resin and is connected to the conductive wiring pattern; and a terminal which is formed on the molding resin and is connected to the conductive post.
  • the conductive wiring pattern is shaped to have a first region extending outwardly from the conductive post and a second region extending vertically from the first region.
  • the second region comprises a plurality of projecting parts each of which extends vertically from the first region, and the projecting pats of the second region are extended from both sides of the first region.
  • the connecting portion may be shaped to decrease in area gradually from the conductive post to the conductive wiring pattern. At least one of the projecting pats may form a part of the conductive post.
  • FIG. 1 is a cross-sectional view showing a conventional chip-size semiconductor package.
  • FIG. 2 is a plan view showing a conventional chip-size semiconductor package.
  • FIG. 3 is an enlarged view showing a part of the chip-size semiconductor package shown in FIG. 2.
  • FIG. 4 is an enlarged view showing a part of another conventional chip-size semiconductor package.
  • FIG. 5 is an enlarged view showing a part of a chip-size semiconductor package according to a first preferred embodiment of the present invention.
  • FIG. 6 is an enlarged view showing a part of a chip-size semiconductor package according to a second preferred embodiment of the present invention.
  • FIG. 7 is an enlarged view showing a part of a chip-size semiconductor package according to a third preferred embodiment of the present invention.
  • FIG. 8 is a cross-sectional view taken on line A-A in FIG. 7.
  • FIG. 9 is an enlarged view showing a part of a chip-size semiconductor package according to a fifth preferred embodiment of the present invention.
  • FIG. 1 is a cross-sectional view showing a conventional chip-size semiconductor package 10 .
  • FIG. 2 is a plan view showing the conventional chip-size semiconductor package 10 , shown in FIG. 1.
  • the chip-size semiconductor package 10 includes a Si chip 12 ; metal pads 14 formed on the Si chip 12 ; a wafer coating 16 formed over the Si chip 12 ; conductive wiring patterns 18 formed on the wafer coating 16 ; a molding resin 24 formed over the wafer coating 16 ; conductive posts 20 formed in the molding resin 24 ; and terminals 22 formed on the molding resin 24 .
  • the conductive wiring patterns 12 are electrically connected to the metal pads 14 through the wafer coating 16 .
  • the terminals 22 are connected to the conductive posts 20 one by one.
  • FIG. 3 is an enlarged view showing a part 30 encircled by a broken line in FIG. 2.
  • a connecting portion (boundary portion) 40 between the conductive post 20 and wiring pattern 18 is extremely narrow and weak. According to the conventional chip-size package, the connecting portion 40 may be broken by stress, which is generated when the molding resin 24 is expanded or contracted.
  • FIG. 4 is an enlarged view showing the part 30 of another conventional chip-size semiconductor package.
  • a connecting portion (boundary portion) 140 is a part which is easily broken in response to stress, so that the connecting portion 140 is shaped to decrease in area gradually from a conductive post 120 to a conductive wiring pattern 118 .
  • the connecting portion 140 may be broken easily.
  • FIG. 5 is an enlarged view showing the part 30 of a chip-size semiconductor package according to a first preferred embodiment of the present invention.
  • a connecting portion (boundary portion) 240 of a conductive wiring pattern 218 and a conductive post 220 is provided with four slits 250 to disperse stress to be applied to the connecting portion 240 .
  • the connecting portion 240 is a part which is easily broken in response to stress, so that the connecting portion 240 is shaped to decrease in area gradually from the conductive post 220 to the conductive wiring pattern 218 .
  • the slits 250 are arranged to be separated by a predetermined distance from each other.
  • the slits 250 are shaped to be rectangular and arranged to extend radially, as shown in FIG. 5.
  • the slits 250 are provided, so that stress applied to the connecting portion 240 is dispersed, and the molding resin is well in contact or bonded with the conductive post 220 and conductive wiring patter 218 . As a result, the connecting portion 240 is not easily broken.
  • FIG. 6 is an enlarged view showing the part 30 of a chip-size semiconductor package according to a second preferred embodiment of the present invention.
  • dummy pattern 350 is formed around a connecting portion (boundary portion) 340 of a conductive wiring pattern 318 and a conductive post 320 .
  • the dummy patterns 350 are arranged along the shape of the connecting portion 340 .
  • the connecting portion 340 is a part which is easily broken in response to stress, so that the connecting portion 340 is shaped to decrease in area gradually from the conductive post 320 to the conductive wiring pattern 318 .
  • the dummy patterns 350 are of conductive patterns which are formed in the same process as the conductive wiring pattern 318 and are arranged parallel to the conductive wiring pattern 318 .
  • the dummy patterns 350 are provided, so that stress applied to the connecting portion 340 is dispersed, and the molding resin is well in contact or bonded with the conductive post 320 and conductive wiring patter 318 . As a result, the connecting portion 340 is not easily broken.
  • FIG. 7 is an enlarged view showing a part of a chip-size semiconductor package according to a third preferred embodiment of the present invention.
  • FIG. 8 is a cross-sectional view taken on line A-A in FIG. 7.
  • a dent 450 is formed around a connecting portion (boundary portion) 440 of a conductive wiring pattern 418 and a conductive post 420 .
  • the connecting portion 440 is a part which is easily broken in response to stress, so that the connecting portion 440 is shaped to decrease in area gradually from the conductive post 420 to the conductive wiring pattern 418 .
  • the dent 450 is shaped to be square.
  • the dent 450 is formed around the connecting portion 440 , so that stress applied to the connecting portion 440 is dispersed, and the molding resin is well in contact or bonded with the conductive post 420 and conductive wiring patter 418 . As a result, the connecting portion 440 is not easily broken.
  • FIG. 9 is an enlarged view showing a part of a chip-size semiconductor package according to a fifth preferred embodiment of the present invention.
  • a conductive wiring pattern 518 is shaped to have a first region 518 a extending outwardly from a conductive post 520 and second regions 518 b each of which is extending or projecting vertically from the first region 518 a .
  • the projecting pats of the second region 518 b are extended from both sides of the first region 518 a .
  • One horizontal line of the projecting pats 518 b forms a part of the conductive post 520 .
  • the connecting portion 540 is a part which is easily broken in response to stress, so that the connecting portion 540 is shaped to decrease in area gradually from the conductive post 520 to the conductive wiring pattern 518 .
  • the conductive wiring pattern 518 is shaped to have the first region 518 a and second regions 518 b extending vertically from the first region 518 a , so that stress applied to the connecting portion 540 is dispersed, and the molding resin is well in contact or bonded with the conductive post 520 and conductive wiring patter 518 .
  • the connecting portion 540 is not easily broken.

Abstract

A chip-size semiconductor package includes a semiconductor chip; a metal pad formed on the semiconductor chip; a wafer coat formed over the semiconductor chip; a conductive wiring pattern formed on the wafer coat, in which the metal pad is electrically connected to the conductive pattern; a molding resin formed over the conductive wiring pattern; a conductive post which is formed in the molding resin and is connected to the conductive wiring pattern; and a terminal which is formed on the molding resin and is connected to the conductive post. A connecting portion (boundary portion) of the conductive wiring pattern and conductive post is provided with a slit to disperse stress to be applied to the connecting portion.

Description

    TECHNICAL FIELD OF THE INVENTION
  • The present invention generally relates to a chip-size semiconductor package, and more particularly to a chip-size semiconductor package having a wiring layer in which stress applied thereto is effectively relaxed. [0001]
    • BACKGROUND OF THE INVENTION
  • Usually, a chip-size semiconductor package includes a Si chip; metal pads formed on the Si chip; a wafer coating formed over the Si chip; conductive wiring patterns formed on the wafer coating; a molding resin formed over the wafer coating; conductive posts formed in the molding resin; and terminals formed on the molding resin. The conductive wiring patterns are electrically connected to the metal pads through the wafer coating. The terminals are connected to the conductive posts one by one. [0002]
  • According to the conventional chip-size package, a connecting portion (boundary portion) between the conductive post and wiring pattern is extremely narrow and weak. Therefore, the connecting portion may be broken by stress, which is generated when the molding resin is expanded or contracted. [0003]
  • According to another conventional chip-size semiconductor package, the connecting portion is shaped to decrease in area gradually from the conductive post to conductive wiring pattern. However, the area to be in contact with the molding resin is increased, so that the molding resin may be easily removed from the conductive post and conductive wiring pattern. As a result, the connecting portion may be broken later. [0004]
    • OBJECTS OF THE INVENTION
  • Accordingly, an object of the present invention is to provide a chip-size semiconductor package in which a connecting portion between a conductive post and a wiring pattern is not easily broken. [0005]
  • Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims. [0006]
    • SUMMARY OF THE INVENTION
  • According to a first aspect of the present invention, a chip-size semiconductor package includes a semiconductor chip; a metal pad formed on the semiconductor chip; a wafer coat formed over the semiconductor chip; a conductive wiring pattern formed on the wafer coat, in which the metal pad is electrically connected to the conductive pattern; a molding resin formed over the conductive wiring pattern; a conductive post which is formed in the molding resin and is connected to the conductive wiring pattern; and a terminal which is formed on the molding resin and is connected to the conductive post. A connecting portion (boundary portion) of the conductive wiring pattern and conductive post is provided with a slit to disperse stress to be applied to the connecting portion. [0007]
  • Preferably, the connecting portion is provided with a plurality of slits, which are separated from each other. The slits may be shaped to be rectangular and arranged to extend radially. Preferably, the connecting portion is shaped to decrease in area gradually from the conductive post to the conductive wiring pattern. [0008]
  • According to a second aspect of the present invention, a chip-size semiconductor package includes a semiconductor chip; a metal pad formed on the semiconductor chip; a wafer coat formed over the semiconductor chip; a conductive wiring pattern formed on the wafer coat, in which the metal pad is electrically connected to the conductive pattern; a molding resin formed over the conductive wiring pattern; a conductive post which is formed in the molding resin and is connected to the conductive wiring pattern; a terminal which is formed on the molding resin and is connected to the conductive post; and a dummy pattern arranged adjacent a connecting portion (boundary portion) of the conductive post and wiring pattern. [0009]
  • Preferably, the dummy pattern is a conductive pattern which is formed in the same process as the conductive wiring pattern and is arranged parallel to the conductive wiring pattern. Further, the dummy pattern may include two parts arranged at the both side of the conductive pattern. Further more, preferably, the connecting portion is shaped to decrease in area gradually from the conductive post to the conductive wiring pattern, and the two parts of the dummy pattern are arranged along the conductive post and conductive wiring pattern. [0010]
  • According to a third aspect of the present invention, a chip-size semiconductor package includes a semiconductor chip; a metal pad formed on the semiconductor chip; a wafer coat formed over the semiconductor chip; a conductive wiring pattern formed on the wafer coat, in which the metal pad is electrically connected to the conductive pattern; a molding resin formed over the conductive wiring pattern; a conductive post which is formed in the molding resin and is connected to the conductive wiring pattern; and a terminal which is formed on the molding resin and is connected to the conductive post. At least one of the conductive wiring pattern and conductive post is provided with a dent around a connecting portion (boundary portion) of the conductive wiring pattern and conductive post. [0011]
  • The dent may be shaped to be square. Preferably, the connecting portion is shaped to decrease in area gradually from the conductive post to the conductive wiring pattern. [0012]
  • According to a fourth aspect of the present invention, a chip-size semiconductor package includes a semiconductor chip; a metal pad formed on the semiconductor chip; a wafer coat formed over the semiconductor chip; a conductive wiring pattern formed on the wafer coat, in which the metal pad is electrically connected to the conductive pattern; a molding resin formed over the conductive wiring pattern; a conductive post which is formed in the molding resin and is connected to the conductive wiring pattern; and a terminal which is formed on the molding resin and is connected to the conductive post. The conductive wiring pattern is shaped to have a first region extending outwardly from the conductive post and a second region extending vertically from the first region. [0013]
  • Preferably, the second region comprises a plurality of projecting parts each of which extends vertically from the first region, and the projecting pats of the second region are extended from both sides of the first region. Further, the connecting portion may be shaped to decrease in area gradually from the conductive post to the conductive wiring pattern. At least one of the projecting pats may form a part of the conductive post.[0014]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view showing a conventional chip-size semiconductor package. [0015]
  • FIG. 2 is a plan view showing a conventional chip-size semiconductor package. [0016]
  • FIG. 3 is an enlarged view showing a part of the chip-size semiconductor package shown in FIG. 2. [0017]
  • FIG. 4 is an enlarged view showing a part of another conventional chip-size semiconductor package. [0018]
  • FIG. 5 is an enlarged view showing a part of a chip-size semiconductor package according to a first preferred embodiment of the present invention. [0019]
  • FIG. 6 is an enlarged view showing a part of a chip-size semiconductor package according to a second preferred embodiment of the present invention. [0020]
  • FIG. 7 is an enlarged view showing a part of a chip-size semiconductor package according to a third preferred embodiment of the present invention. [0021]
  • FIG. 8 is a cross-sectional view taken on line A-A in FIG. 7. [0022]
  • FIG. 9 is an enlarged view showing a part of a chip-size semiconductor package according to a fifth preferred embodiment of the present invention.[0023]
    • DETAILED DISCLOSURE OF THE INVENTION
  • In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced. These preferred embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other preferred embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present inventions. The following detailed description is, therefore, not to be taken in a limiting sense, and scope of the present inventions is defined only by the appended claims. [0024]
  • For better understanding of the present invention, a conventional technology is first described in conjunction with FIGS. [0025] 1 to 4. FIG. 1 is a cross-sectional view showing a conventional chip-size semiconductor package 10. FIG. 2 is a plan view showing the conventional chip-size semiconductor package 10, shown in FIG. 1. The chip-size semiconductor package 10 includes a Si chip 12; metal pads 14 formed on the Si chip 12; a wafer coating 16 formed over the Si chip 12; conductive wiring patterns 18 formed on the wafer coating 16; a molding resin 24 formed over the wafer coating 16; conductive posts 20 formed in the molding resin 24; and terminals 22 formed on the molding resin 24. The conductive wiring patterns 12 are electrically connected to the metal pads 14 through the wafer coating 16. The terminals 22 are connected to the conductive posts 20 one by one.
  • FIG. 3 is an enlarged view showing a [0026] part 30 encircled by a broken line in FIG. 2. As shown in FIG. 3, a connecting portion (boundary portion) 40 between the conductive post 20 and wiring pattern 18 is extremely narrow and weak. According to the conventional chip-size package, the connecting portion 40 may be broken by stress, which is generated when the molding resin 24 is expanded or contracted.
  • FIG. 4 is an enlarged view showing the [0027] part 30 of another conventional chip-size semiconductor package. As described above, a connecting portion (boundary portion) 140 is a part which is easily broken in response to stress, so that the connecting portion 140 is shaped to decrease in area gradually from a conductive post 120 to a conductive wiring pattern 118.
  • However, according to the chip-size semiconductor package, shown in FIG. 4, the area to be in contact with the [0028] molding resin 24 is increased, so that the molding resin 24 may be removed from the conductive post 120 and conductive wiring pattern 118. As a result, the connecting portion 140 may be broken easily.
  • Hereafter, a preferred embodiment of the present invention is described in detail with reference to FIGS. [0029] 5 to 9.
  • FIG. 5 is an enlarged view showing the [0030] part 30 of a chip-size semiconductor package according to a first preferred embodiment of the present invention. According to the first preferred embodiment, a connecting portion (boundary portion) 240 of a conductive wiring pattern 218 and a conductive post 220 is provided with four slits 250 to disperse stress to be applied to the connecting portion 240. The connecting portion 240 is a part which is easily broken in response to stress, so that the connecting portion 240 is shaped to decrease in area gradually from the conductive post 220 to the conductive wiring pattern 218.
  • The [0031] slits 250 are arranged to be separated by a predetermined distance from each other. The slits 250 are shaped to be rectangular and arranged to extend radially, as shown in FIG. 5. According to the first preferred embodiment, the slits 250 are provided, so that stress applied to the connecting portion 240 is dispersed, and the molding resin is well in contact or bonded with the conductive post 220 and conductive wiring patter 218. As a result, the connecting portion 240 is not easily broken.
  • FIG. 6 is an enlarged view showing the [0032] part 30 of a chip-size semiconductor package according to a second preferred embodiment of the present invention. According to the second preferred embodiment, dummy pattern 350 is formed around a connecting portion (boundary portion) 340 of a conductive wiring pattern 318 and a conductive post 320. The dummy patterns 350 are arranged along the shape of the connecting portion 340. The connecting portion 340 is a part which is easily broken in response to stress, so that the connecting portion 340 is shaped to decrease in area gradually from the conductive post 320 to the conductive wiring pattern 318.
  • The [0033] dummy patterns 350 are of conductive patterns which are formed in the same process as the conductive wiring pattern 318 and are arranged parallel to the conductive wiring pattern 318.
  • According to the second preferred embodiment, the [0034] dummy patterns 350 are provided, so that stress applied to the connecting portion 340 is dispersed, and the molding resin is well in contact or bonded with the conductive post 320 and conductive wiring patter 318. As a result, the connecting portion 340 is not easily broken.
  • FIG. 7 is an enlarged view showing a part of a chip-size semiconductor package according to a third preferred embodiment of the present invention. FIG. 8 is a cross-sectional view taken on line A-A in FIG. 7. According to the third preferred embodiment, a [0035] dent 450 is formed around a connecting portion (boundary portion) 440 of a conductive wiring pattern 418 and a conductive post 420. The connecting portion 440 is a part which is easily broken in response to stress, so that the connecting portion 440 is shaped to decrease in area gradually from the conductive post 420 to the conductive wiring pattern 418. The dent 450 is shaped to be square.
  • According to the third preferred embodiment, the [0036] dent 450 is formed around the connecting portion 440, so that stress applied to the connecting portion 440 is dispersed, and the molding resin is well in contact or bonded with the conductive post 420 and conductive wiring patter 418. As a result, the connecting portion 440 is not easily broken.
  • FIG. 9 is an enlarged view showing a part of a chip-size semiconductor package according to a fifth preferred embodiment of the present invention. According to the fourth preferred embodiment, a [0037] conductive wiring pattern 518 is shaped to have a first region 518 a extending outwardly from a conductive post 520 and second regions 518 b each of which is extending or projecting vertically from the first region 518 a. The projecting pats of the second region 518 b are extended from both sides of the first region 518 a. One horizontal line of the projecting pats 518 b forms a part of the conductive post 520.
  • The connecting [0038] portion 540 is a part which is easily broken in response to stress, so that the connecting portion 540 is shaped to decrease in area gradually from the conductive post 520 to the conductive wiring pattern 518.
  • According to the fourth preferred embodiment, the [0039] conductive wiring pattern 518 is shaped to have the first region 518 a and second regions 518 b extending vertically from the first region 518 a, so that stress applied to the connecting portion 540 is dispersed, and the molding resin is well in contact or bonded with the conductive post 520 and conductive wiring patter 518. As a result, the connecting portion 540 is not easily broken.

Claims (17)

What is claimed is:
1. A chip-size semiconductor package, comprising:
a semiconductor chip;
a metal pad formed on the semiconductor chip;
a wafer coat formed over the semiconductor chip;
a conductive wiring pattern formed on the wafer coat, in which the metal pad is electrically connected to the conductive pattern;
a molding resin formed over the conductive wiring pattern;
a conductive post which is formed in the molding resin and is connected to the conductive wiring pattern; and
a terminal which is formed on the molding resin and is connected to the conductive post, wherein a connecting portion (boundary portion) of the conductive wiring pattern and conductive post is provided with a slit to disperse stress to be applied to the connecting portion.
2. A chip-size semiconductor package according to claim 1, wherein
the connecting portion is provided with a plurality of slits, which are separated from each other.
3. A chip-size semiconductor package according to claim 2, wherein
the slits are shaped to be rectangular and arranged to extend radially.
4. A chip-size semiconductor package according to claim 1, wherein
the connecting portion is shaped to decrease in area gradually from the conductive post to the conductive wiring pattern.
5. A chip-size semiconductor package, comprising:
a semiconductor chip;
a metal pad formed on the semiconductor chip;
a wafer coat formed over the semiconductor chip;
a conductive wiring pattern formed on the wafer coat, in which the metal pad is electrically connected to the conductive pattern;
a molding resin formed over the conductive wiring pattern;
a conductive post which is formed in the molding resin and is connected to the conductive wiring pattern;
a terminal which is formed on the molding resin and is connected to the conductive post; and
a dummy pattern arranged adjacent a connecting portion (boundary portion) of the conductive post and wiring pattern.
6. A chip-size semiconductor package according to claim 5, wherein
the dummy pattern is a conductive pattern which is formed in the same process as the conductive wiring pattern and is arranged parallel to the conductive wiring pattern.
7. A chip-size semiconductor package according to claim 5, wherein
the dummy pattern comprises two parts arranged at the both side of the conductive pattern.
8. A chip-size semiconductor package according to claim 7, wherein
the connecting portion is shaped to decrease in area gradually from the conductive post to the conductive wiring pattern,
the two parts of the dummy pattern are arranged along the conductive post and conductive wiring pattern.
9. A chip-size semiconductor package, comprising:
a semiconductor chip;
a metal pad formed on the semiconductor chip;
a wafer coat formed over the semiconductor chip;
a conductive wiring pattern formed on the wafer coat, in which the metal pad is electrically connected to the conductive pattern;
a molding resin formed over the conductive wiring pattern;
a conductive post which is formed in the molding resin and is connected to the conductive wiring pattern; and
a terminal which is formed on the molding resin and is connected to the conductive post, wherein
at least one of the conductive wiring pattern and conductive post is provided with a dent around a connecting portion (boundary portion) of the conductive wiring pattern and conductive post.
10. A chip-size semiconductor package according to claim 9, wherein
the dent is shaped to be square.
11. A chip-size semiconductor package according to claim 9, wherein
the connecting portion is shaped to decrease in area gradually from the conductive post to the conductive wiring pattern.
12. A chip-size semiconductor package, comprising:
a semiconductor chip;
a metal pad formed on the semiconductor chip;
a wafer coat formed over the semiconductor chip;
a conductive wiring pattern formed on the wafer coat, in which the metal pad is electrically connected to the conductive pattern;
a molding resin formed over the conductive wiring pattern;
a conductive post which is formed in the molding resin and is connected to the conductive wiring pattern; and
a terminal which is formed on the molding resin and is connected to the conductive post, wherein
the conductive wiring pattern is shaped to have a first region extending outwardly from the conductive post and a second region extending vertically from the first region.
13. A chip-size semiconductor package according to claim 12, wherein
the second region comprises a plurality of projecting parts each of which extends vertically from the first region.
14. A chip-size semiconductor package according to claim 13, wherein
the projecting pats of the second region are extended from both sides of the first region.
15. A chip-size semiconductor package according to claim 12, wherein
the connecting portion is shaped to decrease in area gradually from the conductive post to the conductive wiring pattern.
16. A chip-size semiconductor package according to claim 15, wherein
at least one of the projecting pats forms a part of the conductive post.
17. A semiconductor device, comprising:
a semiconductor chip;
a pad which is formed on said semiconductor chip;
an insulating film which is formed on said semiconductor chip;
a conductive portion which is electrically connected to said pad, wherein
said conductive portion comprises:
a first portion which is formed on said insulating film and said pad; and
a second portion which is formed on said insulating film, wherein said second portion has a connection part contacting with said first portion formed on said insulating film, wherein said contacting part is gradually narrow toward said first portion.
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