US20030163745A1 - Method to reduce power in a computer system with bus master devices - Google Patents
Method to reduce power in a computer system with bus master devices Download PDFInfo
- Publication number
- US20030163745A1 US20030163745A1 US10/085,307 US8530702A US2003163745A1 US 20030163745 A1 US20030163745 A1 US 20030163745A1 US 8530702 A US8530702 A US 8530702A US 2003163745 A1 US2003163745 A1 US 2003163745A1
- Authority
- US
- United States
- Prior art keywords
- bus master
- memory
- master device
- processor
- low power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3275—Power saving in memory, e.g. RAM, cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0837—Cache consistency protocols with software control, e.g. non-cacheable data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
- G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the present invention relates generally to the field of power management. More specifically, the present invention relates to methods and systems for allowing processors to be placed in low power states.
- ACPI Advanced Configuration and Power Interface
- OS operating system
- ACPI combines power management and plug and play functionality for computer systems.
- ACPI describes a set of valid processor operating states and the allowable transitions between them.
- the upper four states defined for the processor are C 0 , C 1 , C 2 , and C 3 .
- the C 0 state is a normal operation state.
- the C 1 state is low-power, low-latency state that assumes no support from chipset logic that retains all cached context.
- the C 2 state is a lower-power, slightly longer latency state than C 1 that requires chipset support but still retains cached context.
- the C 3 state is a still lower power, longer latency state that also requires chipset support but one in which the cached context may be lost.
- Systems based on the IA-32 architecture typically map the use of the HALT (HLT) instruction to the C 1 state, the STOPGRANT/QUICKSTART assertion to the C 2 state, and Deep Sleep (removal of the processor clock input signal) operation to the C 3 state.
- HALT HLT
- STOPGRANT/QUICKSTART assertion to the C 2 state
- Deep Sleep demoval of the processor clock input signal
- the OS needs to make a policy decision as to which low power state the processor should be placed in based on the input/output (I/ 0 ) activity and the available states of the processor and their attributes.
- the ACPI system provides a bus master status (BM_STS) bit and an arbiter disable (ARB_DIS) bit.
- BM_STS bus master status
- ARB_DIS arbiter disable
- the ACPI system also provides control methods that describe the various available states of the processor.
- the BM_STS and ARB_DIS bits allow the OS to decide when to place the processor into the C 3 state and when to place the processor into the much higher power C 2 state.
- the policy for deciding between the C 2 or C 3 low power states is based on the capabilities of the system in the C 3 state. As mentioned previously the processor is incapable of snooping while in the C 3 state, and additionally memory/cache coherency problems occur during bus master accesses. So the OS policy tracks the activity of bus master accesses via the BM_STS bit. If there is little activity, then it disables the bus arbiter (which prevents bus masters from executing) by setting the BM_STS bit and puts the processor into the C 3 state.
- the interval for which the OS determines the C 2 /C 3 policy will affect the system's power performance.
- the policy for determining the C-state of the processor is performed once every preempt interval.
- a preempt is defined as an interrupt generated by a periodic timer, also known as the timer interrupt. Typically this interval is on the order of 10 ms-20 ms (the interval is dependent of the OS).
- the processor schedules its work to be performed during this preempt time, and when the processor finishes this work it is placed into a low power state.
- the OS looks at the remaining time in the preempt period, and the frequency of the bus master accesses. For entering a C 3 state, the OS insures that the remaining preempt time is greater than the C 3 exit latency, and then decides the likelihood of a bus master access for the remaining preempt time (by examining the BM_STS bit). If there is time for C 3 exit and there has been no bus master activity then the OS will place the processor into the C 3 state.
- an idle low power system wishes to enter into the lowest power processor state possible (the higher the Cx state the lower the power, e.g. C 3 is a much lower power state than C 1 ).
- the system must insure that there are no activities occurring that will affect the coherency of memory and/or caches as the processor is unable to snoop in this state.
- the policy for determining what Cx state occurs at least once per preempt interval, or on the order of once every 10 ms or so. These conditions define an idle C 3 state.
- the OS tracks all cache coherency issues via the BM_STS bit, and the OS concludes that it can't enter a C 3 state if the BM_STS bit is set.
- FIG. 1 is a block diagram illustrating an example of a computer system with non-cacheable memory in accordance to one embodiment of the present invention.
- FIG. 2 is a block diagram illustrating an example of a computer system with write-through cacheable memory in accordance to one embodiment of the present invention.
- a method that avoid setting the BM_STS bit to allow the processor to enter into the C 3 state while maintaining memory coherency is disclosed.
- caching policy of bus master buffers many bus master activities do not create cache coherency issues and therefore need not be tracked by the BM_STS bit, thus allowing the processor to enter the C 3 state more often.
- the bus master status (BM_STS) bit is set with either a bus master read operation or write operation.
- a USB host controller reads descriptors from the memory to determine if there is any operation that the USB host controller needs to perform. Reading the descriptors from the memory occurs every millisecond. Most of the time the descriptors indicate that there is no operation for the USB host controller to perform.
- the BM_STS bit is set because the driver buffer is write-back cacheable, and thus if a bus master read operation is executed to a memory region where the actual data resides in the processor's cache, and the processor is in a C 3 state, then bus master operation can't continue until the processor is awakened. This is because the processor is not able to service snoop cycles while in a C 3 state. To prevent this situation, given any previous traffic that might cause a snoop cycle (BM_STS is set), the OS sets the ARB_DIS bit to prevent any bus master operation.
- the processor can be placed into a low power state.
- memory space used by the driver is marked and maintained as non-cacheable, memory coherency issues go away. Marking this memory space as non-cacheable assures that copies of this memory space are not present in the processor's cache and that there is no need to snoop the processor's cache for any bus master accesses by the device that uses this memory area.
- the BM_STS is designed to NOT be set when a device generates bus master operations to the non-cacheable memory space, the OS can place the processor into the low power C 3 state more often.
- write-through cacheable memory means that there can be multiple copies of the data within the memory and processor cache, however both these copies are maintained coherent; any read operation just reads the local copy, while a write operation to a copy of this data must be copied to the other location (memory or cache).
- bus master memory read operations do not require any interaction of the processor while bus master write operations to memory will require the processor's cache to be snooped (in order to update its copy of the data).
- the BM_STS bit could be designed to be set only when these devices generate bus master write accesses to write through memory areas.
- bus master read accesses to write through cacheable memory areas do not need to set the BM_STS bit thus allowing the OS to place the CPU into the low power C 3 state.
- FIG. 1 is a block diagram illustrating an example of a computer system with non-cacheable memory in accordance to one embodiment of the present invention.
- the USB devices 135 and 140 are connected to the computer system 100 through a USB Host controller 120 .
- the computer system 100 includes a processor 102 , a memory controller unit (MCU) 105 and a memory 110 .
- MCU memory controller unit
- an OS in the computer system 100 schedules a periodic preempt interrupt at every time period (e.g., every 11 seconds). With each preempt interrupt, the OS schedules an amount of work for the processor 102 to do. When the processor 102 completes the work, the processor 102 is idled until a next preempt interrupt. The processor 102 then does some more work scheduled by the OS, and then the processor 102 is idle again.
- the OS puts the processor 102 into one of the low power states C 1 , C 2 , or C 3 , as described earlier.
- Each of these states has different attributes.
- the C 1 state is low power state of about 2 watts and has an exit latency of about 0.5 microseconds.
- the C 2 state is a lower power state of about 1.5 watts and has an exit latency time of about 100 microseconds.
- the C 3 state is a very low power state of about 0.2 watt and has an exit latency of approximately 3 microseconds.
- the C 3 state is a very low power processor state.
- the exit latency time is the time it takes for the processor 102 to restart when there is a preempt interrupt.
- Snooping is important in order to maintain coherency between the processor cache 103 and the memory 110 .
- the processor 102 When the processor 102 is placed into the C 3 state, the processor 102 cannot snoop the bus. For example, while the processor is in the C 3 state, if the USB host controller 120 (or a bus master controller) was to take control of the bus and perform a data write into the memory 110 , and the corresponding data happens to be in the processor cache 103 , then there would be a memory coherency problem. The data in the memory 110 would be more recent than the data in the processor cache 103 but the processor 102 would not have noticed it because it cannot snoop the bus.
- the ACPI specification calls out that the bus master arbiter 145 is disabled. Disabling the bus master arbiter 145 is achieved by setting the arbiter disable (ARB_DIS) bit. This prevents the bus master arbiter 145 from granting the bus to any bus master controller (including the USB host controller) or devices. However, setting the ARB_DIS bit would interfere with the ability of the USB host controller 120 to read its frame lists. As described above, the USB host controller 120 frequently generates a bus master access to the memory 110 (e.g., every one millisecond).
- ARB_DIS arbiter disable
- the portion of memory 110 used by the bus master device is set as non-cacheable, and the BM_STS bit is not set for any bus master accesses made by the bus master device (USB host controller 120 ).
- USB host controller 120 performs a bus master write operation to write into the non-cacheable memory 110 , there is no cache coherency problem to worry about.
- the USB host controller 120 performs a bus master read operation to read from the non-cacheable memory 110 , there is no memory coherency problem.
- the processor 102 does not need to snoop the bus during any bus access by the USB host controller 120 , and therefore can be placed in the low power C 3 state.
- the MCU 105 needs to not issue snoop cycles to the processor 102 for any bus master accesses from the “non-cacheable” bus master device (USB host controller 120 ).
- USB host controller 120 USB host controller 120
- memory attribute registers can be programmed into the MCU identifying which portions of memory are non-cacheable, or a separate signal from the bus master device could identify it as the originator of the bus cycle operation.
- the “non-cacheable” bus master device (USB host controller 120 ) no longer generates cache coherency problems, and the MCU 110 no longer generates snoop cycles to the processor 102 , the “non-cacheable” bus master device can be allowed to operate when the ARB_DIS bit is set (which would normally force all bus master devices to not operate). Note that this only applies to “non-cacheable” bus master devices, all other bus master devices that can create coherency issues need to be disabled when the ARB_DIS bit is set.
- FIG. 2 is a block diagram illustrating an example of a computer system with write-through cacheable memory in accordance to one embodiment of the present invention.
- the memory 210 is set as write-through cacheable for the memory used by the bus master device (in this case the USB host controller 220 ), and the BM_STS bit is only set for bus master write operations from this “write-through cacheable” bus master device, but is not set during bus master read operations from this “write-through cacheable” bus master device.
- the cache 203 and the memory 210 to be coherent with one another when there is a bus master write operation.
- the cache 203 is illustrated as a processor cache, this technique is also applicable to other cache implementation.
- the MCU 210 does not send snoop cycles to the processor 203 for any bus master read operations from this particular “write-through cacheable” bus master device (USB host controller 220 ).
- USB host controller 220 USB host controller 220 .
- memory attribute registers can be programmed into the MCU identifying which portions of memory are write-through cacheable, or a separate signal from the bus master could identify it as the originator of the bus cycle operation.
- the “write-through cacheable” bus master device no longer generates cache coherency problems for memory read cycles, and the MCU 210 no longer generates snoop cycles to the processor 203 for bus master read operations from this “write-through cacheable” bus master device, the “write-through cacheable” bus master device can be allowed to perform bus master read operations when the ARB_DIS bit is set (which would normally force all bus master devices to not operate).
- This “write-through cacheable” bus master device still needs to be prevented from generating bus master write cycles when the ARB_DIS bit is set, however bus master read operations can continue. Note that this only applies to “write-through-cacheable” bus master devices; all other bus master devices that can create coherency issues need to be disabled when the ARB_DIS bit is set.
- the operations of the various methods of the present invention may be implemented by a processing unit in a digital processing system, which executes sequences of computer program instructions.
- the operations may include hardware circuitry with an auxiliary processor dedicated to performing functions of power management.
- the operations may be performed using an application software including instructions that are stored in a memory, which may be considered to be a machine-readable storage media.
- the memory may be random access memory, read only memory, a persistent storage memory, such as mass storage device or any combination of these devices.
- Execution of the sequences of instruction causes the processing unit to perform operations according to the present invention.
- the instructions may be loaded into memory of the computer from a storage device or from one or more other digital processing systems (e.g. a server computer system) over a network connection.
- the instructions may be stored concurrently in several storage devices (e.g. DRAM and a hard disk, such as virtual memory). Consequently, the execution of these instructions may be performed directly by the processing unit.
- the instructions may not be performed directly or they may not be directly executable by the processing unit.
- the executions may be executed by causing the processor to execute an interpreter that interprets the instructions, or by causing the processor to execute instructions which convert the received instructions to instructions which can be directly executed by the processor.
- hard-wired circuitry may be used in place of or in combination with software instructions to implement the present invention.
- the present invention is not limited to any specific combination of hardware circuitry and software, nor to any particular source for the instructions executed by the computer or digital processing system.
Abstract
A system memory accessed by a bus master controller is set as non-cacheable. A bus master status bit is not set for any bus master controller transfer cycles with the non-cacheable memory while the a system processor is in a low power state.
Description
- The present invention relates generally to the field of power management. More specifically, the present invention relates to methods and systems for allowing processors to be placed in low power states.
- The Advanced Configuration and Power Interface (ACPI) specification defines a hardware and software environment that allows operating system (OS) software complete visibility and control of system configuration and power management. ACPI combines power management and plug and play functionality for computer systems. ACPI describes a set of valid processor operating states and the allowable transitions between them. The upper four states defined for the processor are C0, C1, C2, and C3. The C0 state is a normal operation state. The C1 state is low-power, low-latency state that assumes no support from chipset logic that retains all cached context. The C2 state is a lower-power, slightly longer latency state than C1 that requires chipset support but still retains cached context. The C3 state is a still lower power, longer latency state that also requires chipset support but one in which the cached context may be lost. Systems based on the IA-32 architecture typically map the use of the HALT (HLT) instruction to the C1 state, the STOPGRANT/QUICKSTART assertion to the C2 state, and Deep Sleep (removal of the processor clock input signal) operation to the C3 state. In the C1 and C2 states, the system processor can snoop the bus. In the C3 state, the system processor cannot snoop the bus.
- In an ACPI-enabled OS, the OS needs to make a policy decision as to which low power state the processor should be placed in based on the input/output (I/0) activity and the available states of the processor and their attributes. To help the OS makes this policy decision, the ACPI system provides a bus master status (BM_STS) bit and an arbiter disable (ARB_DIS) bit. The ACPI system also provides control methods that describe the various available states of the processor. The BM_STS and ARB_DIS bits allow the OS to decide when to place the processor into the C3 state and when to place the processor into the much higher power C2 state.
- The policy for deciding between the C2 or C3 low power states is based on the capabilities of the system in the C3 state. As mentioned previously the processor is incapable of snooping while in the C3 state, and additionally memory/cache coherency problems occur during bus master accesses. So the OS policy tracks the activity of bus master accesses via the BM_STS bit. If there is little activity, then it disables the bus arbiter (which prevents bus masters from executing) by setting the BM_STS bit and puts the processor into the C3 state.
- Additionally the interval for which the OS determines the C2/C3 policy will affect the system's power performance. For an ACPI OS, the policy for determining the C-state of the processor is performed once every preempt interval. A preempt is defined as an interrupt generated by a periodic timer, also known as the timer interrupt. Typically this interval is on the order of 10 ms-20 ms (the interval is dependent of the OS). The processor schedules its work to be performed during this preempt time, and when the processor finishes this work it is placed into a low power state.
- In placing the processor into the low power state, the OS looks at the remaining time in the preempt period, and the frequency of the bus master accesses. For entering a C3 state, the OS insures that the remaining preempt time is greater than the C3 exit latency, and then decides the likelihood of a bus master access for the remaining preempt time (by examining the BM_STS bit). If there is time for C3 exit and there has been no bus master activity then the OS will place the processor into the C3 state.
- Thus, an idle low power system wishes to enter into the lowest power processor state possible (the higher the Cx state the lower the power, e.g. C3 is a much lower power state than C1). In addition, to enter the C3 state, the system must insure that there are no activities occurring that will affect the coherency of memory and/or caches as the processor is unable to snoop in this state. Furthermore, the policy for determining what Cx state occurs at least once per preempt interval, or on the order of once every 10 ms or so. These conditions define an idle C3 state. However, if there is something that causes cache coherency issues and occurs as frequently as the preempt interval, then the processor will never enter the C3 state. The OS tracks all cache coherency issues via the BM_STS bit, and the OS concludes that it can't enter a C3 state if the BM_STS bit is set.
- The present invention is illustrated by way of example, and not limitation, in the figures of the accompanying drawings in which like references indicate similar elements and in which:
- FIG. 1 is a block diagram illustrating an example of a computer system with non-cacheable memory in accordance to one embodiment of the present invention.
- FIG. 2 is a block diagram illustrating an example of a computer system with write-through cacheable memory in accordance to one embodiment of the present invention.
- In one embodiment, a method that avoid setting the BM_STS bit to allow the processor to enter into the C3 state while maintaining memory coherency is disclosed. By changing caching policy of bus master buffers, many bus master activities do not create cache coherency issues and therefore need not be tracked by the BM_STS bit, thus allowing the processor to enter the C3 state more often.
- In the following description, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well known structures, processes, and devices are shown in block diagram form or are referred to in a summary manner in order to provide an explanation without undue detail.
- Typically, the bus master status (BM_STS) bit is set with either a bus master read operation or write operation. For example, in a system with USB devices, a USB host controller reads descriptors from the memory to determine if there is any operation that the USB host controller needs to perform. Reading the descriptors from the memory occurs every millisecond. Most of the time the descriptors indicate that there is no operation for the USB host controller to perform. Traditionally, the BM_STS bit is set because the driver buffer is write-back cacheable, and thus if a bus master read operation is executed to a memory region where the actual data resides in the processor's cache, and the processor is in a C3 state, then bus master operation can't continue until the processor is awakened. This is because the processor is not able to service snoop cycles while in a C3 state. To prevent this situation, given any previous traffic that might cause a snoop cycle (BM_STS is set), the OS sets the ARB_DIS bit to prevent any bus master operation.
- For a bus master write operation to a write-back cacheable memory area there is a chance that a copy of the memory area might reside within processor's cache. To maintain coherency, any bus master write operation to the write-through cacheable memory area needs to be snooped by the processor's cache. To prevent this situation the OS sets the ARB_DIS bit to prevent any bus master operation.
- By creating design practices that avoid cache and memory coherency issues, the processor can be placed into a low power state. When the memory space used by the driver is marked and maintained as non-cacheable, memory coherency issues go away. Marking this memory space as non-cacheable assures that copies of this memory space are not present in the processor's cache and that there is no need to snoop the processor's cache for any bus master accesses by the device that uses this memory area. When the BM_STS is designed to NOT be set when a device generates bus master operations to the non-cacheable memory space, the OS can place the processor into the low power C3 state more often.
- Alternatively, when the memory space used by the driver is marked and maintained as write-through cacheable, some of the memory coherency issues are resolved. Write-through cacheable memory means that there can be multiple copies of the data within the memory and processor cache, however both these copies are maintained coherent; any read operation just reads the local copy, while a write operation to a copy of this data must be copied to the other location (memory or cache). As such, bus master memory read operations do not require any interaction of the processor while bus master write operations to memory will require the processor's cache to be snooped (in order to update its copy of the data). For this type of configuration, where the bus master device's memory is marked as write-through cacheable, then the BM_STS bit could be designed to be set only when these devices generate bus master write accesses to write through memory areas. However bus master read accesses to write through cacheable memory areas do not need to set the BM_STS bit thus allowing the OS to place the CPU into the low power C3 state.
- To optimize the entry of the C3 state, the following table illustrates how the BM_STS should be set depending on the cache ability of the memory area being accessed:
Current Improved Type of Bus Master Cycle BM_STS BM_STS Memory Read Non-Cacheable Memory Set No change Memory Write Non-Cacheable Memory Set No change Memory Read Write-through Cacheable Memory Set No change Memory Write Write-through Cacheable Memory Set Set Memory Read Write-back Cacheable Memory Set Set Memory Write Write-back Cacheable Memory Set Set - As the table shows, making the bus master buffers non-cacheable totally avoids setting the BM_STS bit, while making bus master buffers write-through cacheable avoids setting the BM_STS bit for any read cycles. Depending on the behavior of the bus master, one of these techniques may be applied to allow the processor to enter into the C3 state more often.
- FIG. 1 is a block diagram illustrating an example of a computer system with non-cacheable memory in accordance to one embodiment of the present invention. The
USB devices computer system 100 through aUSB Host controller 120. Thecomputer system 100 includes aprocessor 102, a memory controller unit (MCU) 105 and amemory 110. Typically, an OS in thecomputer system 100 schedules a periodic preempt interrupt at every time period (e.g., every 11 seconds). With each preempt interrupt, the OS schedules an amount of work for theprocessor 102 to do. When theprocessor 102 completes the work, theprocessor 102 is idled until a next preempt interrupt. Theprocessor 102 then does some more work scheduled by the OS, and then theprocessor 102 is idle again. - When the
processor 102 is idle, the OS puts theprocessor 102 into one of the low power states C1, C2, or C3, as described earlier. Each of these states has different attributes. For example, the C1 state is low power state of about 2 watts and has an exit latency of about 0.5 microseconds. The C2 state is a lower power state of about 1.5 watts and has an exit latency time of about 100 microseconds. The C3 state is a very low power state of about 0.2 watt and has an exit latency of approximately 3 microseconds. The C3 state is a very low power processor state. The exit latency time is the time it takes for theprocessor 102 to restart when there is a preempt interrupt. - Snooping is important in order to maintain coherency between the
processor cache 103 and thememory 110. When theprocessor 102 is placed into the C3 state, theprocessor 102 cannot snoop the bus. For example, while the processor is in the C3 state, if the USB host controller 120 (or a bus master controller) was to take control of the bus and perform a data write into thememory 110, and the corresponding data happens to be in theprocessor cache 103, then there would be a memory coherency problem. The data in thememory 110 would be more recent than the data in theprocessor cache 103 but theprocessor 102 would not have noticed it because it cannot snoop the bus. - To prevent the memory coherency problem, the ACPI specification calls out that the
bus master arbiter 145 is disabled. Disabling thebus master arbiter 145 is achieved by setting the arbiter disable (ARB_DIS) bit. This prevents thebus master arbiter 145 from granting the bus to any bus master controller (including the USB host controller) or devices. However, setting the ARB_DIS bit would interfere with the ability of theUSB host controller 120 to read its frame lists. As described above, theUSB host controller 120 frequently generates a bus master access to the memory 110 (e.g., every one millisecond). - In one embodiment of the present invention, the portion of
memory 110 used by the bus master device is set as non-cacheable, and the BM_STS bit is not set for any bus master accesses made by the bus master device (USB host controller 120). This will cause the OS to ignore any bus master activity from this non-cacheable bus master device, and it will not influence the OS policy for placing theprocessor 102 in to the C3 state. For example, when theUSB host controller 120 performs a bus master write operation to write into thenon-cacheable memory 110, there is no cache coherency problem to worry about. When theUSB host controller 120 performs a bus master read operation to read from thenon-cacheable memory 110, there is no memory coherency problem. Thus, theprocessor 102 does not need to snoop the bus during any bus access by theUSB host controller 120, and therefore can be placed in the low power C3 state. - To optimize this type of configuration, the
MCU 105 needs to not issue snoop cycles to theprocessor 102 for any bus master accesses from the “non-cacheable” bus master device (USB host controller 120). There are many methods for performing this sort of memory typing. For example, memory attribute registers can be programmed into the MCU identifying which portions of memory are non-cacheable, or a separate signal from the bus master device could identify it as the originator of the bus cycle operation. - Further, because the “non-cacheable” bus master device (USB host controller120) no longer generates cache coherency problems, and the
MCU 110 no longer generates snoop cycles to theprocessor 102, the “non-cacheable” bus master device can be allowed to operate when the ARB_DIS bit is set (which would normally force all bus master devices to not operate). Note that this only applies to “non-cacheable” bus master devices, all other bus master devices that can create coherency issues need to be disabled when the ARB_DIS bit is set. - FIG. 2 is a block diagram illustrating an example of a computer system with write-through cacheable memory in accordance to one embodiment of the present invention. The
memory 210 is set as write-through cacheable for the memory used by the bus master device (in this case the USB host controller 220), and the BM_STS bit is only set for bus master write operations from this “write-through cacheable” bus master device, but is not set during bus master read operations from this “write-through cacheable” bus master device. This allows thecache 203 and thememory 210 to be coherent with one another when there is a bus master write operation. Although thecache 203 is illustrated as a processor cache, this technique is also applicable to other cache implementation. - To optimize this type of configuration, the
MCU 210 does not send snoop cycles to theprocessor 203 for any bus master read operations from this particular “write-through cacheable” bus master device (USB host controller 220). There are many methods for performing this sort of memory typing. For example, memory attribute registers can be programmed into the MCU identifying which portions of memory are write-through cacheable, or a separate signal from the bus master could identify it as the originator of the bus cycle operation. - Further because the “write-through cacheable” bus master device no longer generates cache coherency problems for memory read cycles, and the
MCU 210 no longer generates snoop cycles to theprocessor 203 for bus master read operations from this “write-through cacheable” bus master device, the “write-through cacheable” bus master device can be allowed to perform bus master read operations when the ARB_DIS bit is set (which would normally force all bus master devices to not operate). This “write-through cacheable” bus master device still needs to be prevented from generating bus master write cycles when the ARB_DIS bit is set, however bus master read operations can continue. Note that this only applies to “write-through-cacheable” bus master devices; all other bus master devices that can create coherency issues need to be disabled when the ARB_DIS bit is set. - The operations of the various methods of the present invention may be implemented by a processing unit in a digital processing system, which executes sequences of computer program instructions. The operations may include hardware circuitry with an auxiliary processor dedicated to performing functions of power management. The operations may be performed using an application software including instructions that are stored in a memory, which may be considered to be a machine-readable storage media. The memory may be random access memory, read only memory, a persistent storage memory, such as mass storage device or any combination of these devices. Execution of the sequences of instruction causes the processing unit to perform operations according to the present invention. The instructions may be loaded into memory of the computer from a storage device or from one or more other digital processing systems (e.g. a server computer system) over a network connection. The instructions may be stored concurrently in several storage devices (e.g. DRAM and a hard disk, such as virtual memory). Consequently, the execution of these instructions may be performed directly by the processing unit.
- In other cases, the instructions may not be performed directly or they may not be directly executable by the processing unit. Under these circumstances, the executions may be executed by causing the processor to execute an interpreter that interprets the instructions, or by causing the processor to execute instructions which convert the received instructions to instructions which can be directly executed by the processor. In other embodiments, hard-wired circuitry may be used in place of or in combination with software instructions to implement the present invention. Thus, the present invention is not limited to any specific combination of hardware circuitry and software, nor to any particular source for the instructions executed by the computer or digital processing system.
- Although the present invention has been described with reference to specific exemplary embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the invention as set forth in the claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
Claims (33)
1. A method, comprising:
setting a memory used by a bus master device as non-cacheable, the memory and the bus master device being in a computer system;
not setting a bus master status bit (BM_STS) for any bus master memory operation by the bus master device with the memory; and
placing the processor in the computer system into a low power state
2. The method of claim 1 , wherein the low power state is a deep sleep state.
3. The method of claim 1 , wherein the low power state is a C3 state.
4. The method of claim 1 , wherein the memory is coupled to a memory subsystem which does not generate snoop cycles to the processor during any bus master accesses performed by the bus master device.
5. The method of claim 4 , wherein the bus master device is allowed to generate bus master read and write operations when the ARB_DIS bit is set.
6. A computer readable medium having stored thereon sequences of instructions which are executable by a system, and which, when executed by the system, cause the system to perform a method, comprising:
setting a memory used by a bus master device as non-cacheable, the memory and the bus master device are in a computer system;
not setting a bus master status bit (BM_STS) for any bus master memory operation by the bus master device with the memory; and
placing the processor in the computer system into a low power state
7. The computer readable medium of claim 6 , wherein the low power state is a deep sleep state.
8. The computer readable medium of claim 6 , wherein the low power state is a C3 state.
9. The computer readable medium of claim 6 , wherein the memory is coupled to a memory subsystem which does not generate snoop cycles to the processor during any bus master accesses performed by the bus master device.
10. The computer readable medium of claim 9 , wherein the bus master device is allowed to generate bus master read and write operations when the ARB_DIS bit is set.
11. A system, comprising:
a memory set as non-cacheable;
a bus master device coupled to the memory; and
a processor coupled to the memory and the bus master device, wherein the processor is placed into a low power state while the bus master device performs memory operations with the non-cacheable memory and while a bus master status (BM_STS) bit is not set for these bus operations.
12. The system of claim 11 , wherein the low power state is a deep sleep state.
13. The system of claim 11 , wherein the low power state is a C3 state.
14. The system of claim 11 , further comprising a memory subsystem coupled to the memory, wherein the memory subsystem does not generate snoop cycles to the processor during any memory operations performed by the bus master device
15. The system of claim 14 , wherein the bus master device is allowed to generate bus master read and write operations when an arbiter disable (ARB_DIS) bit is set.
16. A method, comprising:
setting a memory used by a bus master device as write through-cacheable, the memory and the bus master device are in a computer system;
not setting the bus master status (BM_STS) bit while the bus master device performs memory read operations with the memory; and
placing the processor in the computer system into a low power state
17. The method of claim 16 , further comprising setting the BM_STS bit while the bus master device performs memory write operations with the memory.
18. The method of claim 17 , wherein the processor is not placed in the low power state while the bus master device performs memory write operations with the memory.
19. The method of claim 17 , wherein the low power state is a C3 state.
20. The method of claim 16 , wherein the memory is coupled to a memory subsystem which does not generate snoop cycles to the processor during any bus master read operations performed by the bus master device
21. The method of claim 20 , wherein the bus master device is allowed to generate bus master read operations when the ARB_DIS bit is set
22. A computer readable medium having stored thereon sequences of instructions which are executable by a system, and which, when executed by the system, cause the system to perform a method, comprising:
setting a memory used by a bus master device as write-through-cacheable, the memory and the bus master device are in a computer system;
not setting a bus master status (BM_STS) bit while the bus master device performs memory read operations with the memory; and
placing a processor in the computer system into a low power state.
23. The computer readable medium of claim 22 , further comprising setting the BM_STS bit while bus master device performs memory write operations with the memory.
24. The computer readable medium of claim 22 , wherein the processor is not placed in the low power state while bus master device performs memory write operations with the memory.
25. The computer readable medium of claim 22 , wherein the low power state is a C3 state.
26. The computer readable medium of claim 22 , wherein the memory is coupled to a memory subsystem which does not generate snoop cycles to the processor during any bus master read accesses performed by the bus master device
27. The computer readable medium of claim 26 , wherein the bus master device is allowed to generate bus master read operations when the ARB_DIS bit is set
28. A system, comprising:
a memory set as write-through cacheable;
a bus master device coupled to the memory; and
a processor coupled to the memory and the bus master device, wherein
the bus master is allowed to perform memory read operations while the processor is in a low power state without setting the bus master status (BM_STS) bit.
29. The system of claim 28 , wherein the processor is not placed into the low power state while the bus master device performs memory write operations with the memory.
30. The system of claim 28 , wherein the BM_STS bit is set while the bus master device performs the memory write operations with the memory.
31. The system of claim 28 , wherein the low power state is a C3 state.
32. The system of claim 28 , further comprising a memory subsystem coupled to the memory, wherein the memory subsystem does not generate snoop cycles to the processor during any bus master read operations performed by the bus master device.
33. The system of claim 32 , wherein the bus master device is allowed to generate bus master read operations when the ARB_DIS bit is set.
Priority Applications (9)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/085,307 US20030163745A1 (en) | 2002-02-27 | 2002-02-27 | Method to reduce power in a computer system with bus master devices |
KR1020047013414A KR100667999B1 (en) | 2002-02-27 | 2003-02-25 | Method to reduce power in a computer system with bus master devices |
PCT/US2003/005835 WO2003073253A2 (en) | 2002-02-27 | 2003-02-25 | Method to reduce power in a computer system with bus master devices |
AU2003217741A AU2003217741A1 (en) | 2002-02-27 | 2003-02-25 | Method to reduce power in a computer system with bus master devices |
KR1020067021404A KR20060122982A (en) | 2002-02-27 | 2003-02-25 | Method to reduce power in a computer system with bus master devices |
GB0420421A GB2403570B (en) | 2002-02-27 | 2003-02-25 | Method to reduce power in a computer system with bus master devices |
DE10392351T DE10392351T5 (en) | 2002-02-27 | 2003-02-25 | A method of reducing power consumption in a computer system with bus master devices |
CNB038044161A CN100351743C (en) | 2002-02-27 | 2003-02-25 | Method to reduce power in a computer system with bus master devices |
TW092104028A TWI281607B (en) | 2002-02-27 | 2003-02-26 | System and method for allowing a processor to be placed into a low power state |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/085,307 US20030163745A1 (en) | 2002-02-27 | 2002-02-27 | Method to reduce power in a computer system with bus master devices |
Publications (1)
Publication Number | Publication Date |
---|---|
US20030163745A1 true US20030163745A1 (en) | 2003-08-28 |
Family
ID=27753600
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/085,307 Abandoned US20030163745A1 (en) | 2002-02-27 | 2002-02-27 | Method to reduce power in a computer system with bus master devices |
Country Status (8)
Country | Link |
---|---|
US (1) | US20030163745A1 (en) |
KR (2) | KR20060122982A (en) |
CN (1) | CN100351743C (en) |
AU (1) | AU2003217741A1 (en) |
DE (1) | DE10392351T5 (en) |
GB (1) | GB2403570B (en) |
TW (1) | TWI281607B (en) |
WO (1) | WO2003073253A2 (en) |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040250035A1 (en) * | 2003-06-06 | 2004-12-09 | Atkinson Lee W. | Method and apparatus for affecting computer system |
EP1548547A1 (en) * | 2003-12-24 | 2005-06-29 | Texas Instruments Incorporated | Method and apparatus for reducing memory current leakage in a mobile device |
US20050144494A1 (en) * | 2003-12-24 | 2005-06-30 | Frederic Bonavita | Method and apparatus for reducing memory current leakage a mobile device |
US20050273633A1 (en) * | 2004-06-02 | 2005-12-08 | Intel Corporation | Hardware coordination of power management activities |
US20050273635A1 (en) * | 2004-06-02 | 2005-12-08 | Wilcox Jeffrey R | Power state coordination between devices sharing power-managed resources |
KR100656353B1 (en) | 2005-07-12 | 2006-12-11 | 한국전자통신연구원 | Method for reducing memory power consumption |
US20060288240A1 (en) * | 2005-06-16 | 2006-12-21 | Intel Corporation | Reducing computing system power through idle synchronization |
US20070005995A1 (en) * | 2005-06-30 | 2007-01-04 | Kardach James P | Power management system for computing platform |
US20070050549A1 (en) * | 2005-08-31 | 2007-03-01 | Verdun Gary J | Method and system for managing cacheability of data blocks to improve processor power management |
US20070055899A1 (en) * | 2005-09-06 | 2007-03-08 | Jui-Ming Wei | Method for power management of central processor unit |
US7620779B1 (en) | 2003-04-09 | 2009-11-17 | Klaiber Alexander C | System and method for handling direct memory accesses |
US7971002B1 (en) | 2005-04-07 | 2011-06-28 | Guillermo Rozas | Maintaining instruction coherency in a translation-based computer system architecture |
US8751753B1 (en) | 2003-04-09 | 2014-06-10 | Guillermo J. Rozas | Coherence de-coupling buffer |
US9575536B2 (en) | 2014-08-22 | 2017-02-21 | Intel Corporation | Methods and apparatus to estimate power performance of a job that runs on multiple nodes of a distributed computer system |
EP3486767A1 (en) * | 2009-12-16 | 2019-05-22 | Waseda University | Method of generating code executable by processor |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7750912B2 (en) * | 2005-11-23 | 2010-07-06 | Advanced Micro Devices, Inc. | Integrating display controller into low power processor |
CN100397301C (en) * | 2006-01-09 | 2008-06-25 | 威盛电子股份有限公司 | Power-saving method of central processor |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5325503A (en) * | 1992-02-21 | 1994-06-28 | Compaq Computer Corporation | Cache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same line |
US5414827A (en) * | 1991-12-19 | 1995-05-09 | Opti, Inc. | Automatic cache flush |
US5802305A (en) * | 1996-05-17 | 1998-09-01 | Microsoft Corporation | System for remotely waking a sleeping computer in power down state by comparing incoming packet to the list of packets storing on network interface card |
US5893141A (en) * | 1993-09-30 | 1999-04-06 | Intel Corporation | Low cost writethrough cache coherency apparatus and method for computer systems without a cache supporting bus |
US5983354A (en) * | 1997-12-03 | 1999-11-09 | Intel Corporation | Method and apparatus for indication when a bus master is communicating with memory |
US6128703A (en) * | 1997-09-05 | 2000-10-03 | Integrated Device Technology, Inc. | Method and apparatus for memory prefetch operation of volatile non-coherent data |
US6205507B1 (en) * | 1996-06-13 | 2001-03-20 | Compaq Computer Corporation | Memory coherency in a processor-to-bus cycle in a multi-processor system |
US6658532B1 (en) * | 1999-12-15 | 2003-12-02 | Intel Corporation | Cache flushing |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0585117A1 (en) * | 1992-08-26 | 1994-03-02 | Cyrix Corporation | Method and system for maintaining cache coherency in a multi-master computer system |
US6052789A (en) * | 1994-03-02 | 2000-04-18 | Packard Bell Nec, Inc. | Power management architecture for a reconfigurable write-back cache |
WO1998044405A1 (en) * | 1997-03-31 | 1998-10-08 | Intel Corporation | Automatic transitioning between acpi c3 and c2 states |
KR100626359B1 (en) * | 1999-09-10 | 2006-09-20 | 삼성전자주식회사 | Method for power management of computer system |
US6633987B2 (en) * | 2000-03-24 | 2003-10-14 | Intel Corporation | Method and apparatus to implement the ACPI(advanced configuration and power interface) C3 state in a RDRAM based system |
-
2002
- 2002-02-27 US US10/085,307 patent/US20030163745A1/en not_active Abandoned
-
2003
- 2003-02-25 GB GB0420421A patent/GB2403570B/en not_active Expired - Fee Related
- 2003-02-25 KR KR1020067021404A patent/KR20060122982A/en not_active Application Discontinuation
- 2003-02-25 WO PCT/US2003/005835 patent/WO2003073253A2/en not_active Application Discontinuation
- 2003-02-25 DE DE10392351T patent/DE10392351T5/en not_active Ceased
- 2003-02-25 CN CNB038044161A patent/CN100351743C/en not_active Expired - Fee Related
- 2003-02-25 AU AU2003217741A patent/AU2003217741A1/en not_active Abandoned
- 2003-02-25 KR KR1020047013414A patent/KR100667999B1/en not_active IP Right Cessation
- 2003-02-26 TW TW092104028A patent/TWI281607B/en not_active IP Right Cessation
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5414827A (en) * | 1991-12-19 | 1995-05-09 | Opti, Inc. | Automatic cache flush |
US5325503A (en) * | 1992-02-21 | 1994-06-28 | Compaq Computer Corporation | Cache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same line |
US5893141A (en) * | 1993-09-30 | 1999-04-06 | Intel Corporation | Low cost writethrough cache coherency apparatus and method for computer systems without a cache supporting bus |
US5802305A (en) * | 1996-05-17 | 1998-09-01 | Microsoft Corporation | System for remotely waking a sleeping computer in power down state by comparing incoming packet to the list of packets storing on network interface card |
US6205507B1 (en) * | 1996-06-13 | 2001-03-20 | Compaq Computer Corporation | Memory coherency in a processor-to-bus cycle in a multi-processor system |
US6128703A (en) * | 1997-09-05 | 2000-10-03 | Integrated Device Technology, Inc. | Method and apparatus for memory prefetch operation of volatile non-coherent data |
US5983354A (en) * | 1997-12-03 | 1999-11-09 | Intel Corporation | Method and apparatus for indication when a bus master is communicating with memory |
US6658532B1 (en) * | 1999-12-15 | 2003-12-02 | Intel Corporation | Cache flushing |
Cited By (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9558116B2 (en) | 2003-04-09 | 2017-01-31 | Intellectual Ventures Holding 81 Llc | Coherence de-coupling buffer |
US7620779B1 (en) | 2003-04-09 | 2009-11-17 | Klaiber Alexander C | System and method for handling direct memory accesses |
US7636815B1 (en) * | 2003-04-09 | 2009-12-22 | Klaiber Alexander C | System and method for handling direct memory accesses |
US7937536B2 (en) | 2003-04-09 | 2011-05-03 | Klaiber Alexander C | Handling direct memory accesses |
US8751753B1 (en) | 2003-04-09 | 2014-06-10 | Guillermo J. Rozas | Coherence de-coupling buffer |
US10540283B2 (en) | 2003-04-09 | 2020-01-21 | Facebook, Inc. | Coherence de-coupling buffer |
US20100138615A1 (en) * | 2003-04-09 | 2010-06-03 | Klaiber Alexander C | Handling direct memory accesses |
US20040250035A1 (en) * | 2003-06-06 | 2004-12-09 | Atkinson Lee W. | Method and apparatus for affecting computer system |
EP1548547A1 (en) * | 2003-12-24 | 2005-06-29 | Texas Instruments Incorporated | Method and apparatus for reducing memory current leakage in a mobile device |
US20050144494A1 (en) * | 2003-12-24 | 2005-06-30 | Frederic Bonavita | Method and apparatus for reducing memory current leakage a mobile device |
US7930572B2 (en) | 2003-12-24 | 2011-04-19 | Texas Instruments Incorporated | Method and apparatus for reducing memory current leakage a mobile device |
US7315952B2 (en) * | 2004-06-02 | 2008-01-01 | Intel Corporation | Power state coordination between devices sharing power-managed resources |
US20050273635A1 (en) * | 2004-06-02 | 2005-12-08 | Wilcox Jeffrey R | Power state coordination between devices sharing power-managed resources |
US7272741B2 (en) | 2004-06-02 | 2007-09-18 | Intel Corporation | Hardware coordination of power management activities |
US20050273633A1 (en) * | 2004-06-02 | 2005-12-08 | Intel Corporation | Hardware coordination of power management activities |
US7971002B1 (en) | 2005-04-07 | 2011-06-28 | Guillermo Rozas | Maintaining instruction coherency in a translation-based computer system architecture |
US7454632B2 (en) | 2005-06-16 | 2008-11-18 | Intel Corporation | Reducing computing system power through idle synchronization |
WO2006138687A3 (en) * | 2005-06-16 | 2007-03-01 | Intel Corp | Reducing computing system power through idle synchronization |
WO2006138687A2 (en) | 2005-06-16 | 2006-12-28 | Intel Corporation | Reducing computing system power through idle synchronization |
US20060288240A1 (en) * | 2005-06-16 | 2006-12-21 | Intel Corporation | Reducing computing system power through idle synchronization |
US20070005995A1 (en) * | 2005-06-30 | 2007-01-04 | Kardach James P | Power management system for computing platform |
US7430673B2 (en) | 2005-06-30 | 2008-09-30 | Intel Corporation | Power management system for computing platform |
KR100656353B1 (en) | 2005-07-12 | 2006-12-11 | 한국전자통신연구원 | Method for reducing memory power consumption |
US20070050549A1 (en) * | 2005-08-31 | 2007-03-01 | Verdun Gary J | Method and system for managing cacheability of data blocks to improve processor power management |
US7475263B2 (en) * | 2005-09-06 | 2009-01-06 | Via Technologies Inc. | Method for power management of central processor unit |
US20070055899A1 (en) * | 2005-09-06 | 2007-03-08 | Jui-Ming Wei | Method for power management of central processor unit |
EP3486767A1 (en) * | 2009-12-16 | 2019-05-22 | Waseda University | Method of generating code executable by processor |
EP2508992B1 (en) * | 2009-12-16 | 2019-06-26 | Waseda University | Method of generating code executable by a processor |
US9575536B2 (en) | 2014-08-22 | 2017-02-21 | Intel Corporation | Methods and apparatus to estimate power performance of a job that runs on multiple nodes of a distributed computer system |
US9921633B2 (en) | 2014-08-22 | 2018-03-20 | Intel Corporation | Power aware job scheduler and manager for a data processing system |
US9927857B2 (en) | 2014-08-22 | 2018-03-27 | Intel Corporation | Profiling a job power and energy consumption for a data processing system |
US10289183B2 (en) | 2014-08-22 | 2019-05-14 | Intel Corporation | Methods and apparatus to manage jobs that can and cannot be suspended when there is a change in power allocation to a distributed computer system |
US10712796B2 (en) | 2014-08-22 | 2020-07-14 | Intel Corporation | Method and apparatus to generate and use power, thermal and performance characteristics of nodes to improve energy efficiency and reducing wait time for jobs in the queue |
Also Published As
Publication number | Publication date |
---|---|
GB2403570B (en) | 2006-11-22 |
CN100351743C (en) | 2007-11-28 |
TW200402619A (en) | 2004-02-16 |
KR20060122982A (en) | 2006-11-30 |
AU2003217741A1 (en) | 2003-09-09 |
TWI281607B (en) | 2007-05-21 |
KR100667999B1 (en) | 2007-01-15 |
DE10392351T5 (en) | 2005-03-10 |
GB0420421D0 (en) | 2004-10-20 |
GB2403570A (en) | 2005-01-05 |
WO2003073253A3 (en) | 2004-02-19 |
WO2003073253A2 (en) | 2003-09-04 |
CN1639671A (en) | 2005-07-13 |
KR20040086459A (en) | 2004-10-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5530932A (en) | Cache coherent multiprocessing computer system with reduced power operating features | |
US5426765A (en) | Multiprocessor cache abitration | |
US5335335A (en) | Multiprocessor cache snoop access protocol wherein snoop means performs snooping operations after host bus cycle completion and delays subsequent host bus cycles until snooping operations are completed | |
US5669003A (en) | Method of monitoring system bus traffic by a CPU operating with reduced power | |
US5737759A (en) | Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests | |
US5913224A (en) | Programmable cache including a non-lockable data way and a lockable data way configured to lock real-time data | |
US20030163745A1 (en) | Method to reduce power in a computer system with bus master devices | |
US7925840B2 (en) | Data processing apparatus and method for managing snoop operations | |
US5325503A (en) | Cache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same line | |
US6658532B1 (en) | Cache flushing | |
US6976131B2 (en) | Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system | |
US9372803B2 (en) | Method and system for shutting down active core based caches | |
US20100235670A1 (en) | Fast L1 Flush Mechanism | |
US20090327609A1 (en) | Performance based cache management | |
US5829027A (en) | Removable processor board having first, second and third level cache system for use in a multiprocessor computer system | |
US5163143A (en) | Enhanced locked bus cycle control in a cache memory computer system | |
JP2007004802A (en) | Snoop operation management in data processor | |
US20040111563A1 (en) | Method and apparatus for cache coherency between heterogeneous agents and limiting data transfers among symmetric processors | |
EP0681241A1 (en) | Processor board having a second level writeback cache system and a third level writethrough cache system which stores exclusive state information for use in a multiprocessor computer system | |
US5913225A (en) | Cache flush mechanism for a secondary cache memory | |
CN115087961A (en) | Arbitration scheme for coherent and non-coherent memory requests | |
JPH06282528A (en) | Method and system for transfer of data | |
US20040250035A1 (en) | Method and apparatus for affecting computer system | |
JPH0922382A (en) | Computer system and method for invalidation of data block stored in external cache of its processor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |