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Número de publicaciónUS20030201536 A1
Tipo de publicaciónSolicitud
Número de solicitudUS 10/423,077
Fecha de publicación30 Oct 2003
Fecha de presentación25 Abr 2003
Fecha de prioridad26 Abr 2002
También publicado comoCN1453834A, CN1652310A, CN1652311A, CN100456438C, CN100459066C, CN100483648C, DE10318921A1, US7259095, US7821135, US20050140013, US20050196959
Número de publicación10423077, 423077, US 2003/0201536 A1, US 2003/201536 A1, US 20030201536 A1, US 20030201536A1, US 2003201536 A1, US 2003201536A1, US-A1-20030201536, US-A1-2003201536, US2003/0201536A1, US2003/201536A1, US20030201536 A1, US20030201536A1, US2003201536 A1, US2003201536A1
InventoresKazuyoshi Ueno
Cesionario originalNec Electronics Corporation
Exportar citaBiBTeX, EndNote, RefMan
Enlaces externos: USPTO, Cesión de USPTO, Espacenet
Semiconductor device and manufacturing process therefor as well as plating solution
US 20030201536 A1
Resumen
An object of this invention is to improve stress-migration resistance and reliability in a semiconductor device comprising a metal region. In an insulating film 101 is formed a lower interconnection consisting of a barrier metal film 102 and a copper-silver alloy film 103, on which is then formed an interlayer insulating film 104. In the interlayer insulating film 104 is formed an upper interconnection consisting of a barrier metal film 106 and a copper-silver alloy film 111. The lower and the upper interconnections are made of a copper-silver alloy which contains silver to an amount more than a solid solution limit of silver to copper.
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Reclamaciones(21)
What is claimed is:
1. A semiconductor device comprising a metal region on a semiconductor substrate, wherein a silver content is more than 1 wt % to the total amount of component metals in the metal region.
2. A semiconductor device comprising a metal region on a semiconductor substrate, wherein the metal region comprises copper and silver; and a silver content to the total amount of component metals in the metal region is more than a solid solution limit of silver to copper.
3. A semiconductor device comprising a metal region on a semiconductor substrate wherein a maximum hysteresis error in a temperature-stress curve in the metal region is 150 MPa or less.
4. A semiconductor device comprising a metal region on a semiconductor substrate wherein a recrystallization temperature of a component metal of the metal region is 200° C. or higher.
5. The semiconductor device as claimed in claim 3, wherein the metal region is made of a silver-containing metal.
6. The semiconductor device as claimed in claim 4, wherein the metal region is made of a silver-containing metal.
7. The semiconductor device as claimed in claim 1, wherein the metal region is an interconnection plug or pad.
8. The semiconductor device as claimed in claim 2, wherein the metal region is an interconnection plug or pad.
9. The semiconductor device as claimed in claim 3, herein the metal region is an interconnection plug or pad.
10. The semiconductor device as claimed in claim 4, wherein the metal region is an interconnection plug or pad.
11. A process for manufacturing a semiconductor device comprising the steps of:
forming a metal region on a semiconductor substrate;
contacting the surface of the metal region with a silver-containing liquid; and
heating the metal region.
12. The process for manufacturing a semiconductor device as claimed in claim 11, wherein the metal region contains copper.
13. The process for manufacturing a semiconductor device as claimed in claim 11, wherein a silver content is more than 1 wt % to the total amount of component metals in the metal region after heating.
14. A process for manufacturing a semiconductor device comprising the steps of:
contacting a semiconductor substrate or a film formed thereon with a silver-containing solution to precipitate silver;
forming a metal region on the precipitated silver; and
heating the metal region.
15. The process for manufacturing a semiconductor device as claimed in claim 14, wherein the metal region contains copper.
16. The process for manufacturing a semiconductor device as claimed in claim 14, wherein a silver content is more than 1 wt % to the total amount of component metals in the metal region after heating.
17. A process for manufacturing a semiconductor device comprising the steps of contacting a device-forming surface of a semiconductor substrate with a silver-containing plating solution; and forming a silver-containing metal region on the semiconductor substrate.
18. The process for manufacturing a semiconductor device as claimed in claim 17, wherein a chloride ion concentration in the plating solution is 100 ppm by weight or less.
19. The process for manufacturing a semiconductor device as claimed in claim 17, wherein the plating solution contains copper at 0.01 to 5 mol/L, silver at 0.01 to 5 mol/L, ethylenediamine at 0.01 to 5 mol/L and water.
20. The process for manufacturing a semiconductor device as claimed in claim 17, wherein the plating solution contains copper at 0.01 to 5 mol/L, silver at 0.01 to 5 mol/L, pyrophosphoric acid or its salt at 0.01 to 5 mol/L and water.
21. The process for manufacturing a semiconductor device as claimed in any of claims 17, wherein the metal region contains copper.
Descripción

[0001] This application is based on Japanese patent application NO.2002-127702, the content of which is incorporated hereinto by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] This invention relates to a semiconductor device comprising a silver-containing metal region and a process for manufacturing the device.

[0004] 2. Description of the Prior Art

[0005] Recent increasing integration of a semiconductor device has required the use of copper as a material for an interconnection or plug. Copper has advantageous properties of a lower resistance and higher electromigration resistance compared with aluminum which has been conventionally used.

[0006] However, as a device has become more compact, electromigration has been significant in such an interconnection using copper. A copper film as a copper interconnection is usually formed by plating, which gives the copper film as an aggregate of a number of polycrystalline copper grains. When a voltage is applied to a copper interconnection having such a structure, mass transfer occurs via a copper grain boundary, leading to electromigration. In a narrower interconnection, a copper grain size is smaller and thus the problem of migration due to mass transfer via such a grain boundary becomes more significant.

[0007] For solving such a problem of electromigration (hereinafter, referred to as “EM”), there have been several attempts where silver is added to a copper interconnection.

[0008] Japanese Laid-open Patent Publication 2000-349085 has disclosed an interconnection made of a silver-containing copper alloy, and described that the interconnection has a silver content within a range of at least 0.1 wt % to less than its maximum solid solution limit, and if more than the maximum solid solution limit, the metal may form a compound with Cu, leading to a rupture or crack in the interconnection.

[0009] Japanese Laid-open Patent Publication 1999-204524 has disclosed an interconnection made of a silver-containing copper alloy and described that a silver content in the interconnection is preferably 1 wt % or less and illustrates forming an interconnection made of a copper alloy containing silver at 0.1 wt % as a specific example.

[0010] Some other attempts using a silver-containing copper interconnection have been made for minimizing electromigration and all of these studies have concluded that in the light of the purpose, a silver content is within its solid solution limit in a copper film and thus at most 1 wt %. There have been developed no methods for consistently forming an alloy containing silver and copper with a silver content higher than the above limit and thus there have been little information about the physical properties of such an alloy film and its effects on device performance when applied in a semiconductor device.

[0011] Meanwhile, stress migration in a copper interconnection has become a significant problem. FIG. 2 shows a schematic cross section of a copper multilayer interconnection formed by a damascene method, where an upper interconnection 121 b is connected with a lower interconnection 121 a and the upper interconnection 121 b consists of a connecting plug and an interconnection formed thereon. In FIG. 2(a), a void 122 is formed on the side of the upper interconnection 121 b. That is, the void is formed in a via region in the upper interconnection 121 b. In FIG. 2(b), a void 122 is formed on the upper surface of the lower interconnection 121 a. Such a void 122 may be caused by an internal stress generated in the copper interconnection due to, for example, a heat history during a semiconductor process. In FIG. 2(a), the void 122 may be formed by upward migration of copper in the via due to copper “pull-up” in the upper interconnection 121 b. In FIG. 2(b), copper may horizontally migrate in the lower interconnection 121 a, leading to formation of the void 122.

[0012] Our studies have demonstrated that such a void-forming phenomenon prominently occurs about at 150° C. which is a practical process temperature for a semiconductor device (for example, in a bonding process and a photoresist baking process). A void thus formed may cause connection defect between a connecting plug and an interconnection, a reduced yield of a semiconductor device and instability in a semiconductor device after a long period use.

[0013] For preventing generation of such stress migration, besides investigating processes, a material itself for a metal region such as an interconnection must be studied besides process investigation.

[0014] Furthermore, the recent needs for much higher level of device operation require developing a material for an interconnection exhibiting higher-speed operability than a copper interconnection.

SUMMARY OF THE INVENTION

[0015] In view of these problems, an objective of this invention is to improve stress migration resistance in a semiconductor device comprising a metal region, and thus to improve reliability of the device.

[0016] Another objective of this invention is to provide a process for consistently manufacturing such a semiconductor device.

[0017] This invention provides a semiconductor device comprising a metal region on a semiconductor substrate, wherein a silver content is more than 1 wt % to the total amount of component metals in the metal region.

[0018] This invention also provides on a semiconductor device comprising a metal region on a semiconductor substrate, wherein the metal region comprises copper and silver; and a silver content to the total amount of component metals in the metal region is more than a solid solution limit of silver to copper.

[0019] The metal region in the above semiconductor device a larger amount of silver than that in a conventional interconnection structure made of a copper-silver alloy, and thus can effectively prevent stress migration when being exposed to a heat history during, for example, a process for manufacturing a semiconductor.

[0020] This invention also provides a semiconductor device comprising a metal region on a semiconductor substrate wherein a maximum hysteresis error in a temperature-stress curve in the metal region is 150 MPa or less.

[0021] When a semiconductor device is exposed to a heat history, a temperature-stress curve for a metal region generally exhibits different patterns in a warming and a cooling processes. An indicator for the difference is defined as a “maximum hysteresis error”. A maximum hysteresis error is the maximum separation width between the curves showing the warming and the cooling processes. For example, in FIG. 8, the maximum width between a warming process a and a cooling process b is a maximum hysteresis error. In the semiconductor device, an irreversible loss is reduced when being exposed to a heat history during a process for manufacturing a semiconductor, and thus stress migration is effectively prevented.

[0022] This invention further provides a semiconductor device comprising a metal region on a semiconductor substrate wherein a recrystallization temperature of a component metal in the metal region is 200° C. or higher. A recrystallization temperature is a temperature at which transformation of crystal grains or grain growth occurs due to atomic diffusion. Since recrystallization may result in a void or distortion in a metal region, a higher recrystallization temperature is an important condition for providing a reliable metal region. The above semiconductor device has a recrystallization temperature higher than 200° C., so that irreversible loss can be minimized when being exposed to a heat history and thus stress migration can be effectively prevented. A recrystallization temperature can be determined by, for example, measuring a hysteresis curve. FIG. 9 shows a method for determining a recrystallization temperature. An inflection point during a warming process, i.e., an intersection between a linear line and a horizontal line after the initiation of temperature-rising corresponds to a recrystallization temperature. In this figure, a recrystallization temperature is 220° C.

[0023] In a semiconductor device according to this invention, the metal region may be made of a silver-containing metal with a shape of an interconnection plug or pad.

[0024] This invention also provides a process for manufacturing a semiconductor device comprising the steps of forming a metal region on a semiconductor substrate; contacting the surface of the metal region with a silver-containing liquid; and heating the metal region.

[0025] According to this process for manufacturing a semiconductor device, contacting the surface of the metal region with a silver-containing liquid results in precipitation of silver and then heating allows silver to diffuse in the metal region. As a result, a silver-containing metal region may be suitably formed. According to this invention, a metal region made of a copper-silver alloy may be consistently formed by a convenient process. Since a plating solution itself does not have to contain silver, the plating solution may be selected more freely.

[0026] This invention also provides a process for manufacturing a semiconductor device comprising the steps of contacting a semiconductor substrate or a film formed thereon with a silver-containing solution to precipitate silver; forming a metal region on the precipitated silver; and heating the metal region.

[0027] According to the process for manufacturing a semiconductor device, the precipitated silver after contacting with the silver-containing solution diffuses in a metal region formed thereon. As a result, a silver-containing metal region may be suitably formed. According to this invention, a metal region made of a copper-silver alloy may be consistently formed by a convenient process. Furthermore, a metal composition in a metal region may be made homogeneous.

[0028] This invention also provides a process for manufacturing a semiconductor device comprising the steps of contacting a device-forming surface of a semiconductor substrate with a silver-containing plating solution; and forming a silver-containing metal region on the semiconductor substrate. The silver-containing plating solution may be contacted with all or a part of the device-forming surface. Specifically, a plating solution is contacted with either of a semiconductor substrate surface, a metal film, an insulating film or a semiconductor film or a surface comprising these in any combination.

[0029] Contacting with a silver-containing plating solution may be conducted after forming a plating film using a silver-free plating solution. The process may comprise, for example, the steps of forming a copper film such that it partially fills a concave formed in an insulating film on a semiconductor substrate; then contacting the surface of the copper film with a silver-containing plating solution to form a silver-containing film on the copper film; and then polishing the whole surface of the substrate to leave the copper film and the silver-containing film only in the concave. Alternatively, this process may comprises the steps of forming a silver-containing film; forming a copper film on the silver-containing film; and polishing the substrate surface as described above.

[0030] According to this process for manufacturing a semiconductor device, a metal region made of a copper-silver alloy may be consistently formed by a convenient process. A homogeneous metal composition may be provided in the metal region.

[0031] In a process for manufacturing a semiconductor device according to this invention, the metal region may contain copper. Furthermore, in a process for manufacturing a semiconductor device according to this invention, a silver content may be more than 1 wt % to the total amount of component metals in the metal region after heating. Thus, a metal region highly resistant to stress migration may be consistently formed.

[0032] When a metal region in this invention is made of a copper-silver alloy, other components may be further added. For example, components such as Zr, In, Al, Ti and Sn may be added up to 1 wt % to the total amount of the metals. Zr and/or In may be added to improve adhesiveness between the metal region and an insulating film and/or between the metal region and a barrier metal film. Al, Ti and Sn may diffuse in the surface of the reactive copper-silver alloy film to be bound to the material atoms constituting the interlayer insulating film, resulting in improved adhesiveness.

[0033] While some aspects of this invention have been described, variations may be made to these. For example, when this invention is applied to an interconnection structure formed by a damascene process, the effects of this invention become more prominent. There will be described such aspects.

[0034] Specifically, a metal region in this invention may be formed by a single or dual damascene process.

[0035] A single damascene process comprises the steps of:

[0036] (a) forming a first interconnection as a metal film on a semiconductor substrate;

[0037] (b) forming a first interlayer insulating film over the whole upper surface of the semiconductor substrate such that it covers the first interconnection;

[0038] (c) selectively removing the first interlayer insulating film to form a connecting hole reaching the upper surface of the first interconnection;

[0039] (d) forming a barrier metal film coating the inner surface of the connecting hole and then forming a metal film filling the connecting hole;

[0040] (e) removing a metal film formed outside the connecting hole;

[0041] (f) forming a second interlayer insulating film over the whole surface of the semiconductor substrate such that it covers the metal film formed in the connecting hole;

[0042] (g) selectively removing the second interlayer insulating film to form an interconnection groove in whose bottom the metal film formed in the connecting hole is exposed;

[0043] (h) forming a barrier metal film coating the inner surface of the interconnection groove and then forming a metal film filling the interconnection groove; and

[0044] (i) removing the metal film formed outside the interconnection groove to form a second interconnection.

[0045] In this process, the first and the second interconnections and the whole connecting hole or a part thereof may be a “metal region” to which a semiconductor device or process according to this invention can be applied. Some of the above steps of (a) to (i) may be omitted as appropriate.

[0046] A dual damascene process comprises the steps of:

[0047] (a) forming a first interconnection as a metal film on a semiconductor substrate;

[0048] (b) forming a first interlayer insulating film over the whole surface of the semiconductor substrate such that it covers the first interconnection;

[0049] (c) selectively removing the first interlayer insulating film to form a connecting hole reaching the upper surface of the first interconnection and to form an interconnection groove which is connected to the upper surface of the connecting hole;

[0050] (d) forming a barrier metal film coating the inner surfaces of the connecting hole and the interconnection groove and then forming a metal film such that it fills the connecting hole and the interconnection groove; and

[0051] (e) removing the metal film formed outside the interconnection groove.

[0052] In this process, the first and the second interconnections and the whole connecting hole or a part thereof may be a “metal region” to which a semiconductor device or process according to this invention can be applied. Some of the above steps of (a) to (e) may be omitted as appropriate.

[0053] The interconnection structure formed by the above damascene process comprises the semiconductor substrate; the first interconnection formed on the semiconductor substrate; the connecting plug connected to the first interconnection; and the second interconnection connected to connecting plug.

[0054] In this semiconductor device, the first and the second interconnections and the whole connecting hole or a part thereof may be a “metal region” to which this invention may be applied.

BRIEF DESCRIPTION OF THE DRAWINGS

[0055]FIG. 1 shows a cross section illustrating an embodiment of a semiconductor device according to this invention.

[0056]FIG. 2 shows a cross section illustrating an interconnection structure in which a void is formed due to stress migration.

[0057] FIGS. 3 to 6 are process diagrams illustrating a process for manufacturing an interconnection structure shown in FIG. 1(a).

[0058]FIG. 7 is a graph showing an example of a hysteresis curve.

[0059]FIG. 8 is a graph showing an example of a hysteresis curve.

[0060]FIG. 9 shows a method for determining a recrystallization temperature.

[0061]FIG. 10 is a drawing illustrating a principle of determination of a via chain resistance.

[0062] FIGS. 11 to 15 are graphs illustrating exemplary results of determination for a hysteresis curve.

[0063]FIG. 16 is a state diagram for an Ag—Cu two-component eutectic compound.

[0064]FIG. 17 shows a relationship between a silver content and an interconnection resistance.

[0065] In these drawings, the symbols have the following meanings; 22 a is a first interconnection; 22 b is a second interconnection; 28 is a connecting plug; 101 is an insulating film; 102 is a barrier metal film; 103 is a copper-silver alloy film; 104 is an interlayer insulating film; 105 is an interconnection groove; 106, 106 a and 106 b are barrier metal films; 107 is a seed metal film; 108 is a silver-containing film; 110 is a copper plating film; 111 is a copper-silver alloy film; 111 a is an interlayer connecting plug; 111 b is a copper-silver alloy film; 114 is a copper-silver alloy plating film; 117 is a copper plating film; 121 a is a lower interconnection; 121 b is an upper interconnection; and 122 is a void.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0066]FIG. 1 is a schematic cross section illustrating an embodiment of semiconductor device according to this invention. FIG. 1(a) shows an embodiment in which this invention is applied to a copper multilayer interconnection structure formed by a so-called dual damascene process. In an insulating film 101, a lower interconnection is formed, which consists of a barrier metal film 102 and a copper-silver alloy film 103. On the insulating film, there is formed an interlayer insulating film 104, in which an upper interconnection consisting of a barrier metal film 106 and a copper-silver alloy film 111 is formed. The upper interconnection has a T-shaped cross section. The lower part of the T-shape is an interconnection connecting plug while the upper part of the T-shape is an upper interconnection.

[0067] The term “alloy” as used herein means a product obtained by melting and coagulating two or more metal elements, and is intended to also include one containing a non-metal or semi-metal element in addition to metal elements. Depending on a mixing style of component elements, an alloy may have a state of a solid solution or intermetallic compound or a mixture thereof. Thus, the term “alloy” as used herein also includes such a product containing a component to its solid solution limit or more.

[0068] In the copper-silver alloy film 103 and the copper-silver alloy film 111, a silver content to the whole alloy film may be preferably 1 wt % or more, more preferably 2 wt % or more to more consistently prevent stress migration. The silver content to the whole alloy film is 3 wt % or more may effectively reduce a maximum hysteresis error, resulting in more stable prevention of stress migration. In particular, when this invention is applied to a process for forming metal interconnections with different interconnection widths, a silver content described above may allow a predetermined amount of silver to be consistently introduced in each interconnection, resulting in effective prevention of stress migration. There is not a particular upper limitation to a silver content to the whole alloy film, but in the light of stable formation of a copper-silver alloy film, it may be preferably 99 wt % or less, more preferably 80 wt % or less, further preferably 50 wt % or less. In the light of resistance reduction, a silver content to the whole alloy film is preferably 90 wt % or more, more preferably 95 wt % or more, further preferably 98 wt % or more.

[0069] A silver content is preferably more than a solid solution limit of silver to copper. Thus, even when a production process is changed, stress migration may be more consistently prevented. Although the reason is not fully understood, a silver content more than a solid solution limit of silver to copper would considerably reduce influence of hysteresis when the copper-silver alloy is exposed to a heat history. This will be described in Examples.

[0070] A solid solution limit of silver to copper will be described with reference to FIG. 16. As shown in FIG. 16, an Ag—Cu two-component eutectic compound has an eutectic point Y of 39.9 wt % (converted to a silver wt % to copper), an eutectic temperature of 779° C., and a maximum solid solution limit of Ag to Cu (Z; a point at which a solid solution limit of Ag to Cu is maximum) of 4.9 wt %. In FIG. 16, a solid solution limit is plotted on Curve X at a temperature and the solid solution limit is maximum at Point Z (maximum solid solution limit). In production of a semiconductor device, a maximum process temperature is about 400° C. at which a solid solution limit is about 1 wt % (converted to an Ag wt % to Cu). In this invention, a silver content to the total amount of component metals in a metal region is preferably more than a solid solution limit of silver to copper. This solid solution limit is preferably a maximum of a solid solution limit within a temperature range of, for example, 0° C. to 400° C.

[0071] There will be an embodiment in which this invention is applied to an interconnection structure formed by a damascene method. FIG. 1(b) shows an example of application of this invention to a copper multilayer interconnection structure formed by a single damascene method. The structure shown in FIG. 1(a) has an advantage that the number of production steps may be reduced by simultaneously forming an interlayer connecting plug and an interconnection. However, since the interlayer connecting plug and the interconnection are formed as an integrated part, influence of stress migration may become significant, leading to higher tendency to formation of a void in a mode shown in FIG. 2(a). On the other hand, in FIG. 1(b), although the number of production steps increases, the copper-silver alloy film is separated into two parts, i.e., the interlayer connecting plug and the interconnection via an intervening barrier metal film 106 b so that stress migration can be much more reduced. In FIG. 1(b), there is formed a lower interconnection consisting of a barrier metal film 102 and a copper-silver alloy film 103 in an insulating film 101. On the insulating film, there is formed an interlayer insulating film 104, in which are formed a via plug consisting of an interlayer connecting plug 111 a as a copper-silver alloy and a barrier metal film 106 a as well as an upper interconnection consisting of a copper-silver alloy film 111 b and a barrier metal film 106 b. In the copper-silver alloy film 103, the interlayer connecting plug 111 a and the copper-silver alloy film 111 b, a silver content to the whole alloy film may be preferably 1 wt % or more, more preferably 2 wt % or more to more consistently prevent stress migration. The silver content to the whole alloy film is 3 wt % or more may effectively reduce a maximum hysteresis error, resulting in more stable prevention of stress migration. In particular, when this invention is applied to a process for forming metal interconnections with different interconnection widths, a silver content described above may allow a predetermined amount of silver to be consistently introduced in each interconnection, resulting in effective prevention of stress migration. There is not a particular upper limitation to a silver content to the whole alloy film, but in the light of stable formation of a copper-silver alloy film, it may be preferably 99 wt % or less, more preferably 80 wt % or less, further preferably 50 wt % or less. A silver content is preferably more than a solid solution limit of silver to copper. Thus, even when a production process is changed, stress migration may be more consistently prevented.

[0072] In the interconnection structures in FIGS. 1(a) and (b), the insulating film 101 and the interlayer insulating film 104 may be made of a material selected from polyorganosiloxanes such as HSQ (hydrogensilsesquioxane), MSQ (methylsilsesquioxane) and MHSQ (methylated hydrogensilsesquioxane); aromatic organic materials such as polyaryl ethers (PAEs), divinylsiloxane-bis-benzocyclobutene (BCB) and Silk®; and materials having a low dielectric constant such as SOG (spin on glass), FOX (flowable oxide), Parylene, Saitop and BCB (BenzoCycloButene). An HSQ may have any of various structures such as a so-called ladder type and a cage type. Such an insulating film with a low dielectric constant may be used to minimize problems such as crosstalk, resulting in improved reliability in a device.

[0073] The insulating film 101 or the interlayer insulating film 104 is preferably made of a material having a substantially equal coefficient of thermal expansion to that for a component metal of the interconnection. Thus, stress migration can be effectively minimize in the connecting plug and the interconnection. In the light of these conditions, for example, when using a copper/silver-containing metal film as a metal interconnection, an interlayer insulating film is preferably made of HSQ (hydrogensilsesquioxane).

[0074] In the interconnection structure shown in FIG. 1, the barrier metal films 102 and 106 may contain a high melting metal such as Ti, W and Ta. Examples of a preferable metal for a barrier metal film include Ti, TiN, W, WN, Ta and TaN. Particularly, a tantalum barrier metal in which Ta and TaN are sequentially laminated is preferably used. The barrier metal film may be formed by an appropriate process such as sputtering and CVD. A thickness of the barrier metal film may be appropriately determined depending on some conditions such as the type of a material and an interconnection structure; for example, about 1 to 30 nm.

[0075] Though not shown in FIG. 1, a diffusion barrier may be disposed between the insulating film 101 and the interlayer insulating film 104 as appropriate. The diffusion barrier can prevent a component metal of the interconnection or plug from being diffused in the insulating film. Furthermore, it may play a role of an etching stopper when forming an interlayer connecting hole in a process for forming an interconnection structure. Examples of a metal for the diffusion barrier include SiC, SiCN, SiN, SiOF and SiON.

[0076] There will be then described a component material of a metal region such as an interconnection in this invention. FIG. 7 shows variation in an internal stress when a copper interconnection is exposed to a heat history consisting of a warming and a cooling processes. The horizontal axis is a temperature while the vertical axis is an internal stress in a copper interconnection. As shown in the figure, hysteresis occurs between a warming process (a) and a cooling process (b).

[0077] As a temperature rises from room temperature, an internal stress is changed from a tensile mode to a compression mode. Then, when a temperature exceeds a recrystallization temperature T1 for copper, plastic deformation occurs and an internal stress is kept at a relatively constant value (a). Then, as a temperature decreases, an internal stress in the interconnection is changed from a compression mode to a tensile mode and then a cooling process proceeds with a relatively constant tensile stress (b).

[0078] As show in the figure, hysteresis between the warming and the cooling processes causes migration of a component metal in the copper interconnection. That is, a larger hysteresis leads to a larger migration or deformation, which may cause disconnection due to a void which leads to a less reliable device.

[0079] In this invention, an interconnection material which can reduce such a hysteresis is selected to provide a reliable interconnection structure. FIG. 8 schematically shows a temperature-stress curve when using different interconnection materials. In this figure, a horizontal axis is a temperature while the vertical axis is an internal stress in an interconnection. FIG. 8(a) shows usual behavior of a copper interconnection, while FIG. 8(b) shows behavior of a copper-silver interconnection as a copper-silver alloy film formed according to this invention.

[0080] Here, as indicated in FIG. 8, a maximum width between Processes (a) and (b) is defined as a maximum hysteresis error. An interconnection material defined in this invention may be used to significantly reduce the maximum hysteresis error. A maximum hysteresis error is preferably 150 MPa or less, more preferably 100 MPa or less. Thus, stress migration can be consistently prevented. Furthermore, when a maximum hysteresis error is 80 MPa, stress migration may be effectively prevented even during forming a fine interconnection with a size of about 0.1 μm.

[0081] In FIG. 7, increase in a recrystallization temperature T1 gives a curve as illustrated in FIG. 8(b). It indicates that increase in a recrystallization temperature T1 in a metal region such as an interconnection is effective for reducing a maximum hysteresis error. During a warming process (a), a plateau of a stress value appears in a region in which a temperature is higher than a recrystallization temperature T1, and thus the recrystallization temperature T1 may be increased to reduce the plateau which then leads to a reduced maximum hysteresis error. That is, difference between the maximum of a process temperature (the rightmost point in the hysteresis curve in FIG. 7 or 8) and a recrystallization temperature T1 may be reduced to reduce a maximum hysteresis error. For effectively reducing a maximum hysteresis error, a recrystallization temperature of a metal region such as an interconnection is preferably 200° C. or higher, more preferably 300° C. or higher. Thus, stress migration can be consistently prevented. Since a process temperature for a semiconductor device is usually 400° C. or lower, a recrystallization temperature may be 350° C. or higher to further consistently prevent stress migration during the process.

[0082] Some embodiments of this invention will be more specifically described with reference to the drawings.

[0083] Embodiment 1

[0084] In this embodiment, this invention will be described with reference to FIG. 3 in terms of application to a copper interconnection formed by a dual damascene method.

[0085] First, on a silicon substrate (not shown) is formed an insulating film 101, on which is then a lower interconnection consisting of a barrier metal film 102 and a copper-silver alloy 103. Here, the lower interconnection can be formed by a procedure described below.

[0086] After forming an interlayer insulating film 104 on the insulating film 101, an interconnection groove 105 with a T-shaped cross section is formed by a multistep dry etching. FIG. 3(a) shows the state at the end of the step.

[0087] Then, a barrier metal film 106 is formed over the whole surface of the substrate (FIG. 3(b)). A component material of the barrier metal film 106 may contain a high melting metal such as titanium, tungsten and tantalum; for example, titanium, titanium nitride, tungsten, tungsten nitride, tantalum and tantalum nitride. It may be a multilayer film in which two or more of these are laminated.

[0088] The barrier metal film 106 may be formed by an appropriate process such as sputtering and CVD.

[0089] Then, a seed metal film 107 is formed on the barrier metal film 106 (FIG. 3(c)). The seed metal film 107 plays a role as a seed for plating growth in the upper surface and may be made of copper or a copper-silver alloy. The seed metal film 107 may be usually formed by sputtering.

[0090] In this state, the substrate surface is contacted with a silver-containing solution to form a silver-containing film 108 on the seed metal film 107 (FIG. 4(a)). Since silver has a lower deposition potential than copper, a silver film is formed as described above. A preferable example of a silver-containing solution is an aqueous solution of silver sulfate. Here, a concentration of the aqueous silver sulfate solution may be 50 ppm by weight to 30 wt % both inclusive. It is particularly desirable that the solution is saturated or supersaturated. Thus, dissolution of copper can be minimized to prevent deformation of the metal region. Such contact with a silver-containing solution deposits silver on the seed metal film 107 to form the silver-containing film 108. Specifically, since silver has lower ionization tendency than copper as a component of the seed metal film 107, a redox reaction occurs on the surface of the seed metal film 107, resulting in deposition of silver to form the silver-containing film 108.

[0091] Then, a copper plating film 110 is formed on the substrate surface by plating (FIG. 4(b)). A plating solution may be, but not limited to, an aqueous solution of copper sulfate.

[0092] Then, the product is annealed at a temperature within a range of 200° C. to 450° C. The annealing can increase the size of copper grains constituting the copper plating film 110, resulting in stable reduction of a resistance. At the same time, silver is diffused from the silver-containing film 108 to the copper plating film 110 to form a film made of a copper-silver alloy in the interconnection groove.

[0093] Subsequently, the copper plating film 110 formed outside the interconnection groove is removed by CMP (chemical mechanical polishing) to form an interconnection structure made of a copper-silver alloy (FIG. 4(c)).

[0094] According to the process described above, a convenient method can be used to consistently form an interconnection structure made of a copper-silver alloy. Furthermore, since a plating solution itself does not have to contain silver, the plating solution may be selected more freely. For example, the above process may be conducted using a plating solution having good filling properties into a narrow groove or hole to consistently form a silver-containing interconnection with a smaller width.

[0095] Embodiment 2

[0096] In this embodiment, a silver-containing plating solution is used to form an interconnection structure made as a copper-silver alloy film.

[0097] After conducting the steps of FIGS. 3(a) to (c) in embodiment 1, a copper-silver alloy plating film 114 is formed on a seed metal film 107 by plating (FIG. 5(a)). The plating solution used preferably contains copper and silver such that a proportion of silver to copper is 0.1% to 80% by weight.

[0098] This plating solution is preferably chloride-ion free. If chloride ions are present in the plating solution, silver is significantly deposited from the plating solution; specifically, deposition occurs before incorporation of silver into the film. An alloy film cannot be, therefore, consistently formed.

[0099] Examples of such a plating solution are as follows.

[0100] (i) Pyrophosphate Plating Solution

[0101] Silver ions can be added to a common copper pyrophosphate plating solution to prepare a pyrophosphate plating solution containing copper and silver. Silver may be added using, for example, a silver nitrate solution, a silver sulfate solution. A specific composition of this plating solution is, for example,

[0102] Copper: 0.01 to 5 mol/L;

[0103] Silver: 0.01 to 5 mol/L;

[0104] Pyrophosphoric acid or its salt: 0.01 to 5 mol/L;

[0105] Water.

[0106] (ii) Ethylenediamine Plating Solution

[0107] Silver ions can be added to a common copper ethylenediamine plating solution to prepare an ethylenediamine plating solution containing copper and silver. Silver may be added using, for example, a silver nitrate solution, a silver sulfate solution. A specific composition of this plating solution is, for example,

[0108] Copper: 0.01 to 5 mol/L;

[0109] Silver: 0.01 to 5 mol/L;

[0110] Ethylenediamine: 0.01 to 5 mol/L: 0.01 to 5 mol/L;

[0111] Water.

[0112] Each of these plating solutions may contain one or more additives as appropriate. For example, it can contain a surfactant such as polyethylene glycol, polypropylene glycol, quaternary ammonium salts and gelatin. These additives may equalize a copper crystal size and give a plating film with a uniform thickness. The surfactant may be generally added in an amount of, but not limited to, 1 to 1000 ppm by weight to the total amount of the plating solution.

[0113] The plating solution is preferably substantially chloride-free. Specifically, it is preferable that a chloride concentration is 0.01 mg/L or less. Thus, deposition of silver due to a reaction with chloride may be effectively prevented so that a metal film made of a copper-silver alloy may be consistently formed.

[0114] Plating conditions may be appropriately determined. They may be, for example, as follows.

[0115] Current density: 0.1 to 100 A/dm2;

[0116] Solution temperature: 10 to 80° C.

[0117] A current applied during plating may be either direct current or pulse current.

[0118] After forming a copper-silver alloy plating film 114 as described above, the substrate surface is polished by CMP to form an upper interconnection consisting of a barrier metal film 106 and a copper-silver alloy film 111.

[0119] According to this embodiment, a convenient method can be used to consistently form an interconnection structure made of a copper-silver alloy. A metal composition in the interconnection structure may be made uniform.

[0120] Embodiment 3

[0121] While one plating solution containing copper and silver has been used in embodiment 2, two plating solutions are used in this embodiment.

[0122] After conducting the steps of FIGS. 3(a) to (c) in embodiment 1, a copper plating film 114 is formed on a seed film 107 by plating (FIG. 6(a)). Here, a plating solution used may be a common copper plating solution, but preferably a chloride-free plating solution. For example, it may be preferably a common copper sulfate plating solution from which chloride ions have been removed, a copper pyrophosphate plating solution or a copper ethylenediamine plating solution. It can prevent silver from reacting with chloride ions in a copper plating film 117 in the subsequent step, to consistently give a metal film made of a copper-silver alloy.

[0123] Then, a copper-silver alloy plating film 114 is formed on the copper plating film 117 by plating (FIG. 6(b)). Here, it is preferable to use a chloride-ion free plating solution; specifically, a pyrophosphate plating solution or an ethylenediamine solution described in embodiment 2.

[0124] Then, the product is annealed at a temperature within a range of 200° C. to 450° C. By the annealing, silver is diffused from the copper-silver alloy plating film 114 to the copper plating film 117 to form a film made of a copper-silver alloy with a relatively uniform composition in the interconnection groove. Furthermore, the size of metal grains constituting these films can be increased, resulting in stable reduction of a resistance.

[0125] Then, the whole substrate surface is made flat by CMP to form an interconnection structure consisting of the barrier metal film 106 and the copper-silver alloy film 111 (FIG. 6(c)).

[0126] According to this embodiment, a convenient method can be used to consistently form an interconnection structure made of a copper-silver alloy. A metal composition in the interconnection structure may be made uniform. In particular, since two plating solutions are used, a plating solution having good filling properties may be used to fill a narrow concave and then a silver-containing plating solution may be used to consistently form a copper-silver alloy film in an interconnection groove with a narrow width and thus to suitably form a reliable interconnection structure.

EXAMPLES Example 1

[0127] Metal interconnections in FIG. 17 were formed by a damascene process. All of these interconnections had dimensions of 0.1 to 0.5 μm (width)×0.3 μm (thickness)×49 mm (length), and silver contents in an interconnection metal were 0, 1.5 and 2.0 wt %. The interconnection was formed by plating using a chloride-ion free plating solution. For the interconnections thus formed, an interconnection resistance was determined and the results shown in FIG. 17 were obtained. This figure shows that resistance increase was inhibited in the interconnection structures in which a silver content to the total amount of the component metals in an interconnection is 1.5 wt % or more. In a copper-silver alloy, a relationship between atom % and wt % is such that, for example, a silver content of 0.9 atom % corresponds to 1.5 wt %.

Example 2

[0128] In this example, a two-layer interconnection structure shown in FIG. 10 was formed to test an yield. This two-layer interconnection structure is called a via chain, in which first interconnections 22 a are formed in parallel and second interconnections 22 b perpendicular to them are formed. The width of the interconnections should be wide such as 5 micron to test the stress-migration reliability effectively. These interconnections are connected to each other via 20,000 connecting plugs 28. In this figure, a semiconductor substrate and an interlayer insulating film are omitted. A given voltage can be applied to the ends of the via chain to measure an electric resistance through 10,000 first interconnections 22 a, 10,000 second interconnections 22 b and 20,000 connecting plugs 28. The resistance is called a chain resistance, which is an effective indicator to determine the quality of the via connection. While the interconnection structure is placed under given thermal environment, variation in a chain resistance may be determined to suitably evaluate its stress-migration resistance.

TABLE 1
Cu/Ag Yield
ratio Interconnection (relative
Sample (by weight) forming process value)
b0 100/0 Plating in a copper 100
sulfate bath
b1 100/0 Plating in a copper 42 to 60
sulfate bath
b2  99.95/0.05 Plating in a silver- 60 to 81
containing
ethylenediamine bath
b3  98/2 Plating in a silver-  88 to 100
containing
ethylenediamine bath

[0129] After preparing the samples, they are left at 150° C. for 500 hours and are then subject to an yield test. As a reference, a via chain yield was determined for a two-layer interconnection structure prepared as described above which was left at room temperature for 500 hours (b0).

[0130] Table 1 shows relative resistances for samples b1 to b3 when a resistance for the reference sample b0 is 100%. In this table, a resistance is described as a range from the results obtained by evaluating a plurality of the samples prepared. A higher value indicates higher stress-migration resistance.

[0131] From the results in this example, stress migration can be effectively prevented by using an interconnection structure made of a silver-copper alloy, particularly an interconnection structure in which a silver content to the total amount of component metals in the interconnection is more than 1 wt %.

Example 3

[0132] For evaluating material properties for the samples in Examples 1 and 2, hysteresis properties and recrystallization temperatures were determined.

[0133] Samples were prepared as follows. On a silicon substrate was deposited a silicon oxide film to 500 nm by plasma CVD, on which was then deposited a Ta film to 50 nm. Then, on the upper surface was deposited a copper plating seed film to 100 to 200 nm by sputtering, on which was then deposited a copper or copper-silver alloy film to 600 to 700 nm using a given plating solution. A composition of the copper or copper-silver alloy film was described in Table 2, in which plating solution 1 contains chloride ions while plating solution 2 does not.

[0134] The samples thus prepared were exposed to thermal cycles of 25° C. to 400° C. In this heat history, a warming rate was 10° C./min in the warming process while a cooling rate was about 10° C./min in the cooling cycle. The thermal cycle was repeated twice and hysteresis properties were evaluated during the second cycle because it was thought to be proper to evaluate hysteresis properties during the second thermal cycle for exactly determining hysteresis properties in the light of the fact that during the first thermal cycle, grains constituting the film grow and that it is important to evaluate stability under practical working conditions or under heating during a process. A recrystallization temperature was also determined during the second thermal cycle.

[0135] Hysteresis properties were evaluated by calculating an internal stress in a plating film from a measured bending of a substrate. A substrate bending was calculated by determining a reflection angle of an irradiated laser beam on the substrate surface. A maximum hysteresis error and a recrystallization temperature were determined from the hysteresis properties thus obtained (a temperature-stress curve during the second thermal cycle). The results are shown in Table 2. Hysteresis curves for some samples are shown in FIGS. 11 to 15, where samples c1, c2, c4, c5 and c6 correspond to FIGS. 11, 14, 12, 13 and 15, respectively.

TABLE 2
Cu/Ag Maximum Recrystal
Composition hysteresis lization
ratio (by Interconnection error temperature
Sample weight) forming process (MPa) (° C.)
c1  100/0 Plating in a copper 210 150
sulfate bath
c2  100/0 Plating in an 160 170
ethylenediamine bath
c3   99/1 Plating in a silver- 150 190
containing
ethylenediamine bath
(Plating solution 1)
c4 98.5/1.5 Plating in a silver- 120 220
containing
ethylenediamine bath
(Plating solution 1)
c5 97.5/2.5 Plating in a silver- 100 250
containing
ethylenediamine bath
(Plating solution 1)
c6 91.7/8.3 Plating in a silver- 80 240
containing
ethylenediamine bath
(Plating solution 2)

[0136] As understood from the above results, when a silver content to the total amount of component metals in an interconnection is more than 1 wt %, a recrystallization temperature is increased and a maximum hysteresis error is significantly reduced. Good properties of b3 in Example 2 may be obtained because of such improvement in hysteresis properties.

[0137] As described above, according to this invention, a reliable semiconductor device having good properties such as stress-migration resistance can be provided because a metal region such as an interconnection structure is made of (i) a metal containing silver at a particular amount, (ii) a metal whose maximum hysteresis error in a temperature-stress curve for a metal region is within a particular range, or (iii) a metal whose recrystallization temperature is within a particular range.

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US7205667 *23 Nov 200417 Abr 2007Fujitsu LimitedSemiconductor device having copper wiring
US7238617 *30 Dic 20043 Jul 2007Dongbu Electronics Co., Ltd.Method for fabricating semiconductor device to minimize terminal effect in ECP process
US7312164 *23 Mar 200525 Dic 2007Micron Technology, Inc.Selective passivation of exposed silicon
US7335596 *22 Jun 200526 Feb 2008Kobe Steel, Ltd.Method for fabricating copper-based interconnections for semiconductor device
US78719247 Mar 200718 Ene 2011Fujitsu Semiconductor LimitedSemiconductor device having copper wiring
Clasificaciones
Clasificación de EE.UU.257/750, 438/686, 257/E21.576, 257/E23.145, 257/E21.175, 438/687, 438/650, 257/E21.174, 257/E21.585, 257/762
Clasificación internacionalH01L23/522, H01L21/768, C25D7/12, H01L23/532, H01L21/288
Clasificación cooperativaH01L21/76877, H01L23/53233, H01L21/288, H01L21/2885, H01L23/5226, H01L21/76843, H01L21/76807, H01L23/53238
Clasificación europeaH01L21/288, H01L21/288E, H01L21/768C3B, H01L23/532M1C4, H01L23/532M1C2, H01L21/768C4