US20030205484A1

US20030205484A1 - Electrochemical/ mechanical polishing

Info

Publication number: US20030205484A1
Application number: US10/138,281
Authority: US
Inventors: Madhav Datta
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2002-05-02
Filing date: 2002-05-02
Publication date: 2003-11-06

Abstract

An electrochemical/mechanical polishing apparatus and method to planarize surfaces of a semiconductor device without damaging relatively soft dielectric materials. The electrochemical/mechanical polishing apparatus comprises a substrate chuck, nozzle assembly, power supply, and sweep mechanism. The substrate chuck receives a substrate to be processed. The nozzle assembly includes a nozzle plate having a plurality of nozzles to dispense an electrolyte solution. A pad is secured to the nozzle plate. The power supply provides a positive electric potential to an electrically conductive layer of the substrate and a negative electric potential to the nozzle plate. The sweep mechanism scans the nozzle assembly along the surface of the substrate, and the pad is positioned sufficiently close to the surface of the substrate to disturb an electrolyte/wafer boundary layer.

Description

FIELD OF THE INVENTION

This application relates to fabrication of semiconductor devices and more particularly to a fabrication process of a semiconductor device including electrochemical/mechanical polishing for planarizing surfaces.

BACKGROUND OF THE INVENTION

During the past decades, the semiconductor industry has increased the power of semiconductor devices in accordance with Moore's law, which predicts that the power of semiconductor devices will double every 18 months. This increase in the power of semiconductor devices has been achieved in part by decreasing feature size of the semiconductor devices. The feature size of semiconductor devices has gone from 0.25 microns to 0.18 microns, and now to 0.13 microns. Undoubtedly, this trend toward smaller semiconductor devices is likely to proceed well beyond the sub- 0.13 micron stage.

However, one potential limiting factor to developing more powerful semiconductor devices is the increasing signal delays at the interconnections (the lines of conductors which connect element of a single semiconductor device and/or connect any number of semiconductor devices together). As the feature size of semiconductor devices has decreased, the density of interconnections on the devices has increased. However, the closer proximity of interconnections increases the line-to-line capacitance of the interconnections, which results in greater signal delay at the interconnections. In general, interconnection delays have been found to increase with the square of the reduction in feature size. In contrast, gate delays (i.e., delay at the gates or mesas of semiconductor devices) have been found to increase linearly with the reduction in feature size.

One conventional approach to compensate for this increase in interconnection delay has been to add more layers of metal. However, this approach has the disadvantage of increasing production costs associated with forming the additional layers of metal. Furthermore, these additional layers of metal generate additional heat, which can adversely affect chip performance and reliability. Consequently, the semiconductor industry has started to use copper rather than aluminum to form the metal interconnections. One advantage of copper is that it has greater electrical conductivity than aluminum. Also, copper is less resistant to electromigration than aluminum. Copper can be formed on a wafer using an electroplating process. One of the limitations of current plating techniques for copper metallization is its inability to provide a flat, planarized surface. While filling and planarization of small features is achieved in so called superfilling baths, conformal plating in large features leaves an uneven plated surface even after overburden plating.

Chemical mechanical polishing (CMP) may be used to planarize surfaces of an integrated circuit. CMP is a process utilizing slurries, pads, and pressure to polish the surface of the integrated circuit. However, low-k dielectrics, which exhibit relatively low mechanical strength, are typically used in conjunction with copper to further minimize line-to-line capacitance of the interconnections. As such, the application of low-k dielectrics as an insulating material necessitate the use of low pressure CMP (soft CMP), making the CMP process an extremely low throughput process. For ultra low-k (ULK) dielectric materials, even soft CMP leads to deformation and delamination at the copper/ULK dielectric interface due to excessive stresses placed upon the ULK dielectric materials. It is also difficult to control CMP due to the insensitivity to the different polish rates of copper and dielectric materials. Furthermore, CMP typically causes defects that can adversely impact final yield: dielectric loss, erosion, dishing, and copper lead breakdown. In certain cases, the slurry used in CMP can cause scratches and residue particles. Scratches can also occur as a result broken diamond tips becoming embedded in the polishing pad during pad conditioning.

Electrochemical polishing is an alternative method to planarize surfaces of an integrated circuit. Electrochemical polishing is a process of polishing metal surfaces by applying an electric current through an electrolytic bath and may be viewed as the reverse of electroplating. Among the advantages is that the copper film is planarized without physical contact and the rate of material removal is much higher than CMP. However, there is a problem of maintaining electrical contact due to the highly viscous electrolytic baths (e.g., 85% phosphoric acid in water). While these baths are effective in achieving adequate polishing and planarization rates, it is difficult to remove defect causing bubbles and maintain an adequate flow of fresh electrolytic fluid. During electropolishing, hydrogen gas is generally formed at the cathode. The hydrogen gas can become entrained in the electrolyte, complicating tool design and presenting a potential safety hazard. In addition, the high electrical resistivity of the bath results in large power requirements and the need to remove the large amount of heat generated from the large power inputs.

Thus, there is a need for an apparatus and method to planarize a metal film without damaging relatively soft dielectric materials.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view of an electrochemical/mechanical polishing apparatus in accordance with one embodiment of the invention. [0008]
FIG. 2 is a bottom perspective view of a lid of the electrochemical/mechanical polishing apparatus shown in FIG. 1. [0009]
FIG. 3 is a perspective view of a nozzle assembly and sweep mechanism of the electrochemical/mechanical polishing apparatus shown in FIG. 1. [0010]
FIG. 4 is a schematic illustration shown in bottom view of a wafer holder and the nozzle assembly of the electrochemical/mechanical polishing apparatus shown in FIG. 1. [0011]
FIG. 5 is a schematic illustration shown in side view of the wafer holder and the nozzle assembly of the electrochemical/mechanical polishing apparatus shown in FIG. 1. [0012]
FIG. 6 is a schematic illustration shown in side view of the nozzle assembly shown in FIG. 1. [0013]
FIG. 7 is a schematic illustration shown in side view of a pad and nozzle plate of the nozzle assembly shown in FIG. 6. [0014]
FIG. 8 is a schematic illustration shown in top view of the pad shown in FIG. 7. [0015]
FIG. 9A is a cross-sectional depiction of an exemplary integrated circuit having a patterned dielectric layer. [0016]
FIG. 9B is a cross-sectional depiction of the structure of FIG. 6A after a seed layer has been formed on the patterned dielectric layer. [0017]
FIG. 9C is a cross-sectional depiction of the structure of FIG. 9B after a conductive layer has been formed over the seed layer. [0018]
FIG. 9D is a cross sectional depiction of the structure of FIG. 6C after electrochemical/mechanical polishing is partially completed. [0019]
FIG. 9E is a cross sectional depiction of the structure of FIG. 6D after electrochemical/mechanical polishing has been completed. [0020]
FIG. 10 is a flowchart illustrating a process for fabricating an exemplary semiconductor device in accordance with the process illustrated in FIGS. [0021] 9A-9E.

DETAILED DESCRIPTION OF THE INVENTION

Detailed descriptions are provided herein. It is to be understood, however, that the present invention may be embodied in various forms. Therefore, specific details disclosed herein are not to be interpreted as limiting, but rather as a basis for the claims and as a representative for teaching one skilled in the art to employ the invention in virtually any appropriately detailed system, structure or manner. [0022]
This invention enables electroplanarization by electrochemical/mechanical polishing such that features filled with metal can be planarized to produce a substantially flat substrate in which embedded metal remains in a dielectric structure to produce a damascene structure. An initial operation in this process involves the formation of recessed trenches, via holes, pad structures, or the like into the dielectric structure. The opening are then filled with a metal by a conventional process such as electroplating, sputtering, or vapor deposition. A minimum amount of metal is added to the substrate to completely fill the feature, but often some degree of additional metal is deposited to help prepare the surface for subsequent planarization by electrochemical/mechanical polishing. [0023]
FIGS. [0024] 1-8 depict an exemplary electrochemical/mechanical polishing apparatus 20. As shown in FIG. 1, the electrochemical/mechanical polishing apparatus 20 includes a rectangular chamber 22 which contains a nozzle assembly 24 and a sweep mechanism 26. An electrolyte reservoir 28, filter 30, filter pump 32, and nozzle pump 34 supply and clean an electrolyte solution for the polishing process. The filter pump 32 draws the electrolyte solution draining from the rectangular chamber 22 through the filter 30 to remove anodic and cathodic byproducts which are formed during electrochemical/mechanical polishing. The nozzle pump 34 draws from the reservoir 28 and pumps the electrolyte solution through flexible hoses 36 to the nozzle assembly 24. An electrical cabinet 37, which contains electronic controls 38 and a power supply 39, is located above the chamber 22.
The [0025] rectangular chamber 22 has a top opening 40 which is covered by a lid 42 and an “O” ring provides a fluid tight seal. As shown in FIG. 2, the lid 42 of the chamber 22 is fitted with a circular depression 44 to receive a wafer 46 such that the lid 42 also serves as a substrate chuck 48. A transfer arm 50 loads the wafer 46 onto the substrate chuck 48 wherein a backside of the wafer 46 is supported by the substrate chuck 48 and a frontside (circuit side) of the wafer 46 faces downwardly. The transfer arm 50 can obtain the wafer 46 from a carrier or from a previous processing station or processing apparatus. Clips 52 secure the wafer 46 in the circular depression 44 and also make electrical connection to an electrically conductive film on the surface of the wafer 46. The electrical connections, which are conventional, are not explicitly shown. After the wafer 46 is loaded into the substrate chuck 48, the lid 42 is secured over the top opening 40 and the rectangular chamber 22 is sealed.
Referring back to FIG. 1, the [0026] rectangular chamber 22 includes a temperature controller 54 having heating 56 and cooling elements 58 to maintain the electrolyte solution at the desired temperature. The temperature of the electrolyte solution may be monitored by a temperature sensor 60. The temperature sensor 60 sends a heating signal to activate the heating elements 56 when the electrolyte solution is below the target temperature and sends a cooling signal to activate the cooling elements 58 when the electrolyte solution is above the target temperature.
FIG. 3 illustrates the [0027] nozzle assembly 24 in greater detail. The nozzle assembly 24 is fixed to a bracket 62, and the bracket 62 moves axially by a sweep mechanism 64. The sweep mechanism 64 includes a threaded rod 66 which is rotated by a drive 68. The nozzle assembly 24 may be moved by any other conventional mechanism such as an X-Z table. The sweep mechanism 64 slowly sweeps the nozzle assembly 24 as indicated by the straight directional arrow. Scanning may be either back-and-forth or uni-directional. The scan speed is adjustable to control the amount of metal film removal. Typically, the scan rate may range from 0.05 to 0.5 cm/s.
Referring to FIGS. [0028] 3-8, the nozzle assembly 24 has an elongated body 70 with a chamber 72 for receiving the electrolyte solution. A nozzle plate 74, which serves the function of a linear cathode, is mounted on the elongated body 70. The nozzle plate 74 contains two parallel central rows of nozzles 76 and may be formed from stainless steel or other electrically conductive material. A pad 78, which is preferably a soft and porous material, is attached to the nozzle plate 74 and includes apertures 80 respective to each of the nozzles 76. The nozzle pump 34 pumps the electrolyte solution into the chamber 72 via fittings 82 which are connected to the flexible hoses 36. The nozzle pump 34 creates adequate pressure within the chamber 72 such that the electrolyte solution spurts out through the nozzle 76, creating an elongated jet of electrolyte solution. In the exemplary embodiment, the nozzle plate 74 is about 25 mm wide and about 325 mm long to enable it to scan over wafer 46 which is 300 mm in diameter. Of course, the dimensions of the nozzle plate may be altered for processing wafers having a diameter other than 300 mm. As well as creating the linear electrolyte jet, the nozzle plate 74 acts as the cathode and is electrically connected to the power supply 39. The pad 78 further includes channels 84 to evacuate the spent electrolyte solution away from the nozzle assembly 24, wherein the spent electrolyte solution is returned to the reservoir 28 for recirculation. It is also noted that the pad 78 becomes saturated with the electrolyte solution because of its porous characteristics.
When the [0029] lid 42 is secured onto the rectangular chamber 22, the nozzle assembly 24 is positioned below the wafer 46 to form an interelectrode gap. The interelectrode gap may be defined as the spacing between the upper surface of the nozzle plate 74 and the surface of the wafer 46. The interelectrode gap may be adjusted by a mechanism (not shown) which controls the vertical position of the nozzle assembly 24. Typically, the interelectrode gap may be set between 1 and 5 millimeters. The pad 78 should be sufficiently close to the surface of the wafer 46 to disturb the wafer/electrolyte boundary layer. The wafer/electrolyte boundary layer is defined as a stagnant zone near the surface of the wafer 46 where the transfer of species such as cupric ions is limited. In other words, mechanical action of the pad 78 modifies the portion of the electrolyte solution located near the surface of the wafer 46 such that rate of replacing the spent electrolyte solution with fresh electrolyte solution is greater at the peaks than at the valleys of the surface of the wafer 46. As such, the surface of the wafer 46 is planarized because the rate of metal removal is greater at the peaks than at the valleys. It is contemplated that the pad gap, that is, the gap between the surface of the pad 78 and the surface of the wafer 46, should be adjusted so that the pad 78 barely contacts the surface of the wafer 46. For a given interelectrode gap, the pad gap may be adjusted by selecting a proper pad thickness. In some applications, particularly dielectric materials exhibiting relatively high strength, the nozzle assembly 24 may be adjusted to a position where the pad 78 contacts the surface of the wafer 46.
During electrochemcial/mechanical polishing, the [0030] nozzle assembly 24 scans from one end of the wafer 46 to the other, and the nozzle pump 34 sends the electrolyte solution through the nozzles 76. The power supply 39 provides a positive electric potential to the wafer 46 and a negative electric potential to the nozzle plate 74. Voltage can be applied either as a steady DC (direct current) or as PC (pulsating current). The electrolyte jet completely fills the interelectrode gap and then runs down over the nozzle assembly 24. Eletrochemical/mechanical polishing only occurs where the electrolyte solution impinges over the nozzle plate 74. The flow rate is typically between 1 and 4 gallons per minute. In addition to the nozzle pump 34, a liquid mass flow controller (LMFC) 86 is provided to control the flow of electrolyte solution into the chamber 72 of the nozzle assembly 24.
The use of a linear electrode has several advantages over a flat or surface electrode. For example, stray currents can only propagate in one direction along a liner electrode as opposed to two directions for a flat surface electrode. As such, electrochemical/mechanical polishing is more uniform because edge effects are eliminated by the area scan of the electrode. Another advantage is that a thin linear electrode has a small surface area so as to reduce the total current required for the electrochemical/mechanical apparatus while maintaining a relatively high local current density. This is particularly important when processing wafers greater than 8 inches which require large power requirements and where large amounts of heat are generated for apparatuses utilizing a non linear electrode. Another advantage for applications which require a small interelectrode gap or a close tolerance is that it is less costly to machine several straight edges than a plane surface. A related advantage is that it is easier to obtain a more uniform flow and current. [0031]
By providing [0032] multiple hoses 36 and a regular, symmetrical pattern of apertures, the flow rate is uniform for each nozzle 76 along the entire length of the nozzle plate 74. Moreover, the removal of heat is more effective with the linear electrode than with flat or surface electrodes due to the relatively short flow distance such that the electrolyte solution does not have the opportunity to become hot. Non-uniform polishing caused by heating of the electrolyte solution, a problem with some prior art polishing apparatuses, is not a problem with the electrochemical/mechanical polishing apparatus 20 due to the reduced heating. Furthermore, any non-uniformities across the width of the nozzle plate 74 are cancelled by the scanning.
FIGS. [0033] 9A-9E illustrates cross-sectional views of an exemplary semiconductor device 100 during various stages of a process in accordance with the invention. Generally, the exemplary process may be employed with any type of substrate surface on which features or “recesses” are to be filled with a conductive material. For example, the substrate may comprise a semiconductor material such as silicon, or insulating materials such as polyimide, quartz, ceramic, or the like. The electrochemical/mechanical apparatus is particularly suited for the planarization of conductive layers deposited on partially fabricated integrated circuits. In one embodiment, the planarization is applied during a damacene process for forming inlaid conductive structures such as pads or interconnects in a patterned dielectric layer of a partially fabricated integrated circuit.
FIG. 9A is a cross-sectional view of the [0034] exemplary semiconductor device 100 at a partially fabricated state. The exemplary semiconductor device 100 comprises a semiconductor wafer 102 such as silicon having a patterned and etched layer of ULK dielectric material to serves as an interlayer dielectric (ILD) 104. The patterned ILD 104 includes trenches 105. One example of a typical ULK dielectric material is xerogel. Xerogel is a porous silica which has several characteristics that make it an attractive interlayer dielectric (ILD). Xerogel has high thermal stability and a low thermal expansion coefficient because it is composed of a highly porous network of SiO₂. It can be produced with a wide range of dielectric constants (1.3-3.0) by tuning the porosity during the deposition process. The porosity also controls the mechanical properties of the xerogel, and thus, can be optimized for damascene processing. Of course, dielectrics other than xerogel may be used to form the ILD such as SILK™ dielectric resins produced by Dow Chemical Company. Other types of low dielectric materials include oxides, aluminum nitrides, paraffins, organic and inorganic aerogels, and the like.
FIG. 9B is a cross-sectional view of the [0035] exemplary semiconductor device 100 at a subsequent step. In this subsequent step, a barrier layer 106 such as Ti/TiN is deposited over the surface of the patterned ILD 104 and a copper seed layer 108 is deposited over the barrier layer 106 by physical vapor deposition.
FIG. 9C is a cross-sectional view of the [0036] exemplary semiconductor device 100 at a subsequent step. In this subsequent step, a layer of conductive material is formed over the patterned ILD 104. The layer of conductive material may be formed by various techniques. In the exemplary embodiment, a copper layer 110 is formed over the seed layer 106 by electroplating. The copper layer 110 is sufficiently thick to fill the trenches and cover the patterned ILD 104. As an alternative to electroplating, other suitable conformal processes such as chemical vapor deposition, sputtering, evaporation, and the like may be used to form the layer of conductive material.
FIGS. 9D and 9E are cross-sectional views of the [0037] exemplary semiconductor 100 device at a subsequent step. The exemplary semiconductor 100 is midway through the electrochemical/mechanical polishing in FIG. 9D wherein a portion of the overburden copper 110 has been removed. FIG. 9E illustrates the exemplary semiconductor device 100 after completion of the electrochemical/mechanical polishing. For removing copper, the electrolyte solution comprises phosphoric acid (10-14M) and a slurry material. The temperature of the electrolyte solution is maintained at the target temperature by the temperature controller 54. For the exemplary semiconductor device 100, the electrolyte solution may be maintained at about 25° C. The transfer arm 50 transfers the wafer 46 from a loading carrier to the substrate chuck 48, and the clips 52 secure the wafer 46 onto the substrate chuck 48. In addition, electrical contact between the power supply 39 and copper layer 110 is formed via the clips 52. The lid 42 is secured over the top opening 40, and the chamber 28 is sealed. The interelectrode gap is set to sufficiently disturb the wafer/electrolyte boundary layer, and the nozzle pump 34 is activated to pump the electrolyte solution into the nozzle assembly 24 wherein jets of electrolyte solution impinge onto the surface of the wafer 46. The power supply 39 is activated, and the wafer 46 acts as an anode and the nozzle plate 74 acts as a cathode such that copper removal is localized at the nozzle plate/wafer interface. Typically, the cell voltage should range from about 515 volts. Depending on the desired removal rate and polishing uniformity, the sweep mechanism 64 is activated to scan the nozzle assembly 24 at approximately 0.5 to 0.5 cm/s. The spent electrolyte solution is evacuated through the channels 84 of the pad 78 and is returned to the reservoir 28 for filtration and recirculation. Typically, the wafer 46 is electrochemically/mechanically polished to the extent that an upper surface of the copper layer 110 is coplanar with an upper surface of the ULK dielectric material 104. When the desired amount of copper is removed, the power supply 39, nozzle pump 34, and sweep mechanism 64 are switched off. The lid 42 is removed from the rectangular chamber 22, and the transfer arm 50 unloads the wafer 46 from the substrate chuck 48 and transfers the wafer 46 to an unloading carrier. The process described above is repeated for the remaining wafers in the unloading carrier.
FIG. 10 is a flowchart [0038] 150 illustrating the process of forming inlaid conductive structures such as pads or interconnects in a patterned dielectric layer for a semiconductor device in accordance with the various stages shown in FIGS. 9A-9E. As described above, the process comprises: depositing and patterning a dielectric layer on the substrate (Block 152); forming a barrier layer and a seed layer on the dielectric layer (Block 154); forming a conductive layer on the seed layer (Block 156); and electrochemical/mechanical polishing the surface of the substrate (Block 158).
In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive case. [0039]

Claims

What is claimed is:

1. An apparatus comprising:

a substrate chuck to receive a substrate;

a nozzle assembly comprising:

a nozzle plate having a plurality of nozzles to dispense an electrolyte solution; and

a pad secured to the nozzle plate;

a power supply to provide a positive electric potential to an electrically conductive layer of the substrate and to provide a negative electric potential to the nozzle plate; and

a sweep mechanism to scan the nozzle assembly along the surface of the substrate, the pad positioned sufficiently close to the surface of the substrate to disturb an electrolyte/wafer boundary layer.

2. The apparatus of claim 1, wherein the pad is relatively soft and porous.

3. The apparatus of claim 1, wherein the nozzle assembly further comprises an elongated body having a chamber to receive the electrolyte solution, and wherein the nozzle plate is disposed on the elongated body.

4. The apparatus of claim 1, wherein the nozzle plate comprises stainless steel.

5. The apparatus of claim 1, wherein the nozzle plate is a linear cathode and the substrate is an anode to electrochemically/mechanically remove a portion of the electrically conductive layer from the substrate.

6. The apparatus of claim 1, wherein the substrate is a semiconductor wafer.

7. The apparatus of claim 1, further comprising:

a chamber having a top opening, the chamber providing a reservoir for the electrolyte solution, the chamber containing the nozzle assembly and the sweep mechanism;

a lid to cover the top opening of the chamber, the substrate chuck disposed on an interior surface of the lid to downwardly face a frontside of the wafer when the lid is secured to the chamber, and the nozzle assembly located below the substrate to form an interlectrode gap, the electrolyte solution filling the interelectrode gap, the electrochemical/mechanical polishing occurring where the electrolyte solution impinges over the nozzle plate.

8. The apparatus of claim 7, further comprising:

a nozzle pump to draw the electrolyte solution from the reservoir and to pump the electrolyte solution to the nozzle assembly.

9. A method comprising:

providing a positive electric potential to an electrically conductive layer of a substrate;

providing a negative electric potential to a linear nozzle plate;

directing a jet of electrolyte solution from the linear nozzle plate to the electrically conductive layer of the substrate;

providing a pad on the linear nozzle plate to disturb an electrolyte/substrate boundary layer; and

scanning the linear nozzle plate along the surface of the electrically conductive layer of the substrate to uniformly electrochemically/mechanically polish the electrically conductive layer.

10. The method of claim 9, maintaining an interelectrode gap during said scanning, the interelectrode gap being the distance between the surface of the substrate and the surface of the linear nozzle plate.

11. The method of claim 9, further comprising:

forming the pad from a relatively soft and porous material to saturate the pad with the electrolyte solution.

12. The method of claim 9, further comprising:

providing a chamber having a reservoir to contain the electrolyte solution and the linear nozzle plate;

sealing the chamber with a lid, the lid having a substrate chuck to receive the substrate, the conductive layer of the substrate facing downwardly when the chamber is sealed with the lid, the linear nozzle plate disposed below the wafer;

channeling spent electrolyte solution away from the pad;

returning the spent electrolyte solution to the reservoir; and

recirculating the spent electrolyte with the electrolyte solution.

13. The method of claim 12, further comprising:

maintaining the electrolyte solution at a target temperature.

14. The method of claim 9, wherein said scanning the linear nozzle plate further comprises sweeping the linear nozzle plate from one end of the substrate to an opposite end of the substrate.

15. The method of claim 9 wherein said directing a jet of electrolyte solution from the linear nozzle plate to the electrically conductive layer of the substrate further comprises:

coupling the linear nozzle plate with a chamber;

pumping the electrolyte solution from the reservoir to the chamber to pressurize the electrolyte solution; and

impinging jets of electrolyte solution onto the surface of the wafer.

16. The method of claim 9, wherein said providing a pad on the linear nozzle plate planarizes the surface of the wafer by establishing a metal removal rate which is greater at peaks of the surface of the substrate than at valleys of the surface of the substrate.

17. A method comprising:

forming a dielectric layer on a substrate;

patterning and etching the dielectric layer to form trenches;

covering the dielectric layer with an electrically conductive layer;

electrochemically/mechanically polishing the surface of the substrate, said electrochemically/mechanically polishing comprising:

scanning the linear nozzle plate along the surface of the electrically conductive layer to uniformly electrochemically/mechanically polish the electrically conductive layer.

18. The method of claim 17, further comprising:

providing a positive electric potential to the electrically conductive layer; and

providing a negative electric potential to a linear nozzle plate.

19. The method of claim 17, wherein the electrically conductive layer is electrochemically/mechanically polished to form interconnect lines for a semiconductor device, and wherein the substrate is a silicon wafer.

20. The method of claim 17, wherein the surface of the substrate is electrochemically/mechanically polished to the extent that a surface of the conductive layer is coplanar with a surface of the dielectric layer.

21. The method of claim 17, wherein the dielectric layer is an ULK dielectric material.

22. The method of claim 17, wherein the electrically conductive layer is copper.

23. The method of claim 17, further comprising:

maintaining an interelectrode gap during said scanning, the interelectrode gap being the distance between the surface of the substrate and a surface of the linear nozzle plate.

24. An apparatus comprising:

a substrate;

a dielectic layer on the substrate, the dielectric layer having trenches;

interconnect lines within the trenches, the interconnect lines having an electrically conductive material, the electrically conductive material and the dielectric layer partially removed by an electrochemical/mechanical polishing apparatus to form an upper surface of the dielectric layer which is coplanar with an upper surface of the electrically conductive material.

25. The apparatus of claim 24, wherein the electrochemical/mechanical polishing apparatus comprises:

a linear nozzle plate to dispense an electrolyte solution onto the substrate;

a pad secured to the linear nozzle plate;

a power supply to negatively bias the linear nozzle plate and to positively bias the electrically conductive bias; and

a sweep mechanism to scan the linear nozzle plate along the surface of the substrate, the pad positioned sufficiently close to the surface of the substrate to disturb an electrolyte/wafer boundary layer.

26. The apparatus of claim 25, wherein the substrate is a silicon wafer to form a semiconductor device.

27. The apparatus of claim 26, wherein the semiconductor device is an integrated circuit.

28. The apparatus of claim 26, wherein the dielectric layer is an ULK dielectric material, and wherein the electrically conductive material is copper.