US20040008561A1 - Stacked gate flash memory cell with reduced distrub conditions - Google Patents
Stacked gate flash memory cell with reduced distrub conditions Download PDFInfo
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- US20040008561A1 US20040008561A1 US10/616,751 US61675103A US2004008561A1 US 20040008561 A1 US20040008561 A1 US 20040008561A1 US 61675103 A US61675103 A US 61675103A US 2004008561 A1 US2004008561 A1 US 2004008561A1
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- 230000015654 memory Effects 0.000 title claims abstract description 47
- 239000002784 hot electron Substances 0.000 claims abstract description 13
- 230000005684 electric field Effects 0.000 claims abstract description 6
- 230000005689 Fowler Nordheim tunneling Effects 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 11
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims 2
- 230000001052 transient effect Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
Definitions
- This invention relates to semiconductor memories and in particular flash memory cells.
- bit line and word line disturbs which are caused by bit line and word line voltages being coupled to the deselected cells as well as the selected cells on the same bit line or word line during erase, program and read operations.
- the effect of the bit line and word line disturb is to change the threshold voltage of the disturbed cells. This is an accumulative effect that over time will cause a memory error, will shorten the program and erase cycles, and reduce product life.
- U.S. Pat. No. 5,880,991 (Hsu et al.) is described an integration of a flash EEPROM with a DRAM and an SRAM on the same chip.
- the process to form the floating gate incorporates the process for making a stacked capacitor for the DRAM.
- U.S. Pat. No. 5,654,917 (Ogura et al.) a process is described for fabricating a flash memory array.
- the embedded structure of the flash memory cells are used in a Domino and Skippy Domino schemes to program and read the cells.
- U.S. Pat. No. 5,479,036 (Hong et al.) a structure and process is described for a split gate flash memory cell.
- the process utilizes self aligned techniques to produce an array of flash memory cells.
- U.S. Pat. No. 5,172,200 (Muragishi et al.) an EEPROM flash memory cell is described which utilizes a lightly doped drain structure for both the drain and the source. An insulating layer with a protruding “visor like” shape is used to improve the resistance of the insulating layer to destruction caused by high electric fields.
- U.S. Pat. No. 5,168,465 Harari
- a split channel and other cell configurations are used to produce an EEPROM.
- the elements of the EEPROM are produced using a cooperative process of manufacture to provide self alignment.
- a programming technique allows each memory cell to store more than one bit of information.
- Bit line and wordline disturb conditions occur in memory arrays that use stacked gate cells. This can occur during programming and reading when a combination of voltages must be applied to a particular stacked gate cell but also extend to other cells that are deselected. A disturb condition also occurs during erasure of a column of cells where word lines for the cells in the column are at a high negative potential and extend to other cells in other columns that are deselected and inhibited for erasure. Although a particular operation (read, program or erase) are not carried out in the other cells that are inhibited, the bias on a bit line or a word line extends to the other cells that are inhibited and can reduce the charge on the floating gates of those cells, albeit at a slow rate.
- the charge on the floating gate of a stacked gate cell determines the threshold voltage which determines the logical value of the stored data in the cell.
- the charge can be reduced over time from repeated disturb operations until the threshold voltage of the stacked gate drops below a point where the stored value is in error.
- a control gate is stacked on top of a floating gate separated by an insulator such as an oxide.
- a lightly doped drain is implanted on the drain side of the stacked gates and a heavily doped source is implanted on the source side of the stacked gates.
- Sidewalls are formed on the sides of the stacked gates, and after the sidewalls are formed a heavily doped drain is implanted into the semiconductor substrate. The heavily doped drain forms a contact region with the lightly doped drain which was implanted previous to the forming of the sidewalls.
- the source in the present invention is used to both program the flash memory cell by means of hot electrons and to erase the memory cell by using Fowler-Nordheim tunneling.
- the lightly doped drain (LDD) greatly reduces the electric field at the drain, reducing the hot electron generation and as a result reducing bit line disturbs during programming.
- Other techniques such as double diffused drain and large angle tilted implanted drain, can be used to produce the effects of the LDD to reduce the electric field and reduce the hot electron generation at the drain.
- a double diffused source can be used in place of a heavily doped arsenic source.
- the present stacked gate flash memory cell is biased similar to prior art with the selected bit lines connected to the drain either floating or connected to zero volts while the source through the selected source line is connected to +5V and the control gate connected to the selected wordline is biased to ⁇ 9V. Unselected wordlines connected to gates of unselected cells are biased to 0V during an erase operation.
- a selected wordline connected to a number of gates is biased to +9V while the selected source line is connected to +5V.
- the selected source line applies the +5V bias to the gates connected to the selected wordline as well as gates connected to wordlines that are not selected.
- the drain of the transistor of the cell that is being programmed is biased to 0V through a selected bit line.
- Unselected bit lines connected to drains of cells not being programmed are pre-biased to Vcc and then biased to +5V to minimize the effects of a transient soft program disturb.
- the transient soft program disturb occurs in cells connected to both selected wordlines at +9V and selected source lines at +5V.
- the gate of the memory cell being read is connected to Vcc through a word line, the source is connected to 0V through the source line and the drain is connected to +1.5V through a bit line.
- a soft read disturb is not a concern because of the LDD structure and the higher drain voltage can be used compared to +1V in prior art.
- FIG. 1 is a cross sectional view of the stacked gate flash memory cell of this invention
- FIG. 2 a is a schematic of a stacked gate flash memory cell of prior art biased in a read mode
- FIG. 2 b is a schematic of the stacked gate flash memory cell of this invention biased in the read mode
- FIG. 3 a is a schematic of a stacked gate flash memory cell of prior art biased in a program mode
- FIG. 3 b is a schematic of the stacked gate flash memory cell of this invention biased in the program mode
- FIG. 4 is a schematic diagram of the stacked gate flash memory cell of this invention biased in a unselected state during programming of another cell along the same wordline,
- FIG. 5 is a schematic diagram showing the cells of this invention in a matrix biased in the selected and unselected state
- FIG. 6 a is a schematic of a stacked gate flash memory cell of prior art biased in an erase mode
- FIG. 6 b is a schematic of a stacked gate flash memory cell of this invention biased in the erase mode.
- FIG. 1 a cross sectional view of the stacked gate flash memory cell of this invention.
- a floating gate 10 is formed on a gate oxide 11 grown on a semiconductor substrate 14 .
- a control gate 12 On top of the floating gate 10 is a control gate 12 separated from the floating gate by an oxide 13 .
- Sidewalls 15 are formed on the stacked gate comprising the floating gate 10 and control gate 12 .
- Implanted in the semiconductor substrate 14 is an N+ drain 16 extending under a sidewall 15 to a region under the edge of one side of the floating gate 10 .
- an N ⁇ lightly doped drain (LDD) 17 is implanted into the semiconductor substrate extending under the sidewall 15 to a region under the edge of the opposite side of the floating gate 10 .
- LDD lightly doped drain
- Both the N+ source 16 and the N ⁇ LDD 17 were implanted into the substrate before the sidewalls 15 were formed on the sides of the stacked floating gate 10 and control gate 12 . After the sidewalls 15 are formed an N+ drain 18 is implanted into the semiconductor substrate 14 . As a of result of the N ⁇ LDD 17 , the electric field of the drain junction is reduced which reduces the hot electron generation at the drain and reduces the bit line disturb conditions during program operations.
- FIG. 2 a a schematic of bias conditions for a read operation is shown for prior art.
- a stacked gate transistor flash memory cell 20 is biased with 1V connected to the drain 21 , Vcc connected to the control gate 22 by means of a wordline (not shown for simplicity), and ground connected to the source 23 through a source line (not shown for simplicity).
- the resistance Rs represents the resistance of the source line.
- FIG. 2 b is shown the stacked gate flash memory cell of this invention biased in a read mode.
- the stacked gate transistor 30 is biased similar to the transistor 20 of prior art shown in FIG. 2 a .
- the control gate 32 is biased to Vcc through a connecting wordline (not shown for simplicity) and the source 33 is biased to ground through a connecting source line (not shown for simplicity) where the source line resistance is Rs.
- the drain 31 is biased greater than 1.5 volts as a result of the low concentration ions in the drain junction resulting from the N ⁇ LDD 17 which allows a stronger bit current to reduce read errors and improve read speed.
- the increased drain voltage can allow a longer and/or a more resistive bit line to be used.
- FIG. 3 a is shown a stacked gate flash memory cell of prior art biased in program mode.
- the stacked gate transistor 40 is biased to +5V on the drain 41 , to +9V on the control gate 42 , and to ground on the source 43 through a source line with a resistance of Rs.
- a current I DS flows through the stacked gate transistor 40 .
- the stacked gate transistor 50 of the flash memory cell of this invention is shown in FIG. 3 b .
- the drain 51 is connected to 0V through a bit line (not shown for simplicity)
- the control gate is biased to +9V through a wordline (not shown for simplicity)
- the source 53 is biased to +5V through a source line (not shown for simplicity) where Rs represents the resistance of the source line.
- the current I SD Flows in an opposite direction compared to that in the transistor 40 of prior art. Even though the drain junction 17 of the stacked gate transistor 50 in FIG. 3 b sees the floating gate, the low concentration of ions in the LDD does not allow an efficient generation of hot electrons for programming the floating gate 54 of the stacked gate transistor 50 .
- the stacked gate of prior art shown in FIG. 3 a uses the drain 41 for hot electron programming and the source 43 for Fowler-Nordheim (FN) tunneling for erase operations.
- the stacked gate flash memory cell of this invention shown in FIG. 3 b uses the source 53 for both hot electron programming and FN tunneling for erasing.
- the present invention has a higher gate to source voltage that can be used to improve program speed.
- the potential for increased gate to source voltage can be used to allow a reduced gate voltage which in turn can simplify high voltage design, reduce junction leakage and improve gate disturb.
- FIG. 4 is shown a circuit diagram for illustrating a soft program disturb that can occur in this invention.
- An unselected flash memory cell 60 is partially biased in a program mode by applying +9V to the control gate 58 by means of a selected wordline and +5V to the source 59 by means of a selected source line.
- the drain 57 is biased to +5V which deselects cell for programming.
- +5V is applied to the unselected bit line 56
- the capacitance C BL of the unselected bit line 56 is charged to +5V.
- a transient current can flow in the unselected memory cell 60 .
- bit line 56 is pre-charged to V CC which minimizes the disturb condition to 5 ⁇ V CC and a total charge time of less than 0.5 us.
- the +5V on the unselected bit line 56 will cause a bit line disturb on cell 61 , shown in FIG. 5.
- the drain side 63 of the stacked gate device 61 is engineered to reduce hot carrier generation by means of an LDD 17 shown in FIG. 1.
- a selected bit line BL 0 55 connects a voltage of 0V to the drain 51 connected to the selected cell 50 and to the drain 64 of an unselected cell 62 .
- An unselected bit line BL 1 56 connects a voltage of 5V to the drain 57 connected to the selected cell 60 and to the drain 66 of an unselected cell 61 .
- a selected word line WL 0 connects +9V to the control gate 52 of the selected cell 50 and to the control gate 58 of an unselected cell 60 .
- a selected source line SL 0 connects +5V to the source 53 of the selected stacked gate flash memory cell 50 , to the source 65 of an unselected cell 62 connected to the selected bit line BL 0 55 , to the source 59 of unselected cell 60 and source 66 of unselected cell 61 .
- An unselected wordline WL 1 connects 0V to the gate 67 of the unselected cell 62 and gate 68 of the unselected cell 61 .
- a wordline disturb can occur on cell 60 , but this disturb condition is minimized because the +5V on the bit line BL 1 and the +5V on the selected source line SL 0 maintain a small channel differential on cell 60 .
- a source line disturb can occur on unselected cell 62 where the selected source line SL 0 provides +5V to the source 65 of cell 62 .
- the gate 67 of cell 62 is bias to 0V by the unselected wordline WL 1 and the drain 64 is biased by the selected bit line BL 0 .
- the source line disturb condition on cell 62 is similar to bit line program disturb found in prior art.
- FIG. 6 a is shown the erase configuration for a stacked gate flash memory cell 40 of prior art.
- a bit line (not shown for simplicity) connects a floating line or 0V to the drain 41
- a wordline (not shown for simplicity) connects ⁇ 9V to the gate 42
- a source line (not shown for simplicity) connects +5V to the source 43 of cell 40 where Rs is the resistance of the source line.
- FIG. 6 b is shown the erase configuration for a stacked gate flash memory cell 40 of this invention.
- the configuration to erase information stored on the floating gate of cell 50 is similar to that of prior art where a bit line (not shown for simplicity) connects a floating line or 0V to the drain 51 , a wordline (not shown for simplicity) connects ⁇ 9V to the gate 52 and a source line (not shown for simplicity) connects +5V to the source 53 of cell 50 where Rs is the resistance of the source line.
- FIG. 7 is shown a method to produce the stacked gate flash memory cell of this invention.
- a gate oxide is grown on the surface of a semiconductor substrate 80 , and a floating gate is formed on top of the gate oxide 81 .
- an oxide layer is formed on top of the floating gate 82 which is used to separate the floating gate from a control gate wich is formed on top of the floating gate 83 .
- a lightly drain is ion implanted into the semiconductor substrate 84 on the drain side of the gate structure.
- a heavily doped source is implanted on the source side of the gate structure 85 and sidewall spacers are formed on the sides of the gate structure 86 . After the sidewalls are formed a heavily doped drain is ion implanted into the semiconductor substrate 87 interfacing the lightly doped drain implanted in step 84 .
Abstract
Description
- 1. Field of Invention
- This invention relates to semiconductor memories and in particular flash memory cells.
- 2. Description of Related Art
- One of the problems associated with a flash memory is bit line and word line disturbs which are caused by bit line and word line voltages being coupled to the deselected cells as well as the selected cells on the same bit line or word line during erase, program and read operations. The effect of the bit line and word line disturb is to change the threshold voltage of the disturbed cells. This is an accumulative effect that over time will cause a memory error, will shorten the program and erase cycles, and reduce product life.
- In U.S. Pat. No. 5,880,991 (Hsu et al.) is described an integration of a flash EEPROM with a DRAM and an SRAM on the same chip. The process to form the floating gate incorporates the process for making a stacked capacitor for the DRAM. In U.S. Pat. No. 5,654,917 (Ogura et al.) a process is described for fabricating a flash memory array. The embedded structure of the flash memory cells are used in a Domino and Skippy Domino schemes to program and read the cells. In U.S. Pat. No. 5,479,036 (Hong et al.) a structure and process is described for a split gate flash memory cell. The process utilizes self aligned techniques to produce an array of flash memory cells. In U.S. Pat. No. 5,172,200 (Muragishi et al.) an EEPROM flash memory cell is described which utilizes a lightly doped drain structure for both the drain and the source. An insulating layer with a protruding “visor like” shape is used to improve the resistance of the insulating layer to destruction caused by high electric fields. In U.S. Pat. No. 5,168,465 (Harari) a split channel and other cell configurations are used to produce an EEPROM. The elements of the EEPROM are produced using a cooperative process of manufacture to provide self alignment. A programming technique allows each memory cell to store more than one bit of information.
- Bit line and wordline disturb conditions occur in memory arrays that use stacked gate cells. This can occur during programming and reading when a combination of voltages must be applied to a particular stacked gate cell but also extend to other cells that are deselected. A disturb condition also occurs during erasure of a column of cells where word lines for the cells in the column are at a high negative potential and extend to other cells in other columns that are deselected and inhibited for erasure. Although a particular operation (read, program or erase) are not carried out in the other cells that are inhibited, the bias on a bit line or a word line extends to the other cells that are inhibited and can reduce the charge on the floating gates of those cells, albeit at a slow rate. The charge on the floating gate of a stacked gate cell determines the threshold voltage which determines the logical value of the stored data in the cell. The charge can be reduced over time from repeated disturb operations until the threshold voltage of the stacked gate drops below a point where the stored value is in error.
- In this invention a stacked gate flash memory cell and its usage is described to produce reduced disturb conditions. A control gate is stacked on top of a floating gate separated by an insulator such as an oxide. A lightly doped drain is implanted on the drain side of the stacked gates and a heavily doped source is implanted on the source side of the stacked gates. Sidewalls are formed on the sides of the stacked gates, and after the sidewalls are formed a heavily doped drain is implanted into the semiconductor substrate. The heavily doped drain forms a contact region with the lightly doped drain which was implanted previous to the forming of the sidewalls.
- The source in the present invention is used to both program the flash memory cell by means of hot electrons and to erase the memory cell by using Fowler-Nordheim tunneling. The lightly doped drain (LDD) greatly reduces the electric field at the drain, reducing the hot electron generation and as a result reducing bit line disturbs during programming. Other techniques, such as double diffused drain and large angle tilted implanted drain, can be used to produce the effects of the LDD to reduce the electric field and reduce the hot electron generation at the drain. Depending upon product requirements such as increased breakdown and reduced band to band tunneling a double diffused source can be used in place of a heavily doped arsenic source.
- During an erase operation the present stacked gate flash memory cell is biased similar to prior art with the selected bit lines connected to the drain either floating or connected to zero volts while the source through the selected source line is connected to +5V and the control gate connected to the selected wordline is biased to −9V. Unselected wordlines connected to gates of unselected cells are biased to 0V during an erase operation.
- During programming of the present flash memory cell, a selected wordline connected to a number of gates is biased to +9V while the selected source line is connected to +5V. The selected source line applies the +5V bias to the gates connected to the selected wordline as well as gates connected to wordlines that are not selected. The drain of the transistor of the cell that is being programmed is biased to 0V through a selected bit line. Unselected bit lines connected to drains of cells not being programmed are pre-biased to Vcc and then biased to +5V to minimize the effects of a transient soft program disturb. The transient soft program disturb occurs in cells connected to both selected wordlines at +9V and selected source lines at +5V. When an unselected bit line is raised to +5V a transient current can flow through the cell which causes a disturb condition. To minimize this effect the unselected bit lines are pre-charged to Vcc which reduces the bit line charging voltage (+5V−Vcc). The +5V bias on unselected bit lines will cause a bit line disturb in cell connected to unselected wordlines. This disturb condition is minimized by the design of the drain that is lightly doped at the drain side of the channel which greatly reduces hot electron generation.
- During a read the gate of the memory cell being read is connected to Vcc through a word line, the source is connected to 0V through the source line and the drain is connected to +1.5V through a bit line. A soft read disturb is not a concern because of the LDD structure and the higher drain voltage can be used compared to +1V in prior art.
- This invention will be described with reference to the accompanying drawings, wherein:
- FIG. 1 is a cross sectional view of the stacked gate flash memory cell of this invention,
- FIG. 2a is a schematic of a stacked gate flash memory cell of prior art biased in a read mode,
- FIG. 2b is a schematic of the stacked gate flash memory cell of this invention biased in the read mode,
- FIG. 3a is a schematic of a stacked gate flash memory cell of prior art biased in a program mode,
- FIG. 3b is a schematic of the stacked gate flash memory cell of this invention biased in the program mode,
- FIG. 4 is a schematic diagram of the stacked gate flash memory cell of this invention biased in a unselected state during programming of another cell along the same wordline,
- FIG. 5 is a schematic diagram showing the cells of this invention in a matrix biased in the selected and unselected state,
- FIG. 6a is a schematic of a stacked gate flash memory cell of prior art biased in an erase mode, and
- FIG. 6b is a schematic of a stacked gate flash memory cell of this invention biased in the erase mode.
- In FIG. 1 is shown a cross sectional view of the stacked gate flash memory cell of this invention. A floating
gate 10 is formed on agate oxide 11 grown on asemiconductor substrate 14. On top of the floatinggate 10 is acontrol gate 12 separated from the floating gate by anoxide 13.Sidewalls 15 are formed on the stacked gate comprising the floatinggate 10 andcontrol gate 12. Implanted in thesemiconductor substrate 14 is anN+ drain 16 extending under asidewall 15 to a region under the edge of one side of the floatinggate 10. On the opposite side of the floatinggate 10 an N− lightly doped drain (LDD) 17 is implanted into the semiconductor substrate extending under thesidewall 15 to a region under the edge of the opposite side of the floatinggate 10. Both theN+ source 16 and the N−LDD 17 were implanted into the substrate before the sidewalls 15 were formed on the sides of the stacked floatinggate 10 andcontrol gate 12. After thesidewalls 15 are formed anN+ drain 18 is implanted into thesemiconductor substrate 14. As a of result of the N−LDD 17, the electric field of the drain junction is reduced which reduces the hot electron generation at the drain and reduces the bit line disturb conditions during program operations. - In FIG. 2a a schematic of bias conditions for a read operation is shown for prior art. Here a stacked gate transistor
flash memory cell 20 is biased with 1V connected to thedrain 21, Vcc connected to thecontrol gate 22 by means of a wordline (not shown for simplicity), and ground connected to thesource 23 through a source line (not shown for simplicity). The resistance Rs represents the resistance of the source line. In FIG. 2b is shown the stacked gate flash memory cell of this invention biased in a read mode. Thestacked gate transistor 30 is biased similar to thetransistor 20 of prior art shown in FIG. 2a. Thecontrol gate 32 is biased to Vcc through a connecting wordline (not shown for simplicity) and thesource 33 is biased to ground through a connecting source line (not shown for simplicity) where the source line resistance is Rs. Thedrain 31 is biased greater than 1.5 volts as a result of the low concentration ions in the drain junction resulting from the N−LDD 17 which allows a stronger bit current to reduce read errors and improve read speed. Alternatively, the increased drain voltage can allow a longer and/or a more resistive bit line to be used. - In FIG. 3a is shown a stacked gate flash memory cell of prior art biased in program mode. The
stacked gate transistor 40 is biased to +5V on thedrain 41, to +9V on thecontrol gate 42, and to ground on thesource 43 through a source line with a resistance of Rs. A current IDS flows through thestacked gate transistor 40. In comparison the stackedgate transistor 50 of the flash memory cell of this invention is shown in FIG. 3b. Thedrain 51 is connected to 0V through a bit line (not shown for simplicity), the control gate is biased to +9V through a wordline (not shown for simplicity), and thesource 53 is biased to +5V through a source line (not shown for simplicity) where Rs represents the resistance of the source line. The current ISD Flows in an opposite direction compared to that in thetransistor 40 of prior art. Even though thedrain junction 17 of the stackedgate transistor 50 in FIG. 3b sees the floating gate, the low concentration of ions in the LDD does not allow an efficient generation of hot electrons for programming the floatinggate 54 of the stackedgate transistor 50. The stacked gate of prior art shown in FIG. 3a uses thedrain 41 for hot electron programming and thesource 43 for Fowler-Nordheim (FN) tunneling for erase operations. The stacked gate flash memory cell of this invention shown in FIG. 3b uses thesource 53 for both hot electron programming and FN tunneling for erasing. The gate to source voltage VGS=9−(5−IDS*RS) for this invention show in FIG. 3b as compared to VGS=9−IDS*RS for the prior art shown in FIG. 3a. Thus the present invention has a higher gate to source voltage that can be used to improve program speed. Alternately, the potential for increased gate to source voltage can be used to allow a reduced gate voltage which in turn can simplify high voltage design, reduce junction leakage and improve gate disturb. - In FIG. 4 is shown a circuit diagram for illustrating a soft program disturb that can occur in this invention. An unselected
flash memory cell 60 is partially biased in a program mode by applying +9V to thecontrol gate 58 by means of a selected wordline and +5V to thesource 59 by means of a selected source line. Thedrain 57 is biased to +5V which deselects cell for programming. When +5V is applied to theunselected bit line 56, the capacitance CBL of theunselected bit line 56 is charged to +5V. During charging of theunselected bit line 56 to +5V, a transient current can flow in theunselected memory cell 60. In order to reduce the disturb effects of this transient current, thebit line 56 is pre-charged to VCC which minimizes the disturb condition to 5−VCC and a total charge time of less than 0.5 us. However, the +5V on theunselected bit line 56 will cause a bit line disturb oncell 61, shown in FIG. 5. To minimize this disturb condition thedrain side 63 of thestacked gate device 61 is engineered to reduce hot carrier generation by means of anLDD 17 shown in FIG. 1. - Continuing to refer to FIG. 5, a small portion of the matrix of interconnected flash memory cells are shown. A selected
bit line BL0 55 connects a voltage of 0V to thedrain 51 connected to the selectedcell 50 and to thedrain 64 of anunselected cell 62. An unselectedbit line BL1 56 connects a voltage of 5V to thedrain 57 connected to the selectedcell 60 and to thedrain 66 of anunselected cell 61. A selected word line WL0 connects +9V to thecontrol gate 52 of the selectedcell 50 and to thecontrol gate 58 of anunselected cell 60. A selected source line SL0 connects +5V to thesource 53 of the selected stacked gateflash memory cell 50, to thesource 65 of anunselected cell 62 connected to the selectedbit line BL0 55, to thesource 59 ofunselected cell 60 andsource 66 ofunselected cell 61. An unselected wordline WL1 connects 0V to thegate 67 of theunselected cell 62 andgate 68 of theunselected cell 61. Besides the disturb condition oncell 61 noted above and caused by the +5V bit line voltage on BL1, a wordline disturb can occur oncell 60, but this disturb condition is minimized because the +5V on the bit line BL1 and the +5V on the selected source line SL0 maintain a small channel differential oncell 60. A source line disturb can occur onunselected cell 62 where the selected source line SL0 provides +5V to thesource 65 ofcell 62. Thegate 67 ofcell 62 is bias to 0V by the unselected wordline WL1 and thedrain 64 is biased by the selected bit line BL0. The source line disturb condition oncell 62 is similar to bit line program disturb found in prior art. - In FIG. 6a is shown the erase configuration for a stacked gate
flash memory cell 40 of prior art. In order to erase information stored on the floating gate ofcell 40, a bit line (not shown for simplicity) connects a floating line or 0V to thedrain 41, a wordline (not shown for simplicity) connects −9V to thegate 42 and a source line (not shown for simplicity) connects +5V to thesource 43 ofcell 40 where Rs is the resistance of the source line. In FIG. 6b is shown the erase configuration for a stacked gateflash memory cell 40 of this invention. The configuration to erase information stored on the floating gate ofcell 50 is similar to that of prior art where a bit line (not shown for simplicity) connects a floating line or 0V to thedrain 51, a wordline (not shown for simplicity) connects −9V to thegate 52 and a source line (not shown for simplicity) connects +5V to thesource 53 ofcell 50 where Rs is the resistance of the source line. - In FIG. 7 is shown a method to produce the stacked gate flash memory cell of this invention. A gate oxide is grown on the surface of a
semiconductor substrate 80, and a floating gate is formed on top of thegate oxide 81. Next an oxide layer is formed on top of the floatinggate 82 which is used to separate the floating gate from a control gate wich is formed on top of the floatinggate 83. A lightly drain is ion implanted into thesemiconductor substrate 84 on the drain side of the gate structure. A heavily doped source is implanted on the source side of thegate structure 85 and sidewall spacers are formed on the sides of thegate structure 86. After the sidewalls are formed a heavily doped drain is ion implanted into thesemiconductor substrate 87 interfacing the lightly doped drain implanted instep 84. - While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
Claims (10)
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US10/616,751 US20040008561A1 (en) | 2000-03-21 | 2003-07-10 | Stacked gate flash memory cell with reduced distrub conditions |
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US09/531,787 US6660585B1 (en) | 2000-03-21 | 2000-03-21 | Stacked gate flash memory cell with reduced disturb conditions |
US10/616,751 US20040008561A1 (en) | 2000-03-21 | 2003-07-10 | Stacked gate flash memory cell with reduced distrub conditions |
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US09/531,787 Division US6660585B1 (en) | 2000-03-21 | 2000-03-21 | Stacked gate flash memory cell with reduced disturb conditions |
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