US20040018668A1 - Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide - Google Patents
Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide Download PDFInfo
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- US20040018668A1 US20040018668A1 US10/178,542 US17854202A US2004018668A1 US 20040018668 A1 US20040018668 A1 US 20040018668A1 US 17854202 A US17854202 A US 17854202A US 2004018668 A1 US2004018668 A1 US 2004018668A1
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- 239000012212 insulator Substances 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 title claims description 25
- 238000002955 isolation Methods 0.000 title description 5
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 72
- 239000010703 silicon Substances 0.000 claims abstract description 72
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 71
- 239000000463 material Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims description 17
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000001939 inductive effect Effects 0.000 claims description 2
- 239000000969 carrier Substances 0.000 abstract description 2
- 239000002243 precursor Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76281—Lateral isolation by selective oxidation of silicon
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Definitions
- the present invention relates to the field of semiconductor manufacturing, and more particularly, to the formation of strained device film for silicon-on-insulator (SOI) devices.
- SOI silicon-on-insulator
- SOI silicon-on-insulator
- CMOS complementary metal-oxide-semiconductor
- SOI technology reduces undesired p-n junction capacitance between source/drain and a substrate by approximately 25% as compared to other conventional techniques for CMOS ICs.
- CMOS ICs fabricated with SOI technology have less active current consumption while maintaining device performance equivalent to that of similar devices formed on bulk-silicon substrates.
- Other advantages of SOI technology include suppression of the short channel effect, suppression of the body-effect, high punch-through immunity, and reduced latch-up and soft errors.
- SOI technology is becoming increasingly more popular due to the low power requirements at high speeds of SOI devices.
- SOI wafers There are many different techniques for formation of SOI wafers. These include SIMOX, which is separation by implanted oxygen technology. Wafer bonding is another technique for forming an isolation layer in a substrate. Forming silicon islands through a series of etch and oxidation steps can provide lateral isolation structure.
- the channel length and gate dielectric thickness are reduced to improve current drive and switching performance.
- Carrier mobility of a MOSFET device is an important parameter because of its direct influence on output current and switching performance. Accordingly, another way to increase device performance is to enhance the channel mobility.
- This enhancement has been provided in certain devices by straining the silicon film. A net strain can be provided by compressive stress of the silicon film, or tensile stress of the silicon film.
- embodiments of the present invention which provide a method of forming strained device film comprising the steps of etching recesses in a buried oxide layer of a silicon-on-insulator (SOI) structure having a substrate, a buried oxide layer on the substrate, and a silicon layer on the buried oxide layer.
- the silicon layer has trenches, and the etching of recesses in the buried oxide layer include etching through the trenches in the silicon layer.
- the recesses in the buried oxide layer and the trenches are filled with a material that induces a net amount of strain in the silicon layer.
- a net amount of strain in the silicon layer may be induced to provide a desired amount of and type of stress.
- nitride is deposited into the recesses and the buried oxide layer and the trenches in the silicon layer.
- Changing the material will change the amount and type of stress, such as either tensile or compressive stress, that produces the net amount of strain in the silicon layer.
- the present invention improves the device performance by enhancing the channel mobility in the SOI devices that are created.
- a silicon-on-insulator (SOI) device with strained silicon film comprising a substrate and a buried oxide layer on the substrate. Silicon islands are provided on the buried oxide layer. The silicon islands are separated from each other by gaps. The buried oxide layer has recesses directly under the gaps. A material fills the recesses and the gaps, this material inducing a net amount of strain in the silicon islands.
- SOI silicon-on-insulator
- FIG. 1 is a schematic, cross-section of a precursor for a silicon-on-insulator (SOI) device constructed in accordance with embodiments of the present invention.
- SOI silicon-on-insulator
- FIG. 2 depicts the structure of FIG. 1 after trenches have been etched into the silicon layer to form silicon islands.
- FIG. 3 shows the structure of FIG. 2 after the buried oxide layer has been etched with an undercutting etch, in accordance with embodiments of the present invention.
- FIG. 4 shows the structure of FIG. 3 following the deposition and planarization of another material, in accordance with embodiments of the present invention.
- FIG. 5 depicts the structure of FIG. 4 after completed devices are formed on the silicon islands, in accordance with embodiments of the present invention.
- FIGS. 6 and 7 depict a method for reducing gate dielectric leakage by differential gate dielectric thicknesses.
- the present invention addresses and solves problems related to the improvement of device performance for SOI devices.
- the present invention achieves this, in part, by the partial replacement of the isolation oxide underneath and between the silicon islands by a different material.
- an undercutting etch is performed through the gaps between the silicon islands and the silicon layer to etch the buried oxide layer in an undercutting manner.
- a material is deposited within the gaps and the recesses formed in the buried oxide layer.
- the material is chosen to provide a desired amount of stress, either tensile or compressive, into the silicon islands to induce a net amount of strain in the silicon film.
- the strained silicon has enhanced carrier mobility, thereby improving the device performance of devices formed on the strained silicon.
- FIG. 1 depicts a schematic, cross-section of a precursor for a SOI device, constructed in accordance with embodiments of the present invention.
- the precursor includes a substrate 10 , which may be a silicon substrate, for example, on top of which is formed a buried oxide layer 12 .
- a silicon film, or layer 14 is formed on the buried oxide layer 12 .
- the precursor may be formed in a conventional manner.
- trenches 16 have been etched into the silicon layer 14 .
- a conventional etching technique and chemistry is employed to etch the silicon layer 14 and stop on the buried oxide layer 12 .
- the trenches 16 separate the SOI layer 14 into silicon islands 18 .
- the etching performed is a conventional anisotropic etch, for example, that produces vertical sidewalls on the silicon islands 18 .
- the anisotropic etch may be a reactive ion etch (RIE) that directionally etches the silicon layer 14 .
- RIE reactive ion etch
- the width of the silicon islands 18 is selected in accordance with conventional techniques.
- the buried oxide layer 12 is etched with an undercutting etch process.
- FIG. 3 the results of the undercutting etch is depicted.
- a conventional etching technique may be performed to etch the buried oxide layer 12 .
- a moderately anisotropic technique may be employed such that undercutting (as indicated at 20 ) is exhibited in the buried oxide layer 12 .
- recesses 22 are created within the buried oxide layer 12 .
- the recesses 22 include portions that are directly beneath the trenchesl 6 in the silicon oxide layer 14 , and portions that are underneath the silicon islands 18 .
- the etching proceeds through the trenches 16 into the buried oxide layer 12 , and the etching is allowed to proceed until the undercuts 20 are produced in the buried oxide layer 12 .
- An isotropic process may also be employed, or a moderately anisotropic process may be employed alternatively.
- the amount of undercutting may be controlled to influence the amount of strain in the silicon islands 18 . In other words, in addition to selecting the material to be deposited, the size of the recess 22 created in the buried oxide layer 12 will have an effect on the strain induced in the silicon islands.
- a new material is introduced that replaces the oxide that has been etched from the buried oxide layer 12 .
- a conventional deposition technique such as plasma enhanced chemical vapor deposition (PECVD) may be employed to deposit the material 24 into the recesses 22 and the trenches 16 .
- the material is selected according to the material's intrinsic properties that will affect the net amount of strain induced in the silicon islands 18 .
- nitride may be used to fill the recesses 22 and the gaps formed by the trenches 16 . Due to its intrinsic properties, nitride provides a tensile stress in the depicted structure of FIG. 4.
- Other materials may be chosen that provide different amounts of tensile stress, or a different type of stress, such as compressive stress. Those of ordinary skill in the art may select the appropriate material based upon the intrinsic properties of the material to produce a desired amount and type of stress.
- the material 24 is planarized by a conventional planarization technique, such as chemical mechanical polishing (CMP), to produce the structure of FIG. 4.
- CMP chemical mechanical polishing
- the stress provided by the replacement material 24 in the structure of FIG. 4 induces a net amount of strain in the silicon islands 18 .
- This net amount of strain modifies the electrical properties of carriers in the silicon film in the silicon islands 18 .
- the device performance of the SOI devices that are subsequently formed will be improved.
- FIG. 5 shows the structure of FIG. 4 after semiconductor devices 26 are formed on the silicon islands 18 . Due to the strained silicon of the silicon islands 18 , induced by the replacement material 24 in the buried oxide layer 12 and between the silicon islands 18 , there is improved channel mobility in the devices 26 so that the devices exhibit increased performance.
- Another aspect provides a method for reducing gate dielectric leakage by differential gate dielectric thicknesses.
- Gate dielectric leakage is the most around the drain and source areas, while in the middle of the channel, it is four or five orders of magnitude less. Since the tunneling is exponentially dependent on dielectric thickness, a thicker dielectric is needed at the source/drain edge to suppress gate leakage. A thin dielectric is needed elsewhere to increase gate control of the channel inversion.
- gate oxide is etched from the side in buffered HF solution that has a very controllable etch rate. A lateral etch to the edge of the extension junction is performed.
- both the gate and the silicon are oxidized at a low temperature (e.g., ⁇ 750° C. to prevent extension dopant diffusion. Doped polysilicon and n+ Si will oxidize much faster than lightly doped p-channel.
Abstract
Description
- The present invention relates to the field of semiconductor manufacturing, and more particularly, to the formation of strained device film for silicon-on-insulator (SOI) devices.
- The advantages of silicon-on-insulator (SOI) technology for complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are well documented. Typically, SOI technology reduces undesired p-n junction capacitance between source/drain and a substrate by approximately 25% as compared to other conventional techniques for CMOS ICs. Furthermore, CMOS ICs fabricated with SOI technology have less active current consumption while maintaining device performance equivalent to that of similar devices formed on bulk-silicon substrates. Other advantages of SOI technology include suppression of the short channel effect, suppression of the body-effect, high punch-through immunity, and reduced latch-up and soft errors. As the demand increases for battery-operated equipment, SOI technology is becoming increasingly more popular due to the low power requirements at high speeds of SOI devices.
- There are many different techniques for formation of SOI wafers. These include SIMOX, which is separation by implanted oxygen technology. Wafer bonding is another technique for forming an isolation layer in a substrate. Forming silicon islands through a series of etch and oxidation steps can provide lateral isolation structure.
- In standard MOSFET technology, the channel length and gate dielectric thickness are reduced to improve current drive and switching performance. Carrier mobility of a MOSFET device is an important parameter because of its direct influence on output current and switching performance. Accordingly, another way to increase device performance is to enhance the channel mobility. This enhancement has been provided in certain devices by straining the silicon film. A net strain can be provided by compressive stress of the silicon film, or tensile stress of the silicon film.
- It is desirable to provide the isolation advantages of SOI technology and silicon islands, yet also provide the improved device performance achieved through enhancement of carrier mobility.
- There is a need for providing a strained silicon film in an SOI device having silicon islands to increase the device performance by enhancing the carrier mobility in the silicon film.
- This and other needs are met by embodiments of the present invention which provide a method of forming strained device film comprising the steps of etching recesses in a buried oxide layer of a silicon-on-insulator (SOI) structure having a substrate, a buried oxide layer on the substrate, and a silicon layer on the buried oxide layer. The silicon layer has trenches, and the etching of recesses in the buried oxide layer include etching through the trenches in the silicon layer. The recesses in the buried oxide layer and the trenches are filled with a material that induces a net amount of strain in the silicon layer.
- By replacing some of the buried oxide layer with other material, a net amount of strain in the silicon layer may be induced to provide a desired amount of and type of stress. For example, in certain embodiments, nitride is deposited into the recesses and the buried oxide layer and the trenches in the silicon layer. Changing the material will change the amount and type of stress, such as either tensile or compressive stress, that produces the net amount of strain in the silicon layer. Hence, the present invention improves the device performance by enhancing the channel mobility in the SOI devices that are created.
- The earlier stated needs are also met by embodiments of the present invention which provide a silicon-on-insulator (SOI) device with strained silicon film, comprising a substrate and a buried oxide layer on the substrate. Silicon islands are provided on the buried oxide layer. The silicon islands are separated from each other by gaps. The buried oxide layer has recesses directly under the gaps. A material fills the recesses and the gaps, this material inducing a net amount of strain in the silicon islands.
- The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
- FIG. 1 is a schematic, cross-section of a precursor for a silicon-on-insulator (SOI) device constructed in accordance with embodiments of the present invention.
- FIG. 2 depicts the structure of FIG. 1 after trenches have been etched into the silicon layer to form silicon islands.
- FIG. 3 shows the structure of FIG. 2 after the buried oxide layer has been etched with an undercutting etch, in accordance with embodiments of the present invention.
- FIG. 4 shows the structure of FIG. 3 following the deposition and planarization of another material, in accordance with embodiments of the present invention.
- FIG. 5 depicts the structure of FIG. 4 after completed devices are formed on the silicon islands, in accordance with embodiments of the present invention.
- FIGS. 6 and 7 depict a method for reducing gate dielectric leakage by differential gate dielectric thicknesses.
- The present invention addresses and solves problems related to the improvement of device performance for SOI devices. The present invention achieves this, in part, by the partial replacement of the isolation oxide underneath and between the silicon islands by a different material. In certain embodiments of the invention, an undercutting etch is performed through the gaps between the silicon islands and the silicon layer to etch the buried oxide layer in an undercutting manner. Following the etch of the buried oxide layer, a material is deposited within the gaps and the recesses formed in the buried oxide layer. The material is chosen to provide a desired amount of stress, either tensile or compressive, into the silicon islands to induce a net amount of strain in the silicon film. The strained silicon has enhanced carrier mobility, thereby improving the device performance of devices formed on the strained silicon.
- FIG. 1 depicts a schematic, cross-section of a precursor for a SOI device, constructed in accordance with embodiments of the present invention. The precursor includes a
substrate 10, which may be a silicon substrate, for example, on top of which is formed a buriedoxide layer 12. A silicon film, orlayer 14, is formed on the buriedoxide layer 12. The precursor may be formed in a conventional manner. - In FIG. 2,
trenches 16 have been etched into thesilicon layer 14. A conventional etching technique and chemistry is employed to etch thesilicon layer 14 and stop on the buriedoxide layer 12. Thetrenches 16 separate theSOI layer 14 intosilicon islands 18. The etching performed is a conventional anisotropic etch, for example, that produces vertical sidewalls on thesilicon islands 18. The anisotropic etch may be a reactive ion etch (RIE) that directionally etches thesilicon layer 14. The width of thesilicon islands 18 is selected in accordance with conventional techniques. - Following the etching of the
trenches 16 into thesilicon layer 14 to create theislands 18, the buriedoxide layer 12 is etched with an undercutting etch process. In FIG. 3, the results of the undercutting etch is depicted. A conventional etching technique may be performed to etch the buriedoxide layer 12. A moderately anisotropic technique may be employed such that undercutting (as indicated at 20) is exhibited in the buriedoxide layer 12. Hence, with the etching thus performed,recesses 22 are created within the buriedoxide layer 12. Therecesses 22 include portions that are directly beneath the trenchesl6 in thesilicon oxide layer 14, and portions that are underneath thesilicon islands 18. The etching proceeds through thetrenches 16 into the buriedoxide layer 12, and the etching is allowed to proceed until theundercuts 20 are produced in the buriedoxide layer 12. An isotropic process may also be employed, or a moderately anisotropic process may be employed alternatively. The amount of undercutting may be controlled to influence the amount of strain in thesilicon islands 18. In other words, in addition to selecting the material to be deposited, the size of therecess 22 created in the buriedoxide layer 12 will have an effect on the strain induced in the silicon islands. - Having formed the
recesses 22 in the buriedoxide layer 12, and thetrenches 16 between thesilicon islands 18, a new material is introduced that replaces the oxide that has been etched from the buriedoxide layer 12. A conventional deposition technique, such as plasma enhanced chemical vapor deposition (PECVD) may be employed to deposit the material 24 into therecesses 22 and thetrenches 16. The material is selected according to the material's intrinsic properties that will affect the net amount of strain induced in thesilicon islands 18. As an exemplary material, nitride may be used to fill therecesses 22 and the gaps formed by thetrenches 16. Due to its intrinsic properties, nitride provides a tensile stress in the depicted structure of FIG. 4. Other materials may be chosen that provide different amounts of tensile stress, or a different type of stress, such as compressive stress. Those of ordinary skill in the art may select the appropriate material based upon the intrinsic properties of the material to produce a desired amount and type of stress. - The
material 24 is planarized by a conventional planarization technique, such as chemical mechanical polishing (CMP), to produce the structure of FIG. 4. The stress provided by thereplacement material 24 in the structure of FIG. 4 induces a net amount of strain in thesilicon islands 18. This net amount of strain modifies the electrical properties of carriers in the silicon film in thesilicon islands 18. Hence, the device performance of the SOI devices that are subsequently formed will be improved. - FIG. 5 shows the structure of FIG. 4 after
semiconductor devices 26 are formed on thesilicon islands 18. Due to the strained silicon of thesilicon islands 18, induced by thereplacement material 24 in the buriedoxide layer 12 and between thesilicon islands 18, there is improved channel mobility in thedevices 26 so that the devices exhibit increased performance. - These materials are exemplary only, as other materials may be used without departing from the spirit and the scope of the present invention.
- Another aspect provides a method for reducing gate dielectric leakage by differential gate dielectric thicknesses. Gate dielectric leakage is the most around the drain and source areas, while in the middle of the channel, it is four or five orders of magnitude less. Since the tunneling is exponentially dependent on dielectric thickness, a thicker dielectric is needed at the source/drain edge to suppress gate leakage. A thin dielectric is needed elsewhere to increase gate control of the channel inversion.
- After annealing the extension implants, gate oxide is etched from the side in buffered HF solution that has a very controllable etch rate. A lateral etch to the edge of the extension junction is performed. Next, both the gate and the silicon are oxidized at a low temperature (e.g., <750° C. to prevent extension dopant diffusion. Doped polysilicon and n+ Si will oxidize much faster than lightly doped p-channel.
- After the oxidation, 25 to 30 Angstroms thick dielectric is formed over the n+ regions. The thickness will drastically reduce large leakage and also reduce Miller capacitance. The process follows by spacer formation, source/drain implant and silicidation. The process is depicted in FIGS. 6 and 7.
- Although the present invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being limited only by the terms of the appended claims.
Claims (17)
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/178,542 US6680240B1 (en) | 2002-06-25 | 2002-06-25 | Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide |
KR1020047021192A KR100996725B1 (en) | 2002-06-25 | 2003-06-04 | A silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide |
AU2003238916A AU2003238916A1 (en) | 2002-06-25 | 2003-06-04 | A silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide |
PCT/US2003/017824 WO2004001798A2 (en) | 2002-06-25 | 2003-06-04 | A silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide |
JP2004515743A JP4452883B2 (en) | 2002-06-25 | 2003-06-04 | Silicon-on-insulator device having strained device film partially substituted with insulating oxide and method for manufacturing the same |
CNB03813263XA CN1333454C (en) | 2002-06-25 | 2003-06-04 | A silicon-on-insulator device with strain film and method for forming strain film |
EP03734436A EP1516362A2 (en) | 2002-06-25 | 2003-06-04 | A silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide |
TW092116498A TWI289895B (en) | 2002-06-25 | 2003-06-18 | A silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide |
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US10/178,542 US6680240B1 (en) | 2002-06-25 | 2002-06-25 | Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide |
Publications (2)
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US6680240B1 US6680240B1 (en) | 2004-01-20 |
US20040018668A1 true US20040018668A1 (en) | 2004-01-29 |
Family
ID=29999123
Family Applications (1)
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US10/178,542 Expired - Lifetime US6680240B1 (en) | 2002-06-25 | 2002-06-25 | Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide |
Country Status (8)
Country | Link |
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US (1) | US6680240B1 (en) |
EP (1) | EP1516362A2 (en) |
JP (1) | JP4452883B2 (en) |
KR (1) | KR100996725B1 (en) |
CN (1) | CN1333454C (en) |
AU (1) | AU2003238916A1 (en) |
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Also Published As
Publication number | Publication date |
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JP4452883B2 (en) | 2010-04-21 |
WO2004001798A3 (en) | 2004-07-29 |
AU2003238916A8 (en) | 2004-01-06 |
EP1516362A2 (en) | 2005-03-23 |
JP2005531144A (en) | 2005-10-13 |
WO2004001798A2 (en) | 2003-12-31 |
US6680240B1 (en) | 2004-01-20 |
CN1333454C (en) | 2007-08-22 |
KR20050013248A (en) | 2005-02-03 |
AU2003238916A1 (en) | 2004-01-06 |
TWI289895B (en) | 2007-11-11 |
TW200400564A (en) | 2004-01-01 |
KR100996725B1 (en) | 2010-11-25 |
CN1659696A (en) | 2005-08-24 |
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