US20040021233A1 - Vertical conduction flip-chip device with bump contacts on single surface - Google Patents
Vertical conduction flip-chip device with bump contacts on single surface Download PDFInfo
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- US20040021233A1 US20040021233A1 US10/613,326 US61332603A US2004021233A1 US 20040021233 A1 US20040021233 A1 US 20040021233A1 US 61332603 A US61332603 A US 61332603A US 2004021233 A1 US2004021233 A1 US 2004021233A1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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Abstract
A flip-chip MOSFET structure has a vertical conduction semiconductor die in which the lower layer of the die is connected to a drain electrode on the top of the die by a diffusion sinker or conductive electrode. The source and gate electrodes are also formed on the upper surface of the die and have coplanar solder balls for connection to a circuit board. The structure has a chip scale package size. The back surface of the die, which is inverted when the die is mounted may be roughened or may be metallized to improve removal of heat from the die. Several separate MOSFETs can be integrated side-by-side into the die to form a series connection of MOSFETs with respective source and gate electrodes at the top surface having solder ball connectors. Plural solder ball connectors may be provided for the top electrodes and are laid out in respective parallel rows. The die may have the shape of an elongated rectangle with the solder balls laid out symmetrically to a diagonal to the rectangle.
Description
- This application is a divisional of U.S. application Ser. No. 09/780,080, filed Feb. 9, 2001 which relates to and claims the filing date of Provisional Application Serial No. 60/181,504, filed Feb. 10, 2000 and further relates to and claims the filing date of Provisional Application Serial No. 60/224,062, filed Aug. 9, 2000.
- This invention relates to semiconductor device packages and the method of making such packages and more specifically relates to a chip-scale package and method of its manufacture.
- Semiconductor device packages are well known for housing and protecting semiconductor die and for providing output connections to the die electrodes. Commonly, the semiconductor die are diced from a large parent wafer in which the die diffusions and metallizing are made in conventional wafer processing equipment. Such die may be diodes, field effect transistors, thyristors and the like. The die are fragile and the die surfaces must be protected from external environment. Further, convenient leads must be connected to the die electrodes for connection of the die in electrical circuits.
- Commonly, such die are singulated from the wafer, as by sawing, and the bottom of the die is mounted on and connected to a portion of a circuit board which has conforming sections to receive respective die. The top electrodes of the die are then commonly wire bonded to other portions of the circuit board, which are then used for external connections. Such wire connections are delicate and slow the mounting process. They also provide a relatively high resistance and inductance.
- It is desirable in many applications that the packaged semiconductor devices be mountable from one side of the package, to enable swift and reliable mounting on a circuit board, as well as low resistance connections.
- This invention provides a novel semiconductor die package comprising a “flip-chip” that is mountable on a circuit board or other electronic interface using one surface of the chip. In particular, the package has contacts, for example, gate, source and drain electrode contacts (for a MOSFET) on the same side of the package, and can be mounted by forming solder ball contacts on the surface of the chip which interface with the external gate, source and drain connections respectively on the circuit board.
- The source connection to the chip is made with solder balls on the source electrode of the chip, the solder balls being positioned so that they will interface with appropriate source electrical connections on the circuit board. The package is configured so that the drain electrode is on the same surface.
- In one embodiment, the active junctions reside in a layer of relatively low carrier concentration (for example P−) below the source electrode and above a substrate of relatively high carrier concentration of the same type (for example, P+). At least one drain electrode is positioned on the same surface at a region separate from the source electrode. A diffusion region or “sinker” extends from and beneath the top drain electrode, through the layer of relatively low carrier concentration to the substrate. The diffusion region has the same carrier concentration and type as the substrate (for example, P+). Thus, an electrical path is established from the source electrode, through the active elements, and into the substrate, through the diffusion region and to the top drain electrode.
- As noted, the drain electrode is on the same surface as the source and gate electrodes and can thus be mounted to the circuit board using solder balls that correspond to locations of appropriate external drain connections.
- In another embodiment, instead of using diffusion regions beneath the drain contacts, the layer of relatively low carrier concentration may be etched to the substrate and filled with the drain electrode. This may be done concurrently with the step of etching trenches for a vertical conduction trench-type device, for example.
- In a still further embodiment of the invention, two vertical conduction MOSFET devices are formed in a common chip, with their source regions being laterally interdigitated and with a common drain substrate. This structure forms an inherent bidirectional switch. All contacts are available at the top surface, and the contact balls may be located along straight rows which may be symmetrical around a diagonal to a rectangular chip to simplify connection to a circuit board support. The bottom of the chip may have a thick metal layer to provide a low resistance current path between adjacent devices with common drains. It can also improve thermal conduction when the chip is mounted with its top surface facing a printed circuit board support.
- Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
- FIG. 1 is a perspective view of a first embodiment of the invention.
- FIG. 2 is a top view of the metallizing pattern of the device of FIG. 1, prior to the formation of the contact bumps.
- FIG. 3 shows the wafer of FIG. 2 after the formation of solder bumps.
- FIG. 4 is a cross section of FIG. 2 taken through a small area corresponding to the area at section line4-4 in FIG. 2, and shows the source and drain top metallizations.
- FIG. 5 is a layout showing the size and spacing of the contact balls of FIGS. 1 and 3.
- FIG. 6 is a cross-section of FIG. 2 taken across section line6-6 in FIGS. 2 and across the gate bus.
- FIG. 7 shows the use of a P+ sinker diffusion to enable the connection of a top contact of drain metal to the P+ substrate.
- FIG. 8 shows a modified contact structure for making contact from the top surface drain of FIG. 4 to the P+ substrate.
- FIG. 9 is a top view of the metallized top surface of another embodiment of the invention.
- FIG. 10 shows FIG. 9 with rows of contact balls in place.
- FIG. 11 is a cross-section of FIG. 9 for a planar junction pattern instead of the trench structure of FIG. 4.
- FIG. 12 is a cross-section of a further embodiment of the invention which is similar to that of FIG. 4 but uses two MOSFETs in a common chip, producing a bidirectional conduction device and is a cross-section of FIG. 14 taken across section line12-12 in FIG. 14.
- FIG. 13 is a circuit diagram of the device of FIG. 12.
- FIG. 14 is a top view of a device such as that of FIGS. 12 and 13.
- FIG. 15 is a front view of the device of FIG. 14.
- FIGS.16 to 19 show further variants of the device of FIG. 14.
- FIG. 20 shows a cross-sectional view of a lower surface of a die according to the present invention.
- FIGS.1 to 6 show a first embodiment of the invention which is in the form of a flip-chip power MOSFET having all electrodes in one planar surface and having contact bumps to enable contact to traces or other electrical conductors of a support structure such as a printed circuit board. The device to be described could be any other type device such as a P/N or Schottky diode, an IGBT, a thyristor, an integrated circuit die having plural components and the like. Further, the device of FIGS. 1 to 6 is shown as a P channel device. The conductivity types can be reversed to make an N channel device. Further, the device of FIGS. 1 to 6 is shown as a trench type device, but it could be a planar cellular or stripe structure as well as will be later described.
- The completed device, ready for mounting, is shown in FIG. 1 and consists of a
silicon die 30 having upper source electrode metallizing 31 (usually aluminum which may be from 2 microns to 8 microns thick), drain electrode metallizing 32 and gate electrode metal pad 33 (FIG. 2) andgate bus 34. - The die is processed in wafer form, as partly shown in FIGS. 2 and 3. Contact balls are formed on the wafer, shown in FIGS. 1, 3 and4 as
source contact ball 40 onsource metal 31,drain contact balls gate contact ball 43 on gate pad metallizing 33. The die within the wafer are then singulated and are ready for assembly on a circuit board or the like. - FIGS. 4 and 6 show a trench-type power MOSFET geometry for the device of FIGS. 1 and 3. Thus, for a P channel device, a P+ silicon substrate 50 is used and a lower concentration P type,
junction receiving layer 51 is epitaxially grown atop P+ substrate 50. An N type base or channel diffusion 52 (FIGS. 4 and 5) is then formed. - Thereafter, and using conventional techniques, a plurality of
parallel trenches trenches 60 to 64, shown as gate insulation layers 70 to 74 respectively. Aconductive polysilicon gate 75 is then deposited into each of the trenches and over the gate oxide layers and is then etched away to leave polysilicon only in the trenches and gate bus and pad regions. After that, aTEOS layer 80 is deposited and patterned, leaving insulation caps 76 and 77 (which may be TEOS) over the top of thepolysilicon 75 intrenches 60 and 61 (FIG. 4). - A P+ source diffusion 53 is formed in the top of
N diffusion 52 are etched throughlayers openings 81 and 82 (FIG. 4) are next etched through the P+ source layer 53 and intochannel layer 52, and N+ contact diffusions are formed in the bottoms ofopenings type channel regions 52. This aluminum layer is separated, by etching, intosource contact 31,drain contact 32 andgate pad 33. - FIG. 5 shows the novel configuration of
contact balls solder balls - In FIG. 4, the
drain metal 32 is shown as contacting an upwardly extending portion of P+ substrate 50. This is a schematic representation, and in practice, the contact fromsurface drain 32 to P+ substrate 50 is made as shown in FIGS. 7 or 8. Thus, in FIG. 7, a P+ “sinker”diffusion 90 is employed to make the contact. In FIG. 8, atrench 91 is formed, as during the trench etching process for making the active area, and is filled with metal orconductive polysilicon 92. - The operation of the device of FIGS.1 to 8 will be apparent to those of ordinary skill. Thus, to turn the device on, and with suitable potentials applied to the source and drain
electrodes gate 75 will cause the N type silicon adjacent the gate oxide layers 70 to 74 to invert to the P type, thus completing a circuit fromsource electrode 31, throughsource regions 53, through the inversion regions toP region 51, P+ substrate 50 and then laterally through P+ substrate 50 and upwardly (throughregions 90 or 92) to drainelectrode 31. - The novel device of FIGS.1 to 8 brings the size of the device ready for mounting to a minimum; that is, to the size of the die. The die itself has an extremely low RDSON, using a vertical construction, cellular trench technology. For example, the design can employ over 110×106 cells per in2. However, unlike the standard trench FET design, the drain connection is brought to the front or top of the die. There is no need for back-grinding the bottom die surface or for metal deposition on the bottom surface of the die. By not back grinding, the thicker P+ substrate allows for lower lateral resistance to flow of drain current. Preferably, the bottom die 30 surface may be rough and unpolished to increase its surface area to assist in heat removal from the chip, as illustrated in FIG. 20.
- After metal, a silicon nitride (or other dielectric) passivation layer is deposited. The silicon nitride passivation is patterned to leave4 openings per die with a pitch, for example, of 0.8 mm. The die size may typically be about 0.060″×0.060″. Larger devices of 0.123″×0.023″ are also typical. The silicon is so designed as to provide a 20 volt P-channel device with an R*A of 46.8 ohm-mm2 at Vgs of 4.5 volt.
- While a metal layer is not required on the bottom surface of
substrate 50, it can be useful to use such a metal layer as a current conductor or to make thermal contact to a heat sink. - Other surface geometries, with a larger number of solder balls for higher current capacity can also be used. Thus, as shown in FIGS. 9 and 10, a
larger die 100 can be laid out so that its top surface provides asource electrode 101, twodrain electrodes die 100 and agate pad 104 with runners orbus drain electrodes source 101 receives 8 solder balls also aligned in parallel rows. A single solder ball is connected togate pad 104. By aligning the solder balls in respective parallel rows, the respective conductive traces on the printed circuit board receiving the device can be laid out in simple straight lines. - FIG. 11 shows how the device of FIG. 9 can be carried out with planar technology, and as an N channel device. Thus, in FIG. 11, die100 is formed with an N+ substrate 110, an N type epitaxial (epi)
layer 111 and with spaced polygonalP channel diffusions 112, 113, 114. Each ofdiffusions 112, 113 and 114 receives an N+ source diffusion 115, 116 and 117 respectively and a P+ contact diffusion 118, 119 and 120 respectively. A suitable gate structure, including apolysilicon gate latice 121 overlies a conventional gate oxide and is covered by aninsulation layer 122 to insulate the gate latice from overlyingsource electrode 101 which contacts the source regions and channel regions in the usual manner. An N+ sinker provides a conductive path from the N+ substrate to drainelectrode 103. - It is also possible to make the die with bidirectional conduction characteristics in which two series connected MOSFETs are integrated into a single chip. Thus, as shown in FIG. 12 the die can be formed in the manner of FIGS.1 through 8 for a P channel trench implementation. Thus, using the numerals used in FIGS. 1 to 8, the
bidirectional die 130 of FIG. 12 integrates two such devices in a single die. The two devices are identified with the numerals of FIGS. 4, followed by an “A” and a “B” respectively, but with acommon substrate 50. Two respective gate structures will also be provided, each having the structure of FIGS. 5 and 6. Asubstrate metallization 131 is also shown. - The circuit diagram of the bidirectional device is shown in FIG. 13 and consists of two
MOSFETs common drain MOSFETs - FIGS. 14 and 15 show a top view of the chip or die130 of FIG. 12. The
chip 130 may have the bottom conductive drain electrode 131 (FIG. 15) and will have respective gate ball electrodes G1 and G2 which may have respective gate runners orbus Drain 131 electrode may be a thick low resistance metal layer (as compared to the conventional source electrode thickness). Thebottom conductor 131 may be eliminated if P+ substrate 50 has a high enough conductivity, but it can be useful as a heat sink. - The source electrodes of each of
FETs - In accordance with a further aspect of the invention, the height of chip or die130 is greater than its width. Thus, it is a non-square, elongated rectangle. Further, the die bumps S1, S2, G1 and G2 are symmetric around a diagonal of the
die 130, shown as dotted linediagonal line 150 in FIG. 14. Thus, the source and gate electrodes will be in the same location regardless of the up/down orientation of the chip. Since the die has rotational symmetry, no pin marking is necessary and simple pattern recognition apparatus can determine die orientation or placement during attachment to a surface. - As pointed out previously, and in accordance with the invention, the source balls S1 are in a line or row which is spaced from and parallel to the line of source balls S2.
- FIGS. 16, 17,18 and 19 show alternate arrangements for FET1 (FET 140) and FET2 (FET 141) of FIGS. 13, 14 and 15 where similar numerals identify similar parts. The silicon die of FIGS. 16 to 19 may have an area of about 0.120″×0.120″. Note that in each case, source balls S1 and S2 lie in respective vertical and parallel rows, making it easy to use straight conductors for their parallel connection by either straight metal strips or straight metallizing lines on a printed circuit board. Further note that the sources of
FETs - Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.
Claims (29)
1. A flip chip semiconductor device comprising a silicon wafer having parallel first and second major surfaces; at least one P region and at least one N region in said wafer which meet at a PN junction within said silicon wafer; first and second coplanar, laterally spaced and metallized layers formed on said first major surface and insulated form one another and connected to said P region and said N region respectively; and a bottom metallized layer extending across said second major surface.
2. The device of claim 1 which includes a third metallized layer atop said first major surface which is coplanar with and laterally spaced from said first and second metallized layers; said first, second and third metallized layers comprising source, drain and gate electrodes respectively of a MOSgated device.
3 The device of claim 1 which further includes at least one contact bump connected to each of said metallized layers.
4 The device of claim 2 which further includes at least one contact bump connected to each of said metallized layers.
5. The device of claim 1 wherein said bottom metallized layer is substantially thicker than all of said first and second metallized layers.
6. The device of claim 2 wherein said bottom metallized layer is substantially thicker than all of said first and second metallized layers.
7. The device of claim 2 wherein said bottom metallized layer is substantially thicker than all of said first and second metallized layers.
8. The device of claim 4 wherein said bottom metallized layer is substantially thicker than all of said first and second metallized layers.
9. The device of claim 2 wherein a plurality of contact bumps are connected to each of said first and second metallized layers; said plurality of contact bumps connected to said first metallized layer being aligned along a first straight row; said plurality of contact bumps connected to said second metallized layer being aligned along a second straight row.
10. The device of claim 9 wherein said first and second rows are parallel to one another.
11. The device of claim 9 which includes a third metallized layer atop said first major surface which is coplanar with and laterally spaced from said first and second metallized layers; said first, second and third metallized layers comprising source, drain and gate electrodes respectively of a MOSgated device.
12. A flip chip semiconductor device comprising a silicon wafer having first and second parallel major surfaces; at least one P region and at least one N region in said wafer which meet at a PN junction within said silicon wafer; first and second coplanar, laterally spaced metallized layers formed on said first major surface and insulated form one another and connected to said P region and said N region respectively; and a plurality of contact bumps connected to each of said first and second metallized layers; said plurality of contact bumps connected to said first metallizing layer being aligned along a first straight row; said plurality of contact bumps connected to said second metallizing layer being aligned along a second straight row.
13. The device of claim 12 which includes a third metallized layer atop said first major surface which is coplanar with and laterally spaced from said first and second metallized layers; said first, second and third metallizing layers comprising source, drain and gate electrodes respectively of a MOSgated device.
14. The device of claim 12 and a bottom metallized layer extending across said second major surface.
15. The device of claim 12 wherein said bottom metallized layer is substantially thicker than all of said first and second metallized layers.
16. The device of claim 12 wherein said first and second rows are parallel to one another.
17. The device of claim 12 wherein said silicon wafer is a rectangular wafer having an area defined by a given length and a given width, said length being greater than said width; said first and second rows of bumps being parallel to one another and being symmetric about a diagonal line across said wafer.
18. The device of claim 17 which includes a third metallized layer atop said first major surface which is coplanar with and laterally spaced from said first and second metallized layers; said first, second and third metallized layers comprising source, drain and gate electrodes respectively of a MOSgated device.
19. The device of claim 14 wherein said silicon wafer is a rectangular wafer having an area defined by a given length and a given width, said length being greater than said width; said first and second rows of bumps being parallel to one another and being symmetric about a diagonal line across said wafer.
20. The device of claim 12 which further includes a bottom metallized layer extending across said second major surface.
21. A bidirectional conduction flip chip device comprising a silicon wafer having first and second parallel major surfaces; first and second laterally separated MOSgated devices formed in said silicon wafer; said first and second MOSgated devices comprising a first and a second source region respectively of one conductivity formed into a first and second spaced lateral area respectively of said first major surface, a first and second channel region respectively of a second conductivity type receiving said first and second source region, respectively a common drain region receiving said first and second channel regions and extending to said second major surface, and a first and second gate structure respectively disposed on said first major surface and operable to invert respective portions of said first and second channel regions to allow conduction from said first and second source regions respectively to said drain region; first and second laterally spaced source metallized layers disposed atop said first major surface and connected to said first and second source regions respectively; and first and second laterally spaced gate metallized layers atop said first major surface and connected to said first and second gate structures respectively.
22. The device of claim 21 which further includes at least one contact bump connected to each of said source and gate metallized layers.
23. The device of claim 22 which includes a respective plurality of contact bumps connected to each of said source metallized layers; each of said plurality of contact bumps arranged in respective spaced rows which are parallel to one another.
24. The device of claim 21 wherein said first and second source regions are disposed in laterally interdigitated relation with respect to one another.
25. The device of claim 23 wherein said first and second source regions are disposed in laterally interdigitated relation with respect to one another.
26. The device of claim 21 which further includes a metal layer on said second major surface.
27. A semiconductor device comprising a silicon die having first and second parallel surfaces; a region of one conductivity type extending from said first surface and into the body of said die; a junction pattern defined in said device formed by a plurality of laterally spaced diffusions of the other conductivity type into said region of one conductivity type; a first conductive electrode formed atop said first surface and in contact with said first plurality of diffusions; a second conductive electrode formed atop said first surface which is coplanar with and laterally spaced from and insulated from said first conductive electrode and in electrical contact with the body of said die through a high conductivity element; and at least one solder ball connector formed atop each of said first and second conductive electrodes respectively; the current path from said first conductive electrode to said second conductive electrode having a vertical component which is generally perpendicular to said first surface.
28. A semiconductor device according to claim 27 , wherein said high conductivity element is a sinker diffusion of higher conductivity than said body region.
29. A semiconductor device according to claim 27 , wherein said high conductivity element is a metallic material residing in a trench formed in said body of said die.
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US10/613,326 US20040021233A1 (en) | 2000-02-10 | 2003-07-03 | Vertical conduction flip-chip device with bump contacts on single surface |
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US22406200P | 2000-08-09 | 2000-08-09 | |
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US10/613,326 US20040021233A1 (en) | 2000-02-10 | 2003-07-03 | Vertical conduction flip-chip device with bump contacts on single surface |
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US09/780,080 Division US6653740B2 (en) | 2000-02-10 | 2001-02-09 | Vertical conduction flip-chip device with bump contacts on single surface |
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US10/613,326 Abandoned US20040021233A1 (en) | 2000-02-10 | 2003-07-03 | Vertical conduction flip-chip device with bump contacts on single surface |
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Also Published As
Publication number | Publication date |
---|---|
CN1315195C (en) | 2007-05-09 |
US20010045635A1 (en) | 2001-11-29 |
EP1258040A4 (en) | 2009-07-01 |
EP1258040A1 (en) | 2002-11-20 |
US6653740B2 (en) | 2003-11-25 |
KR100721139B1 (en) | 2007-05-25 |
TW493262B (en) | 2002-07-01 |
JP2004502293A (en) | 2004-01-22 |
JP4646284B2 (en) | 2011-03-09 |
KR20070010188A (en) | 2007-01-22 |
JP2007235150A (en) | 2007-09-13 |
KR100699552B1 (en) | 2007-03-26 |
KR20020073547A (en) | 2002-09-26 |
AU2001238081A1 (en) | 2001-08-20 |
WO2001059842A1 (en) | 2001-08-16 |
CN1401141A (en) | 2003-03-05 |
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