US20040084320A1 - Copper interconnect by immersion/electroless plating in dual damascene process - Google Patents

Copper interconnect by immersion/electroless plating in dual damascene process Download PDF

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US20040084320A1
US20040084320A1 US10/284,557 US28455702A US2004084320A1 US 20040084320 A1 US20040084320 A1 US 20040084320A1 US 28455702 A US28455702 A US 28455702A US 2004084320 A1 US2004084320 A1 US 2004084320A1
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copper
copper electroplating
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electroplating method
power supply
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Kaiser Wong
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Xerox Corp
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Xerox Corp
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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition

Definitions

  • One common metal used for forming metal lines (also referred to as wiring) on a wafer is aluminum.
  • Aluminum is used because it is relatively inexpensive compared to other conductive materials, it has low resistivity and is also relatively easy to etch.
  • Aluminum is also used as a material for forming interconnections in vias to connect the different metal layers.
  • via/contact holes As the size of via/contact holes is scaled down to a sub-micron region, the step coverage problem appears, which has led to reliability problems when using aluminum to form the interconnection between different wiring layers.
  • the poor step coverage in the sub-micron via/contact holes result in high current density and enhance the electromigration.
  • interconnect One material which has received considerable attention as a replacement material for VLSI interconnect metallizations is copper. Since copper has higher resistance electromigration property and lower resistivity than aluminum, it is a more preferred material for interconnect (plugs and wiring) formation than aluminum. However, one serious disadvantage of using copper metallization is that it is difficult to etch. Thus, where it was relatively easier to etch aluminum after deposition to form wiring lines or plugs (both wiring and plugs are referred to as interconnects), substantial additional cost and time are now required to etch copper.
  • Dual Damascene processing eliminates not only the need for metal etch (which is increasingly challenging in aluminum interconnects and nearly impossible with copper), but also the need for dielectric gap fill (another challenging process).
  • This technique involves the creation of interconnect lines by first etching a trench or canal in a planar dielectric layer, and then filling that trench with metal, such as aluminum or copper.
  • a second level is involved where a series of holes (i.e., contacts or vias) are etched and filled in addition to the trench.
  • a diffusion barrier such as tantalum is deposited by PVD first to prevent copper diffusion.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • electroplating electroplating
  • electroless plating electroless plating
  • a method of fabrication of copper interconnect by means of copper electroplating is disclosed.
  • critical steps such as deposition of copper seed layer and chemical mechanical polishing (CMP) are required.
  • CMP chemical mechanical polishing
  • both the seed layer deposition and CMP are not required.
  • FIG. 1A is a schematic illustration of a side elevation of a silicon wafer having trenches coated with Ta/TaN barrier layer and a copper seed layer before electroplating;
  • FIG. 1B is a schematic illustration of a side elevation of the silicon wafer of FIG. 1 being electroplated with copper to fill trenches;
  • FIG. 2 is a schematic illustration of a side elevation of the silicon wafer after copper plating utilizing CMP (Chemical Mechanical Polishing) to remove excess copper/barrier layer and planarize copper/silicon oxide surface;
  • CMP Chemical Mechanical Polishing
  • FIG. 3 is a schematic illustration of a side elevation of the structure of a silicon wafer to be copper plate in accordance with the invention:
  • FIG. 4 illustrates the copper plating of the silicon wafer of FIG. 3.
  • FIGS. 5 through 9 illustrates various integrated circuit technologies suitable for this invention.
  • This invention describes a fabrication method of copper interconnects using copper electroplating.
  • electrodeposition electroplating
  • the wafer is typically coated with a thin conductive layer of copper (seed layer) and immersed in a solution containing cupric ions. Electrical contact is made to the seed layer, and current is passed such the reaction Cu 2+ + 2 e ⁇ ⁇ Cu occurs at the wafer surface.
  • the wafer electrically connected so that metal ions (cupric ions) are reduced to metal (copper) atoms, is referred to as the cathode.
  • FIG. 1A is a schematic illustration of a side elevation of a silicon wafer 18 having trenches 10 coated with Ta/TaN barrier layer 14 and a copper seed layer 12 before electroplating.
  • FIG. 1B is a schematic illustration of a side elevation of the silicon wafer of FIG. 1 being electroplated with copper 20 .
  • the copper 20 fill trenches 10 coated with Ta/TaN barrier layer 14 on a wafer formed from silicon 18 and silicon dioxide 16 layers by a copper 22 strip connected to an anode in a solution 28 containing cupric ions.
  • FIG. 2 is a schematic illustration of a side elevation of the silicon wafer formed from silicon 18 and silicon dioxide 16 after copper plating utilizing CMP to remove excess copper/barrier layer and planarize copper/silicon oxide surface 10 with the Ta/TaN barrier layer 14 .
  • Copper CMP is more complex because of the need to remove the tantalum or tantalum nitride barrier layers and copper uniformly without overpolishing any features. This is difficult because current copper deposition processes are not as uniform as the oxide deposition process. Copper also has the properties that add to the polish difficulties. It is a soft metal and subject to scratching and embedded particles during polishing. Also because copper is highly electrochemically active and does not form a natural protecive oxide, it corrodes easily. Therefore protecting the copper surface during polishing, clean and subsequent processing will be essential.
  • the electrical contact for the copper eletroplating is not made to the seed layer, as depicted from FIG. 1B as for the conventional method. Therefore no seed layer is required in this unique plating method.
  • FIG. 3 which shows a cross-sectional view of a transistor structure with source 48 , drain 38 , gate electrode 42 and gate oxide 44 , a metal layer 40 and N-type substrate 46 are connected to the p-type implanted regions 38 .
  • the negative terminal (cathode) of the power supply (battery) is made to contact to the back side of the wafer which is a n-type silicon wafer 46 .
  • a diffusion barrier layer such as tantalum 50 is deposited in a conventinal way, but this barrier layer is patterned to the defined areas such as in the trenches and vias. As shown in FIG. 3, the trenches 10 and vias 50 are formed by depositing field oxide 36 , nitride 34 , and oxide 32 layers with a barrier layer of tantalum 30 .
  • the wafer is then subject to a solution 52 containing cupric ions for copper electroplating 20 and the trenches and vias are filled up as illustrated in FIG. 4 (only showing filling of trenches). Tantalum plugs near the gate region are deposited by conventional method). The copper deposit fills up the trenches to the top and the power to the plating bath is then terminated. In this unique way of copper electroplating no seed layer is required to initiate plating and no CMP is needed to remove excess copper and barrier layer from the surface of the dielectric layer to planarize the copper/dielectric surface. The critical processing steps required by the conventional plating method are totally eliminated.
  • FIGS. 5 through 9 illustrates these different configurations.
  • a PMOS device having gate electrode 42 on a gate oxide 44 (with field oxide 36 and dielectric layer 58 ), with P+ source 70 and P+ drain 72 on a n-type substrate 56 is connected to a cathode to the power supply 22 for electroplating as a transistor configuration in accordance with one embodiment of the invention invention.
  • CMOS device P-well
  • gate electrode 42 on a gate oxide 44 (with field oxide 36 and dielectric layer 58 ), with P+ source 70 , P+ drain 72 , with N+ source 74 , N+ drain 76 , all on a n-type substrate 56 is connected to a cathode and the anode to a P ⁇ well 80 to the power supply 22 for electroplating as a transistor configuration in accordance with another embodiment of the invention.
  • CMOS device P-well
  • gate electrode 42 having gate electrode 42 on a gate oxide 44 (with field oxide 36 and dielectric layer 58 ), with P+ source 70 , P+ drain 72 , with N+ source 74 , N+ drain 76 , all on a n-type substrate 56 is connected to the power supply 22 for electroplating as a transistor configuration.
  • a bias is alos provided cathode and the anode to a P ⁇ well 80 and the n-type substrate 56 .
  • CMOS device twin-well having gate electrode 42 on a gate oxide 44 (with field oxide 36 and dielectric layer 58 ), with P+ source 70 , P+ drain 72 , with N+ source 74 , N+ drain 76 , all on a n-type substrate 56 with a n-epitaxy layer 84 is connected to a cathode and the anode to a P ⁇ well 80 to the power supply 22 for electroplating as a transistor configuration in accordance with another embodiment of the invention.
  • CMOS device twin-well having gate electrode 42 on a gate oxide 44 (with field oxide 36 and dielectric layer 58 ), with P+ source 70 , P+ drain 72 , with N+ source 74 , N+ drain 76 , all on a n-type substrate 56 with a n-epitaxy layer 84 is connected to a cathode and the anode to a P ⁇ well 80 to the power supply 22 for electroplating as a transistor configuration in accordance with another embodiment of the invention.
  • a bias is alos provided cathode and the anode to a P ⁇ well 80 and the n-type substrate 56 .
  • FIG. 9 there is shown a diode device having oxide layers 32 in association with a P ⁇ well 80 on layered on a n-type substrate 56 for connection to an anode of a power supply 22 for plating in accordance with the invention.

Abstract

A method of fabrication of copper interconnect by means of copper electroplating is disclosed. In the conventional method of fabricating copper interconnect for integrated circuits, critical steps such as deposition of copper seed layer and chemical mechanical polishing (CMP) are required. However in this invention, both the seed layer deposition and CMP are not required.

Description

    BACKGROUND
  • In the manufacture of devices on a semiconductor wafer, it is now the practice to fabricate multiple levels of conductive (typically metal) layers above a substrate. The multiple metallization layers are employed in order to accommodate higher densities as device dimensions shrink well below one micron design rules. Thus, semiconductor “chips” having three and four levels of metallization are becoming more prevalent as device geometries shrink to sub-micron levels. [0001]
  • One common metal used for forming metal lines (also referred to as wiring) on a wafer is aluminum. Aluminum is used because it is relatively inexpensive compared to other conductive materials, it has low resistivity and is also relatively easy to etch. Aluminum is also used as a material for forming interconnections in vias to connect the different metal layers. However, as the size of via/contact holes is scaled down to a sub-micron region, the step coverage problem appears, which has led to reliability problems when using aluminum to form the interconnection between different wiring layers. The poor step coverage in the sub-micron via/contact holes result in high current density and enhance the electromigration. [0002]
  • One material which has received considerable attention as a replacement material for VLSI interconnect metallizations is copper. Since copper has higher resistance electromigration property and lower resistivity than aluminum, it is a more preferred material for interconnect (plugs and wiring) formation than aluminum. However, one serious disadvantage of using copper metallization is that it is difficult to etch. Thus, where it was relatively easier to etch aluminum after deposition to form wiring lines or plugs (both wiring and plugs are referred to as interconnects), substantial additional cost and time are now required to etch copper. [0003]
  • One typical practice in the art is to fabricate copper plugs and wiring by inlaid (Damascene) structures by employing CMP. Dual Damascene processing eliminates not only the need for metal etch (which is increasingly challenging in aluminum interconnects and nearly impossible with copper), but also the need for dielectric gap fill (another challenging process). This technique involves the creation of interconnect lines by first etching a trench or canal in a planar dielectric layer, and then filling that trench with metal, such as aluminum or copper. In dual damascene processing, a second level is involved where a series of holes (i.e., contacts or vias) are etched and filled in addition to the trench. A diffusion barrier such as tantalum is deposited by PVD first to prevent copper diffusion. A variety of techniques have been developed to deposit copper, including chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, electroplating, and electroless plating. If electroplating is employed, a copper seed layer is required to deposit on top of the diffusion barrier as a prerequisite for the subsequent electroplating operation. After copper deposition, a chemical mechanical polishing (CMP) process is required to remove excess copper and barrier layer and planarize the dielectric surface. [0004]
    • SUMMARY
  • A method of fabrication of copper interconnect by means of copper electroplating is disclosed. In the conventional method of fabricating copper interconnect for integrated circuits, critical steps such as deposition of copper seed layer and chemical mechanical polishing (CMP) are required. However in this invention, both the seed layer deposition and CMP are not required. [0005]
  • These together with other objects of the invention, along with the various features of novelty which characterize the invention, are pointed out with particularity in the claims annexed to and forming a part of this disclosure. For a better understanding of the invention, its operating advantages and the specific objects obtained by its uses, reference should be made to the accompanying drawings and descriptive matter in which there are illustrated preferred embodiments of the invention.[0006]
    • DESCRIPTION OF THE DRAWING
  • FIG. 1A is a schematic illustration of a side elevation of a silicon wafer having trenches coated with Ta/TaN barrier layer and a copper seed layer before electroplating; [0007]
  • FIG. 1B is a schematic illustration of a side elevation of the silicon wafer of FIG. 1 being electroplated with copper to fill trenches; [0008]
  • FIG. 2 is a schematic illustration of a side elevation of the silicon wafer after copper plating utilizing CMP (Chemical Mechanical Polishing) to remove excess copper/barrier layer and planarize copper/silicon oxide surface; [0009]
  • FIG. 3 is a schematic illustration of a side elevation of the structure of a silicon wafer to be copper plate in accordance with the invention: [0010]
  • FIG. 4 illustrates the copper plating of the silicon wafer of FIG. 3; and [0011]
  • FIGS. 5 through 9 illustrates various integrated circuit technologies suitable for this invention.[0012]
    • DETAILED DESCRIPTION
  • This invention describes a fabrication method of copper interconnects using copper electroplating. In the case of electrodeposition (electroplating) of copper onto a silicon wafer, the wafer is typically coated with a thin conductive layer of copper (seed layer) and immersed in a solution containing cupric ions. Electrical contact is made to the seed layer, and current is passed such the reaction Cu[0013] 2++2e−→Cu occurs at the wafer surface. The wafer, electrically connected so that metal ions (cupric ions) are reduced to metal (copper) atoms, is referred to as the cathode.
  • Another electrically active surface, known as the anode (copper metal), is present in the conductive solution to complete the electrical circuit. At the anode, an oxiation reaction occurs that balances the current flow at the cathode, thus maintaining electrical neutrality in the solution. In the case of copper plating, all cupric ions removed from solution at the wafer surface are replaced by dissolution from a solid copper anode. FIG. 1A is a schematic illustration of a side elevation of a [0014] silicon wafer 18 having trenches 10 coated with Ta/TaN barrier layer 14 and a copper seed layer 12 before electroplating. FIG. 1B is a schematic illustration of a side elevation of the silicon wafer of FIG. 1 being electroplated with copper 20. The copper 20 fill trenches 10 coated with Ta/TaN barrier layer 14 on a wafer formed from silicon 18 and silicon dioxide 16 layers by a copper 22 strip connected to an anode in a solution 28 containing cupric ions.
  • CMP (chemical mechanical polishing) is required after copper electroplating to remove excess copper and diffusion barrier layer and to planarize the metal-dielectric. FIG. 2 is a schematic illustration of a side elevation of the silicon wafer formed from [0015] silicon 18 and silicon dioxide 16 after copper plating utilizing CMP to remove excess copper/barrier layer and planarize copper/silicon oxide surface 10 with the Ta/TaN barrier layer 14. Copper CMP is more complex because of the need to remove the tantalum or tantalum nitride barrier layers and copper uniformly without overpolishing any features. This is difficult because current copper deposition processes are not as uniform as the oxide deposition process. Copper also has the properties that add to the polish difficulties. It is a soft metal and subject to scratching and embedded particles during polishing. Also because copper is highly electrochemically active and does not form a natural protecive oxide, it corrodes easily. Therefore protecting the copper surface during polishing, clean and subsequent processing will be essential.
  • In accordance with the invention, the electrical contact for the copper eletroplating is not made to the seed layer, as depicted from FIG. 1B as for the conventional method. Therefore no seed layer is required in this unique plating method. Referring to FIG. 3, which shows a cross-sectional view of a transistor structure with [0016] source 48, drain 38, gate electrode 42 and gate oxide 44, a metal layer 40 and N-type substrate 46 are connected to the p-type implanted regions 38. The negative terminal (cathode) of the power supply (battery) is made to contact to the back side of the wafer which is a n-type silicon wafer 46. Before copper electroplating, a diffusion barrier layer (plug) such as tantalum 50 is deposited in a conventinal way, but this barrier layer is patterned to the defined areas such as in the trenches and vias. As shown in FIG. 3, the trenches 10 and vias 50 are formed by depositing field oxide 36, nitride 34, and oxide 32 layers with a barrier layer of tantalum 30.
  • The wafer is then subject to a [0017] solution 52 containing cupric ions for copper electroplating 20 and the trenches and vias are filled up as illustrated in FIG. 4 (only showing filling of trenches). Tantalum plugs near the gate region are deposited by conventional method). The copper deposit fills up the trenches to the top and the power to the plating bath is then terminated. In this unique way of copper electroplating no seed layer is required to initiate plating and no CMP is needed to remove excess copper and barrier layer from the surface of the dielectric layer to planarize the copper/dielectric surface. The critical processing steps required by the conventional plating method are totally eliminated.
  • This unique electroplating method can be applied to various MOS (metal oxide semiconductor) field-effect transistors (FET) technologies such as PMOS (p-channel) and CMOS (complementary metal oxide semiconductor) IC technollogies. FIGS. 5 through 9 illustrates these different configurations. Referring to FIG. 5A, a PMOS device having [0018] gate electrode 42 on a gate oxide 44 (with field oxide 36 and dielectric layer 58), with P+ source 70 and P+ drain 72 on a n-type substrate 56 is connected to a cathode to the power supply 22 for electroplating as a transistor configuration in accordance with one embodiment of the invention invention.
  • Similarly, as shown in FIG. 5B, a CMOS device (P-well) having [0019] gate electrode 42 on a gate oxide 44 (with field oxide 36 and dielectric layer 58), with P+ source 70, P+ drain 72, with N+ source 74, N+ drain 76, all on a n-type substrate 56 is connected to a cathode and the anode to a P− well 80 to the power supply 22 for electroplating as a transistor configuration in accordance with another embodiment of the invention.
  • In another embodiment shown in FIG. 6, a CMOS device (P-well) having [0020] gate electrode 42 on a gate oxide 44 (with field oxide 36 and dielectric layer 58), with P+ source 70, P+ drain 72, with N+ source 74, N+ drain 76, all on a n-type substrate 56 is connected to the power supply 22 for electroplating as a transistor configuration. A bias is alos provided cathode and the anode to a P− well 80 and the n-type substrate 56.
  • In yet anothert embodiment shown in FIG. 7, a CMOS device (twin-well) having [0021] gate electrode 42 on a gate oxide 44 (with field oxide 36 and dielectric layer 58), with P+ source 70, P+ drain 72, with N+ source 74, N+ drain 76, all on a n-type substrate 56 with a n-epitaxy layer 84 is connected to a cathode and the anode to a P− well 80 to the power supply 22 for electroplating as a transistor configuration in accordance with another embodiment of the invention.
  • In still yet another embodiment shown in FIG. 7, a CMOS device (twin-well) having [0022] gate electrode 42 on a gate oxide 44 (with field oxide 36 and dielectric layer 58), with P+ source 70, P+ drain 72, with N+ source 74, N+ drain 76, all on a n-type substrate 56 with a n-epitaxy layer 84 is connected to a cathode and the anode to a P− well 80 to the power supply 22 for electroplating as a transistor configuration in accordance with another embodiment of the invention. A bias is alos provided cathode and the anode to a P− well 80 and the n-type substrate 56.
  • Referring to FIG. 9, there is shown a diode device having [0023] oxide layers 32 in association with a P− well 80 on layered on a n-type substrate 56 for connection to an anode of a power supply 22 for plating in accordance with the invention.
  • It should further be noted that numerous changes in details of construction and the combination and arrangement of elements may be resorted to without departing from the true spirit and scope of the invention as hereinafter claimed. [0024]

Claims (20)

What is claimed is:
1. A copper electroplating method for fabrication of copper interconnect for integrated circuits, comprising:
providing silicon wafer as an active surface having a bottom metal layer;
depositing a diffusion layers patterned to define areas having trenches and vias;
connecting a negative terminal of a power supply to contact to the bottom metal layer of the wafer; and
and copper electroplating said silicon wafer.
2. The copper electroplating method according to claim 1, further comprising:
said silicon wafer is a n-type silicon wafer.
3. The copper electroplating method according to claim 1, further comprising:
depositing tantalum patterned to the defined areas in the trenches and vias.
4. The copper electroplating method according to claim 1, further comprising:
depositing field oxide, nitride, and oxide layers with a barrier layer of tantalum to form the trenches and vias
5. The copper electroplating method according to claim 4, further comprising:
depositing within the nitride layer a gate oxide having deposited thereon a gate electrode.
6. The copper electroplating method according to claim 1, further comprising:
providing a PMOS structure for electroplating.
7. The copper electroplating method according to claim 1, further comprising:
providing a CMOS structure for electroplating with a bias power supply connected between a P− well layer and a n-type substrate.
8. The copper electroplating method according to claim 1, further comprising:
providing a CMOS structure for electroplating wherein a P− well layer is connected to an anode of a power supply.
9. The copper electroplating method according to claim 1, further comprising:
providing a CMOS structure for electroplating wherein a P− well layer is connected to an anode of a power supply and twin well layers consisting of N− epitaxy and N+ substrate are connected to a cathode.
10. The copper electroplating method according to claim 1, further comprising:
providing a CMOS structure for electroplating wherein a P− well layer is connected to an anode of a power supply with a bias power supply connected between a P− well layer and a n-type substrate.
11. The copper electroplating method according to claim 1, further comprising:
providing a diode device having a n-type substrate connected to an anode for copper eletroplating.
12. A copper electroplating method for fabrication of copper interconnect for integrated circuits, comprising:
providing transistor structure defining an active surface having a bottom metal layer;
depositing a diffusion layers patterned to define areas having trenches and vias and forming a source, drain, gate electrodes;
connecting a negative terminal of a power supply to contact to the bottom metal layer of the wafer; and
and copper electroplating said transistor structure.
13. The copper electroplating method according to claim 12, further comprising:
depositing within the nitride layer a gate oxide having deposited thereon a gate electrode.
14. The copper electroplating method according to claim 12, further comprising:
providing a PMOS structure for electroplating.
15. The copper electroplating method according to claim 12, further comprising:
providing a CMOS structure for electroplating with a bias power supply connected between a P− well layer and a n-type substrate.
16. The copper electroplating method according to claim 12, further comprising:
providing a CMOS structure for electroplating wherein a P− well layer is connected to an anode of a power supply.
17. The copper electroplating method according to claim 12, further comprising:
providing a CMOS structure for electroplating wherein a P− well layer is connected to an anode of a power supply and twin well layers consisting of N− epitaxy and N+ substrate are connected to a cathode.
18. The copper electroplating method according to claim 12, further comprising:
providing a CMOS structure for electroplating wherein a P− well layer is connected to an anode of a power supply with a bias power supply connected between a P− well layer and a n-type substrate.
19. The copper electroplating method according to claim 12, further comprising:
providing a diode structure having a n-type substrate connected to an anode for copper eletroplating.
20. A copper electroplating method for fabrication of copper interconnect for integrated circuits, comprising:
providing transistor structure defining an active surface having a bottom metal layer;
depositing a diffusion layers patterned to define areas having trenches and vias and forming a source, drain, gate electrodes;
depositing field oxide, nitride, and oxide layers with a barrier layer of tantalum to form the trenches and vias
depositing tantalum patterned to the defined areas in the trenches and vias;
connecting a negative terminal of a power supply to contact to the bottom metal layer of the wafer; and
and copper electroplating said transistor structure.
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US20120318673A1 (en) * 2006-05-04 2012-12-20 International Business Machines Corporation Apparatus and method for electrochemical processing of thin films on resistive substrates
US20150130064A1 (en) * 2008-02-22 2015-05-14 International Business Machines Corporation Methods of manufacturing semiconductor devices and a semiconductor structure

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