US20040087096A1 - Non-volatile memory compatible with logic devices and fabrication method thereof - Google Patents

Non-volatile memory compatible with logic devices and fabrication method thereof Download PDF

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US20040087096A1
US20040087096A1 US10/287,711 US28771102A US2004087096A1 US 20040087096 A1 US20040087096 A1 US 20040087096A1 US 28771102 A US28771102 A US 28771102A US 2004087096 A1 US2004087096 A1 US 2004087096A1
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active region
dielectric layer
volatile memory
gate
spacers
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Wen-Yueh Jang
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Winbond Electronics Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape

Definitions

  • the present invention generally relates to semiconductor processes and structures, and more particularly, to a non-volatile memory compatible with logic devices and a fabrication method for the same.
  • SOC system-on-chip
  • NVM non-volatile memory
  • One object of the present invention is to utilize a non-volatile memory compatible with logic devices so that the non-volatile memory is easily embedded into the logic devices processes.
  • the other object of the present invention is to use a non-volatile memory compatible with logic devices so that the non-volatile memory is rapidly programmed by a hot carrier effect induced from impact ionization.
  • Another object of the present invention is to use a non-volatile memory compatible with logic devices so that the hot carrier effect of the drain is further enhanced to increase impact ionization by the proposed device structure.
  • the present invention sets forth a non-volatile memory compatible with logic devices and method.
  • a substrate has a first active region and a second active region. Thereafter, a first dielectric layer is formed on the first active region and the second active region.
  • a conductive layer is deposited on the first dielectric layer to form a first gate on the first active region and to form a second gate on the second active region, and then the first dielectric layer is partially exposed.
  • a second dielectric layer is deposited on the first dielectric layer such that electrons can be trapped in the second dielectric layer.
  • a third dielectric layer is formed on the second dielectric layer.
  • a anisotropic etching process is then performed to form spacers adjacent to the first gate and second gate.
  • conducting an implantation and an annealing step can create a source/drain on the substrate adjoining the spacers to make the non-volatile memory compatible with the logic devices.
  • Processes of fabricating logic devices allow the non-volatile devices in the first active region to be embedded so that the non-volatile memory is more preferably compatible with the logic devices. Due to the hot carrier effect happen near the drain of the first active region, many electrons trapped in the second dielectric layer under the spacers are able to keep up the programming state of the non-volatile memory. Specifically, since drain electrical field is imposed along the channel region in the first active region, an impact ionization of the hot (high energy) electrons occurs and then a portion of electrons are attracted to the second dielectric layer near drain side by the gate electric field. Drain current of the programmed transistor will decrease due to higher serial resistance near the drain. The drain current of the programmed transistor will decrease further if the source and the drain are interchanged.
  • Performing the pocket implantation before forming the spacers preferably generates a higher electrical field near the drain to increase electron impact ionization thus electron-trapping in the second dielectric layer under the spacers. Further, that a LDD (Lightly Doped Drain) formed on the first active region forms a depletion region under the spacers will enhance electron impact ionization rate. When the first gate of the first active region turns on, more electrons are trapped in the second dielectric layer by the hot carrier effect to increase the programming efficiency of the non-volatile memory.
  • LDD Lightly Doped Drain
  • each proposed non-volatile memory cell can store two bits by electron trapped in the second dielectric layer near both the drain and the source. Because the electrons trapped near the source side during a reading operation will reduce more drain current than that near the drain side, the stored two bits can be read out separately.
  • non-volatile memory compatible with logic devices is provided in the present invention.
  • a great number of electrons are trapped in the second dielectric layer by the hot carrier effect.
  • two-bit data stored in the second dielectric layer under the spacers are easily read leading to high storage density of the nonvolatile memory.
  • standard logic device processes are applied to embedded the non-volatile memory into the logic devices so that the compatibility of the non-volatile memory and logic devices is readily met for a preferred scalability.
  • FIGS. 1 - 9 are schematic, cross-sectional views of a non-volatile memory compatible with logic devices according to the present invention.
  • the present invention is directed to a non-volatile memory compatible with logic devices to improve the shortcomings of the SOC in the prior art. Processes of the logic devices are applied to fabricate the non-volatile memory embedded into the logic devices. Moreover, in the non-volatile memory, a great number of electrons are injected into a dielectric layer adjoining a gate to speed up the programming steps of the non-volatile memory.
  • FIGS. 1 - 9 are schematic, cross-sectional views of a non-volatile memory compatible with logic devices according to the present invention.
  • a substrate 200 has a first active region 202 and a second active region 204 , in which the first active region 202 and the second active region 204 allow formation of non-volatile memory and a logic device, respectively.
  • An isolated region 206 is preferably located between the first active region 202 and the second active region 204 .
  • a first dielectric layer 208 is formed on the first active region 202 and the second active region 204 .
  • performing a thermal oxidation forms the first dielectric layer 208 which includes a material of silicon oxide (SiO 2 ) and has a thickness range of about 12 to 80 angstroms.
  • forming a conductive layer 210 on the first dielectric layer 208 creates gates of the non-volatile memory and the logic devices.
  • a chemical vapor deposition (CVD) is used to form the conductive layer 210 whose material includes polysilicon or polycide and has a thickness range of about 1000 to 3000 angstroms.
  • conducting a lithography and etching process forms a first gate 212 on the first active region 202 and to creates a second gate 214 on the second active region 204 , and then the first dielectric layer 208 is partially exposed.
  • an anisotropic etching process is carried out to form a vertical sidewall of the first gate 212 .
  • the etching reagents used in the anisotropic process comprise HBr, HCl, O 2 or combinations thereof.
  • a isotropic etching process is carried out to form a slant sidewall 216 connected to the vertical sidewall of the first gate 212 to expose a portion of the first dielectric layer 208 .
  • the etching reagents of the isotropic etching process comprise HBr, HCl, O 2 , SF 6 or combinations thereof. Further, the flow rate and the bias voltage used in the isotropic etching process are lower than those of the anisotropic process to form an encroachment gate profile.
  • a second dielectric layer 218 is formed on the first dielectric layer 208 .
  • performing a chemical vapor deposition (CVD) forms the second dielectric layer 218 which includes a material of silicon nitrides (Si 3 N 4 ) and oxynitrides (SiO x N y ) and has a thickness range of about 10 to 500 angstroms.
  • the second dielectric layer 218 can be created by a nitride implantation on the source/drain region and the implanting depth of the nitride has a range of about 10 to 300 angstroms.
  • a lithography step is performed to expose the first active region 202 and a photoresist layer 220 is deposited on the second dielectric layer 218 and the second gate 214 of the second active region 204 .
  • a pocket implantation 222 is performed on the second dielectric layer 218 of the first active region 202 .
  • the dopant of the pocket implantation 222 includes boron (B) which has an implanting energy range of about 10 to 150 keV and an implanting concentration range of about 1 ⁇ 10 13 to 5 ⁇ 10 14 /cm 2 .
  • a lightly doped drain (LDD) 224 is performed on the substrate 200 of the active region.
  • the dopant of the LDD step includes arsenic (As) which has an implanting energy range of about 5 to 100 keV and an implanting concentration range of about 1 ⁇ 10 13 to 2 ⁇ 10 14 cm 2 .
  • a source/region extension 228 is formed on the second active region 204 and a photoresistor layer 220 covers the first active region 202 .
  • the dopant of the source/region extension 228 includes arsenic (As) which has an implanting energy range of about 10 to 150 keV and an implanting concentration range of about 5 ⁇ 10 13 to 1 ⁇ 10 15 /cm 2
  • As arsenic
  • a third dielectric layer is formed on the second dielectric.
  • performing a chemical vapor deposition (CVD) forms the third dielectric layer which includes a material of silicon oxide (SiO x ) and has a thickness range of about 150 to 2000 angstroms.
  • An anisotropic etching process is then performed to form spacers 226 a, 226 b adjacent to the first gate 212 and second gate 214 .
  • an implantation and an annealing procedure are performed to form a source/drain 230 a, 230 b on the substrate 200 adjoining the spacers 226 a, 226 b so that the non-volatile memory compatible with the logic devices is formed.
  • the non-volatile memory accompanies logic device processes makes the non-volatile memory compatible with the logic devices. Specifically, due to the hot carrier effect near the drain 230 a of the first active region 202 , electrons will be trapped in the second dielectric layer 218 under the spacers 226 a during the programming step of the non-volatile memory. Also, since the drain electrical field is applied along the channel region in the first active region 202 , an impact ionization of the electrons near the drain 230 a occurs so that a portion of electrons is injected into the second dielectric layer 218 .
  • performing the pocket implantation 222 before forming the spacers 226 a generates a higher electrical field near the drain to increase electron impact ionization. Then, there is a higher possibility of these electrons generated by impact ionization to be trapped in the second dielectric layer 218 under the spacers 226 a near the drain side. Further, an LDD formed on the first active region 202 is able to form a depletion region near the drain 230 b to cover the second dielectric layer 218 under the spacers 226 a is also helpful to electrons impact ionization and trapped in the second dielectric layer 218 . When the first gate 212 of the first active region 202 turns on for programming, more electrons are trapped in the second dielectric layer 218 by the enhanced hot carrier effect to increase the programming efficiency of the non-volatile memory.
  • a source/drain extension 228 formed on the second active region 204 of the logic devices reduces the depletion region of the second active region 204 to reduce the serial resistance of the second active region 204 and to improve the device performance when the second gate 214 of the second active region 204 turns on.
  • the non-volatile memory compatible with logic devices can trap a great number of electrons in the second dielectric layer 218 efficiently by an enhanced hot carrier effect.
  • two bits can be saved as electrons trapped in the second dielectric layer near both the drain and source. Drain current reduction during a reading operation can be differentiated by different current reduction for electrons trapped in source and drain. Therefore, two-bit data stored in the second dielectric layer 218 under the spacers can be easily read separately leading to high storage density of the non-volatile memory.
  • standard logic device processes are applied to embed the nonvolatile memory into the logic devices so that the compatibility of the non-volatile memory and logic devices is readily met for a preferred scalability.

Abstract

A non-volatile memory compatible with logic devices and processes are described. The non-volatile memory has a substrate, a first dielectric layer, a first gate, a second gate, a second dielectric layer, a plurality of spacers and a source/drain. A first active region and a second active region are formed on the substrate. When hot carrier effect occurs near the drain, the second dielectric layer located under the spacers is able to retain electrons so that the non-volatile memory is programmed.

Description

    FIELD OF THE INVENTION
  • The present invention generally relates to semiconductor processes and structures, and more particularly, to a non-volatile memory compatible with logic devices and a fabrication method for the same. [0001]
    • BACKGROUND OF THE INVENTION
  • With the rapid developments of semiconductor techniques, system-on-chip (SOC) products are widely used in daily routines and improve the quality of the life. Generally, the SOC consists of logic devices and non-volatile memory (NVM). The non-volatile memory is always embedded into the logic devices. [0002]
  • Traditionally, as the non-volatile memory needs to be embedded into the logic devices, one method is using multiple transistors connected to form a single polysilicon non-volatile memory. Such a method has poor density due to large cell size of the NVM. The other method is combined logic device processes and non-volatile memory processes. However, since at least two polysilicon layers need to be deposited, the processes are both too complex and high overall manufacturing cost. [0003]
  • Consequently, how to make the non-volatile memory compatible with the logic devices and to create a high-density of the SOC so that both the non-volatile memory and the logic devices are optimized is currently a main issue for semiconductor manufacturers. [0004]
    • SUMMARY OF THE INVENTION
  • One object of the present invention is to utilize a non-volatile memory compatible with logic devices so that the non-volatile memory is easily embedded into the logic devices processes. [0005]
  • The other object of the present invention is to use a non-volatile memory compatible with logic devices so that the non-volatile memory is rapidly programmed by a hot carrier effect induced from impact ionization. [0006]
  • Another object of the present invention is to use a non-volatile memory compatible with logic devices so that the hot carrier effect of the drain is further enhanced to increase impact ionization by the proposed device structure. [0007]
  • According to the above objects, the present invention sets forth a non-volatile memory compatible with logic devices and method. A substrate has a first active region and a second active region. Thereafter, a first dielectric layer is formed on the first active region and the second active region. A conductive layer is deposited on the first dielectric layer to form a first gate on the first active region and to form a second gate on the second active region, and then the first dielectric layer is partially exposed. A second dielectric layer is deposited on the first dielectric layer such that electrons can be trapped in the second dielectric layer. [0008]
  • A third dielectric layer is formed on the second dielectric layer. A anisotropic etching process is then performed to form spacers adjacent to the first gate and second gate. Finally, conducting an implantation and an annealing step can create a source/drain on the substrate adjoining the spacers to make the non-volatile memory compatible with the logic devices. [0009]
  • Processes of fabricating logic devices allow the non-volatile devices in the first active region to be embedded so that the non-volatile memory is more preferably compatible with the logic devices. Due to the hot carrier effect happen near the drain of the first active region, many electrons trapped in the second dielectric layer under the spacers are able to keep up the programming state of the non-volatile memory. Specifically, since drain electrical field is imposed along the channel region in the first active region, an impact ionization of the hot (high energy) electrons occurs and then a portion of electrons are attracted to the second dielectric layer near drain side by the gate electric field. Drain current of the programmed transistor will decrease due to higher serial resistance near the drain. The drain current of the programmed transistor will decrease further if the source and the drain are interchanged. [0010]
  • Performing the pocket implantation before forming the spacers preferably generates a higher electrical field near the drain to increase electron impact ionization thus electron-trapping in the second dielectric layer under the spacers. Further, that a LDD (Lightly Doped Drain) formed on the first active region forms a depletion region under the spacers will enhance electron impact ionization rate. When the first gate of the first active region turns on, more electrons are trapped in the second dielectric layer by the hot carrier effect to increase the programming efficiency of the non-volatile memory. In addition, because the electrons will only be trapped in the second dielectric layer near the drain side, if the source and the drain are interchanged, each proposed non-volatile memory cell can store two bits by electron trapped in the second dielectric layer near both the drain and the source. Because the electrons trapped near the source side during a reading operation will reduce more drain current than that near the drain side, the stored two bits can be read out separately. [0011]
  • In summary, non-volatile memory compatible with logic devices is provided in the present invention. A great number of electrons are trapped in the second dielectric layer by the hot carrier effect. In addition, two-bit data stored in the second dielectric layer under the spacers are easily read leading to high storage density of the nonvolatile memory. More importantly, standard logic device processes are applied to embedded the non-volatile memory into the logic devices so that the compatibility of the non-volatile memory and logic devices is readily met for a preferred scalability.[0012]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description when taken in conjunction with the accompanying drawings, wherein: [0013]
  • FIGS. [0014] 1-9 are schematic, cross-sectional views of a non-volatile memory compatible with logic devices according to the present invention.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • The present invention is directed to a non-volatile memory compatible with logic devices to improve the shortcomings of the SOC in the prior art. Processes of the logic devices are applied to fabricate the non-volatile memory embedded into the logic devices. Moreover, in the non-volatile memory, a great number of electrons are injected into a dielectric layer adjoining a gate to speed up the programming steps of the non-volatile memory. [0015]
  • FIGS. [0016] 1-9 are schematic, cross-sectional views of a non-volatile memory compatible with logic devices according to the present invention. In FIG. 1, a substrate 200 has a first active region 202 and a second active region 204, in which the first active region 202 and the second active region 204 allow formation of non-volatile memory and a logic device, respectively. An isolated region 206 is preferably located between the first active region 202 and the second active region 204.
  • Thereafter, a first [0017] dielectric layer 208 is formed on the first active region 202 and the second active region 204. For example, performing a thermal oxidation forms the first dielectric layer 208 which includes a material of silicon oxide (SiO2) and has a thickness range of about 12 to 80 angstroms.
  • In FIG. 2, forming a [0018] conductive layer 210 on the first dielectric layer 208 creates gates of the non-volatile memory and the logic devices. For example, a chemical vapor deposition (CVD) is used to form the conductive layer 210 whose material includes polysilicon or polycide and has a thickness range of about 1000 to 3000 angstroms.
  • In FIG. 3, conducting a lithography and etching process forms a [0019] first gate 212 on the first active region 202 and to creates a second gate 214 on the second active region 204, and then the first dielectric layer 208 is partially exposed. In the preferred embodiment of the present invention, when the first gate 212 on the first active region 202 is formed, an anisotropic etching process is carried out to form a vertical sidewall of the first gate 212. The etching reagents used in the anisotropic process comprise HBr, HCl, O2 or combinations thereof.
  • A isotropic etching process is carried out to form a [0020] slant sidewall 216 connected to the vertical sidewall of the first gate 212 to expose a portion of the first dielectric layer 208. The etching reagents of the isotropic etching process comprise HBr, HCl, O2, SF6 or combinations thereof. Further, the flow rate and the bias voltage used in the isotropic etching process are lower than those of the anisotropic process to form an encroachment gate profile.
  • When the [0021] second gate 214 is formed on the second active region 204, an anisotropic etching process is used to form a vertical sidewall of the second gate 214.
  • In FIG. 4, a second [0022] dielectric layer 218 is formed on the first dielectric layer 208. For example, performing a chemical vapor deposition (CVD) forms the second dielectric layer 218 which includes a material of silicon nitrides (Si3N4) and oxynitrides (SiOxNy) and has a thickness range of about 10 to 500 angstroms. Also, the second dielectric layer 218 can be created by a nitride implantation on the source/drain region and the implanting depth of the nitride has a range of about 10 to 300 angstroms.
  • In FIG. 5, a lithography step is performed to expose the first [0023] active region 202 and a photoresist layer 220 is deposited on the second dielectric layer 218 and the second gate 214 of the second active region 204. Afterward, a pocket implantation 222 is performed on the second dielectric layer 218 of the first active region 202. In the preferred embodiment of the present invention, the dopant of the pocket implantation 222 includes boron (B) which has an implanting energy range of about 10 to 150 keV and an implanting concentration range of about 1×1013 to 5×1014/cm2.
  • In FIG. 6, a lightly doped drain (LDD) [0024] 224 is performed on the substrate 200 of the active region. The dopant of the LDD step includes arsenic (As) which has an implanting energy range of about 5 to 100 keV and an implanting concentration range of about 1×1013 to 2×1014 cm2.
  • In FIG. 7, a source/[0025] region extension 228 is formed on the second active region 204 and a photoresistor layer 220 covers the first active region 202. The dopant of the source/region extension 228 includes arsenic (As) which has an implanting energy range of about 10 to 150 keV and an implanting concentration range of about 5×1013 to 1×1015/cm2 The second dielectric layer 218 on the second active region 204 is then removed.
  • In FIG. 8, a third dielectric layer is formed on the second dielectric. For example, performing a chemical vapor deposition (CVD) forms the third dielectric layer which includes a material of silicon oxide (SiO[0026] x) and has a thickness range of about 150 to 2000 angstroms. An anisotropic etching process is then performed to form spacers 226 a, 226 b adjacent to the first gate 212 and second gate 214. Finally, in FIG. 9, an implantation and an annealing procedure are performed to form a source/ drain 230 a, 230 b on the substrate 200 adjoining the spacers 226 a, 226 b so that the non-volatile memory compatible with the logic devices is formed.
  • Still referring to FIG. 9, the non-volatile memory accompanies logic device processes makes the non-volatile memory compatible with the logic devices. Specifically, due to the hot carrier effect near the [0027] drain 230 a of the first active region 202, electrons will be trapped in the second dielectric layer 218 under the spacers 226 a during the programming step of the non-volatile memory. Also, since the drain electrical field is applied along the channel region in the first active region 202, an impact ionization of the electrons near the drain 230 a occurs so that a portion of electrons is injected into the second dielectric layer 218.
  • Significantly, a large amount of electrons are retained in the [0028] second dielectric layer 218 for the purpose of data storage. Because the device is shrunk greatly as technology advances, a channel decrement is magnified to generate a high drain electrical field in the first active region 202 such that more and more hot (high energy) electrons are injected into the second dielectric layer 218.
  • In the preferred embodiment of the present invention, performing the [0029] pocket implantation 222 before forming the spacers 226 a generates a higher electrical field near the drain to increase electron impact ionization. Then, there is a higher possibility of these electrons generated by impact ionization to be trapped in the second dielectric layer 218 under the spacers 226 a near the drain side. Further, an LDD formed on the first active region 202 is able to form a depletion region near the drain 230 b to cover the second dielectric layer 218 under the spacers 226 a is also helpful to electrons impact ionization and trapped in the second dielectric layer 218. When the first gate 212 of the first active region 202 turns on for programming, more electrons are trapped in the second dielectric layer 218 by the enhanced hot carrier effect to increase the programming efficiency of the non-volatile memory.
  • A source/[0030] drain extension 228 formed on the second active region 204 of the logic devices reduces the depletion region of the second active region 204 to reduce the serial resistance of the second active region 204 and to improve the device performance when the second gate 214 of the second active region 204 turns on.
  • According the above-mentioned, the non-volatile memory compatible with logic devices can trap a great number of electrons in the [0031] second dielectric layer 218 efficiently by an enhanced hot carrier effect. With source and drain interchanged during programming, two bits can be saved as electrons trapped in the second dielectric layer near both the drain and source. Drain current reduction during a reading operation can be differentiated by different current reduction for electrons trapped in source and drain. Therefore, two-bit data stored in the second dielectric layer 218 under the spacers can be easily read separately leading to high storage density of the non-volatile memory. More importantly, standard logic device processes are applied to embed the nonvolatile memory into the logic devices so that the compatibility of the non-volatile memory and logic devices is readily met for a preferred scalability.
  • As is understood by a person skilled in the art, the foregoing preferred embodiments of the present invention are illustrative rather than limiting of the present invention. It is intended that various modifications and similar arrangements be included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structure. [0032]

Claims (28)

What is claimed is:
1. A method for forming a non-volatile memory compatible with logic devices, the method comprising the steps of:
providing a substrate having a first active region and a second active region;
forming a first dielectric layer on the first active region and the second active region, respectively;
forming a conductive layer on the first dielectric layer;
performing a first lithography and etching step to generate a first gate on the first active region and to generate a second gate on the second active region, while exposing the first dielectric layer;
forming a second dielectric layer on the first dielectric layer so that electrons on the first active region can be trapped in the second dielectric layer;
forming a third dielectric layer on the second dielectric layer;
performing a second lithography and etching step to form a plurality of spacers adjoining the first gate and the second gate, respectively, so that the second dielectric layer under the spacers is able to trap the electrons; and
forming a source/drain adjacent to the spacers on the first active region and the second active region.
2. The method of claim 1, further comprising an isolated region between the first active region and the second active region.
3. The method of claim 1, wherein the first active region comprises a non-volatile memory.
4. The method of claim 1, wherein the second active region comprises a logic device.
5. The method of claim 1, wherein the step of forming the first gate on the first active region comprises:
performing a anisotropic etching to form a vertical sidewall of the first gate; and
performing a isotropic etching such that the first gate has a slant sidewall connected to the vertical sidewall to adjoin the second dielectric layer.
6. The method of claim 5, wherein the second dielectric layer comprises silicon nitrides or oxynitrides.
7. The method of claim 1, wherein the second dielectric layer has a thickness range of about 10 to 500 angstroms.
8. The method of claim 1, wherein the step of forming the second dielectric layer comprises an ion implantation.
9. The method of claim 1, after the step of forming the second dielectric layer, further comprising a pocket implantation on the first active region under the spacers.
10. The method of claim 9, wherein an implanting concentration of the pocket implantation has a range of about 1×1013 to 5×1014/cm2.
11. The method of claim 1, after the step of forming the second dielectric layer, further comprising a LDD step on the first active region under the spacers.
12. The method of claim 11, wherein a doping concentration of the LDD step has a range of about 1×1013 to 2×1014/cm2.
13. The method of claim 1, after the step of forming the second dielectric layer, further comprising a source/drain extension implantation adjacent to the source/drain on the second active region.
14. The method of claim 13, wherein an implanting concentration of the source/drain extension implantation has a range of about 5×1013 to 1×1015/cm2.
15. A non-volatile memory compatible with logic devices, the non-volatile memory comprising:
a substrate including a first active region a second active region, wherein an isolated region is positioned between the first active region and the second active region;
a first dielectric layer which is located on the first active region and on the second active region, respectively;
a first gate on the first dielectric layer of the first active region;
a second gate on the first dielectric layer of the second active region;
a second dielectric layer located on the first dielectric layer;
a plurality of spacers adjoining the first gate and the second gate, wherein the second dielectric layer under the spacers is able to trap electrons; and
a source/drain adjacent to the spacers on the first active region and the second active region.
16. The non-volatile memory of claim 15, wherein the first active region comprises a non-volatile memory.
17. The non-volatile memory of claim 15, wherein the second active region comprises a logic device.
18. The non-volatile memory of claim 15, wherein the first gate on the first active region comprises:
a vertical sidewall; and
a slant sidewall connected to the vertical sidewall so that a bottom width is smaller than a top width of the first gate along the channel region to enhance hot electron effect.
19. The non-volatile memory of claim 15, wherein the first gate on the first active region comprises a vertical sidewall.
20. The non-volatile memory of claim 15, wherein the second dielectric layer comprises silicon nitrides or oxynitrides.
21. The non-volatile memory of claim 15, wherein the second dielectric layer has a thickness range of about 10 to 100 angstroms.
22. The non-volatile memory of claim 15, wherein the second dielectric layer is formed by an ion implantation.
23. The non-volatile memory of claim 15, further comprising a pocket implantation on the first active region under the spacers.
24. The non-volatile memory of claim 23, wherein an implanting concentration of the pocket implantation has a range of about 1×1013 to 5×1014/cm2.
25. The non-volatile memory of claim 15, further comprising an LDD on the first active region under the spacers.
26. The non-volatile memory of claim 25, wherein a doping concentration of the LDD has a range of about 1×1013 to 2×1014/cm2.
27. The non-volatile memory of claim 15, wherein the second active region further comprises a source/drain extension implantation adjacent to the source/drain on the second active region.
28. The non-volatile memory of claim 27, wherein an implanting concentration of the source/drain extension implantation in the second active region has a range of about 5×1013 to 1×1015 cm2.
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