US20040113909A1 - Interface and method of interfacing between a parametric modelling unit and a polygon based rendering system - Google Patents

Interface and method of interfacing between a parametric modelling unit and a polygon based rendering system Download PDF

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US20040113909A1
US20040113909A1 US10/435,759 US43575903A US2004113909A1 US 20040113909 A1 US20040113909 A1 US 20040113909A1 US 43575903 A US43575903 A US 43575903A US 2004113909 A1 US2004113909 A1 US 2004113909A1
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patch
data
subdivision
leaf
level
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Simon Fenney
Jonathan Redshaw
John Russell
Clifford Gibson
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Imagination Technologies Ltd
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Imagination Technologies Ltd
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Assigned to IMAGINATION TECHNOLOGIES LIMITED reassignment IMAGINATION TECHNOLOGIES LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FENNEY, SIMON, GIBSON, CLIFFORD, REDSHAW, JONATHAN MARK, RUSSELL, JOHN
Publication of US20040113909A1 publication Critical patent/US20040113909A1/en
Priority to US11/232,760 priority Critical patent/US7227546B2/en
Priority to US11/638,545 priority patent/US7362328B2/en
Priority to US12/148,043 priority patent/US7768511B2/en
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T17/00Three dimensional [3D] modelling, e.g. data description of 3D objects
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T17/00Three dimensional [3D] modelling, e.g. data description of 3D objects
    • G06T17/20Finite element generation, e.g. wire-frame surface description, tesselation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T17/00Three dimensional [3D] modelling, e.g. data description of 3D objects
    • G06T17/30Polynomial surface description

Definitions

  • This invention relates to an interface for use in a 3-d graphics system comprising a parametric modelling unit and a polygon based rendering system.
  • a known alternative to modelling objects using a mesh of polygons is to segment the object into areas and fit a number of curved, high order surfaces, frequently termed patches, to the different areas of the object being modelled. These patches are generally defined as parametric surfaces with the surface shape governed by a grid of control points.
  • An advantage of using high order surfaces is that the set of control points usually requires a much smaller amount of data to represent a particular model than the equivalent polygon mesh.
  • High order surfaces are also generally easier to manipulate when animating an object which is changing in shape.
  • a major disadvantage of modelling using high order surfaces is that it introduces added complexity in the rasterization stage of the rendering system.
  • a plurality of curved surfaces patches are fitted to the surface of the object to define areas of the object.
  • a number of different standards for defining the behaviour of such patches with respect to their defining control points are known.
  • One such standard is Bezier patches, for example see “Advanced Animation and Rendering Techniques” pp 66-68 by Watt & Watt or “Computer Graphics Principles and Practice” pp 471-530 by Foley Van Dam et al.
  • Methods of transforming the control points corresponding to one format of patch to new positions corresponding to a different patch type so that the final surfaces are identical are also known. These patches are often of bicubic order.
  • each of x(s,t), y(s,t), and z(s,t) are scalar parametric polynomials of the same degree, and 0 ⁇ s,t ⁇ 1.
  • the polynomial is of degree 6.
  • the Bezier equations and the respective x, y, and z components of the surface's control points define the shape of the surface.
  • a non-rational surface extends the definition by introducing a fourth polynomial w(s,t) with a corresponding additional positive “w” value in each of the control points.
  • Q is a matrix of scalar constants and P is the matrix of control points for the surface
  • Q [ - 1 3 - 3 1 3 - 6 3 0 - 3 3 0 0 1 0 0 0 ]
  • ⁇ ⁇ P [ P _ 00 ⁇ P _ 01 ⁇ P _ 02 ⁇ P _ 03 P _ 10 ⁇ P _ 11 ⁇ P _ 12 ⁇ P _ 03 P _ 20 ⁇ P _ 21 ⁇ P _ 22 ⁇ P _ 03 P _ 30 ⁇ P _ 31 ⁇ P _ 32 ⁇ P _ 03 ]
  • Conversion of the patches to tessellating triangles via the recursive subdivision method is achieved by initially dividing each patch into two sub-patches across either one of its two parameter dimensions (i.e. s or t). This is shown in FIGS. 1 a and 1 b, in which the patch, with control points, has been portrayed in its parameter space. Each of the sub-patches can then be further sub-divided until the correct level of sub-division is achieved. Once this has been achieved, the resulting sub-patches are each treated as non-planar quadrilaterals, and a set pattern of triangles is superimposed onto the sub-patches, the vertices of the triangles calculated, and the triangles output.
  • FIG. 2 is a schematic showing conceptual processing of a patch by subdivision with three levels of subdivision applied. From FIG. 2, it can be seen that the processing takes the form of a binary tree progressing from the original, or “root”, patch, through intermediate levels of patches to end-point patches termed “leaf” patches. Each leaf patch is used to generate the vertices defining the tessellating triangles required for the rasterization stage of rendering.
  • the present invention in a first aspect aims to ameliorate these problems. It provides an interface for converting parametric modelled data to polygon based data using recursive sub-division in a way which provides high computational performance whilst minimising memory and memory bandwidth usage.
  • a second problem which occurs when interfacing between parametric data and polygon based data in a combined graphics system is that different levels of subdivision may be required to convert parametric data relating to a first patch and parametric data relating to a second patch, where the first and second patches represent adjacent areas of the object being modelled. Patches which define highly curved surfaces must be more highly subdivided than patches which represent a flatter surface when converting the parametric data to polygon based data if the benefits of parametric modelling are not to be lost. If conversion of adjacent patches is not constrained to apply the same level of subdivision to each patch, then cracks can appear in the modelled object because the surface with the higher level of subdivision has extra sample points and thus potentially a slightly different shape. The problem of cracking is illustrated in FIG. 4.
  • Another solution is to process each patch to a level of subdivision sufficient to represent the surface adequately, and to then insert a so-called “stitching mesh” between adjacent surface patches which have different subdivision levels.
  • the stitching mesh thus covers any potential cracks as shown in FIG. 5 a .
  • two adjacent patches are subdivided to different levels—one uses 2 ⁇ 4 sub-patches while the other is represented by no subdivisions, i.e. a single quadrilateral.
  • the ‘abutting’ contour on the 2 ⁇ 4 patch consists of vertices, A, B, C, D, & E, while the equivalent for the 1 ⁇ 1 subdivision consists of the edge AE.
  • the additional triangles, ABC, ACE and CDE are created.
  • Clark ““A Fast Scan Line Algorithm for Rendering Parametric Surfaces”. Computer Graphics 13(2), 289-99] proposed an alternative technique which even permits different levels of subdivision within each patch. As part of this method, the cracking problem, had to be ‘solved’. Clark's solution is to deliberately ‘flatten’ the edges of higher subdivision regions where they meet lower subdivision regions. This is shown in FIG. 5 b . The ‘shared’ boundary between the high-subdivision region and the lowe-subdivision area has been ‘flattened’ on the high subdivision region so that it mathematically matches the boundary of the low-subdivision region. Comparing this to the approach in FIG. 5 a , it can be seen that the vertices, B, C, & D now lie on the line AE.
  • the present invention in a second aspect therefore supports “irregular patch” processing, that is processing of patch data to different subdivision levels in different subdivision directions within the patch but avoiding the problems with Clark's scheme.
  • “irregular patch” processing that is processing of patch data to different subdivision levels in different subdivision directions within the patch but avoiding the problems with Clark's scheme.
  • an interface according to claim 8 .
  • Preferred features of the second aspect of the invention are detailed in dependent claim 9 .
  • Irregular levels of sub-division are supported by automatically generating a mesh from the final sub-patch that has a suitable number of vertices along each edge of the quadrilateral. This allows simple joining of polygonised patches without cracks appearing.
  • a further problem with known interfacing techniques is so-called polygon popping.
  • polygon popping is a term used to describe the sudden movements in the points of the tessellated polygons that can occur when a small fractional change in the subdivision control value causes an extra step of processing (i.e. an extra binary subdivision of the patch) to be performed.
  • edge subdivision control value may take any value
  • the preferred tessellation technique is constrained to perform binary patch subdivision to the next nearest power of 2. Thus increasing the subdivision ratio even a small amount may cause the actual level of subdivision to increase dramatically.
  • FIG. 3 a the curved surface has been subdivided into two quadrilateral regions.
  • the ‘front-most’ curved edge of the patch is thus approximated by the line segments AB and BC.
  • FIG. 3 b the level of subdivision is increased (in one dimension only) so that along the front edge, two new points, D & E, have been generated.
  • the front edge of the patch is then represented by the line segments AD, DB, BE and EC.
  • the change in shape from ABC to ADBEC is relatively large, and the new points D & E can be said to have jumped or “popped” into view. This is most readily seen in this example with point E which will have appeared to have jumped from the position E′.
  • the present invention in a third aspect, aims to ameliorate the visual problems associated with polygon popping.
  • Preferred features of the third aspect of the invention are defined in dependent claims 2 and 3 .
  • Preferred method steps are defined in dependent claims 5 to 7 .
  • the present invention in a third aspect produces a smoother looking animated image when changing levels of detail of a model using high order surfaces.
  • it uses a weighted blend between the linear and cubic subdivision of the final tessellated leaf-patch.
  • the weighting factor for this blend is preferably determined by the ratio between the required subdivision value and next smaller power of 2.
  • non-rational Bezier surfaces have the very convenient property that the differences between a corner control point and each of its two nearest edge control points are scalar multiples of the respective first partial derivatives. This is shown in FIG. 19 wherein ‘Tangent S’ coincides with the difference of corner point P 00 and its neighbour control point P 10 , while ‘Tangent T’ coincides with the difference between the corner and control point P 01 .
  • the invention will present a method of computing the surface normal which is not only robust but also efficiently computes the normals for Rational Bezier surfaces.
  • FIG. 1 a is a schematic diagram showing the subdivision of an n ⁇ 1 th level patch in t to form a top half n th level subpatch and a bottom half n th level subpatch (These are shown physically separated in the diagram for clarity.);
  • FIG. 1 b is a schematic diagram showing the subdivision of an n ⁇ 1 th level patch in S to form a left half n th level subpatch and a right half nth level subpatch;
  • FIG. 2 is a schematic diagram showing the possible choices of subdivision options of a root patch to intermediate patches and ultimately to leaf-patches for a patch being subdivided into 8 leaf sub-patches, the choice of S or T subdivision direction at each stage being determined by supplied subdivision parameters;
  • FIG. 3 a is a diagram showing a curved surface approximated by a first tessellation process producing vertices ABC along the ‘front edge’, while FIG. 3 b shows the same surface approximated by a second tessellation process producing vertices ADBEC along the front edge showing the relatively large change in shape between tessellation processes resulting in polygon popping;
  • FIG. 4 illustrates the problem of cracking when adjacent patches are subdivided to different subdivision ratios
  • FIG. 5 a is a stitching mesh used by known polygonisation systems to overcome the problem of cracking
  • FIG. 5 b shows Clark's approach to stopping the cracking problem
  • FIG. 5 c shows the “T-Joint” problem in computer graphics
  • FIG. 6 is a schematic diagram showing a preferred embodiment of an interface
  • FIG. 7 is a schematic showing the calculation stages of a subcalculation unit
  • FIGS. 8 a , 8 b, 8 c and 8 d show respectively the indexing of rows and columns of patch data for top half subdivision in t, bottom half subdivision in t, left half subdivision in S and right half subdivision in S using the calculation of FIG. 7;
  • FIG. 9 is a schematic of a two stage subdivision unit
  • FIG. 10 is a flow chart showing the operation of the control unit
  • FIG. 11 is a preferred tessellation pattern
  • FIG. 12 is an alternative tessellation pattern
  • FIG. 13 a is a tessellation pattern for a right edge irregular leaf-patch
  • FIG. 13 b shows the junction of the irregular patch from 13a and a higher subdivision level patch.
  • FIG. 14 is a schematic showing generation of fan patches for estimating the additional vertices of the irregular patch of FIG. 13 a;
  • FIG. 15 is a flow chart showing operation of the control unit during fan patch processing
  • FIG. 16 is a schematic showing the correspondence between the control points P 00 , P 30 , and P 33 of a leaf-patch and the vertices V 0 , V 2 , V 6 and V 4 of the tessellating triangles;
  • FIG. 17 is a schematic showing the generation of a combined value for vertices V 1 , V 3 , V 5 , V 7 and V 8 ;
  • FIG. 18 is a diagram relating to which vertices are used in the calculation of the centre vertex V 8 for different leaf-patches.
  • FIG. 19 illustrates one example of the behaviour of tangent vectors at the corners of a non-rational bicubic Bezier Patch
  • FIG. 20 shows the additional partial subdivision steps applied to a (regular) leaf patch to generate control points suitable for constructing the surface normals at the 9 “tessellation” vertices (i.e. those shown in FIG. 11);
  • FIG. 21 shows the subset of control points of a rational bicubic Bezier patch used by the invention to generate the surface normal for a particular corner point of the patch;
  • FIG. 22( a ) describes the steps taken to produce the required control points for the generation of 9 vertex normals for a tessellated leaf patch
  • FIG. 22( b ) further describes a part of this normal generation process
  • FIG. 23 describes the steps/apparatus used in the derivation of a candidate tangent vector in one parameter dimension at the corner of a rational Bezier patch
  • FIG. 24 describes the steps/apparatus used to combine three candidate tangent vectors at a patch corner to produce a surface normal.
  • the interface is intended for use in a 3-d graphics system using a parametric modelling unit and a polygon based rendering system to allow the parametric data modelling the object to be converted to a format which can be used by the polygon based rendering system to process the data for display.
  • FIG. 6 is a block diagram of the interface.
  • the interface 10 includes an input buffer 12 , format converter 14 , recursion buffer 16 , subdivision unit 18 , weighting processor 20 , direction processor 24 , output buffer 26 and control unit 22 .
  • patches are used to define a surface.
  • a typical, bicubic patch is defined by 16 control points.
  • Each control point is an N-dimensional vector defines a number of elements (usually including (xyzw) position, colour, and texture mapping information).
  • the data for each patch is grouped by control point and it is this control point grouped data which are input to the interface 10 via the input buffer 12 .
  • the subdivision unit requires the data to be grouped by element rather than by control point.
  • the input buffer 12 takes the control point grouped data, rearranges the data to the element-wise format required by the subdivision unit 18 and outputs the data to the format convertor 14 .
  • the subdivision unit of the interface 10 is designed to process a particular standard of patch known as a Bezier Bicubic Patch.
  • Other patch formats for example based on Catmull-Rom and B-Splines, are also used in 3D modelling.
  • a format converter 14 is provided. The format of the patch represented by the element-wise data output by the input buffer 12 is determined. If the format of the data is not Bezier bicubic, the format converter 14 converts the data to Bezier bicubic format via a series of optimised matrix multiplies. Methods of converting between various patch formats are known in the field of 3-d graphics and are not described here.
  • the format converter 14 maintains a library of conversion algorithms and applies the appropriate conversion algorithm to the data to covert it to Bezier bicubic format.
  • the recursion buffer, or store, 16 provides storage for data corresponding to two patches; the root patch and an intermediate patch.
  • the root patch must be accessed multiple times during the subdivision process because it is the starting point to each intermediate patch.
  • Storing intermediate patch data in the recursion buffer 14 reduces the data transfer in the interface, improving efficiency and reducing processing time. This area of the recursion buffer 14 effectively provides a working area for intermediate results.
  • Patch subdivision to the required level is performed by the subdivision unit 18 .
  • the input to the subdivision unit 18 is fed from the recursion buffer 16 .
  • Subdivision is split into four categories: subdivision in t taking the top half of the patch, subdivision in t taking the bottom half of the patch, subdivision in s taking the left half of the patch and subdivision in s taking the right half of the patch.
  • a Bezier patch has 16 control points and the control point data is arranged in a 4 ⁇ 4 matrix Subdivision from a first level patch, n ⁇ 1, to the next level sub-patch, n, in any category is achieved by applying the following recursive equations to the patch data:
  • a i n A i n ⁇ 1 ;
  • Ai, Bi, Ci and Di refer to appropriate elements of a 4 ⁇ 4 control point matrix according to the category of subdivision. The way in which the element indexing is controlled is described below for each category of subdivision.
  • FIG. 7 shows a subcalculation unit.
  • the input to the subcalculation unit is 4 control point values A n ⁇ 1 , B n ⁇ 1 , C n ⁇ 1 and D n ⁇ 1 , of an n ⁇ 1 th level patch.
  • a first calculation stage comprises 3 adders 46 , 48 and 50 arranged in parallel and each coupled to the input and to a second calculation stage.
  • One of the adders 46 is also coupled to a fourth calculation stage.
  • the second calculation stage comprises 2 adders 52 and 54 arranged in parallel. Each adder is coupled to the output of 2 of the 3 adders of the first calculation stage. One adder 52 is coupled directly to the fourth calculation stage, Both adders 52 and 54 are coupled to the third calculation stage.
  • the third calculation stage comprises a single adder 56 which takes as its input the outputs from both adders 52 and 54 of the second calculation stage.
  • the output of the adder 56 is coupled to the fourth calculation stage.
  • the fourth calculation stage comprises 3 dividers 58 , 60 and 62 arranged in parallel which respectively divide the output of adder 46 by 2, the output of adder 52 by 4 and the output of adder 56 by 8.
  • R C n ⁇ 1 +D n ⁇ 1 .
  • Each subcalculation unit calculates the values of four new control points in the nth level sub-patch. Calculation of each set of four new control points is independent of the calculation of the other 12 control points. Thus, by using four subcalculation units in parallel, the 16 new control points of the n th level sub-patch may be calculated in a minimum number of clock cycles thereby achieving a high throughput.
  • the outputs of the four subcalculation units are assembled in the output multiplexer (mux) 44 to generate the control point matrix for the n th level sub-patch.
  • the subcalculation units are required to work on different elements of the 4 ⁇ 4 control point matrix depending on which category of subdivision is being carried out. However, by including input and output multiplexers in the subdivision unit, four identical subcalculation units may be used to calculate the new control points. The function of the input and output muxes will now be described.
  • the function of the input mux is to allow the rows and columns of the n ⁇ 1 th level patch control point matrix to be swapped to control the category of subdivision implemented by the subcalculation units.
  • the rows of the control point matrix are indexed A to D and the columns of the control point matrix 1 to 4 from left to right.
  • the direction of indexing for the rows depends on whether a top half patch or bottom half patch is to be generated.
  • the rows are indexed starting with A as the top row of the matrix and ending with D as the bottom row of the matrix.
  • the top row of control points of the nth level top half sub-patch are identical to the top row of control points of the n ⁇ 1th level patch.
  • the remaining three rows of the nth top half sub-patch are related to the rows of the control points of the nth level patch as defined in the equation 1 above.
  • the bottom row of control points of the nth level bottom half sub-patch are identical to the bottom row of the control points of the n ⁇ 1th level patch and the remaining rows are related to the rows of the n ⁇ 1th level matrix in accordance with equation 1.
  • FIGS. 8 a and 8 b show the appropriate indexing of a n ⁇ 1th level patch in order to perform division in t taking the top half sub-patch and division in t taking the bottom half sub-patch respectively.
  • the rows of the may first be inverted and then processed as for top half sub-patch generation forming interim data which must then be arranged to form the required sub-patch data.
  • the columns of the patch are indexed A to D and the rows are indexed 1 to 4 from top to bottom.
  • the direction of indexing for the columns depends on whether a left half sub-patch or right half sub-patch is to be generated.
  • the columns are indexed starting with A as the left column and ending with D as the right column of the patch.
  • the left hand column of control points of the level left half subpatch are identical to the left hand column of control points of the n ⁇ 1th level patch.
  • the remaining three columns of the left half sub-patch are related to the columns of the control points of the n ⁇ 1th level patch as defined in the equation 1 above.
  • the right hand column of control points of the nth level right half sub-patch is identical to the right hand column of the control points of the n ⁇ 1th level patch and the remaining columns are related to the columns of the n ⁇ 1th level patch in accordance with equation 1.
  • FIGS. 8 c and 8 d show the appropriate indexing of a n ⁇ 1th level patch in order to perform division in s taking the left half sub-patch and division in s taking the right half sub-patch respectively.
  • the rows and columns of the patch may first be swapped and the rearranged patch processed as for top half sub-patch generation.
  • the rows are inverted then the rows and columns swapped. Processing for a top half sub-patch subdivided in t is performed and the resulting control points rearranged by the output mux to correspond to the required right half subpatch.
  • the function of the output mux is analogous to that of the input mux. It arranges the interim data output by the subdivision unit according to the category of subdivision to form the required subpatch control point matrix. Assuming that the subcalculation unit is set up to perform top half subdivision in t, the output of the subcalculation unit must be rearranged to produce bottom half subdivision in t and left and right half subdivision in s.
  • the output mux assembles the four outputs of the subcalculation units into a single matrix and reverses the rearrangement carried out by the input mux to produce the required subpatch control matrix.
  • the element-wise control data for the n th level sub-patch has been assembled in the appropriate order, that is as per FIG. 7 a , 7 b, 7 c or 7 d according to the category of subdivision, it is either outputted to the weighting processor 20 and direction processor 24 if it relates to a leaf patch, or returned to the recursion buffer 16 if it relates to an intermediate patch.
  • the subdivision unit 18 comprises a number of stages. Each stage performs one level of subdivision. The second stage subdivision may be bypassed if the required level of subdivision is reached after processing by the first stage. In the presently preferred embodiment, two stages, a first stage 30 and a second stage 32 , are implemented in the subdivision unit 18 . Inclusion of two subdivision stages has the advantage of increasing the raw calculation performance of the system for a given amount of data bandwidth from the recursion buffer. The number of stages may be changed to provide the required size/performance trade-off in the final system. Each stage consists of an input multiplexer 34 , four subcalculation processors 36 , 38 , 40 and 42 and an output multiplexer 44 .
  • the input mux 34 rearranges the matrix according to the category of subdivision required and passes four control points of the n ⁇ 1th level patch to each subcalculation unit for processing.
  • the output of each subcalculation unit is fed to the output mux 44 which assembles the outputs of the subcalculation unit and arranges the matrix into the required sub-patch according to the category of subdivision required.
  • the output from the output mux 44 of stage 1 is processed as the input to the input mux 34 of stage 2 .
  • the stage 2 output is either fed back to the recursion buffer 16 , or fed on to the following calculations stages if a leaf patch has been reached.
  • the operation of the subdivision unit 18 is controlled by a series of instructions presented from the control unit 22 .
  • the control unit 22 operates on the algorithm presented in the flowchart of FIG. 10.
  • the control unit 22 causes a root patch to be taken from the recursion buffer 16 and passed to the input mux 34 of the first stage.
  • the control unit 22 determines whether subdivision in the t dimension is required by testing the subdivision values of the left and right hand edges of the root patch control matrix. If neither the left nor the right hand edge value lies between the values 1.0 and 2.0, subdivision of the patch in t is required. The left and right hand edge values are divided by 2. A command to divide in t is sent by the control unit 22 to the subdivision unit 18 causing the appropriate rearrangement of the data by the input mux and arrangement of the interim data by the output mux. Having divided in t it is then necessary to calculate new subdivision values for the top and bottom edges. If top half subdivision is carried out then the top row of the control matrix is unchanged and the top value for the top half sub-patch is carried over from the undivided matrix.
  • top half subdivision results in the bottom row of the sub-patch differing from that of the undivided matrix.
  • the bottom value must therefore be updated.
  • the new value is calculated as either the average or preferably the geometric mean of the top and bottom values of the undivided matrix.
  • the geometric mean is preferable because it more usefully distributes the levels of subdivision across the patch.
  • For bottom half subdivision it is the top value of the subdivided matrix which must be calculated whilst the bottom edge value is carried over from the undivided matrix.
  • the top edge value is calculated in the same way as that of the bottom edge value for top half subdivision.
  • the control unit 22 continues subdivision in the t dimension until the exit condition is met, at which point processing advances to the s dimension.
  • the exit condition is met when either the left or the right hand edge value lies between 1.0 and 2.0 indicating that further subdivision in t of the entire patch is not required. Further processing of the patch may however be required if the resulting patch is irregular. Processing of irregular patches is described later.
  • Processing in the s dimension proceeds in a similar way but with the top and bottom edge values being tested to determine whether subdivision in s is required.
  • New right and left edge values are calculated for the left half subdivision and right half subdivision respectively.
  • the new right and left edge values are calculated as either the average or preferably the geometric mean of the left and right edge values of the undivided matrix.
  • the control unit 22 monitors the number of passes through its algorithm that have been completed. On the first pass, the control unit 22 sends a control signal to the subcalculation unit 18 to force the top half sub-patch to be calculated for division in t, and the left half sub-patch to be calculated for division in s. A history of the commands sent to the subdivision unit 18 from the control unit 22 is recorded. This command history is then used on subsequent passes to ensure that all the other sequences are exercised. The final pass of the control unit algorithm has been executed when dividing in t always takes the bottom half sub-patch as output, and dividing in s always takes the right half sub-patch as output.
  • the leaf-patch is said to be regular.
  • the regular leaf patch is processed to generate nine vertices of a grid of triangles arranged to cover the patch as shown in FIG. 11 by a converter.
  • the converter is incorporating processer 20 .
  • the tessellating triangles cover a square with three vertices set out in a regular array on each side of the square and the ninth vertex positioned in the centre of the square.
  • the triangles are arranged fanning around the square so that each of the eight triangles shares the centre vertex of the square.
  • Alternative patterns such as that shown in FIG. 12 and often seen in prior art, can also be used.
  • FIG. 16 shows schematically the conversion from the control point data of a regular patch to the nine vertices of the tessellating triangles.
  • the 16 control points of the patch are arranged in a 4 ⁇ 4 matrix with the points indexed Pij where j varies from 0 to 3 and indicates which row of the matrix the control point is located with row 0 being the top row and i varies from 0 to 3 and indicates which column of the matrix the control point is located with column 0 being the left hand column.
  • the four outer vertices of the tessellating triangles are derived directly from the outer control points of the regular leaf patch.
  • the top left vertex, V 0 takes the value of the top left control point, P 00
  • the top right vertex, V 2 takes the value of the top right control point, P 30
  • the bottom left vertex, V 6 takes the value of the bottom left control point, P 03
  • the bottom right vertex, V 4 takes the value of the bottom right is control point, P 33 .
  • w is the weight factor, derived from the fractional part of the edge subdivision ratio
  • D is a first vertex value derived at leaf-patch subdivision level
  • C is s second vertex value derived at the sub-leaf patch subdivision level.
  • D is calculated by taking the mean of the two corner vertices; in the case of FIG. 16, V 0 and V 2 correspond to points A and B respectively.
  • C a left half subdivision in s is performed and C takes the value of the top right control point of the left half subdivided patch.
  • the calculation for the ‘C’ point in the tope and bottom edges is analogous.
  • the vertex, V 1 is calculated according to equation 2. This calculation is performed by a combiner.
  • the combiner may be an integral part of the tessellation unit 20 .
  • FIG. 18 a shows a chequer board arrangement showing the relative position of leaf patches to the root patch for 16 leaf patches.
  • the leaf patch squares are arranged in four rows and four columns and cover the root patch. Half the squares are shaded and the remaining squares are unshaded in an alternating pattern. The top left square is shaded.
  • This preferred patterning scheme guarantees that as the subdivision level ‘crosses a power of two boundary’, the arrangement of triangles will not abruptly change. As the subdivision level is increased, any new triangles created are guaranteed to ‘lie inside’ the parent triangles. This is shown in FIG. 18 b. For example, the introduced centre point in the upper left leaf patch of the more highly tessellated region (shown on the right) would depend on the top-left to centre half-diagonal from the ‘parent’ leaf (on the left). Note that this is alternating operation would not be necessary for the triangulation pattern shown in FIG. 17.
  • Subdivision is terminated in any one direction, s or t, if either one of the relevant edge values lies between 10 and 2.0. Further processing of the leaf patch is required if it is irregular, that is if one or more edges have an edge value which lies outside the range 1.0 to 2.0.
  • An irregular leaf patch may be considered to be a regular leaf patch which requires additional vertices on the edge whose subdivision value is outside range to enable it to be joined to the adjacent patch.
  • the irregular leaf patch is first treated as a regular leaf patch and the nine vertices for the patch are calculated as described above. To calculate the additional vertices, further subdivision is performed. The further subdivision may be carried out in the same subdivision unit as subdivision to form leaf-patches and may be controlled from the control unit 22 .
  • the conversion of the fan patches to provide additional vertices may be carried out in the converter for the leaf-patches or in a separate converter.
  • FIGS. 13 a and 14 An example of subdivision processing for an irregular leaf patch with a right edge value outside the range 1.0 to 2.0 is shown in FIGS. 13 a and 14 .
  • the right edge subdivision value would be between 2.0 and 4.0 indicating that one additional level of subdivision is required to generate two extra vertices (V 23 and V 34 ) required on the right hand edge to prevent cracking.
  • the additional vertices are provided on the edge of the leaf patch whose edge value is outside the 1.0 to 2.0 range; in this case the right hand edge.
  • the triangles described by the additional vertices fan out from the centre vertex of the patch, splitting the original triangles spanning this edge in two.
  • the right edge of the irregular patch has five (instead of three) vertices, namely V 2 , V 23 , V 3 , V 34 and V 4 in a clockwise direction, defining four triangles all with a common vertex at V 8 : V 8 -V 2 -V 23 , V 8 -V 23 -V 3 , V 8 -V 3 -V 34 and V 8 -V 34 -V 4 .
  • V 23 and V 34 are calculated by performing further subdivisions in until the right edge value is made to lie between 1.0 and 2.0 and by using the output of the additional subdivision to form a series of fan patches which are used to generate the new vertices, V 23 and V 34 .
  • the fan patches are not used in the calculation of the nine standard vertices, V 0 to V 8 , corresponding to the vertices for a regular leaf-patch.
  • the irregular patch processing steps are summarised in the flow diagram of FIG. 15.
  • the edge values of the irregular patch are tested to determine which edge values are outside the range 1.0 to 2.0. Processing proceeds on an edge-wise basis. In the case of the example of FIGS. 13 a and 14 , only the right hand edge value is outside the range. This indicates that only subdivision in t is required.
  • the control unit 22 sends the appropriate command signal to the subdivision unit 18 to divide the irregular patch in L.
  • the edge values of the fan patches are computes as described above for the appropriate general form of subdivision.
  • the top and bottom half subpatches returned by 18 define upper and lower fan patches which may be used to compute the additional vertices V 23 and V 24 .
  • the control unit 22 maintains a history of the fan patch generation to ensure the generation of all appropriate fan patches. In this case, after generation of a top half (an patch and a bottom half fan patch, all edge values are within the range 1.0 and 2.0 and no further subdivision to form fan patches is required.
  • the additional vertex V 23 is obtained by calculating the centre right vertex of the upper fan patch in accordance with equation 2 described above.
  • the additional vertex V 24 is calculated by estimating the centre right vertex of the lower fan patch in accordance with equation 2 above.
  • the irregular leaf polygon data is generated by combining the vertices generated by the normal subdivision process to form a leaf patch, the “first plurality of vertices'”, and the additional vertices calculated from the fan patches, the “fan patch values'”.
  • the surface normal generation unit 24 takes the output of the subdivision unit 18 and calculates the surface normal associated with each vertex. (Note that in the preferred embodiment, the units 20 and 24 are separate but, in an alternative embodiment, they could share a number of calculations that they have in common.)
  • the surface normal is used to indicate the direction that the surface being modelled is facing at the sample point and is required for subsequent lighting and texturing calculations.
  • the direction processor 24 calculates the normal for each vertex of the leaf patch including any additional vertices calculated from irregular patches.
  • the same linear interpolation method as described previously by equation 2 is also applied to the normals of interior vertices, i.e. the output normal may be a blend of the neighbouring vertices' normals and the ‘correct’ normal.
  • the invention performs additional ‘partial’ subdivisions of the leaf. This processing is shown in FIG. 20.
  • three additional partial subdivisions one in S ( 20 ( iii )), one in T ( 20 ( ii ), and an additional subdivision ( 20 ( iv )) are sufficient to produce child sub-patches such that positions of V 1 , V 3 , V 5 , V 7 and V 0 , are at the corners of at least one sub-patch.
  • control points of each sub-patch are needed to generate the vertex normals and in the preferred embodiment only the minimum required control points are calculated.
  • the control points which are needed are shown in grey or black, while those that aren't required are shown in white.
  • the invention computes the normals for rational Bezier patches in an efficient manner, the method and reasoning behind which will now be presented.
  • T ⁇ a ⁇ ⁇ b ⁇ ( 0 , 0 ) lim o ⁇ 0 ⁇ ( B _ 3 ⁇ ⁇ D ⁇ ( e ⁇ ⁇ a , e ⁇ ⁇ b ) - B _ 3 ⁇ ⁇ D ⁇ ( 0 , 0 ) ⁇ B _ 3 ⁇ ⁇ D ⁇ ( e ⁇ ⁇ a , e ⁇ ⁇ b ) - B _ 3 ⁇ ⁇ D ⁇ ( e ⁇ ⁇ a , e ⁇ ⁇ b ) - B _ 3 ⁇ ⁇ D ⁇ ( 0 , 0 ) ⁇ )
  • the Bezier functions are bicubic. Extensions of this scheme to embodiments using surfaces of higher order should be straightforward to one skilled in the art.
  • This invention's method computes up to three potential tangent candidates, these being the ‘S’, ‘T’, and ‘diagonal’ tangent candidates.
  • the control points used for the calculation of a particular vertex normal will be called C, S 1 , S 2 , S 3 , T 1 , T 2 , T 3 , and D.
  • this naming scheme and the required control vertices for vertex V 0 is also shown in FIG. 21.
  • the leaf patch's control points are supplied, 200 , and for each of the V 0 , V 2 , V 4 , and V 6 vertices the correct set of 8 control points (C, S 1 , S 2 , S 3 , T 1 , T 2 , T 3 , D) are selected, 201 , and supplied in turn to the corner normal unit, 202 . Note that only the X, Y, Z, and W components of the control points are required in the surface normal generation unit.
  • Unit 201 is a MUX that chooses which of the original leaf patch control points correspond to each of the four sets of 8 points.
  • the four selections are as follows:
  • Vertex V 0 this is shown in FIG. 21.
  • the orientation of the ‘virtual’ S, T, and diagonal tangent candidates rotates by 90° with each successive corner vertex. This is done to maintain a consistent orientation of the surface normal.
  • control points by mirroring of the existing axis directions could be used but this would require an additional flag to be supplied to unit ‘ 202 ’ to indicate if the result of the cross products should be negated. Such a negation would have to be indicated for at least vertices V 2 and V 6 . (Vertex V 4 would need no negation as both axes would have been flipped).
  • Unit 203 performs a partial subdivision of the leaf patch in order to compute new control points suitable for the generation of surface normals for vertices V 1 and V 6 .
  • the set required has been illustrated in FIG. 20( ii ).
  • Unit 204 is another multiplexor which selects the required points for each of V 1 and V 5 respectively and supplied them to the corner normal unit, 202 .
  • the selection process is analogous to that of unit 201 and should be obvious to one skilled in the art given the previous description.
  • units 205 and 206 produce the two sets of control points needed for the normals of vertices V 3 and V 7 (see FIG. 20( iii ).
  • Units 207 and 208 produce the set of eight control points needed to generate the surface normal for V 8 .
  • This set is illustrated in FIG. 20( iv ).
  • the four control points shown on the right edge of FIG. 20( iv ) can be obtained by a single subdivision of the right edge of FIG. 20( ii ), while the bottom edge is computed from a single subdivision of the bottom edge of FIG. 20( iii ).
  • the control point corresponding to “D” can be obtained from either the second bottom row of FIG. 20( iii ) or alternatively from the second right most column of 20 ( ii ).
  • a preferred embodiment overlaps the calculation of several vertex normals via a combination of multiple units and a pipelined architecture.
  • the level of parallelism could be varied as a cost/performance trade-off.
  • the “corner normal unit”, 202 is now dismissed with reference to FIG. 22 b. Note that for clarity, this figure only describes the computation of a single normal.
  • the eight chosen control points are input, 220 .
  • the C point and three S points are sent to the “S Candidate” computation unit, 221
  • C and three T points are sent to the “T Candidate” computation unit, 222
  • C and D are sent to the “Diagonal Candidate” unit.
  • the three computed tangent candidates, T S , T T , and T Diag are then input into ‘candidate selection and normal calculation’ unit, 224 .
  • the preferred embodiment uses a pipelined architecture to compute each of the products, such as S 1 XYZ C W or S 2 w C XYZ , “simultaneously”. Similarly, the comparison operations are also carried out in a pipelined fashion.
  • the first two products, S 1 XYZ C W and C XYZ S 1 w are compared. (Those familiar with floating point arithmetic will appreciate that equality tests are simpler than subtraction). If these products are not equal then the T S tangent vector is computed in step 241 by taking the difference of the two.
  • T S is set to be the difference of the pair, 243 .
  • the final pair of products, S 3 XYZ C W and C XYZ S 3W are compared, 244 , and if different, T S , is computed, while if they are identical, then the tangent is marked as being zero.
  • an additional ‘optimisation’ can be included to initially test if the w or ‘wright’ component values are identical before optionally performing the multiplication. This could potentially reduce the computation delay for cases where the patches are non-rational, i.e. where the w values are constant.
  • T X or T Y may be a zero vector, and set in intermediate vector, T NZ , to be either ⁇ T T ( 251 ) or T S ( 253 ) respectively. If both vectors are non-zero, then a candidate surface normal is produced in step 254 by taking the vector cross product of T S and T T . The candidate normal is then compared against zero, 255 . If it is not zero, then it is used as the surface normal, 256 . If it is zero, then the intermediate vector is set in step 253 .
  • step 251 T NZ was sent to be the negative of T T . This is done to maintain consistency of the normal orientation. It should be appreciated that negation of floating point values is trivial.
  • the normals thus calculated for vertices V 1 , V 3 , V 5 , V 7 , and V 8 represent those at the maximum fractional subdivision level within the leaf patch.
  • the same blending process used to eliminate polygon popping is also applied to produce the final normal vector results.
  • the calculation of normals for irregular leaf patches must undergo extra levels of subdivision akin to that previously described.
  • the invention computes the surface normals for rational Bezier surfaces without requiring expensive division operations. This is a significant saving.
  • the normals that are output are not unit vectors—with the preferred embodiment it is assumed that the subsequent shading and transformation units, which are not described in the document, will be capable of performing this sample task if required.
  • the final stage of the pipelined tessellation process is performed in the output buffer 26 .
  • the input buffer 12 took the control point grouped data and regrouped the data by element.
  • the output buffer 26 is required to perform the reverse task of grouping the data from the calculation stages by vertex.
  • the output buffer 26 takes the vertices calculated by the weighting processor 20 and the normals calculated by the surface normal processor 24 , groups together the data for each element by vertex and outputs it for subsequent use in the transformation, lighting, texturing and rasterization of the image for display.

Abstract

An interface for use in a 3-d graphics system comprising a parametric modelling unit for modelling objects as high order surfaces, and a polygon based rendering system for rendering polygon modelled objects for display. The interface comprises an input for receiving data and a subdivision unit coupled to the input for processing the data. The interface includes a converter coupled to the subdivision unit for determining from leaf patch data a first plurality of values representing vertices of tessellating polygons describing the leaf patch, and for determining from sub-leaf patch data a second plurality of values representing the vertices of tessellating polygons describing the sub-leaf patch. The interface also has a combiner, coupled to the converter, for combining the values to form leaf polygon data defining the polygon vertices at a first subdivision level, and an output coupled to the combiner for outputting the leaf polygon data.

Description

  • This invention relates to an interface for use in a 3-d graphics system comprising a parametric modelling unit and a polygon based rendering system. [0001]
  • BACKGROUND TO THE INVENTION
  • Traditional 3D rendering systems use a mesh of polygons (usually triangles) to model the objects within a scene. Triangles have the advantage that they are of a simple form, and it is therefore relatively easy to perform operations such as transformation, lighting, texturing and rasterization on them in order to produce an image for display. [0002]
  • A known alternative to modelling objects using a mesh of polygons is to segment the object into areas and fit a number of curved, high order surfaces, frequently termed patches, to the different areas of the object being modelled. These patches are generally defined as parametric surfaces with the surface shape governed by a grid of control points. An advantage of using high order surfaces is that the set of control points usually requires a much smaller amount of data to represent a particular model than the equivalent polygon mesh. High order surfaces are also generally easier to manipulate when animating an object which is changing in shape. A major disadvantage of modelling using high order surfaces is that it introduces added complexity in the rasterization stage of the rendering system. [0003]
  • It is also known to use high order surfaces for the modelling stage and to convert the surfaces to a series of tessellating triangles before performing processing stages such as rasterization. This combined method benefits from the advantages of using curved surfaces without adding complexity to the rasterization stage but requires a suitable interface to process the surface patch data to form polygon based data. Two methods are commonly employed in the tessellation process for converting the curved surface to a series of polygons: either forward differencing or recursive subdivision. The present invention is derived from the recursive subdivision method. [0004]
  • In the parametric modelling stage of a combined 3-D graphics system (i.e. one that combines a tessellation stage to produce polygons for the latter rendering stage), a plurality of curved surfaces patches are fitted to the surface of the object to define areas of the object. A number of different standards for defining the behaviour of such patches with respect to their defining control points are known. One such standard is Bezier patches, for example see “Advanced Animation and Rendering Techniques” pp 66-68 by Watt & Watt or “Computer Graphics Principles and Practice” pp 471-530 by Foley Van Dam et al. Methods of transforming the control points corresponding to one format of patch to new positions corresponding to a different patch type so that the final surfaces are identical are also known. These patches are often of bicubic order. [0005]
  • Of the common parametric patches, there are two main variations. The first is the family of ‘standard’ mpm-rational surface patches, while the second is the super-set of rational patches. Rational patches have certain modelling advantages over the simpler non-rational variety but can be slightly more complex to process in some respects. Both types of patches are well described in the previous two references, however to simplify description of the embodiment, the following summary is presented. For a non-rational parametric surface, the 3D position can be described as: [0006] B _ non - rational ( s , t ) = ( x ( s , t ) y ( s , t ) z ( s , t ) )
    Figure US20040113909A1-20040617-M00001
  • where each of x(s,t), y(s,t), and z(s,t) are scalar parametric polynomials of the same degree, and 0≦s,t≦1. In the case of a bicubic (i.e. the product of two cubics) Bezier surface the polynomial is of degree 6. The Bezier equations and the respective x, y, and z components of the surface's control points define the shape of the surface. [0007]
  • A non-rational surface extends the definition by introducing a fourth polynomial w(s,t) with a corresponding additional positive “w” value in each of the control points. The surface position is then defined by: [0008] B _ rational ( s , t ) = 1 w ( s , t ) ( x ( s , t ) y ( s , t ) z ( s , t ) )
    Figure US20040113909A1-20040617-M00002
  • It is also well known in the art (see previous references) that the popular types of parametric surfaces patches can be conveniently expressed in matrix form. For example, a bicubic Bezier patch, {overscore (B)}[0009] bez(s,t) can be expressed as; B _ bez ( s , t ) = [ s 3 s 2 s1 ] Q P Q T [ t 3 t 2 t 1 ]
    Figure US20040113909A1-20040617-M00003
  • where Q is a matrix of scalar constants and P is the matrix of control points for the surface [0010] Q = [ - 1 3 - 3 1 3 - 6 3 0 - 3 3 0 0 1 0 0 0 ] P = [ P _ 00 P _ 01 P _ 02 P _ 03 P _ 10 P _ 11 P _ 12 P _ 03 P _ 20 P _ 21 P _ 22 P _ 03 P _ 30 P _ 31 P _ 32 P _ 03 ]
    Figure US20040113909A1-20040617-M00004
  • Note that P is numbered as P[0011] ST.
  • Conversion of the patches to tessellating triangles via the recursive subdivision method is achieved by initially dividing each patch into two sub-patches across either one of its two parameter dimensions (i.e. s or t). This is shown in FIGS. 1[0012] a and 1 b, in which the patch, with control points, has been portrayed in its parameter space. Each of the sub-patches can then be further sub-divided until the correct level of sub-division is achieved. Once this has been achieved, the resulting sub-patches are each treated as non-planar quadrilaterals, and a set pattern of triangles is superimposed onto the sub-patches, the vertices of the triangles calculated, and the triangles output.
  • FIG. 2 is a schematic showing conceptual processing of a patch by subdivision with three levels of subdivision applied. From FIG. 2, it can be seen that the processing takes the form of a binary tree progressing from the original, or “root”, patch, through intermediate levels of patches to end-point patches termed “leaf” patches. Each leaf patch is used to generate the vertices defining the tessellating triangles required for the rasterization stage of rendering. [0013]
  • In the known system of recursive sub-division, tessellation is traditionally implemented on a CPU as a large number of calculations are required for each stage. Examining the series of calculations involved shows that, when using a CPU, it is efficient to store the intermediate results on a stack, as the same intermediate result is used on a number of the paths to the leaf patches, Use of the stack therefore minimises the number of calculations performed. We have appreciated that for a hardware implementation this is not practical for two reasons: internal (i.e. on-chip) storage is expensive and the retrieval of large amounts of externally stored data can cause a bottleneck in the performance of the system. [0014]
  • The present invention in a first aspect aims to ameliorate these problems. It provides an interface for converting parametric modelled data to polygon based data using recursive sub-division in a way which provides high computational performance whilst minimising memory and memory bandwidth usage. [0015]
  • According to the invention in a first aspect, there is provided an interface according to [0016] claim 12. Preferred features of the first aspect of the invention are defined in dependent claims 13 to 16.
  • There is also provided a method of interfacing between a parametric modelling unit and a polygon based rendering system according to [0017] claim 16. Preferred method steps are defined in dependent claims 17 to 19.
  • A second problem which occurs when interfacing between parametric data and polygon based data in a combined graphics system is that different levels of subdivision may be required to convert parametric data relating to a first patch and parametric data relating to a second patch, where the first and second patches represent adjacent areas of the object being modelled. Patches which define highly curved surfaces must be more highly subdivided than patches which represent a flatter surface when converting the parametric data to polygon based data if the benefits of parametric modelling are not to be lost. If conversion of adjacent patches is not constrained to apply the same level of subdivision to each patch, then cracks can appear in the modelled object because the surface with the higher level of subdivision has extra sample points and thus potentially a slightly different shape. The problem of cracking is illustrated in FIG. 4. [0018]
  • One solution to the problem of cracking is to use the same level of subdivision on all patches. However, this results in some patches being excessively subdivided when they could be tessellated adequately at a less divided level and does not target the processing to the areas where it is necessary to produce adequate results. [0019]
  • Another solution is to process each patch to a level of subdivision sufficient to represent the surface adequately, and to then insert a so-called “stitching mesh” between adjacent surface patches which have different subdivision levels. The stitching mesh thus covers any potential cracks as shown in FIG. 5[0020] a. In the diagram, two adjacent patches are subdivided to different levels—one uses 2×4 sub-patches while the other is represented by no subdivisions, i.e. a single quadrilateral. The ‘abutting’ contour on the 2×4 patch consists of vertices, A, B, C, D, & E, while the equivalent for the 1×1 subdivision consists of the edge AE. To prevent a gap in the surface from appearing, the additional triangles, ABC, ACE and CDE are created.
  • Unfortunately, such connecting meshes may introduce abrupt changes in surface direction. We have also appreciated that stitching the edges of adjacent patches together is computationally intensive and requires the stitching mesh to be regenerated as the subdivision level changes. [0021]
  • Clark [“A Fast Scan Line Algorithm for Rendering Parametric Surfaces”. Computer Graphics 13(2), 289-99] proposed an alternative technique which even permits different levels of subdivision within each patch. As part of this method, the cracking problem, had to be ‘solved’. Clark's solution is to deliberately ‘flatten’ the edges of higher subdivision regions where they meet lower subdivision regions. This is shown in FIG. 5[0022] b. The ‘shared’ boundary between the high-subdivision region and the lowe-subdivision area has been ‘flattened’ on the high subdivision region so that it mathematically matches the boundary of the low-subdivision region. Comparing this to the approach in FIG. 5a, it can be seen that the vertices, B, C, & D now lie on the line AE.
  • Although this scheme is mathematically correct, it has a subtle flaw. Computer graphics hardware has limited precision and is unable to represent exact polygon vertex locations. It is therefore frequently impossible to exactly place a flattened vertex on the shared boundary. This leads to problems caused by “T-Joints”, as well known in the art. This is illustrated in FIG. 5[0023] c, wherein an inaccuracy causes a very small gap to appear. Although this gap is typically tiny, it can still be visible in the rendered images as sets of semi-random pixel holes lying along the edges of the otherwise abutting triangles. As the image is animated, these will ‘twinkle’ on and off and are easily seen.
  • We have appreciated that these T-Joints could be fixed by again introducing stitching polygons,.however this is a rather inefficient approach since such polygons are tiny and the ‘set-up’ costs involved in polygon rendering would be better utilised on more significantly sized polygons. [0024]
  • Yet another approach, as used by Pixar's Renderman system, is to subdivide the patches until the resulting polygons are smaller than a pixel. These micro-polygons can then be treated as ‘points’. This methord generates vast amounts of data and is not really suitable for real-time rendering. [0025]
  • The options for crack-free subdivision in the current art can thus be summarised as follows: [0026]
  • 1) Subdivide all patches of the model to the same subdivision level, This is simple but wasteful of resources. [0027]
  • 2) Within each patch subdivide uniformly, and then use stitching polygons to hide gabs between patches divided non-uniformly. It is not ideal as the stitching polygons are additional costs and can induce abrupt changes in direction (as seen in FIG. 5[0028] a).
  • 3) Use Clark's method, allowing non-uniform subdivision even within patches, but suffer from T-Joint problems. [0029]
  • 4) Apply further stitching polygons to Clark's method. [0030]
  • 5) Subdivide the mesh into micro-polygons. [0031]
  • We have appreciated that allowing non-uniform subdivision along patch edges is desirable since it allows the joining of different patches without cracking at the joints. It is also desirable to allow non-uniform subdivision within patches, as is possible with Clark's method, as this can allow a more efficient use of polygons as a gradual transition from a high subdivision edge on one side of a patch to a low subdivision edge on the opposite would require fewer polygons than in a system where the patch is internally subdivided uniformly. We have also appreciated that a system which does not need stitching polygons, either internally or on the boundaries, and also does not introduce T-Joints is highly desirable. [0032]
  • The present invention in a second aspect therefore supports “irregular patch” processing, that is processing of patch data to different subdivision levels in different subdivision directions within the patch but avoiding the problems with Clark's scheme. By forming different numbers of vertices on different edges of the “irregular” patch, we have eliminated the need for stitching meshes to prevent cracking between the tessellated patches that are modelling adjacent areas of objects. Supporting irregular tessellation allows adjacent edges of adjoining patches to have the same number of polygon vertices without affecting the level of subdivision of the patch for the remaining edges An example, showing the boundary of two unequally subdivided patches, is given in FIG. 13[0033] b.
  • According to the present invention in a second aspect, there is provided an interface according to [0034] claim 8. Preferred features of the second aspect of the invention are detailed in dependent claim 9. There is also provided a method of interfacing between a parametric modelling unit and a polygon based rendering system according to claim 10.
  • Irregular levels of sub-division are supported by automatically generating a mesh from the final sub-patch that has a suitable number of vertices along each edge of the quadrilateral. This allows simple joining of polygonised patches without cracks appearing. [0035]
  • A further problem with known interfacing techniques is so-called polygon popping. For the interfacing of different patches it has been assumed that each edge of every patch has its own subdivision control value. To allow the smooth animation of objects as the lever of subdivision changes, these values are assumed to take floating point or at least contain fractional parts. Polygon popping is a term used to describe the sudden movements in the points of the tessellated polygons that can occur when a small fractional change in the subdivision control value causes an extra step of processing (i.e. an extra binary subdivision of the patch) to be performed. Although the edge subdivision control value may take any value, the preferred tessellation technique is constrained to perform binary patch subdivision to the next nearest power of 2. Thus increasing the subdivision ratio even a small amount may cause the actual level of subdivision to increase dramatically. For example if the subdivision value specified for each edge is 4, then subdivision results in 16 leaf patches. If the subdivision value for each edge is increased from 4 to 4.1, the next larger power of 2 is 8 and the resulting subdivision gives rise to 64 leaf patches. Thus many new triangles have appeared in the object. Unless this process is well controlled it causes undesirable visual effects in the animation as shown in FIG. 3. [0036]
  • In FIG. 3[0037] a, the curved surface has been subdivided into two quadrilateral regions. The ‘front-most’ curved edge of the patch is thus approximated by the line segments AB and BC. In FIG. 3b, the level of subdivision is increased (in one dimension only) so that along the front edge, two new points, D & E, have been generated. The front edge of the patch is then represented by the line segments AD, DB, BE and EC. The change in shape from ABC to ADBEC is relatively large, and the new points D & E can be said to have jumped or “popped” into view. This is most readily seen in this example with point E which will have appeared to have jumped from the position E′.
  • The present invention, in a third aspect, aims to ameliorate the visual problems associated with polygon popping. [0038]
  • According to the present invention in a third aspect there is provided an interface according to [0039] claim 1.
  • Preferred features of the third aspect of the invention are defined in [0040] dependent claims 2 and 3. There is also provided a method of interfacing between a parametric modelling unit and a polygon based rendering system according to claim 4. Preferred method steps are defined in dependent claims 5 to 7.
  • The present invention in a third aspect produces a smoother looking animated image when changing levels of detail of a model using high order surfaces. Preferably it uses a weighted blend between the linear and cubic subdivision of the final tessellated leaf-patch. The weighting factor for this blend is preferably determined by the ratio between the required subdivision value and next smaller power of 2. [0041]
  • When lighting and shading operations are applied to surfaces in 3-D graphics, there is usually a requirement that the surface normal at a point, i.e. a vector perpendicular to the surface at that location, be known. For the purposes of shading a tessellated surface, surface normals need only be computed at the computed triangle verticles. [0042]
  • As descrived by Watt and Watt, Forley et al, and Farin, [“Curves and Surfaces for CAGD. A Practical Guide”. 4[0043] th Edition, Academic Press, ISBN 0-12-249054-1, pp 244-247], the standard way to obtain the normal at a point is to calculate two (linearly independent) tangent vectors at that point and take their cross product. If desired, the result can later be converted into a unit computing the first partial derivatives of the surface with respect to the s and t parameters.
  • Without loss of generality, if we restrict the surface normal calculations to only be done at the corner points of patches, then non-rational Bezier surfaces have the very convenient property that the differences between a corner control point and each of its two nearest edge control points are scalar multiples of the respective first partial derivatives. This is shown in FIG. 19 wherein ‘Tangent S’ coincides with the difference of corner point P[0044] 00 and its neighbour control point P10, while ‘Tangent T’ coincides with the difference between the corner and control point P01.
  • A number of systems use this fact (in addition to repeated subdivision) to compute the normals at various locations on the patch. [0045]
  • Unfortunately, this calculation can frequently fail. The requirement is that the tangent vectors are linearly independent and control points of the Bezier patch, especially those neighbouring the corner points, can sometimes be coincident. This means that one or both of the first partial derivates may be zero, resulting in an incorrect normal. Such surfaces patches are often referred to as ‘degenerate’, and some systems may consider them to be ‘illegal’. This is rather unfortunate as such surface arrangements of control points are often needed to model completely valid shapes and can easily be generated by modelling software packages. [0046]
  • One known and rather pragmatic solution is that of evaluating the surface at two points slightly offset from the corner in the s and t parameters. The two tangent vectors are then approximated by taking the differences between these computed points and the patch corner. This will usually provide an adequate result, but is costly in terms of additional calculation. [0047]
  • By referring back to the definition of a tangent vector and applying calculus, one can see that the 2[0048] nd partial derivative can be employed if the first is zero. Watt and Watt [“Advanced Animation and Rendering Techniques. Theory and Practice”. ACM Press. ISBN 0-201-54412-1] demonstrate, again for non-rational Beziers patches, that in this situation the difference between the corner control point and the subsequent multiple of the 2nd partial derivative. Again referring to FIG. 19, if P01 and P00 were coincident, for example, then the difference of P02 and P00 would yield a potential tangent. If this were also zero, a similar process can be employed for the 3rd partial derivative by taking the difference with P03.
  • Unfortunately, even this approach can fail. All the points along an edge of patch may be coincident, as may occur when a patch is modelling an octant of a sphere and the patch has become ‘triangular’. In this particular situation a 2[0049] nd partial derivative may be chosen. Farin also describes an even subtler problem: although non-zero partial derivatives in s and t might exist, in some situations they can be parallel. The cross product will then give a zero, and hence invalid, normal. Farin describes the solution for one particular case.
  • In a fourth aspect, the invention will present a method of computing the surface normal which is not only robust but also efficiently computes the normals for Rational Bezier surfaces. [0050]
  • Embodiments of the invention will now be described in more detail in accordance with the accompanying drawings in which: [0051]
  • FIG. 1[0052] a is a schematic diagram showing the subdivision of an n−1th level patch in t to form a top half nth level subpatch and a bottom half nth level subpatch (These are shown physically separated in the diagram for clarity.);
  • FIG. 1[0053] b is a schematic diagram showing the subdivision of an n−1th level patch in S to form a left half nth level subpatch and a right half nth level subpatch;
  • FIG. 2 is a schematic diagram showing the possible choices of subdivision options of a root patch to intermediate patches and ultimately to leaf-patches for a patch being subdivided into 8 leaf sub-patches, the choice of S or T subdivision direction at each stage being determined by supplied subdivision parameters; [0054]
  • FIG. 3[0055] a is a diagram showing a curved surface approximated by a first tessellation process producing vertices ABC along the ‘front edge’, while FIG. 3b shows the same surface approximated by a second tessellation process producing vertices ADBEC along the front edge showing the relatively large change in shape between tessellation processes resulting in polygon popping;
  • FIG. 4 illustrates the problem of cracking when adjacent patches are subdivided to different subdivision ratios; [0056]
  • FIG. 5[0057] a is a stitching mesh used by known polygonisation systems to overcome the problem of cracking;
  • FIG. 5[0058] b shows Clark's approach to stopping the cracking problem;
  • FIG. 5[0059] c shows the “T-Joint” problem in computer graphics;.
  • FIG. 6 is a schematic diagram showing a preferred embodiment of an interface; [0060]
  • FIG. 7 is a schematic showing the calculation stages of a subcalculation unit; [0061]
  • FIGS. 8[0062] a, 8 b, 8 c and 8 d show respectively the indexing of rows and columns of patch data for top half subdivision in t, bottom half subdivision in t, left half subdivision in S and right half subdivision in S using the calculation of FIG. 7;
  • FIG. 9 is a schematic of a two stage subdivision unit; [0063]
  • FIG. 10 is a flow chart showing the operation of the control unit; [0064]
  • FIG. 11 is a preferred tessellation pattern; [0065]
  • FIG. 12 is an alternative tessellation pattern; [0066]
  • FIG. 13[0067] a is a tessellation pattern for a right edge irregular leaf-patch;
  • FIG. 13[0068] b shows the junction of the irregular patch from 13a and a higher subdivision level patch.
  • FIG. 14 is a schematic showing generation of fan patches for estimating the additional vertices of the irregular patch of FIG. 13[0069] a;
  • FIG. 15 is a flow chart showing operation of the control unit during fan patch processing; [0070]
  • FIG. 16 is a schematic showing the correspondence between the control points P[0071] 00, P30, and P33 of a leaf-patch and the vertices V0, V2, V6 and V4 of the tessellating triangles;
  • FIG. 17 is a schematic showing the generation of a combined value for vertices V[0072] 1, V3, V5, V7 and V8; and
  • FIG. 18 is a diagram relating to which vertices are used in the calculation of the centre vertex V[0073] 8 for different leaf-patches.
  • FIG. 19 illustrates one example of the behaviour of tangent vectors at the corners of a non-rational bicubic Bezier Patch; [0074]
  • FIG. 20 shows the additional partial subdivision steps applied to a (regular) leaf patch to generate control points suitable for constructing the surface normals at the 9 “tessellation” vertices (i.e. those shown in FIG. 11); [0075]
  • FIG. 21 shows the subset of control points of a rational bicubic Bezier patch used by the invention to generate the surface normal for a particular corner point of the patch; [0076]
  • FIG. 22([0077] a) describes the steps taken to produce the required control points for the generation of 9 vertex normals for a tessellated leaf patch;
  • FIG. 22([0078] b) further describes a part of this normal generation process;
  • FIG. 23 describes the steps/apparatus used in the derivation of a candidate tangent vector in one parameter dimension at the corner of a rational Bezier patch; [0079]
  • FIG. 24 describes the steps/apparatus used to combine three candidate tangent vectors at a patch corner to produce a surface normal.[0080]
  • DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION
  • The interface is intended for use in a 3-d graphics system using a parametric modelling unit and a polygon based rendering system to allow the parametric data modelling the object to be converted to a format which can be used by the polygon based rendering system to process the data for display. [0081]
  • FIG. 6 is a block diagram of the interface. The [0082] interface 10 includes an input buffer 12, format converter 14, recursion buffer 16, subdivision unit 18, weighting processor 20, direction processor 24, output buffer 26 and control unit 22.
  • In parametric modelling units, patches are used to define a surface. A typical, bicubic patch is defined by 16 control points. Each control point is an N-dimensional vector defines a number of elements (usually including (xyzw) position, colour, and texture mapping information). Typically for 3D graphics systems, the data for each patch is grouped by control point and it is this control point grouped data which are input to the [0083] interface 10 via the input buffer 12. The subdivision unit requires the data to be grouped by element rather than by control point.
  • The [0084] input buffer 12 takes the control point grouped data, rearranges the data to the element-wise format required by the subdivision unit 18 and outputs the data to the format convertor 14.
  • The subdivision unit of the [0085] interface 10 is designed to process a particular standard of patch known as a Bezier Bicubic Patch. Other patch formats, for example based on Catmull-Rom and B-Splines, are also used in 3D modelling. To enable the interface 10 to process other patch formats, a format converter 14 is provided. The format of the patch represented by the element-wise data output by the input buffer 12 is determined. If the format of the data is not Bezier bicubic, the format converter 14 converts the data to Bezier bicubic format via a series of optimised matrix multiplies. Methods of converting between various patch formats are known in the field of 3-d graphics and are not described here. The format converter 14 maintains a library of conversion algorithms and applies the appropriate conversion algorithm to the data to covert it to Bezier bicubic format.
  • The recursion buffer, or store, [0086] 16, provides storage for data corresponding to two patches; the root patch and an intermediate patch. The root patch must be accessed multiple times during the subdivision process because it is the starting point to each intermediate patch. Storing intermediate patch data in the recursion buffer 14 reduces the data transfer in the interface, improving efficiency and reducing processing time. This area of the recursion buffer 14 effectively provides a working area for intermediate results.
  • Patch subdivision to the required level is performed by the [0087] subdivision unit 18. The input to the subdivision unit 18 is fed from the recursion buffer 16. Subdivision is split into four categories: subdivision in t taking the top half of the patch, subdivision in t taking the bottom half of the patch, subdivision in s taking the left half of the patch and subdivision in s taking the right half of the patch.
  • A Bezier patch has 16 control points and the control point data is arranged in a 4×4 matrix Subdivision from a first level patch, n−1, to the next level sub-patch, n, in any category is achieved by applying the following recursive equations to the patch data: [0088]
  • A i n =A i n−1;
  • B i n=(A i n−1 +B i n−1)/2;
  • C i n=(A i n−1+2B i n−1 +C i n−1)/4;
  • D i n=(A i n−1+3B i n−1+3C i n−1 +D i n−1)/8;  Eqn 1
  • where Ai, Bi, Ci and Di refer to appropriate elements of a 4×4 control point matrix according to the category of subdivision. The way in which the element indexing is controlled is described below for each category of subdivision. [0089]
  • The above equations are recursive; for example calculation of B[0090] i n requires the previous of Ai n −1 and Bi n −1 . The subdivision calculations are performed efficiently by pipelining the operations as shown in FIG. 7 and described below.
  • FIG. 7 shows a subcalculation unit. The input to the subcalculation unit is 4 control point values A[0091] n−1, Bn−1, Cn−1 and Dn−1, of an n−1th level patch. A first calculation stage comprises 3 adders 46, 48 and 50 arranged in parallel and each coupled to the input and to a second calculation stage. One of the adders 46 is also coupled to a fourth calculation stage.
  • The second calculation stage comprises 2 [0092] adders 52 and 54 arranged in parallel. Each adder is coupled to the output of 2 of the 3 adders of the first calculation stage. One adder 52 is coupled directly to the fourth calculation stage, Both adders 52 and 54 are coupled to the third calculation stage.
  • The third calculation stage comprises a [0093] single adder 56 which takes as its input the outputs from both adders 52 and 54 of the second calculation stage. The output of the adder 56 is coupled to the fourth calculation stage.
  • The fourth calculation stage comprises 3 [0094] dividers 58, 60 and 62 arranged in parallel which respectively divide the output of adder 46 by 2, the output of adder 52 by 4 and the output of adder 56 by 8.
  • The output of the subcalculation unit outputs are control point values of the n[0095] th level patch, namely An=An−1, and the outputs of the three dividers 58, 60 and 62 as Bn, Cn and Dn respectively.
  • The pipelined system achieves high system clock rates. [0096]
  • Calculation of A[0097] n, Bn, Cn and Dn the values of control points in the subpatch from An−1, Bn−1, Cn−1 and Dn−1 the values of the corresponding control points in the patch which is being subdivided, is performed by the subcalculation unit in a series of additions. The first stage of the calculation is to calculate in parallel first stage intermediate values P, Q and R where
  • P=A n−1 +B n−1
  • Q=B n−1 +C n−1
  • R=C n−1 +D n−1.
  • The second stage is to calculate in parallel second stage intermediate values S and T where S=P+Q and T=Q+R. [0098]
  • The third stage is to calculate a third stage intermediate value U, where U=S+T. [0099]
  • In the fourth stage the values V=P/2, W=S/4 and X=U/8 are calculated in parallel and the values A[0100] n=An−1, Bn=V, Cn=W and Dn=X are outputted from the subcalculation unit.
  • Each subcalculation unit calculates the values of four new control points in the nth level sub-patch. Calculation of each set of four new control points is independent of the calculation of the other 12 control points. Thus, by using four subcalculation units in parallel, the 16 new control points of the n[0101] th level sub-patch may be calculated in a minimum number of clock cycles thereby achieving a high throughput. The outputs of the four subcalculation units are assembled in the output multiplexer (mux) 44 to generate the control point matrix for the nth level sub-patch.
  • The subcalculation units are required to work on different elements of the 4×4 control point matrix depending on which category of subdivision is being carried out. However, by including input and output multiplexers in the subdivision unit, four identical subcalculation units may be used to calculate the new control points. The function of the input and output muxes will now be described. [0102]
  • Input Mux [0103]
  • The function of the input mux is to allow the rows and columns of the n−1[0104] th level patch control point matrix to be swapped to control the category of subdivision implemented by the subcalculation units.
  • For subdivision in t, the rows of the control point matrix are indexed A to D and the columns of the [0105] control point matrix 1 to 4 from left to right. The direction of indexing for the rows depends on whether a top half patch or bottom half patch is to be generated. To generate a top half patch, the rows are indexed starting with A as the top row of the matrix and ending with D as the bottom row of the matrix. Thus the top row of control points of the nth level top half sub-patch are identical to the top row of control points of the n−1th level patch. The remaining three rows of the nth top half sub-patch are related to the rows of the control points of the nth level patch as defined in the equation 1 above. Similarly, the bottom row of control points of the nth level bottom half sub-patch are identical to the bottom row of the control points of the n−1th level patch and the remaining rows are related to the rows of the n−1th level matrix in accordance with equation 1.
  • FIGS. 8[0106] a and 8 b show the appropriate indexing of a n−1th level patch in order to perform division in t taking the top half sub-patch and division in t taking the bottom half sub-patch respectively. Thus, to generate a bottom half from subdivision in t, the rows of the may first be inverted and then processed as for top half sub-patch generation forming interim data which must then be arranged to form the required sub-patch data.
  • For subdivision in se the columns of the patch are indexed A to D and the rows are indexed 1 to 4 from top to bottom. The direction of indexing for the columns depends on whether a left half sub-patch or right half sub-patch is to be generated. To generate a left half sub-patch, the columns are indexed starting with A as the left column and ending with D as the right column of the patch. Thus the left hand column of control points of the level left half subpatch are identical to the left hand column of control points of the n−1th level patch. The remaining three columns of the left half sub-patch are related to the columns of the control points of the n−1th level patch as defined in the [0107] equation 1 above. Similarly, the right hand column of control points of the nth level right half sub-patch is identical to the right hand column of the control points of the n−1th level patch and the remaining columns are related to the columns of the n−1th level patch in accordance with equation 1.
  • FIGS. 8[0108] c and 8 d show the appropriate indexing of a n−1th level patch in order to perform division in s taking the left half sub-patch and division in s taking the right half sub-patch respectively. Thus, to generate a left half sub-patch from subdivision in s, the rows and columns of the patch may first be swapped and the rearranged patch processed as for top half sub-patch generation. Similarly to generate a right half sub-patch from subdivision in s, the rows are inverted then the rows and columns swapped. Processing for a top half sub-patch subdivided in t is performed and the resulting control points rearranged by the output mux to correspond to the required right half subpatch.
  • Output Mux [0109]
  • The function of the output mux is analogous to that of the input mux. It arranges the interim data output by the subdivision unit according to the category of subdivision to form the required subpatch control point matrix. Assuming that the subcalculation unit is set up to perform top half subdivision in t, the output of the subcalculation unit must be rearranged to produce bottom half subdivision in t and left and right half subdivision in s. The output mux assembles the four outputs of the subcalculation units into a single matrix and reverses the rearrangement carried out by the input mux to produce the required subpatch control matrix. [0110]
  • Once the element-wise control data for the n[0111] th level sub-patch has been assembled in the appropriate order, that is as per FIG. 7a, 7 b, 7 c or 7 d according to the category of subdivision, it is either outputted to the weighting processor 20 and direction processor 24 if it relates to a leaf patch, or returned to the recursion buffer 16 if it relates to an intermediate patch.
  • In the interface, the subdivision calculation is implemented as shown in FIG. 9. This implementation of the subdivision architecture has been found to be very efficient. A prior-art method presented in Watt & Watt requires more ‘caling’ steps which can become a significant cost in a hardware floating point implementation. The [0112] subdivision unit 18 comprises a number of stages. Each stage performs one level of subdivision. The second stage subdivision may be bypassed if the required level of subdivision is reached after processing by the first stage. In the presently preferred embodiment, two stages, a first stage 30 and a second stage 32, are implemented in the subdivision unit 18. Inclusion of two subdivision stages has the advantage of increasing the raw calculation performance of the system for a given amount of data bandwidth from the recursion buffer. The number of stages may be changed to provide the required size/performance trade-off in the final system. Each stage consists of an input multiplexer 34, four subcalculation processors 36, 38, 40 and 42 and an output multiplexer 44.
  • In the first stage, data for an element of the patch is read from the [0113] recursion buffer 16. The input and output muxes 34 and 44 respectively allow the rows and columns of the matrix of elements to be rearranged controlling the calculation which is performed. The calculations options are
  • Subdivide in s, output left half [0114]
  • Subdivide in s, output right half [0115]
  • Subdivide in t, output top half [0116]
  • Subdivide in t, output bottom half [0117]
  • Bypass [0118]
  • The [0119] input mux 34 rearranges the matrix according to the category of subdivision required and passes four control points of the n−1th level patch to each subcalculation unit for processing. The output of each subcalculation unit is fed to the output mux 44 which assembles the outputs of the subcalculation unit and arranges the matrix into the required sub-patch according to the category of subdivision required. The output from the output mux 44 of stage 1 is processed as the input to the input mux 34 of stage 2. The stage 2 output is either fed back to the recursion buffer 16, or fed on to the following calculations stages if a leaf patch has been reached.
  • The use of the input and output muxes eliminates the need for four separate blocks of subcalculation units and therefore minimises the number of component parts of the curved surface subdivision system. [0120]
  • The operation of the [0121] subdivision unit 18 is controlled by a series of instructions presented from the control unit 22. The control unit 22 operates on the algorithm presented in the flowchart of FIG. 10. The control unit 22 causes a root patch to be taken from the recursion buffer 16 and passed to the input mux 34 of the first stage.
  • It is assumed that the assignment of the four patch subdivision levels, corresponding to the four edges of the patch, have been computed externally either in software or hardware. [0122]
  • The [0123] control unit 22 determines whether subdivision in the t dimension is required by testing the subdivision values of the left and right hand edges of the root patch control matrix. If neither the left nor the right hand edge value lies between the values 1.0 and 2.0, subdivision of the patch in t is required. The left and right hand edge values are divided by 2. A command to divide in t is sent by the control unit 22 to the subdivision unit 18 causing the appropriate rearrangement of the data by the input mux and arrangement of the interim data by the output mux. Having divided in t it is then necessary to calculate new subdivision values for the top and bottom edges. If top half subdivision is carried out then the top row of the control matrix is unchanged and the top value for the top half sub-patch is carried over from the undivided matrix. However, top half subdivision results in the bottom row of the sub-patch differing from that of the undivided matrix. The bottom value must therefore be updated. The new value is calculated as either the average or preferably the geometric mean of the top and bottom values of the undivided matrix. The geometric mean is preferable because it more usefully distributes the levels of subdivision across the patch. For bottom half subdivision, it is the top value of the subdivided matrix which must be calculated whilst the bottom edge value is carried over from the undivided matrix. The top edge value is calculated in the same way as that of the bottom edge value for top half subdivision.
  • The [0124] control unit 22 continues subdivision in the t dimension until the exit condition is met, at which point processing advances to the s dimension. The exit condition is met when either the left or the right hand edge value lies between 1.0 and 2.0 indicating that further subdivision in t of the entire patch is not required. Further processing of the patch may however be required if the resulting patch is irregular. Processing of irregular patches is described later.
  • Processing in the s dimension proceeds in a similar way but with the top and bottom edge values being tested to determine whether subdivision in s is required. New right and left edge values are calculated for the left half subdivision and right half subdivision respectively. The new right and left edge values are calculated as either the average or preferably the geometric mean of the left and right edge values of the undivided matrix. Once the s dimension exit condition is met, t is re-checked and the processing loops as required. The exit condition for s subdivision is met when either the left or right edge value is between 1.0 and [0125] 2.0. As with t subdivision, further processing of the resulting patch may be necessary if it is irregular.
  • Once both s and t exit conditions have been met the root or intermediate patch has been processed to a first level of subdivision and has generated data representing an end-point, leaf patch. A command is then sent from the [0126] control unit 22 to the subdivision unit 18 to output its leaf patch data.
  • The [0127] control unit 22 monitors the number of passes through its algorithm that have been completed. On the first pass, the control unit 22 sends a control signal to the subcalculation unit 18 to force the top half sub-patch to be calculated for division in t, and the left half sub-patch to be calculated for division in s. A history of the commands sent to the subdivision unit 18 from the control unit 22 is recorded. This command history is then used on subsequent passes to ensure that all the other sequences are exercised. The final pass of the control unit algorithm has been executed when dividing in t always takes the bottom half sub-patch as output, and dividing in s always takes the right half sub-patch as output.
  • Processing of Regular Leaf Latches [0128]
  • If the leaf patch has each of its final edge values between 1.0 and 2.0, then the leaf-patch is said to be regular. The regular leaf patch is processed to generate nine vertices of a grid of triangles arranged to cover the patch as shown in FIG. 11 by a converter. Preferably the converter is incorporating [0129] processer 20. The tessellating triangles cover a square with three vertices set out in a regular array on each side of the square and the ninth vertex positioned in the centre of the square. The triangles are arranged fanning around the square so that each of the eight triangles shares the centre vertex of the square. Alternative patterns, such as that shown in FIG. 12 and often seen in prior art, can also be used.
  • One advantage of the arrangement in FIG. 11 over that of FIG. 12 is that the triangles produced will be independent of the order of the original patch's control points. That is, swapping the definition of S and T in the original patch, or reversing the order of the control points will produce identical results. A second advantage is that it is closer in pattern to that generated when processing ‘irregular’ leaf patches. [0130]
  • Conversion from the leaf patch to the nine output vertex positions is performed in the “Leaf Patch Tessellation Unit” [0131] 20. The corresponding surface normals for these vertices are similarly computed in the “Surface Normal Generation Unit” 24. At this stage in the processing operation, the algorithm for minimizing polygon popping is implemented.
  • FIG. 16 shows schematically the conversion from the control point data of a regular patch to the nine vertices of the tessellating triangles. Assume that the 16 control points of the patch are arranged in a 4×4 matrix with the points indexed Pij where j varies from 0 to 3 and indicates which row of the matrix the control point is located with [0132] row 0 being the top row and i varies from 0 to 3 and indicates which column of the matrix the control point is located with column 0 being the left hand column. Assume also that the nine vertices of tessellating triangles are arranged in a 3×3 square with the top left vertex indexed V0 and the index incrementing clockwise around the 3×3 square to the centre left vertex, V7, and the central vertex being indexed V8.
  • The four outer vertices of the tessellating triangles are derived directly from the outer control points of the regular leaf patch. The top left vertex, V[0133] 0, takes the value of the top left control point, P00, the top right vertex, V2, takes the value of the top right control point, P30, the bottom left vertex, V6, takes the value of the bottom left control point, P03, and the bottom right vertex, V4, takes the value of the bottom right is control point, P33.
  • Generation of the remaining 5 vertices, V[0134] 1, V3, V5, V7 and V8, is slightly more complex.
  • Consider the diagram of FIG. 17, where the curve can be considered to be one of the edges of the leaf patch, with points A and B being two of the corner vertices, say V[0135] 0 and V2. If a further subdivision were performed, this would yield a new point on the curve C, which would correspond to a possible position of the middle vertex, V1. Conversely, if the number of subdivisions were to remain the same, then the curve would be approximated by the line AB, and V1 would lie on the line at point D. In order to achieve a smooth transition between points C and D as the level of subdivision changes, a new point E is calculated along the line CD, and this is used as the value of V1. This is expressed in the following equation:
  • E=wC+(1−w) D   Equation 2
  • where w is the weight factor, derived from the fractional part of the edge subdivision ratio, D is a first vertex value derived at leaf-patch subdivision level and C is s second vertex value derived at the sub-leaf patch subdivision level. (Note that the fractional part of the edge ratio is trivially obtained by examining the mantissa of a binary floating point representation of the value). [0136]
  • D is calculated by taking the mean of the two corner vertices; in the case of FIG. 16, V[0137] 0 and V2 correspond to points A and B respectively. To calculate C, a left half subdivision in s is performed and C takes the value of the top right control point of the left half subdivided patch. To calculate the value of C for the left(right) edge, the Bezier curve along the left(right) edge of the leaf-patch is evaluated at t=½. Note that this is identical to just computing Dn in FIG. 7. The calculation for the ‘C’ point in the tope and bottom edges is analogous. Once the values of C (the second value) and n (the first value) have been calculated, the vertex, V1, is calculated according to equation 2. This calculation is performed by a combiner. The combiner may be an integral part of the tessellation unit 20.
  • This calculation is repeated for each edge of the leaf patch quadrilateral. The centre point is calculated in a similar fashion, however the calculation of point C for V[0138] 8 requires a subdivision in both the s and t dimensions. This can be efficient done by using, say, the ‘C’ values computed from the top and bottom edges, computing two additional ‘C’ values from the two centre rows of control points, and then re-applying the method of these four values.
  • Because of the preferred tessellation pattern, i.e. shown in FIG. 11, in the calculation of D for V[0139] 8, one of the diagonal pairs of vertices, either (V0, V4) or (V2, V6) are used. The choice of which diagonal pair is based on the relative position of the leaf patch to the root patch. FIG. 18a shows a chequer board arrangement showing the relative position of leaf patches to the root patch for 16 leaf patches. The leaf patch squares are arranged in four rows and four columns and cover the root patch. Half the squares are shaded and the remaining squares are unshaded in an alternating pattern. The top left square is shaded. Referring to FIG. 18, tho shaded leaf patches use (V0,V4) in the calculation of point D whilst the calculation of D for the unshaded leaf patches uses (V2,V6). For other numbers of leaf patches, similar diagrams can be constructed applying the same patterning technique.
  • This preferred patterning scheme guarantees that as the subdivision level ‘crosses a power of two boundary’, the arrangement of triangles will not abruptly change. As the subdivision level is increased, any new triangles created are guaranteed to ‘lie inside’ the parent triangles. This is shown in FIG. 18[0140] b. For example, the introduced centre point in the upper left leaf patch of the more highly tessellated region (shown on the right) would depend on the top-left to centre half-diagonal from the ‘parent’ leaf (on the left). Note that this is alternating operation would not be necessary for the triangulation pattern shown in FIG. 17.
  • Irregular Patch Processing [0141]
  • Subdivision is terminated in any one direction, s or t, if either one of the relevant edge values lies between 10 and 2.0. Further processing of the leaf patch is required if it is irregular, that is if one or more edges have an edge value which lies outside the range 1.0 to 2.0. An irregular leaf patch may be considered to be a regular leaf patch which requires additional vertices on the edge whose subdivision value is outside range to enable it to be joined to the adjacent patch. The irregular leaf patch is first treated as a regular leaf patch and the nine vertices for the patch are calculated as described above. To calculate the additional vertices, further subdivision is performed. The further subdivision may be carried out in the same subdivision unit as subdivision to form leaf-patches and may be controlled from the [0142] control unit 22. The conversion of the fan patches to provide additional vertices may be carried out in the converter for the leaf-patches or in a separate converter.
  • An example of subdivision processing for an irregular leaf patch with a right edge value outside the range 1.0 to 2.0 is shown in FIGS. 13[0143] a and 14. In this example, the right edge subdivision value would be between 2.0 and 4.0 indicating that one additional level of subdivision is required to generate two extra vertices (V23 and V34) required on the right hand edge to prevent cracking. The additional vertices are provided on the edge of the leaf patch whose edge value is outside the 1.0 to 2.0 range; in this case the right hand edge. The triangles described by the additional vertices fan out from the centre vertex of the patch, splitting the original triangles spanning this edge in two. Thus, in the example, the right edge of the irregular patch has five (instead of three) vertices, namely V2, V23, V3, V34 and V4 in a clockwise direction, defining four triangles all with a common vertex at V8: V8-V2-V23, V8-V23-V3, V8-V3-V34 and V8-V34-V4.
  • V[0144] 23 and V34 are calculated by performing further subdivisions in
    Figure US20040113909A1-20040617-P00999
    until the right edge value is made to lie between 1.0 and 2.0 and by using the output of the additional subdivision to form a series of fan patches which are used to generate the new vertices, V23 and V34. The fan patches are not used in the calculation of the nine standard vertices, V0 to V8, corresponding to the vertices for a regular leaf-patch.
  • The processing required to generate the additional vertices for the irregular leaf-patch of FIGS. 13[0145] a and 14 is described by way of example. By following the example, it will be clear to the skilled man how to generate additional vertices for other types of irregular patch.
  • As the example has a right edge value in the range 2.0 to 4.0 it will be seen that only one level of subdivision will be required to bring the right edge value within the range 1.0 to 2.0. The irregular patch processing steps are summarised in the flow diagram of FIG. 15. The edge values of the irregular patch are tested to determine which edge values are outside the range 1.0 to 2.0. Processing proceeds on an edge-wise basis. In the case of the example of FIGS. 13[0146] a and 14, only the right hand edge value is outside the range. This indicates that only subdivision in t is required. The control unit 22 sends the appropriate command signal to the subdivision unit 18 to divide the irregular patch in L. The edge values of the fan patches are computes as described above for the appropriate general form of subdivision. The top and bottom half subpatches returned by 18 define upper and lower fan patches which may be used to compute the additional vertices V23 and V24. The control unit 22 maintains a history of the fan patch generation to ensure the generation of all appropriate fan patches. In this case, after generation of a top half (an patch and a bottom half fan patch, all edge values are within the range 1.0 and 2.0 and no further subdivision to form fan patches is required.
  • The additional vertex V[0147] 23 is obtained by calculating the centre right vertex of the upper fan patch in accordance with equation 2 described above. The additional vertex V24 is calculated by estimating the centre right vertex of the lower fan patch in accordance with equation 2 above.
  • None of the other vertices of the fan patches are required in the tessellation process. The irregular leaf polygon data is generated by combining the vertices generated by the normal subdivision process to form a leaf patch, the “first plurality of vertices'”, and the additional vertices calculated from the fan patches, the “fan patch values'”. [0148]
  • Background to Calculation of the Direction of the Vertex Surface Normals [0149]
  • The surface [0150] normal generation unit 24 takes the output of the subdivision unit 18 and calculates the surface normal associated with each vertex. (Note that in the preferred embodiment, the units 20 and 24 are separate but, in an alternative embodiment, they could share a number of calculations that they have in common.) The surface normal is used to indicate the direction that the surface being modelled is facing at the sample point and is required for subsequent lighting and texturing calculations. The direction processor 24 calculates the normal for each vertex of the leaf patch including any additional vertices calculated from irregular patches. To minimise the shading analog of polygon popping, the same linear interpolation method as described previously by equation 2, is also applied to the normals of interior vertices, i.e. the output normal may be a blend of the neighbouring vertices' normals and the ‘correct’ normal.
  • Note that, ideally, it is actually the final shading and texturing values that should be ‘blended’. In the preferred embodiment this is not done due to constraints imposed by external graphics standards (e.g. Microsoft's DirectX). To one skilled in the art it should be apparent that the presented ‘polygon popping reduction’ method could easily be applied after the vertex shading is computed should these constraints be removed. [0151]
  • As known in the prior art, computation of surface normals can be simpler for the four vertices located at the corners of non-rotational Bezier patches. An example of this has been shown in FIG. 19. The invention adapts this principal for use with rational patches. [0152]
  • Since only four of the points initially lie at the corners of a leaf patch, the invention performs additional ‘partial’ subdivisions of the leaf. This processing is shown in FIG. 20. In the case of the nine vertices of a regular leaf patch (the numbering of which is that used in FIG. 11), three additional partial subdivisions (one in S ([0153] 20(iii)), one in T (20(ii), and an additional subdivision (20(iv)) are sufficient to produce child sub-patches such that positions of V1, V3, V5, V7 and V0, are at the corners of at least one sub-patch. Note that not all control points of each sub-patch are needed to generate the vertex normals and in the preferred embodiment only the minimum required control points are calculated. In FIG. 20, the control points which are needed (either directly for computation of a corner normal or for generation of the required child patch's control points) are shown in grey or black, while those that aren't required are shown in white.
  • As stated, the invention computes the normals for rational Bezier patches in an efficient manner, the method and reasoning behind which will now be presented. [0154]
  • The position of a rational surface at parameter location (s,t)(s,t) is given by: [0155] B _ 3 D ( s , t ) = B _ x y z ( s , t ) B w ( s , t )
    Figure US20040113909A1-20040617-M00005
  • while the definition of the unit length tangent vector, at (0,0) in the direction (a,b) is defined by: [0156] T ^ a b ( 0 , 0 ) = lim o 0 ( B _ 3 D ( e a , e b ) - B _ 3 D ( 0 , 0 ) B _ 3 D ( e a , e b ) - B _ 3 D ( 0 , 0 ) )
    Figure US20040113909A1-20040617-M00006
  • Examining the “difference” terms in the expression we have . . . [0157] B _ 3 D ( e a , e b ) - B _ 3 D ( 0 , 0 ) = B _ x y z ( e a , e b ) w ( e a , e b ) - B _ x y z ( 0 , 0 ) w ( 0 , 0 )
    Figure US20040113909A1-20040617-M00007
  • . . . which implies . . . [0158]
  • Since the scalar value (w(ea,eb)w(0,0) is positive and non-zero, it can be applied to both top and bottom of the above limit equation giving: [0159] T ^ a b ( 0 , 0 = lim e 0 ( B _ x y z ( e a , e b ) · w ( 0 , 0 ) - B _ x y z ( 0 , 0 ) · w ( e a , e b ) B _ x y z ( e a , e b ) · w ( 0 , 0 ) - B _ x y z ( 0 , 0 ) · w ( e a , e b ) ) ) eqn 3
    Figure US20040113909A1-20040617-M00008
  • Restricting our attention to rational Bezier parametric surfaces and noting that the (0,0)(0,0) point of Bezier patch corresponds to the {overscore (P)}[0160] 00 control point, we thus need to examine the behaviour of . . .
  • {overscore (B)} xyz(ea,eb).P 00w ·{overscore (P)} 00XYZ .w(ea,eb).
  • For convenience, we will define [0161]
  • {overscore (B)} Delta(ea,eb)={overscore (B)} xyz(ea,eb).P 00w −{overscore (P)} 00XYZ .w(ea,eb).
  • In the preferred embodiment, the Bezier functions are bicubic. Extensions of this scheme to embodiments using surfaces of higher order should be straightforward to one skilled in the art. [0162]
  • We now express the bicubic homogenous Bezier surface (i.e. prior to the division of the x, y, and z components by the w component) at (ea,eb) in the matrix form to obtain: [0163]
  • It can thus be seen that this can be expressed as: [0164] B _ ( e a , e b ) = ( [ e 3 a 3 e 2 a 2 e a 0 ] + [ 0 0 0 1 ] ) Q P Q T ( [ e 3 b 3 e 2 b 2 e b 0 ] T + [ 0 0 0 1 ] T ) = [ e 3 a 3 e 2 a 2 e a 0 ] Q P Q T [ e 3 b 3 e 2 b 2 e b 0 ] T + [ 0 0 0 1 ] Q P Q T [ e 3 b 3 e 2 b 2 e b 0 ] T [ e 3 a 3 e 2 a 2 e a 0 ] Q P Q T [ 0 0 0 1 ] T + [ 0 0 0 1 ] Q P Q T [ 0 0 0 1 ] T
    Figure US20040113909A1-20040617-M00009
  • Noting the particular properties of the Q matrix, this simplifies to [0165] B _ ( e a , e b ) = [ e 3 a 3 e 2 a 2 e a 0 ] Q P Q T [ e 3 b 3 e 2 b 2 e b 0 ] T + [ 1 0 0 0 ] P Q T [ e 3 b 3 e 2 b 2 e b 0 ] T + [ e 3 a 3 e 2 a 2 e a 0 ] Q P [ 1 0 0 0 ] T + P 00
    Figure US20040113909A1-20040617-M00010
  • which in turn reduces to . . . [0166] B _ ( ea , eb ) = [ e 3 a 3 e 2 a 2 ea 0 ] QPQ T [ e 3 b 3 e 2 b 2 eb 0 ] T + P top - row Q T [ e3b3 e2b2 eb 0 ] T + [ e 3 a 3 e 2 a 2 ea 0 ] QP left - column + P 00
    Figure US20040113909A1-20040617-M00011
  • This invention's method computes up to three potential tangent candidates, these being the ‘S’, ‘T’, and ‘diagonal’ tangent candidates. [0167]
  • Derivation of a candidate tangent vector in the ‘S’ direction: [0168]
  • If we consider the case of producing a tangent vector in the ‘S’ direction, then equations 3 and 4 respectively reduce to: [0169] T ^ s ( 0 , 0 ) = lim e 0 ( B Delta ( e , 0 ) B Delta ( e , 0 ) )
    Figure US20040113909A1-20040617-M00012
  • and [0170]
  • {overscore (B)}(e,0)=└e 3 e 2 e 0┘QP left columns +P 00
  • Examining {overscore (B)}[0171] Delta(e,0) we find: B _ Delta ( e , 0 ) = B _ xyz ( e , 0 ) · P 00 w - P 00 xyz · w ( e , 0 ) = ( [ e 3 e 2 e 0 ] QP left column xyz + P 00 xyz ) P 00 w - P 00 xyz ( [ e 3 e 2 e 0 ] QP left - column w + P 00 w ) = [ e 3 e 2 e 0 ] QP left - column xyz · P 00 w P 00 xyz [ e 3 e 2 e 0 ] QP left - column w
    Figure US20040113909A1-20040617-M00013
  • We now consider 3 cases: [0172] 1. T ^ s ( 0 , 0 ) = lim e 0 ( B _ Delta ( e , 0 ) B _ Delta ( e , 0 ) ) = lim e 0 ( 1 e · B _ Delta ( e , 0 ) 1 e · B _ Delta ( e , 0 ) ) 2. T ^ s ( 0 , 0 ) = lim e 0 ( B _ Delta ( e , 0 ) B _ Delta ( e , 0 ) ) = lim e 0 ( 1 e 2 · B _ Delta ( e , 0 ) 1 e 2 · B _ Delta ( e , 0 ) ) 3. T ^ s ( 0 , 0 ) = lim e 0 ( B _ Delta ( e , 0 ) B _ Delta ( e , 0 ) ) = lim e 0 ( 1 e 3 · B _ Delta ( e , 0 ) 1 e 3 · B _ Delta ( e , 0 ) )
    Figure US20040113909A1-20040617-M00014
  • For each of the above cases, from calculus it is known that if the limits as e→0 of both the numerator and denominator exist (and the limit is non zero), then the limit of the entire expression exists). [0173]
  • Case 1: [0174]
  • Starting with the numerator/denominator ‘contents’ we have [0175] lim e 0 1 e B _ Delta = lim e 0 [ e 2 e 1 0 ] Q P _ left - column xyz · P 00 w - P _ 00 xyz [ e 2 e 1 0 ] QP left - column w = [ 0 0 1 0 ] Q P _ left - column xyz · P 00 w - P _ 00 xyz [ 0 0 1 0 ] QP left - column w = [ - 3 3 0 0 ] P _ left - column xyz · P 00 w - P _ 00 xyz [ - 3 3 0 0 ] QP left - column w = 3 ( ( P _ 10 xyz · P _ 00 xyz ) · P 00 w - P _ 00 xyz ( P 10 w - P 00 w ) ) = 3 ( P 10 xyz P 00 w - P _ 00 xyz P 10 w )
    Figure US20040113909A1-20040617-M00015
  • The limit clearly exists and will be non-zero if and only if {overscore (P)}[0176] 10 xyz P00w≠P00xyzP10w. If this condition holds then a tangent vector in the direction S is given by {overscore (T)}S1={overscore (P)}10 xyz P00w≠P00xyzP10 w . Note that the length of the vector is immaterial at this point.
  • Case 2: [0177]
  • if the condition of [0178] case 1 is not met, (i.e. {overscore (P)}10 xyz P00w≠P00xzyP10 w ), then the limits of the second case are examined. This gives: lim e 0 1 e 2 B _ Delta ( e , 0 ) = lim e 0 1 e ( B _ Delta ( e , 0 ) )
    Figure US20040113909A1-20040617-M00016
  • Noting that . . . [0179] 1 e B _ Delta ( e , 0 ) = [ e 2 e 1 0 ] Q P _ left_column xyz · P 00 w - P _ 00 xyz [ e 2 e 1 0 ] QP left_column w = [ e 2 e 0 0 ] Q P _ left_column xyz · P 00 w - P _ 00 xyz [ e 2 e 0 0 ] QP left_column w + [ 0 0 1 0 ] Q P _ left_column xyz · P 00 w - P _ 00 xyz [ 0 0 1 0 ] QP left_column w
    Figure US20040113909A1-20040617-M00017
  • . . . we see that the second part of the sum is the same as the result from [0180] case 1, which have assumed to be zero. We thus get lim e 0 1 e 2 B Delta ( e , 0 ) = lim e 0 1 e [ e 2 e 0 0 ] Q P _ left column xyz · P 00 w - P _ 00 xyz [ e 2 e 0 0 ] QP left_column w = lim e 1 e [ e e 0 0 ] Q P _ left_column xyz · P 00 w - P _ 00 xyz [ e e 0 0 ] QP left_column w = [ 0 1 0 0 ] Q P _ left_column xyz · P 00 w - P _ 00 xyz [ 0 1 0 0 ] QP left_column w = [ 3 - 6 3 0 ] P left_column xyz · P 00 w - P _ 00 xyz [ 3 - 6 3 0 ] P left_column w = ( 3 P _ 20 xyz - 6 P _ 10 xyz + 3 P _ 00 xyz ) P 00 w - P _ 00 xyz ( 3 P _ 20 w - 6 P _ 10 xyz + 3 P _ 00 xyz ) = ( 3 P _ 20 xyz + 3 P _ 00 xyz ) P 00 w - P _ 00 xyz ( 3 P _ 20 w + 3 P _ 00 xyz ) · 6 ( P _ 10 xyz P 00 w - P _ 00 xyz P _ 10 w )
    Figure US20040113909A1-20040617-M00018
  • Again we have assumed {overscore (P)}[0181] 10 xyz P00w={overscore (P)}00xyzP10 w and so this = ( 3 P _ 20 xyz + 3 P _ 00 xyz ) · P 00 w - P _ 00 xyz ( 3 P _ 20 w + 3 P _ 00 w ) becomes = 3 ( P _ 20 xyz P 00 w - P _ 00 xyz P _ 20 w )
    Figure US20040113909A1-20040617-M00019
  • Thus if the chosen conditions hold, there is a valid ‘S’ tangent {overscore (T)}[0182] 03={overscore (P)}30 xyz P00w−{overscore (P)}00xyz{overscore (P)}30 w if this is non-zero.
  • Case 3: [0183]
  • Should both [0184] cases 2 and 3 fail, then using a similar argument to these presented, an “S” may be computed from {overscore (T)}03={overscore (P)}30 xyz P00w−{overscore (P)}00xyz{overscore (P)}30 w , provided that is non zero.
  • Derivation of a Candidate Tangent Vector in the ‘T’ Direction: [0185]
  • This follows exactly the same reasoning as for the “S” tangent, and so will not be discussed here. [0186]
  • Derivation of a Candidate Tangent Vector in the ‘diagonal’ Direction: [0187]
  • If the {overscore (T)}[0188] and {overscore (T)} candidate tangent are linearly dependent then by themselves they are not suitable for generating the normal vector. In this case it is necessary to manufacture another tangent candidate, which will be referred to as the ‘diagonal’ tangent candidate.
  • For the purposes of the preferred embodiment, it is assumed that at least one of {overscore (T)}[0189] or {overscore (T)} is non-zero—the first non-zero choice will be called {overscore (T)}NZ. Under these conditions, a ‘diagonal’ tangent vector candidate will be chosen to the {overscore (T)}diag={overscore (P)}11 xyz P00w−{overscore (P)}00xyz{overscore (P)}11 w . The mathematics behind this choice is somewhat more involved, and so will not be presented here.
  • It should now be clear that with the above method, up to eight control points may be required for the computation of a particular corner vertex's normal. FIG. 21 illustrates the set for the case of the V[0190] 0 (i.e. (s,t)=(0,0)) corner vertex. Because the choice of control points will change depending on the vertex normal being calculated, a different nomenclature will be employed for the remainder of the discussion. The control points used for the calculation of a particular vertex normal will be called C, S1, S2, S3, T1, T2, T3, and D. As an example, the correspondence between this naming scheme and the required control vertices for vertex V0 is also shown in FIG. 21.
  • Preferred embodiment of “Surface Normal generation Unit” The surface normal generation unit, [0191] 24, is now explained with reference to FIG. 22a.
  • The leaf patch's control points are supplied, [0192] 200, and for each of the V0, V2, V4, and V6 vertices the correct set of 8 control points (C, S1, S2, S3, T1, T2, T3, D) are selected, 201, and supplied in turn to the corner normal unit, 202. Note that only the X, Y, Z, and W components of the control points are required in the surface normal generation unit.
  • [0193] Unit 201 is a MUX that chooses which of the original leaf patch control points correspond to each of the four sets of 8 points. In the preferred embodiment, the four selections are as follows:
  • Vertex V[0194] 0: this is shown in FIG. 21. V 2 : C = P 30 { = V2 } D = P 21 S 1 = P 31 S 2 = P 32 S 3 = P 33 T 1 = P 20 T 2 = P 10 T 3 = P 00 V 4 : C = P 33 { = V4 } D = P 22 S 1 = P 23 S 2 = P 13 S 3 = P 03 and T 1 = P 32 T 2 = P 31 T 3 = P 30 V 6 : C = P 03 { = V6 } D = P 12 S 1 = P 02 S 2 = P 01 S 3 = P 00 T 1 = P 13 T 2 = P 23 T 3 = P 33
    Figure US20040113909A1-20040617-M00020
  • It should be noted that, in the preferred embodiment, the orientation of the ‘virtual’ S, T, and diagonal tangent candidates rotates by 90° with each successive corner vertex. This is done to maintain a consistent orientation of the surface normal. [0195]
  • In an alternative embodiment, selection of the control points by mirroring of the existing axis directions could be used but this would require an additional flag to be supplied to unit ‘[0196] 202’ to indicate if the result of the cross products should be negated. Such a negation would have to be indicated for at least vertices V2 and V6. (Vertex V4 would need no negation as both axes would have been flipped).
  • [0197] Unit 203 performs a partial subdivision of the leaf patch in order to compute new control points suitable for the generation of surface normals for vertices V1 and V6. The set required has been illustrated in FIG. 20(ii). Unit 204 is another multiplexor which selects the required points for each of V1 and V5 respectively and supplied them to the corner normal unit, 202. The selection process is analogous to that of unit 201 and should be obvious to one skilled in the art given the previous description.
  • In a similar fashion, [0198] units 205 and 206 produce the two sets of control points needed for the normals of vertices V3 and V7 (see FIG. 20(iii).
  • [0199] Units 207 and 208 produce the set of eight control points needed to generate the surface normal for V8. This set is illustrated in FIG. 20(iv). Note that the four control points shown on the right edge of FIG. 20(iv) can be obtained by a single subdivision of the right edge of FIG. 20(ii), while the bottom edge is computed from a single subdivision of the bottom edge of FIG. 20(iii). The control point corresponding to “D” can be obtained from either the second bottom row of FIG. 20(iii) or alternatively from the second right most column of 20(ii).
  • For performance reasons, a preferred embodiment overlaps the calculation of several vertex normals via a combination of multiple units and a pipelined architecture. In alternative embodiments, the level of parallelism could be varied as a cost/performance trade-off. [0200]
  • The “corner normal unit”, [0201] 202, is now dismissed with reference to FIG. 22b. Note that for clarity, this figure only describes the computation of a single normal. The eight chosen control points are input, 220. The C point and three S points are sent to the “S Candidate” computation unit, 221, C and three T points are sent to the “T Candidate” computation unit, 222, while C and D are sent to the “Diagonal Candidate” unit. The three computed tangent candidates, TS, TT, and TDiag, are then input into ‘candidate selection and normal calculation’ unit, 224.
  • The function of [0202] 221 will now be described with reference to the flowchart in FIG. 23. Although not explicitly shown in this figure, the preferred embodiment uses a pipelined architecture to compute each of the products, such as S1 XYZ CW or S2 w CXYZ, “simultaneously”. Similarly, the comparison operations are also carried out in a pipelined fashion. At step 210, the first two products, S1 XYZ CW and CXYZS1 w are compared. (Those familiar with floating point arithmetic will appreciate that equality tests are simpler than subtraction). If these products are not equal then the TS tangent vector is computed in step 241 by taking the difference of the two. If, on the other hand, the two products are equal, then the next pair of products, S2 XYZ CW and CXYZS2 w are compared, 242. If these differ, TS is set to be the difference of the pair, 243. Instead, if the products were identical, then the final pair of products, S3 XYZ CW and CXYZS3W, are compared, 244, and if different, TS, is computed, while if they are identical, then the tangent is marked as being zero.
  • In an alternative embodiment an additional ‘optimisation’ can be included to initially test if the w or ‘wright’ component values are identical before optionally performing the multiplication. This could potentially reduce the computation delay for cases where the patches are non-rational, i.e. where the w values are constant. [0203]
  • It should thus be noted that only one vector subtract unit is required and in the preferred embodiment, this is pipelined. In alternative embodiments, the subtract unit could also be shared with [0204] units 222 and 223.
  • [0205] Unit 222 is similar to that 221 except that it computes TT, while unit 223 simply calculates TDiag=DXYZCW−CXYZDW.
  • [0206] Unit 224 is now described with reference to FIG. 24. Tests 250 and 252 check for the special cases where either TX or TY may be a zero vector, and set in intermediate vector, TNZ, to be either −TT (251) or TS (253) respectively. If both vectors are non-zero, then a candidate surface normal is produced in step 254 by taking the vector cross product of TS and TT. The candidate normal is then compared against zero, 255. If it is not zero, then it is used as the surface normal, 256. If it is zero, then the intermediate vector is set in step 253.
  • If the intermediate vector was required, then the alternative normal calculation is employed, [0207] 257. This computes the cross product of the intermediate vector and the diagonal tangent candidate. Note that in step 251, TNZ was sent to be the negative of TT. This is done to maintain consistency of the normal orientation. It should be appreciated that negation of floating point values is trivial.
  • As stated earlier, the normals thus calculated for vertices V[0208] 1, V3, V5, V7, and V8 represent those at the maximum fractional subdivision level within the leaf patch. For the smaller fractional levels, the same blending process used to eliminate polygon popping is also applied to produce the final normal vector results. Similarly, the calculation of normals for irregular leaf patches must undergo extra levels of subdivision akin to that previously described.
  • It should thus be appreciated that the invention computes the surface normals for rational Bezier surfaces without requiring expensive division operations. This is a significant saving. With the preferred embodiment, the normals that are output are not unit vectors—with the preferred embodiment it is assumed that the subsequent shading and transformation units, which are not described in the document, will be capable of performing this sample task if required. [0209]
  • Returning to FIG. 6, the final stage of the pipelined tessellation process is performed in the [0210] output buffer 26. The input buffer 12 took the control point grouped data and regrouped the data by element. The output buffer 26 is required to perform the reverse task of grouping the data from the calculation stages by vertex. The output buffer 26 takes the vertices calculated by the weighting processor 20 and the normals calculated by the surface normal processor 24, groups together the data for each element by vertex and outputs it for subsequent use in the transformation, lighting, texturing and rasterization of the image for display.
  • It should be noted that the features described by reference to particular figures and at different points of the description may be used in combinations other than those particularly described or shown. All such modification are encompassed within the scope of the invention as set forth in the following claims. [0211]
  • With respect to the above description, it is to be realized that equivalent apparatus and methods are deemed readily apparent to one skilled in the art, and all equivalent apparatus and methods to those illustrated in the drawings and described in the specification are intended to be encompassed by the present invention. Therefore, the foregoing is considered as illustrative only of the principles of the invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation shown and described, and accordingly, all suitable modifications and equivalents may be resorted to, falling within the scope of the invention. [0212]
  • For example, alternative patterns of tessellating triangles are considered to fall within the scope of the invention. [0213]

Claims (28)

1. An interface for use in a 3-d graphics system comprising a parametric modelling unit for modelling objects as high order surfaces and a polygon based rendering system for rendering polygon modelled objects for display, the interface comprising:
a) an input, for receiving data representing at least one high order surface patch;
b) a subdivision unit, coupled to the input, for processing the data to form leaf patch data representing the patch at a first level of subdivision and for further processing the data to form sub-leaf patch data representing the patch at a second level of subdivision;
c) a converter, coupled to the subdivision unit, for determining from the leaf patch data a first plurality of values representing vertices of tessellating polygons describing the leaf patch, and for determining from the sub-leaf patch data a second plurality of value representing the vertices of tessellating polygons describing the sub-leaf patch;
d) a combiner, coupled to the converter, for combining the first and second plurality of values to form leaf polygon data defining the polygon vertices at the first subdivision level; and
e) an output, coupled to the combiner, for outputting the leaf polygon data.
2. An interface according to claim 1, wherein the combiner is a weighting processor for performing a weighted average of the first and second plurality of values.
3. An interface according to claim 2, further comprising a control unit, coupled to the subdivision unit and to the weighting processor, for controlling processing of the data by the subdivision unit and for generating a fractional value, w, for use by the weighting processor in the weighted average of the first and second plurality of values.
4. A method of interfacing between a parametric modelling unit and a polygon based rendering system in a 3-d graphics systems, the method comprising the steps of
a) receiving data representing at least one high order surface patch;
b) processing the data to form leaf patch data representing the patch at a first level of subdivision;
c) determining from the leaf patch data a first plurality of values representing the vertices of a plurality of tessellating polygons describing the leaf patch;
d) further processing the data to form sub-leaf patch data representing the patch at a second level of subdivision;
e) determining from the sub-leaf patch data a second plurality of values representing the vertices of the plurality of tessellating polygons describing the sub leaf patch;
f) combining the first and second plurality of values to form leaf polygon data defining the polygon vertices at the first subdivision level; and
g) outputting the leaf polygon data.
5. A method according to claim 4, wherein processing the data in step (d) requires a single level of subdivision of the leaf patch data.
6. A method according to either claim 4 or claim 5, wherein the combination of first and second plurality of values in step (f) is a weighted average.
7. A method according to claim 6, further comprising the step of controlling the processing of data by the subdivision unit and generating a fractional value, w, for use in the weighted average.
8. An interface for a 3-d graphics system comprising a parametric modelling unit and a polygon based rendering system, the interface comprising:
a) an input for receiving data representing at least one high order surface patch, patch subdivision data representing a first level of subdivision required for the patch, and edge subdivision data representing a second level of subdivision required for at least one edge of the patch;
b) a subdivision unit, coupled to the input, for processing the data to form leaf patch data representing the patch at the first level of subdivision and further processing the data to form fan patch data representing the patch at the second level of subdivision;
c) a converter, coupled to the subdivision unit, for determining from the leaf patch data a first plurality of values representing the vertices of tessellating polygons describing the leaf patch and for determining from the fan patch data fan patch values representing vertices of additional tessellating polygons to those represented by the first plurality of values further describing the leaf patch;
d) a combiner, coupled to the converter, for combining the first plurality of values and the fan patch values to form irregular leaf polygon data defining the vertices of an irregular pattern of tessellating polygons at the first subdivision level; and
e) an output, coupled to the combiner, for outputting the irregular leaf polygon data.
9. An interface according to claim 8, further comprising a control unit, coupled to the subdivision unit, for controlling the processing of the data by the subdivision unit to subdivide the patch in a first direction to the required level in the first direction and to subsequently subdivide the patch in a second direction to the required level in the second direction.
10. A method of interfacing between a parametric modelling unit and a polygon based rendering system in a 3-d graphics system, the method comprising the steps of:
a) receiving data representing at least one high order surface patch, patch subdivision data representing a first level of subdivision required for the patch, and edge subdivision data representing a second level of subdivision required for at least one edge of the patch;
b) processing the data to form leaf patch data representing the patch at the first level of subdivision;
c) determining from the leaf patch data a first plurality of values representing the vertices of tessellating polygons describing the leaf patch;
d) further processing the data to form fan patch data representing the patch at the second level of subdivision;
e) determining from the fan patch data fan patch values representing vertices of additional tessellating polygons to those represented by the first plurality of values, the additional tessellating polygons further describing the leaf patch;
f) combining the first plurality of values and the fan patch values to form irregular leaf polygon data defining the vertices of an irregular pattern of tessellating polygons at the first subdivision level; and
g) outputting the irregular leaf polygon data.
11. A method according to claim 10, further comprising the step of controlling the processing of the data by the subdivision unit to subdivide the patch in a first direction to the required level in the first direction and to subsequently subdivide the patch in a second direction to the required level in the second direction.
12. An interface for a 3-d graphics system comprising a parametric modelling unit and a polygon based rendering system, the interface comprising:
a) an input for receiving data representing at least one high order surface patch;
b) an input multiplexer, coupled to the input, for rearranging the data;
c) a subdivision unit, coupled to the input multiplexor, for processing the data to form interim data representing one portion of the patch at a level of subdivision in a first subdivision direction;
d) an output multiplexer, coupled to the subdivision unit, for arranging the interim data to form leaf patch data representing the required portion of the patch in the required direction at the level of subdivision;
e) a control unit, coupled to the input multiplexor and to the output multiplexor, for controlling the rearrangement of the data and the arrangement of the interim data to allow generation of the required portion of the patch in the required direction;
f) a polygonisation processor, coupled to the output multiplexor, for determining leaf polygon data representing the vertices of tessellating polygons describing the required portion of the patch at the level or subdivision in the required direction; and
g) an output, coupled to the polygonisation processor, for outputting the leaf polygon data.
13. An interface according to claim 12, wherein the subdivision unit comprises four subcalculation units, coupled in parallel to the input and output multiplexers and to the control unit, each subcalculation unit processing a quarter of the data to form a quarter of the interim data and wherein the control unit selects from the data the quarter of data for processing by each subcalculation unit.
14. An interface according to claim 13, wherein each subdivision unit comprises:
a) a first calculation stage, coupled to the input multiplexor for receiving data comprising four values An−1, Bn−1, Cn−1 and Dn−1 and coupled to second and fourth calculation stages, the first calculation stage comprising three adders for performing in parallel the additions:
P=A n−1 +B n−1; Q=B n−1 +C n−1; R=C n−1 +D n−1;
 and for outputting P to the fourth calculation stage and P, Q and R to the second calculation stage;
b) the second calculation stage, coupled to the first, and fourth calculation stages and to a third calculation stage, comprising two adders for performing in parallel the additions:
S=P+Q; T=Q+R;
 and for outputting S to the fourth calculation stage and S and T to the third calculation stage;
c) the third calculation stage, coupled to the second and fourth calculation stages, comprising one adder for performing the addition:
U−S+T;
 and for outputting U to the fourth calculation stage;
d) the fourth calculation stage comprising three dividers for performing in parallel the divisions:
V=P/2; W=S/4; X=U/8;
 and for outputting V, W and X to an output; and
e) an output, coupled to the first and fourth calculation stages and to the output multiplexor of the subdivision unit, for outputting the quarter interim data An=An−1, Bn=V, Cn=W and Dn=X.
15. An interface according to any of claims 12 to 14, further comprising a recursion buffer coupled to the input multiplexer and to the output multiplexer for storing data representing a root patch and processed data.
16. A method of interfacing between a parametric modelling unit and a polygon based rendering system in a 3-d graphics system, the method comprising the steps of:
a) receiving data representing at least one high order surface patch;
b) rearranging the data;
c) processing the rearranged data to form interim data representing one portion of the patch at a level of subdivision in a first subdivision direction;
d) arranging the interim data to form leaf patch data representing the required portion of the patch in the required direction at the level of subdivision;
e) wherein the steps of rearranging of the data and arranging of the interim data are controlled to generate the required portion of the patch in the required direction;
f) determining leaf polygon data representing the vertices of tessellating polygons describing the required portion of the patch at the level of subdivision in the required direction; and
g) outputting the leaf polygon data;
17. A method according to claim 17, further comprising the steps of separating the data into quarters, processing in parallel the four quarters of data, and assembling the quarter interim data.
18. A method according to claim 17, wherein the processing in each subdivision unit comprises the steps of:
a) receiving data comprising four values An−1, Bn−1, Cn−1 and Dn−1, performing in parallel the additions:
P=A n—1 +B n−1; Q=B n−1 +C n−1; R=C n−1 +D n−1;
b) performing in parallel the additions:
S=P+Q; T=Q+R;
c) performing the addition:
U=S+T;
d) performing in parallel the divisions:
V=P/2; W=S/4; X=U/8; and
e) outputting the quarter interim data An=An−1, Bn=V, Cn=W and Dn=X.
19. A method according to claim 18, further comprising the step of storing data representing a root patch and processed data for reducing the processing time.
20. An interface substantially as hereinbefore described with reference to any of FIGS. 6 to 17.
21. A method of interfacing between a parametric modelling unit and a polygon based rendering system substantially as hereinbefore described with reference to any of FIGS. 6 to 17.
22. A 3-d graphics system comprising apparatus for determining a surface normal vector for a vertex of a surface patch used in modelling of an object to be shaded by the system, the apparatus comprising:
means for subdividing the patch to produce a plurality of sub-patches each having corner vertices;
means for deriving the locations of control points required for derivation of a surface normal for a vertex;
means for deriving a plurality of candidate tangent vectors at a vertex from the control point locations; and
means for deriving a surface normal from the candidate tangent vectors.
23. A method for determining a surface normal vector for a vertex of a surface patch used in modelling of an object to be shaded in a 3-d graphics system, the method comprising the steps of:
subdividing the patch to produce a plurality of sub-patches each having corner vertices;
deriving the locations of control points required for determining a surface normal for a vertex;
deriving a plurality of candidate tangent vectors at a vertex from the control point data; and
deriving a surface normal from the candidate tangent vectors.
24. A method for determining a surface normal for a vertex according to claim 23 in which the step of deriving the locations of control points comprises:
deriving a first subset of control points along one edge of the patch adjacent to a chosen corner;
deriving a second subset of control points along the other edge of the patch adjacent to the chosen corner;
deriving a third subset of control points consisting of a control point off-set from the corner of the patch in each of a set of chosen parameter dimensions;
wherein the step deriving a plurality of candidate tangent vectors comprises deriving first, second and third candidate tangent vectors from each respective subset of control points and the corner points; and
selecting two of the three candidate tangent vectors to derive a surface normal at the chosen corner.
25. A method for determining surface normal vectors for vertexes of a surface patch used in modelling of an object to be shaded in a 3-d graphic system, the method comprising the steps of:
deriving surface normals for four corner vertices;
partially subdividing the patch in a first parameter dimension to derive a first subset of control points of a first sub-patch;
partially subdividing in a second parameter dimension to derive a second subset of control points of a second sub-patch;
performing a third partial subdivision to derive a third subset of control points from the first and second subsets of control points;
deriving surface normals for two mid-point vertices using the first subset of control points;
deriving surface normals for the remaining two mid-point vertices from the second subset of control points;
deriving a surface normal for a vertex at the centre of the patch from the third subset of control points.
26. A method according to claim 23 and 24 wherein a candidate tangent vector at a corner control point is derived by repeatedly selecting control points from a given subset of control points in any given order; and
deriving a first weighted vector by multiplying a chosen control point's components by a weighting component of the corner control point;
deriving a second weighting vector by multiplying the components of the corner control point by a weighting vector of a chosen control point;
deriving a difference vector between the first and second weighted vectors; and
using the difference vector as the candidate tangent vector if it is non-zero, and otherwise progressing to the next control point of the subset.
27. A 3-d graphics system comprising apparatus for determining a surface normal vector for a vertex of a surface patch used in modelling of an object to be shaded by the system substantially as herein described with reference to FIGS. 20-24 of the drawings.
28. A method for determining a surface normal vector for a vertex of a surface patch used in modelling an object to be shaded in a 3-d graphics system substantially as herein described with reference to FIGS. 20-24 of the drawings.
US10/435,759 2002-05-10 2003-05-09 Interface and method of interfacing between a parametric modelling unit and a polygon based rendering system Abandoned US20040113909A1 (en)

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Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060033737A1 (en) * 2004-08-16 2006-02-16 Old William M Methods and system for visualizing data sets
US20060044313A1 (en) * 2004-08-26 2006-03-02 Lake Adam T Subdividing geometry images in graphics hardware
US20060050072A1 (en) * 2004-08-11 2006-03-09 Ati Technologies Inc. Unified tessellation circuit and method therefor
US20060125824A1 (en) * 2004-12-14 2006-06-15 Adrian Sfarti Rapid zippering for real time tesselation of bicubic surfaces
US20070106155A1 (en) * 2005-10-31 2007-05-10 Novelis, Inc. System and method for reducing angular geometric distortion in an imaging device
US20070268287A1 (en) * 2006-05-22 2007-11-22 Magnin Paul A Apparatus and method for rendering for display forward-looking image data
US20080049018A1 (en) * 2000-07-28 2008-02-28 Adrian Sfarti Bicubic Surface Real Time Tesselation Unit
US20080287801A1 (en) * 2006-08-14 2008-11-20 Novelis, Inc. Imaging device, imaging system, and methods of imaging
US20100186061A1 (en) * 2009-01-18 2010-07-22 Gavriel Raanan Distributed processing for interactive video
US7785286B2 (en) 2006-03-30 2010-08-31 Volcano Corporation Method and system for imaging, diagnosing, and/or treating an area of interest in a patient's body
USRE42534E1 (en) * 2000-07-28 2011-07-12 Adrian Sfarti Bicubic surface real-time tesselation unit
US20110225576A1 (en) * 2010-03-09 2011-09-15 Jacob Guedalia Data streaming for interactive decision-oriented software applications
US20130297059A1 (en) * 2012-04-09 2013-11-07 Autodesk, Inc. Three-dimensional printing preparation
US20140225891A1 (en) * 2008-02-01 2014-08-14 Microsoft Corporation Efficient geometric tessellation and displacement
TWI451358B (en) * 2007-02-14 2014-09-01 Photint Venture Group Inc Banana codec
US20150317818A1 (en) * 2012-11-02 2015-11-05 Imagination Technologies, Ltd. On Demand Geometry and Acceleration Structure Creation
US20160049001A1 (en) * 2013-06-25 2016-02-18 Google Inc. Curvature-Driven Normal Interpolation for Shading Applications
US20160063737A1 (en) * 2014-08-29 2016-03-03 Ati Technologies Ulc Extension of the mpeg/sc3dmc standard to polygon meshes
US9754409B2 (en) 2013-12-04 2017-09-05 Canon Kabushiki Kaisha Method, apparatus and system for tessellating a parametric patch
US20190311536A1 (en) * 2018-04-05 2019-10-10 Imagination Technologies Limited Tessellation Hardware Subdivision of Patches Into Sub-Patches
US20220392139A1 (en) * 2018-04-05 2022-12-08 Imagination Technologies Limited Ordering of Patch Selection in Tessellation Operations

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050156930A1 (en) * 2004-01-20 2005-07-21 Matsushita Electric Industrial Co., Ltd. Rendering device and rendering method
JP4255449B2 (en) * 2005-03-01 2009-04-15 株式会社ソニー・コンピュータエンタテインメント Drawing processing apparatus, texture processing apparatus, and tessellation method
US20080043023A1 (en) * 2006-08-15 2008-02-21 Microsoft Corporation Approximating subdivision surfaces with bezier patches
US7952580B1 (en) * 2007-08-31 2011-05-31 Adobe Systems Incorporated Classification of exterior and interior triangles for artwork rendering
US8643644B2 (en) * 2008-03-20 2014-02-04 Qualcomm Incorporated Multi-stage tessellation for graphics rendering
JP5078712B2 (en) * 2008-04-01 2012-11-21 任天堂株式会社 Image processing program, image processing apparatus, image processing system, and image processing method
US8243075B2 (en) * 2008-10-14 2012-08-14 Autodesk, Inc. Graphics processing unit accelerated dynamic radial tessellation
US20100231586A1 (en) * 2009-03-13 2010-09-16 Zebra Imaging, Inc. Processing Graphics Primitives in an Epsilon View Volume
US20100231585A1 (en) * 2009-03-13 2010-09-16 Zebra Imaging, Inc. Systems and Methods for Processing Graphics Primitives
US20100253683A1 (en) * 2009-04-01 2010-10-07 Munkberg Carl J Non-uniform tessellation technique
US8884957B2 (en) 2009-09-09 2014-11-11 Advanced Micro Devices, Inc. Tessellation engine and applications thereof
US8698802B2 (en) * 2009-10-07 2014-04-15 Nvidia Corporation Hermite gregory patch for watertight tessellation
US8810572B2 (en) * 2011-10-31 2014-08-19 Qualcomm Incorporated Tessellation cache for object rendering
CN103268634B (en) * 2012-02-24 2016-08-24 苏州蓝海彤翔系统科技有限公司 A kind of out-of-core models fast parallel adaptive simplifying method based on Vertex Clustering
US9007380B1 (en) * 2012-05-01 2015-04-14 Google Inc. Animated 3D buildings in virtual 3D environments
US9305397B2 (en) * 2012-10-24 2016-04-05 Qualcomm Incorporated Vertex order in a tessellation unit
US9196088B2 (en) 2013-03-14 2015-11-24 Robert Bosch Gmbh System and method for classification of three-dimensional models in a virtual environment
KR102104057B1 (en) 2013-07-09 2020-04-23 삼성전자 주식회사 Tessellation method for assigning a tessellation factor per point and devices performing the method
DE102014007914A1 (en) * 2014-05-27 2015-12-03 Elektrobit Automotive Gmbh Graphing roads and routes using hardware tessellation
GB2552260B (en) 2015-06-05 2019-04-10 Imagination Tech Ltd Tessellation method
GB2539042B (en) 2015-06-05 2019-08-21 Imagination Tech Ltd Tessellation method using displacement factors
GB2533443B (en) 2015-06-05 2018-06-06 Imagination Tech Ltd Tessellation method using recursive sub-division of triangles
US10242496B2 (en) * 2017-04-24 2019-03-26 Intel Corporation Adaptive sub-patches system, apparatus and method
US11017265B1 (en) 2020-01-29 2021-05-25 ReportsNow, Inc. Systems, methods, and devices for image processing
CN112330556B (en) * 2020-11-03 2022-04-19 燕山大学 Spherical screen projection geometric correction method based on rational Bessel curved surface
US11158031B1 (en) 2021-05-24 2021-10-26 ReportsNow, Inc. Systems, methods, and devices for image processing
WO2022250654A1 (en) * 2021-05-24 2022-12-01 Uiarmor.Com Llc Systems, methods, and devices for image processing

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5428718A (en) * 1993-01-22 1995-06-27 Taligent, Inc. Tessellation system
US5995109A (en) * 1997-04-08 1999-11-30 Lsi Logic Corporation Method for rendering high order rational surface patches
US6078331A (en) * 1996-09-30 2000-06-20 Silicon Graphics, Inc. Method and system for efficiently drawing subdivision surfaces for 3D graphics
US20010013866A1 (en) * 1999-01-27 2001-08-16 Alexander Migdal Adaptive subdivision of mesh models
US6563501B2 (en) * 2000-07-28 2003-05-13 Adrian Sfarti Bicubic surface rendering
US6597356B1 (en) * 2000-08-31 2003-07-22 Nvidia Corporation Integrated tessellator in a graphics processing unit
US20040001060A1 (en) * 2002-07-01 2004-01-01 Silicon Graphics, Inc. Accurate boolean operations for subdivision surfaces and relaxed fitting
US6707452B1 (en) * 2000-07-19 2004-03-16 Pixar Method and apparatus for surface approximation without cracks

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2726134B2 (en) * 1990-01-12 1998-03-11 三菱電機株式会社 3D model sampling and normal vector calculation method
JPH07271999A (en) * 1994-03-31 1995-10-20 Oki Electric Ind Co Ltd Outputting method for three-dimensional topography
JPH07311858A (en) * 1994-05-18 1995-11-28 Sony Corp Method and device for preparing free curved surface
US5828467A (en) * 1996-10-02 1998-10-27 Fuji Xerox Co., Ltd. Block noise prevention by selective interpolation of decoded image data
JP3732317B2 (en) * 1997-09-17 2006-01-05 株式会社ソニー・コンピュータエンタテインメント Information processing apparatus and method, and transmission medium
JP2001067491A (en) * 1999-08-30 2001-03-16 Sega Corp Method and device for image display using redivided polygon
JP3377488B2 (en) * 2000-02-10 2003-02-17 株式会社ナムコ GAME SYSTEM AND INFORMATION STORAGE MEDIUM
JP4483025B2 (en) * 2000-05-18 2010-06-16 ソニー株式会社 Image processing apparatus and information processing apparatus
WO2002075663A2 (en) * 2001-02-01 2002-09-26 Mental Images, G.M.B.H. & Co. Kg. Generating smooth feature lines for subdivision surfaces
US6940503B2 (en) * 2001-05-10 2005-09-06 Ati International Srl Method and apparatus for processing non-planar video graphics primitives
JP3522714B2 (en) * 2001-06-05 2004-04-26 松下電器産業株式会社 Image generation method

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5428718A (en) * 1993-01-22 1995-06-27 Taligent, Inc. Tessellation system
US6078331A (en) * 1996-09-30 2000-06-20 Silicon Graphics, Inc. Method and system for efficiently drawing subdivision surfaces for 3D graphics
US5995109A (en) * 1997-04-08 1999-11-30 Lsi Logic Corporation Method for rendering high order rational surface patches
US6057848A (en) * 1997-04-08 2000-05-02 Lsi Logic Corporation System for rendering high order rational surface patches
US6100894A (en) * 1997-04-08 2000-08-08 Lsi Logic Corporation Patch-division unit for high-order surface patch rendering systems
US20010013866A1 (en) * 1999-01-27 2001-08-16 Alexander Migdal Adaptive subdivision of mesh models
US6707452B1 (en) * 2000-07-19 2004-03-16 Pixar Method and apparatus for surface approximation without cracks
US6563501B2 (en) * 2000-07-28 2003-05-13 Adrian Sfarti Bicubic surface rendering
US6597356B1 (en) * 2000-08-31 2003-07-22 Nvidia Corporation Integrated tessellator in a graphics processing unit
US20040001060A1 (en) * 2002-07-01 2004-01-01 Silicon Graphics, Inc. Accurate boolean operations for subdivision surfaces and relaxed fitting

Cited By (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080049018A1 (en) * 2000-07-28 2008-02-28 Adrian Sfarti Bicubic Surface Real Time Tesselation Unit
USRE42534E1 (en) * 2000-07-28 2011-07-12 Adrian Sfarti Bicubic surface real-time tesselation unit
US7532213B2 (en) * 2000-07-28 2009-05-12 Adrian Sfarti Bicubic surface real time tesselation unit
US20060050072A1 (en) * 2004-08-11 2006-03-09 Ati Technologies Inc. Unified tessellation circuit and method therefor
US20100053158A1 (en) * 2004-08-11 2010-03-04 Ati Technologies Ulc Unified tessellation circuit and method therefor
US7639252B2 (en) * 2004-08-11 2009-12-29 Ati Technologies Ulc Unified tessellation circuit and method therefor
US20060033737A1 (en) * 2004-08-16 2006-02-16 Old William M Methods and system for visualizing data sets
US7750914B2 (en) * 2004-08-26 2010-07-06 Intel Corporation Subdividing geometry images in graphics hardware
US20060044313A1 (en) * 2004-08-26 2006-03-02 Lake Adam T Subdividing geometry images in graphics hardware
US8462159B2 (en) 2004-08-26 2013-06-11 Intel Corporation Subdividing geometry images in graphics hardware
US8217942B2 (en) 2004-08-26 2012-07-10 Intel Corporation Subdividing geometry images in graphics hardware
US20060125824A1 (en) * 2004-12-14 2006-06-15 Adrian Sfarti Rapid zippering for real time tesselation of bicubic surfaces
US7295204B2 (en) * 2004-12-14 2007-11-13 Adrian Sfarti Rapid zippering for real time tesselation of bicubic surfaces
US20070106155A1 (en) * 2005-10-31 2007-05-10 Novelis, Inc. System and method for reducing angular geometric distortion in an imaging device
US8047996B2 (en) 2005-10-31 2011-11-01 Volcano Corporation System and method for reducing angular geometric distortion in an imaging device
US8414496B2 (en) 2005-10-31 2013-04-09 Volcano Corporation System and method for reducing angular geometric distortion in an imaging device
US10512446B2 (en) 2006-03-30 2019-12-24 Volcano Corporation Method and system for imaging, diagnosing, and/or treating an area of interest in a patient's body
US7785286B2 (en) 2006-03-30 2010-08-31 Volcano Corporation Method and system for imaging, diagnosing, and/or treating an area of interest in a patient's body
US8491567B2 (en) 2006-03-30 2013-07-23 Volcano Corporation Method and system for imaging, diagnosing, and/or treating an area of interest in a patient's body
US7612773B2 (en) * 2006-05-22 2009-11-03 Magnin Paul A Apparatus and method for rendering for display forward-looking image data
US20070268287A1 (en) * 2006-05-22 2007-11-22 Magnin Paul A Apparatus and method for rendering for display forward-looking image data
WO2007139697A3 (en) * 2006-05-22 2008-03-20 Novelis Investments Canada Apparatus and method for rendering for display forward-looking image data
US20080287801A1 (en) * 2006-08-14 2008-11-20 Novelis, Inc. Imaging device, imaging system, and methods of imaging
TWI451358B (en) * 2007-02-14 2014-09-01 Photint Venture Group Inc Banana codec
US9547936B2 (en) * 2008-02-01 2017-01-17 Microsoft Technology Licensing, Llc Efficient geometric tessellation and displacement
US10269176B2 (en) * 2008-02-01 2019-04-23 Microsoft Technology Licensing, Llc Efficient geometric tessellation and displacement
US20170109927A1 (en) * 2008-02-01 2017-04-20 Microsoft Technology Licensing, Llc Efficient geometric tessellation and displacement
US20140225891A1 (en) * 2008-02-01 2014-08-14 Microsoft Corporation Efficient geometric tessellation and displacement
US20130160055A1 (en) * 2009-01-18 2013-06-20 Happy Cloud Inc. Distributed processing for interactive video
US20100186061A1 (en) * 2009-01-18 2010-07-22 Gavriel Raanan Distributed processing for interactive video
US20110225576A1 (en) * 2010-03-09 2011-09-15 Jacob Guedalia Data streaming for interactive decision-oriented software applications
US20130297059A1 (en) * 2012-04-09 2013-11-07 Autodesk, Inc. Three-dimensional printing preparation
US11203157B2 (en) 2012-04-09 2021-12-21 Autodesk, Inc. Three-dimensional printing preparation
US10248740B2 (en) * 2012-04-09 2019-04-02 Autodesk, Inc. Three-dimensional printing preparation
US10339696B2 (en) * 2012-11-02 2019-07-02 Imagination Technologies Limited On demand geometry and acceleration structure creation with discrete production scheduling
US11568592B2 (en) 2012-11-02 2023-01-31 Imagination Technologies Limited On demand geometry and acceleration structure creation with tile object lists
US20150317818A1 (en) * 2012-11-02 2015-11-05 Imagination Technologies, Ltd. On Demand Geometry and Acceleration Structure Creation
US10943386B2 (en) 2012-11-02 2021-03-09 Imagination Technologies Limited On demand geometry and acceleration structure creation with tile object lists
US10186070B2 (en) * 2012-11-02 2019-01-22 Imagination Technologies Limited On demand geometry and acceleration structure creation
US10242487B2 (en) * 2012-11-02 2019-03-26 Imagination Technologies Limited On demand geometry and acceleration structure creation
US9965893B2 (en) * 2013-06-25 2018-05-08 Google Llc. Curvature-driven normal interpolation for shading applications
US20160049001A1 (en) * 2013-06-25 2016-02-18 Google Inc. Curvature-Driven Normal Interpolation for Shading Applications
US9754409B2 (en) 2013-12-04 2017-09-05 Canon Kabushiki Kaisha Method, apparatus and system for tessellating a parametric patch
US10055857B2 (en) * 2014-08-29 2018-08-21 Ati Technologies Ulc Extension of the MPEG/SC3DMC standard to polygon meshes
US20160063737A1 (en) * 2014-08-29 2016-03-03 Ati Technologies Ulc Extension of the mpeg/sc3dmc standard to polygon meshes
US20190311536A1 (en) * 2018-04-05 2019-10-10 Imagination Technologies Limited Tessellation Hardware Subdivision of Patches Into Sub-Patches
US10977860B2 (en) * 2018-04-05 2021-04-13 Imagination Technologies Limited Tessellation hardware subdivision of patches into sub-patches
US11354859B2 (en) 2018-04-05 2022-06-07 Imagination Technologies Limited Tessellation hardware subdivision of patches into sub-patches
US20220392139A1 (en) * 2018-04-05 2022-12-08 Imagination Technologies Limited Ordering of Patch Selection in Tessellation Operations
US11676337B2 (en) 2018-04-05 2023-06-13 Imagination Technologies Limited Tessellation hardware subdivision of patches into sub-patches
US11928768B2 (en) * 2018-04-05 2024-03-12 Imagination Technologies Limited Ordering of patch selection in tessellation operations

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