US20040119113A1 - Programmable memory transistor - Google Patents
Programmable memory transistor Download PDFInfo
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- US20040119113A1 US20040119113A1 US10/324,346 US32434602A US2004119113A1 US 20040119113 A1 US20040119113 A1 US 20040119113A1 US 32434602 A US32434602 A US 32434602A US 2004119113 A1 US2004119113 A1 US 2004119113A1
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- 238000009792 diffusion process Methods 0.000 claims abstract description 52
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 37
- 229920005591 polysilicon Polymers 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000012212 insulator Substances 0.000 claims abstract description 24
- 239000003990 capacitor Substances 0.000 claims abstract description 19
- 239000004020 conductor Substances 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 230000005669 field effect Effects 0.000 claims description 8
- 239000002356 single layer Substances 0.000 claims description 3
- 239000000969 carrier Substances 0.000 claims description 2
- 230000008878 coupling Effects 0.000 abstract description 8
- 238000010168 coupling process Methods 0.000 abstract description 8
- 238000005859 coupling reaction Methods 0.000 abstract description 8
- 230000014759 maintenance of location Effects 0.000 description 17
- 238000012360 testing method Methods 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000006731 degradation reaction Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000005641 tunneling Effects 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000001747 exhibiting effect Effects 0.000 description 2
- 238000011835 investigation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- -1 e.g. Substances 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000028161 membrane depolarization Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- the present invention generally relates to semiconductor devices. More particularly, this invention relates to a programmable memory transistor having a floating gate that exhibits improved voltage retention.
- PMT Programmable memory transistors
- EPROM electrically programmable read only memory
- EEPROM electrically erasable programmable read only memory
- IGFET insulated gate field effect transistor
- nonvolatile refers to the retention of memory without the need of a power source, here by trapping a charge on a “floating” gate disposed above the IGFET channel region and typically below a conventional control gate electrode, such that the control and floating gates are “stacked.”
- the floating gate is described as “floating” because it is electrically insulated from the channel region by a gate oxide, typically insulated from the control gate by a “tunnel” oxide, and not directly accessed by any electrical conductor.
- PMT's can be electrically programmed after manufacture by placing an electrical charge on the floating gate by the effects of tunneling or avalanche injection from the control gate electrode through the tunnel oxide.
- the charge is trapped there until it is deliberately removed, such as by exposure to ultraviolet light.
- the trapped charge on the PMT floating gate raises the threshold voltage of the underlying channel region of the IGFET, thus raising the “turn on” voltage of the IGFET to a value above the voltage otherwise required for the IGFET. Accordingly, the IGFET stays “off” even when a normal turn-on voltage is applied to its control gate electrode.
- PMT's are typically fabricated in the same semiconductor substrate as MOS (metal-oxide-semiconductor) transistors, which are single-polysilicon layer structures and therefore require fewer patterning steps than PMT's. Therefore, PMT's have been proposed that make use of a single polysilicon layer, such as that disclosed in U.S. Pat. No. 6,324,097.
- FIG. 1 An example of another single-polysilicon PMT is shown in FIG. 1, in which a PMT 110 is fabricated on a semiconductor substrate 112 doped with an N-type impurity.
- a P-well 114 is formed in a surface region of the substrate 112 , and divided by a field oxide 116 into two active regions.
- An NMOS transistor 118 is formed in one of the active regions and conventionally includes source and drain regions 120 and 122 in the P-well 114 , a channel 124 between the source and drain regions 120 and 122 , and a gate electrode 126 separated from the channel 124 by a gate insulator 128 (e.g., silicon dioxide).
- Source and drain metal 130 and 132 make ohmic contact with the source and drain regions 120 and 122 , respectively.
- the gate electrode 126 of the NMOS transistor 118 is a floating gate, in that it is not directly connected to a gate metal or other conductor.
- the gate electrode 126 is defined by a single polysilicon layer that also defines a second floating gate 146 of a control gate structure 138 fabricated in the second active region of the substrate 112 (on the right-hand side of FIG. 1).
- the control gate structure 138 represented in FIG. 1 includes two N+ contact diffusions 142 within an N-well 144 (though a single contact diffusion 142 or more than two contact diffusions 142 could be present).
- the N-well 144 serves as the control gate of the control gate structure 138 , effectively replacing the second polysilicon layer of a conventional double-polysilicon PMT.
- the control gate (N-well) 144 is separated from the second floating gate 146 by a gate oxide 148 , creating what is effectively a coupling capacitor.
- a control gate metal 150 contacts the N+ contact diffusions 142 to provide ohmic contact with the control gate 144 .
- the drain region 122 is biased at a high voltage level while the source region 120 and substrate 112 are electrically connected to ground, so that electrons are ejected from the drain region 122 through the gate insulator 128 into the floating gate 126 .
- Vth the measured mean decay of a stored potential
- Vth the measured mean decay of a stored potential
- Vth degradation There are three distinct phases of Vth degradation for nominal PMT's, each associated with a different possible physical mechanism of charge distribution/conduction and each having its own empirical “activation energy.”
- the low field conduction mechanism is generally accepted as being conduction by thermionic emission.
- the present invention is directed to a programmable memory transistor (PMT) that exhibits significantly better performance in terms of charge retention and reliability.
- the PMT of this invention is able to make use of a single polysilicon layer, and is capable of memory retention times of five orders of magnitude greater than similar single-polysilicon PMT's.
- the PMT also provides improved testability as a result of a greater measurement sensitivity for defects.
- the PMT of this invention generally comprises an insulated gate field effect transistor (IGFET) and a capacitor structure on a semiconductor substrate.
- IGFET insulated gate field effect transistor
- the IGFET comprises source and drain regions in a surface of the substrate, a channel between the source and drain regions, a gate insulator overlying the channel, and a first floating gate on the gate insulator.
- the capacitor structure comprises a lightly-doped well of a first conductivity type in the surface of the substrate, a heavily-doped first diffusion of the first conductivity type in the lightly-doped well, and a second diffusion of a second conductivity type in the lightly-doped well and spaced apart from the first diffusion so as to define therebetween a surface region of the lightly-doped well.
- the capacitor structure further comprises a control gate insulator that overlies the surface region of the lightly-doped well, a second floating gate on the control gate insulator, and a conductor in ohmic contact with the lightly-doped well through the first diffusion and in further contact with the lightly-doped well through the second diffusion.
- the first and second floating gates are electrically connected, preferably as a result of being formed of the same polysilicon layer, to maintain the first and second floating gates at the same potential.
- the second floating gate is capacitively coupled to the lightly-doped well through the control gate insulator so as to define a control gate for the first floating gate.
- a sufficient voltage can be applied to the lightly-doped well to cause ejection of electrons from the drain region of the insulated gate field effect transistor and trap some of the ejected electrons in the first floating gate.
- PMT's fabricated with the oppositely-doped diffusions as described above do not experience the initial drop in Vth that occurs with conventional single-polysilicon PMT's when exposed to elevated temperatures, e.g., during a data retention bake.
- the PMT of this invention is capable of far superior data retention over comparable single-polysilicon PMT's.
- An additional benefit of the invention is the ability to simplify and/or shorten the aforementioned stress test performed on conventional PMT's to evaluate device reliability on the basis of the initial Vth drop.
- FIG. 1 is a schematic cross-sectional view of a programmable memory transistor in accordance with the prior art.
- FIGS. 2 and 3 are schematic cross-sectional and plan views, respectively, of a programmable memory transistor in accordance with the present invention.
- FIGS. 4 through 9 are graphs comparing the voltage retention characteristics of programmable memory transistors configured in accordance with FIGS. 1 and 2.
- FIGS. 2 and 3 schematically represent a single-polysilicon PMT 10 capable of exhibiting superior memory retention in accordance with the present invention.
- the PMT 10 is similar to prior art double-polysilicon (“Poly 1 /Poly 2 ”) PMT's except that the second polysilicon layer is replaced with a lightly-doped well.
- the PMT 10 differs from prior art single-polysilicon PMT's (e.g., FIG. 1) by the use of diffusions of opposite conductivity type within a lightly-doped well that defines the control gate for the PMT, the effect of which is improved memory retention resulting from the elimination of the initial Vth drop observed with prior art single-polysilicon PMT's.
- the PMT 10 is fabricated on a silicon (preferably monocrystalline) substrate 12 doped with an N-type impurity, e.g., phosphorus, arsenic or another pentavalent element.
- a suitable doping level for the substrate 12 is on the order of about 5 ⁇ 10 15 cm ⁇ 2 .
- a P-well 14 is formed in a surface region of the substrate 12 by doping with boron or another trivalent element at a level of about 5 ⁇ 10 16 cm 2 .
- a field oxide 16 divides the P-well 14 into two active regions, one of which is occupied by an NMOS transistor 18 , while the other is occupied by a coupling capacitor 38 .
- the NMOS transistor 18 is formed to conventionally include source and drain regions 20 and 22 in the P-well 14 , a channel 24 between the source and drain regions 20 and 22 , and a polysilicon floating gate electrode 26 separated from the channel 24 by a gate oxide 28 .
- the source and drain regions 20 and 22 are more heavily doped than the substrate 12 , preferably at a level of about 1 ⁇ 10 20 cm ⁇ 2 .
- Source and drain metal 30 and 32 make ohmic contact with the source and drain regions 20 and 22 , respectively.
- a third region 23 heavily doped p-type for making ohmic contact with the P-well 14 .
- the polysilicon floating gate electrode 26 of the NMOS transistor 18 is formed by a layer of polysilicon that also defines a floating gate electrode 46 of the coupling capacitor 38 .
- the floating gate electrode 46 overlies a tunneling oxide 48 above a surface region of a lightly-doped N-type (NHV) diffusion 44 .
- the NHV diffusion 44 is preferably doped at a level of about 2 ⁇ 10 17 cm ⁇ 2 .
- Two diffusions 42 and 43 are shown as being formed within the NHV diffusion 44 , a first of which is a contact diffusion 42 heavily doped n-type, such as on the order of about 1 ⁇ 10 20 cm ⁇ 2 .
- the second diffusion is an injecting diffusion 43 heavily doped p-type, such as on the order of about 1 ⁇ 10 20 cm ⁇ 2 .
- the floating gate electrode 46 serves as an upper capacitor plate of the coupling capacitor 38 .
- the channel between the diffusions 42 and 43 in the NHV diffusion 44 serves as the second capacitor plate of the coupling capacitor 38 and the control gate for the NMOS transistor 18 .
- a control gate metal 50 contacts both the N+ contact diffusion 42 and the P+ injecting diffusion 43 through a dielectric layer 52 overlying the surface of the substrate 12 .
- the N+ contact diffusion 42 provides ohmic contact with the NHV diffusion 44 .
- the P+ injecting diffusion 43 does not provide ohmic contact with the NHV diffusion 44 .
- the P+ injecting diffusion 43 provides what is termed herein a “stitch” contact, and is believed to source holes into a P-type inversion layer at the surface of the NHV diffusion 44 when the PMT 10 is being programmed.
- the presence of the P+ injecting diffusion 43 has been demonstrated to greatly improve the memory retention of the PMT 10 as compared to a PMT that differs by having a pair of N+ contact diffusions (e.g., FIG. 1).
- all layers used in the PMT 10 are core process layers in NMOS processes, enabling the coupling capacitor 38 and the NMOS transistor 18 (as will as other MOS devices) to be fabricated simultaneously in the same substrate 12 .
- PMT's in accordance with FIG. 1 (“control”) and FIG. 2 were processed side-by-side on a PMT test array.
- the PMT's were fabricated on a monocrystalline silicon substrate with a twelve micrometer-thick N-type epitaxy having an impurity concentration of about 5 ⁇ 10 15 cm ⁇ 2 .
- P-wells were formed in surface regions of the substrate by doping with boron at a level of about 5 ⁇ 10 16 cm ⁇ 2 to a depth of about four micrometers.
- the source and drain regions of the NMOS transistors and the N+ contact diffusions of the coupling capacitors were heavily doped with arsenic to a level of about 1 ⁇ 10 20 cm ⁇ 2 and a depth of about 0.4 micrometers, while the P+ injecting diffusions of the PMT's of this invention and the P-well contact were heavily doped with boron to a level of about 1 ⁇ 10 20 cm ⁇ 2 and a depth of about 0.4 micrometers.
- the floating gates were patterned from a single layer of polysilicon deposited by low pressure chemical vapor deposition (LPCVD) to a thickness of about 3500 Angstroms.
- LPCVD low pressure chemical vapor deposition
- All devices were erased with a deep UV bake and then programmed from an initial Vth of about 2V.
- Programming the PMT's involved applying drain and gate voltages to the NMOS for a few milliseconds or less. With the source region grounded, a positive voltage of less than the NMOS breakdown voltage (BVdss) was applied through a current limiting resistor to the drain region and a positive voltage on the order of about 3 MV/cm applied to the control gate metal of each device, with the result that “hot” electrons were ejected from the drain regions and became stored on the polysilicon floating gates.
- BVdss NMOS breakdown voltage
- the control PMT's reached a Vth of about 7.5V, while the PMT's processed in accordance with this invention reached a higher Vth of about 8.5V.
- the PMT's were then subjected to a standard data retention bake at temperatures of about 160° C., 180° C. or 235° C.
- the control PMT'S experienced a rapid initial drop in Vth of between about 1.5 and 2.0V after the first hour of baking. After the initial Vth drop, the control PMT's stabilized and Vth began to drop at a much slower rate. As evidenced by FIGS.
- the PMT of this invention is characterized by improved testability as a result of a greater measurement sensitivity for defects. More particularly, the initial voltage drop exhibited by prior art PMT's necessitated a prolonged stress test to determine at what level their Vth's would stabilize. By eliminating the initial Vth drop, a defective PMT can be quickly identified by its displaying any rapid drop in Vth after programming.
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Abstract
Description
- Not applicable.
- Not applicable.
- (1) Field of the Invention
- The present invention generally relates to semiconductor devices. More particularly, this invention relates to a programmable memory transistor having a floating gate that exhibits improved voltage retention.
- (2) Description of the Related Art
- Programmable memory transistors (PMT), including electrically programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM) devices, are a type of insulated gate field effect transistor (IGFET) having nonvolatile memory. As used in the art, “nonvolatile” refers to the retention of memory without the need of a power source, here by trapping a charge on a “floating” gate disposed above the IGFET channel region and typically below a conventional control gate electrode, such that the control and floating gates are “stacked.” The floating gate is described as “floating” because it is electrically insulated from the channel region by a gate oxide, typically insulated from the control gate by a “tunnel” oxide, and not directly accessed by any electrical conductor. PMT's can be electrically programmed after manufacture by placing an electrical charge on the floating gate by the effects of tunneling or avalanche injection from the control gate electrode through the tunnel oxide. Once an electrical charge is placed on the floating gate, the charge is trapped there until it is deliberately removed, such as by exposure to ultraviolet light. The trapped charge on the PMT floating gate raises the threshold voltage of the underlying channel region of the IGFET, thus raising the “turn on” voltage of the IGFET to a value above the voltage otherwise required for the IGFET. Accordingly, the IGFET stays “off” even when a normal turn-on voltage is applied to its control gate electrode.
- Stacked control and floating gates require two separate conductor layers, typically polysilicon, resulting in a double-polysilicon (“Poly1/Poly2”) device structure. PMT's are typically fabricated in the same semiconductor substrate as MOS (metal-oxide-semiconductor) transistors, which are single-polysilicon layer structures and therefore require fewer patterning steps than PMT's. Therefore, PMT's have been proposed that make use of a single polysilicon layer, such as that disclosed in U.S. Pat. No. 6,324,097. An example of another single-polysilicon PMT is shown in FIG. 1, in which a
PMT 110 is fabricated on asemiconductor substrate 112 doped with an N-type impurity. A P-well 114 is formed in a surface region of thesubstrate 112, and divided by afield oxide 116 into two active regions. AnNMOS transistor 118 is formed in one of the active regions and conventionally includes source anddrain regions well 114, achannel 124 between the source anddrain regions gate electrode 126 separated from thechannel 124 by a gate insulator 128 (e.g., silicon dioxide). Source anddrain metal drain regions gate electrode 126 of theNMOS transistor 118 is a floating gate, in that it is not directly connected to a gate metal or other conductor. Instead, thegate electrode 126 is defined by a single polysilicon layer that also defines a second floatinggate 146 of acontrol gate structure 138 fabricated in the second active region of the substrate 112 (on the right-hand side of FIG. 1). Thecontrol gate structure 138 represented in FIG. 1 includes twoN+ contact diffusions 142 within an N-well 144 (though asingle contact diffusion 142 or more than twocontact diffusions 142 could be present). The N-well 144 serves as the control gate of thecontrol gate structure 138, effectively replacing the second polysilicon layer of a conventional double-polysilicon PMT. The control gate (N-well) 144 is separated from the second floatinggate 146 by agate oxide 148, creating what is effectively a coupling capacitor. Acontrol gate metal 150 contacts theN+ contact diffusions 142 to provide ohmic contact with thecontrol gate 144. - When programming the
prior art PMT 110, an electrical charge is placed on thefloating gate 126 of theNMOS transistor 118 by the effect of tunneling or avalanche injection from thechannel 124 of thegate electrode 126 through thegate insulator 128 to thefloating gate 126. For this purpose, a sufficiently high potential must be applied to thecontrol gate metal 150 to capacitively induce a charge in thefloating gate 146 as well as thefloating gate 126 as a result of thegates drain region 122 is biased at a high voltage level while thesource region 120 andsubstrate 112 are electrically connected to ground, so that electrons are ejected from thedrain region 122 through thegate insulator 128 into thefloating gate 126. - Because of the large interfacial barrier energy provided by the
gate insulator 128, a charge stored onto thefloating gate 126 has a long intrinsic storage time. For PMT's of the type shown in FIG. 1, the measured mean decay of a stored potential (Vth) may be about 0.2V/decade•hours at 160° C. Assuming an initial programmed mean Vth of about 8V, it would require about 1021 years for the PMT to discharge to a Vth of 3V. At the end of ten years, the leakage would have dropped to an average of one electron per day. Vth degradation in thePMT 110 is the result of and limited by physical processes. The magnitudes of the electric field and temperature dictate what conduction processes will be dominant. There are three distinct phases of Vth degradation for nominal PMT's, each associated with a different possible physical mechanism of charge distribution/conduction and each having its own empirical “activation energy.” First there is an initial period of rapid Vth loss, which is believed to be associated with the depolarization/dielectric absorption behavior observed to a lesser or greater degree in all capacitor dielectrics. Second, there is an intermediate period of charge loss associated with a high (but less than 6Mvolt/cm, where Fowler-Nordheim tunneling is dominant) but decaying electric field. It is possible that there is movement of trapped electrons during this intermediate period, which has an “activation energy” of about 0.2 eV. Ultimately, there is a long period of low field leakage through the gate insulator. The low field conduction mechanism is generally accepted as being conduction by thermionic emission. - When subjected to elevated temperatures, e.g., 160° C. or more, PMT's experience a significant initial drop in Vth attributed to the first degradation phase noted above. Thereafter, Vth stabilizes, though continuing to drop at a much lower rate attributed to the second and third degradation phases noted above. This lower rate is sufficiently low to permit the reliability of the device to be judged based on the initial Vth drop. Accordingly, PMT's typically undergo a data retention bake, or stress test, that involves baking at a sufficiently high temperature to cause the initial drop in Vth. A PMT is deemed to have passed the stress test if its Vth has not dropped below a predetermined level at the completion of the high temperature bake.
- From the above, it can be appreciated that PMT's capable of exhibiting more stable Vth, corresponding to improved reliability and memory retention time, would be desirable. It would also be desirable to eliminate the requirement for a stress test to ascertain reliability of a PMT.
- The present invention is directed to a programmable memory transistor (PMT) that exhibits significantly better performance in terms of charge retention and reliability. The PMT of this invention is able to make use of a single polysilicon layer, and is capable of memory retention times of five orders of magnitude greater than similar single-polysilicon PMT's. The PMT also provides improved testability as a result of a greater measurement sensitivity for defects.
- The PMT of this invention generally comprises an insulated gate field effect transistor (IGFET) and a capacitor structure on a semiconductor substrate. The IGFET comprises source and drain regions in a surface of the substrate, a channel between the source and drain regions, a gate insulator overlying the channel, and a first floating gate on the gate insulator. The capacitor structure comprises a lightly-doped well of a first conductivity type in the surface of the substrate, a heavily-doped first diffusion of the first conductivity type in the lightly-doped well, and a second diffusion of a second conductivity type in the lightly-doped well and spaced apart from the first diffusion so as to define therebetween a surface region of the lightly-doped well. The capacitor structure further comprises a control gate insulator that overlies the surface region of the lightly-doped well, a second floating gate on the control gate insulator, and a conductor in ohmic contact with the lightly-doped well through the first diffusion and in further contact with the lightly-doped well through the second diffusion. The first and second floating gates are electrically connected, preferably as a result of being formed of the same polysilicon layer, to maintain the first and second floating gates at the same potential.
- As a result of the above structure, the second floating gate is capacitively coupled to the lightly-doped well through the control gate insulator so as to define a control gate for the first floating gate. As such, a sufficient voltage can be applied to the lightly-doped well to cause ejection of electrons from the drain region of the insulated gate field effect transistor and trap some of the ejected electrons in the first floating gate. According to the invention, PMT's fabricated with the oppositely-doped diffusions as described above do not experience the initial drop in Vth that occurs with conventional single-polysilicon PMT's when exposed to elevated temperatures, e.g., during a data retention bake. As such, the PMT of this invention is capable of far superior data retention over comparable single-polysilicon PMT's. An additional benefit of the invention is the ability to simplify and/or shorten the aforementioned stress test performed on conventional PMT's to evaluate device reliability on the basis of the initial Vth drop.
- Other objects and advantages of this invention will be better appreciated from the following detailed description.
- FIG. 1 is a schematic cross-sectional view of a programmable memory transistor in accordance with the prior art.
- FIGS. 2 and 3 are schematic cross-sectional and plan views, respectively, of a programmable memory transistor in accordance with the present invention.
- FIGS. 4 through 9 are graphs comparing the voltage retention characteristics of programmable memory transistors configured in accordance with FIGS. 1 and 2.
- FIGS. 2 and 3 schematically represent a single-
polysilicon PMT 10 capable of exhibiting superior memory retention in accordance with the present invention. ThePMT 10 is similar to prior art double-polysilicon (“Poly1/Poly2”) PMT's except that the second polysilicon layer is replaced with a lightly-doped well. ThePMT 10 differs from prior art single-polysilicon PMT's (e.g., FIG. 1) by the use of diffusions of opposite conductivity type within a lightly-doped well that defines the control gate for the PMT, the effect of which is improved memory retention resulting from the elimination of the initial Vth drop observed with prior art single-polysilicon PMT's. - As seen in FIG. 2, the
PMT 10 is fabricated on a silicon (preferably monocrystalline)substrate 12 doped with an N-type impurity, e.g., phosphorus, arsenic or another pentavalent element. A suitable doping level for thesubstrate 12 is on the order of about 5×1015 cm−2. A P-well 14 is formed in a surface region of thesubstrate 12 by doping with boron or another trivalent element at a level of about 5×1016 cm2. Afield oxide 16 divides the P-well 14 into two active regions, one of which is occupied by anNMOS transistor 18, while the other is occupied by acoupling capacitor 38. TheNMOS transistor 18 is formed to conventionally include source and drainregions channel 24 between the source and drainregions gate electrode 26 separated from thechannel 24 by agate oxide 28. The source and drainregions substrate 12, preferably at a level of about 1×1020 cm−2. Source and drainmetal regions third region 23 heavily doped p-type for making ohmic contact with the P-well 14. - The polysilicon floating
gate electrode 26 of theNMOS transistor 18 is formed by a layer of polysilicon that also defines a floatinggate electrode 46 of thecoupling capacitor 38. The floatinggate electrode 46 overlies atunneling oxide 48 above a surface region of a lightly-doped N-type (NHV)diffusion 44. TheNHV diffusion 44 is preferably doped at a level of about 2×1017 cm−2. Two diffusions 42 and 43 are shown as being formed within theNHV diffusion 44, a first of which is acontact diffusion 42 heavily doped n-type, such as on the order of about 1×1020 cm−2. In contrast, the second diffusion is an injectingdiffusion 43 heavily doped p-type, such as on the order of about 1×1020 cm−2. The floatinggate electrode 46 serves as an upper capacitor plate of thecoupling capacitor 38. The channel between the diffusions 42 and 43 in theNHV diffusion 44 serves as the second capacitor plate of thecoupling capacitor 38 and the control gate for theNMOS transistor 18. Acontrol gate metal 50 contacts both theN+ contact diffusion 42 and theP+ injecting diffusion 43 through adielectric layer 52 overlying the surface of thesubstrate 12. Those skilled in the art will appreciate that conventional MOS processing can be used to form the PMT shown in FIG. 2, such that specific processing steps and techniques will not be discussed here in any detail. - According to conventional practice, the
N+ contact diffusion 42 provides ohmic contact with theNHV diffusion 44. As a result of its opposite conductivity type, theP+ injecting diffusion 43 does not provide ohmic contact with theNHV diffusion 44. Instead, and according to the present invention, theP+ injecting diffusion 43 provides what is termed herein a “stitch” contact, and is believed to source holes into a P-type inversion layer at the surface of theNHV diffusion 44 when thePMT 10 is being programmed. The presence of theP+ injecting diffusion 43 has been demonstrated to greatly improve the memory retention of thePMT 10 as compared to a PMT that differs by having a pair of N+ contact diffusions (e.g., FIG. 1). In addition to its performance advantages, all layers used in thePMT 10 are core process layers in NMOS processes, enabling thecoupling capacitor 38 and the NMOS transistor 18 (as will as other MOS devices) to be fabricated simultaneously in thesame substrate 12. - In an investigation leading to the present invention, PMT's in accordance with FIG. 1 (“control”) and FIG. 2 were processed side-by-side on a PMT test array. The PMT's were fabricated on a monocrystalline silicon substrate with a twelve micrometer-thick N-type epitaxy having an impurity concentration of about 5×1015 cm−2. P-wells were formed in surface regions of the substrate by doping with boron at a level of about 5×1016 cm−2 to a depth of about four micrometers. The source and drain regions of the NMOS transistors and the N+ contact diffusions of the coupling capacitors were heavily doped with arsenic to a level of about 1×1020 cm−2 and a depth of about 0.4 micrometers, while the P+ injecting diffusions of the PMT's of this invention and the P-well contact were heavily doped with boron to a level of about 1×1020 cm−2 and a depth of about 0.4 micrometers. After forming the gate oxide and tunneling oxide layers (about 250 Angstroms), the floating gates were patterned from a single layer of polysilicon deposited by low pressure chemical vapor deposition (LPCVD) to a thickness of about 3500 Angstroms.
- All devices were erased with a deep UV bake and then programmed from an initial Vth of about 2V. Programming the PMT's involved applying drain and gate voltages to the NMOS for a few milliseconds or less. With the source region grounded, a positive voltage of less than the NMOS breakdown voltage (BVdss) was applied through a current limiting resistor to the drain region and a positive voltage on the order of about 3 MV/cm applied to the control gate metal of each device, with the result that “hot” electrons were ejected from the drain regions and became stored on the polysilicon floating gates.
- After programming, the control PMT's reached a Vth of about 7.5V, while the PMT's processed in accordance with this invention reached a higher Vth of about 8.5V. The PMT's were then subjected to a standard data retention bake at temperatures of about 160° C., 180° C. or 235° C. As represented by the data plotted in FIGS. 7 through 9, the control PMT'S experienced a rapid initial drop in Vth of between about 1.5 and 2.0V after the first hour of baking. After the initial Vth drop, the control PMT's stabilized and Vth began to drop at a much slower rate. As evidenced by FIGS. 4 through 6, under the same test conditions the PMT's of this invention did not experience an initial drop in Vth, but rather Vth decayed at a slow rate through the entire data retention bake in a similar manner exhibited by the control PMT's after their initial drop in Vth. Given that the programmed Vth was initially higher and that the rate of decay was overall slower, the PMT's of this invention exhibited superior data retention with respect to the control PMT's.
- From the results represented in FIGS. 4 through 9, it was concluded that PMT's configured in accordance with this invention are capable of memory retention times of about five orders of magnitude greater than the control PMT's. An explanation was not evident as to why the PMT's of the invention did not experience an initial drop in Vth during the data retention bake. However, it is believed that the P+ injecting diffusion sourced carriers to the lightly-doped NHV diffusion to create an inversion in the surface region of the NHV diffusion, which is suspected of resulting in a more complete electron injection, i.e., few (if any) electrons trapped inside the gate oxide. The higher Vth of the PMT's processed in accordance with the invention was attributed to the P+ stitch contact allowing a higher voltage on the control gate inversion channel.
- From the investigation, it was further concluded that the PMT of this invention is characterized by improved testability as a result of a greater measurement sensitivity for defects. More particularly, the initial voltage drop exhibited by prior art PMT's necessitated a prolonged stress test to determine at what level their Vth's would stabilize. By eliminating the initial Vth drop, a defective PMT can be quickly identified by its displaying any rapid drop in Vth after programming.
- While the invention has been described in terms of a preferred embodiment, it is apparent that other forms could be adopted by one skilled in the art. For example, doping ranges other than those noted could be employed, the
NHV diffusion 44 need not be in a P-well 14 but instead could be formed in another N-type region or in a P-type substrate, and the entire PMT cell could be formed in a P-type substrate. Accordingly, the scope of the invention is to be limited only by the following claims.
Claims (9)
Priority Applications (3)
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US10/324,346 US6762453B1 (en) | 2002-12-19 | 2002-12-19 | Programmable memory transistor |
EP03078777A EP1432039B1 (en) | 2002-12-19 | 2003-11-28 | Programmable memory transistor |
DE60334276T DE60334276D1 (en) | 2002-12-19 | 2003-11-28 | Programmable memory transistor |
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US10/324,346 US6762453B1 (en) | 2002-12-19 | 2002-12-19 | Programmable memory transistor |
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US20040119113A1 true US20040119113A1 (en) | 2004-06-24 |
US6762453B1 US6762453B1 (en) | 2004-07-13 |
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US20040173825A1 (en) * | 2003-03-07 | 2004-09-09 | Lyu Guy-Ho | Semiconductor devices and methods of forming the same |
US20070007577A1 (en) * | 2005-07-06 | 2007-01-11 | Matrix Semiconductor, Inc. | Integrated circuit embodying a non-volatile memory cell |
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US20080121973A1 (en) * | 2006-07-04 | 2008-05-29 | Richtek Technology Corp. | Fully logic process compatible non-volatile memory cell with a high coupling ratio and process of making the same |
CN105632889A (en) * | 2014-11-04 | 2016-06-01 | 北大方正集团有限公司 | Method of manufacturing capacitor, capacitor and capacitor module |
US20170062449A1 (en) * | 2011-03-15 | 2017-03-02 | Hewlett-Packard Development Company, L.P. | Memory cell having closed curve structure |
US10468425B2 (en) * | 2014-02-04 | 2019-11-05 | Stmicroelectronics S.R.L. | Embedded non-volatile memory with single polysilicon layer memory cells erasable through band to band tunneling induced hot electron and programmable through Fowler-Nordheim tunneling |
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CN105632889A (en) * | 2014-11-04 | 2016-06-01 | 北大方正集团有限公司 | Method of manufacturing capacitor, capacitor and capacitor module |
Also Published As
Publication number | Publication date |
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US6762453B1 (en) | 2004-07-13 |
EP1432039A2 (en) | 2004-06-23 |
DE60334276D1 (en) | 2010-11-04 |
EP1432039A3 (en) | 2008-03-05 |
EP1432039B1 (en) | 2010-09-22 |
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