US20040124462A1 - Multiple conductive plug structure including at least one conductive plug region and at least one between-conductive-plug region for lateral rf mos devices - Google Patents

Multiple conductive plug structure including at least one conductive plug region and at least one between-conductive-plug region for lateral rf mos devices Download PDF

Info

Publication number
US20040124462A1
US20040124462A1 US10/360,365 US36036503A US2004124462A1 US 20040124462 A1 US20040124462 A1 US 20040124462A1 US 36036503 A US36036503 A US 36036503A US 2004124462 A1 US2004124462 A1 US 2004124462A1
Authority
US
United States
Prior art keywords
region
plug
conductive
dopant concentration
semiconductor material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US10/360,365
Other versions
US6762456B1 (en
Inventor
Pablo D'Anna
Alan Yan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qorvo US Inc
Original Assignee
Sirenza Microdevices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/033,839 external-priority patent/US6686627B2/en
Assigned to SIRENZA MICRODEVICES, INC. reassignment SIRENZA MICRODEVICES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YAN, ALAN, D'ANNA, PABLO
Priority to US10/360,365 priority Critical patent/US6762456B1/en
Application filed by Sirenza Microdevices Inc filed Critical Sirenza Microdevices Inc
Assigned to SIRENZA MICRODEVICES, INC. reassignment SIRENZA MICRODEVICES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: XEMOD, INC.
Priority to PCT/US2004/002278 priority patent/WO2004073015A2/en
Publication of US20040124462A1 publication Critical patent/US20040124462A1/en
Publication of US6762456B1 publication Critical patent/US6762456B1/en
Application granted granted Critical
Assigned to RF MICRO DEVICES, INC. reassignment RF MICRO DEVICES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SIRENZA MICRODEVICES
Assigned to BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT reassignment BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Assignors: RF MICRO DEVICES, INC.
Assigned to RF MICRO DEVICES, INC. reassignment RF MICRO DEVICES, INC. CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF THE ASSIGNOR TO SIRENZA MICRODEVICES, INC. PREVIOUSLY RECORDED ON REEL 020927 FRAME 0907. ASSIGNOR(S) HEREBY CONFIRMS THE NAME OF THE ASSIGNEE IS RF MICRO DEVICES, INC.. Assignors: SIRENZA MICRODEVICES, INC.
Assigned to RF MICRO DEVICES, INC. reassignment RF MICRO DEVICES, INC. TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS (RECORDED 3/19/13 AT REEL/FRAME 030045/0831) Assignors: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Assigned to QORVO US, INC. reassignment QORVO US, INC. MERGER (SEE DOCUMENT FOR DETAILS). Assignors: RF MICRO DEVICES, INC.
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743Making of internal connections, substrate contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/4175Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41766Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like

Definitions

  • the present invention is in the field of lateral RF MOS devices. More specifically, the present invention relates to a lateral MOS structure utilized to build an RF MOS device with an improved hot carrier reliability and improved RF performance.
  • An LDMOS device structure with a plug formed on a partially filled trench has another drawback. Indeed, such a structure does not allow one to substantially planarize the LDMOS device structure. This issue is important because a planarized LDMOS structure can be used to increase the degree of freedom in designing an RF LDMOS amplifier device with the required characteristics. For instance, the substantially planarized LDMOS structure can be used to design an RF LDMOS high power amplifier device with an improved RF gain, improved collector efficiency, and a wider usable bandwidth (BW) as compared with an RF LDMOS devices designed by using a conventional non-planarized LDMOS structure.
  • BW wider usable bandwidth
  • the present invention provides a substantially planarized multiple conductive plug LDMOS structure with a multiple enhanced drain drift region.
  • the LDMOS structure of the present invention allows one design an RF LDMOS power amplifier for wireless applications with substantially improved RF performance because of significantly reduced hot carrier vulnerability and improved drain-source breakdown voltage.
  • One aspect of the present invention is directed to a lateral RF MOS transistor with at least one conductive plug structure.
  • the lateral RF MOS transistor with at least one conductive plug structure comprises: (a) a semiconductor material of the first, P conductivity type, or an epi layer, having a first (epi layer) dopant concentration and a top surface; (b) a conductive gate overlying the top surface of the epi layer and insulated from the epi layer by silicon dioxide; ®) a first enhanced drain drift region of the second, N conductivity type, having a second dopant concentration, formed in the epi layer and extended at a first depth level inside the epi layer; (d) a second enhanced drain drift region of N conductivity type, having a third dopant concentration, formed in the epi layer and extended at a second depth level inside the epi layer; (e) a drain region of N conductivity type, having a drain dopant concentration and formed in the epi layer; (f) a body region of P conductivity type, having a body region dopant concentration, including a first end underlying the conductive gate, formed in the
  • the plug region further comprises at least one conductive plug region formed in the epi layer, and at least one between-conductive-plug region of the first, P conductivity type, having a between-conductive-plug dopant concentration formed in the epi layer.
  • the conductive plug region contacts the body contact region of the epi layer, and the between-conductive-plug region contacts the conductive plug region.
  • the plug region further comprises two conductive plug regions formed in the epi layer, and at least one between-conductive-plug region of P conductivity type formed in the epi layer and located between two conductive plug regions.
  • the first conductive plug region contacts the body contact region of the epi layer.
  • both the first conductive plug region and the second conductive plug region connect the body contact region of the epi layer to a highly conductive substrate of the structure.
  • the dopant concentration of the second enhanced drain drift region is higher than the dopant concentration of the first enhanced drain drift region, and the drain region dopant concentration is higher than the dopant concentration of the second enhanced drain drift region.
  • the body region dopant concentration is at least equal to the dopant concentration of the epi layer, and the body contact region dopant concentration is greater than the body region dopant concentration.
  • the first (and/or the second) conductive plug comprises: a metal plug, a silicided plug, a tungsten silicide plug, a titanium silicide plug, a cobalt silicide plug, and/or a platinum silicide plug.
  • FIG. 1A depicts a prior art lateral MOS structure having a “narrow” trench filled with a single conductive plug connecting the source region at the chip surface to the backside.
  • FIG. 1B illustrates a prior art lateral MOS structure having a “narrow” trench filled with a single conductive plug connecting the source region at the chip surface to the substrate.
  • FIG. 2 shows the “narrow” trench of the prior art lateral MOS in more details.
  • FIG. 3 illustrates a lateral RF MOS device of the present invention including a plug region including one conductive plug region connecting the body contact region and the substrate, and one between-conductive-plug region.
  • FIG. 4 shows a lateral RF MOS device of the present invention including a plug region including two conductive plug regions and two between-conductive-plug regions.
  • the present application incorporates in its entirety the U.S. Pat. No. 5,949,104 “Source Connection Structure for Lateral RF MOS devices”.
  • the '104 patent discloses a lateral MOS structure 10 having a single plug 12 connecting the source region 17 at the chip surface 20 to its backside 23 (in one embodiment of '104 patent), or, as depicted in FIG. 1B, to a substrate 28 (in another embodiment of '104 patent).
  • the single lateral MOS plug structure allows one to obtain an increase in the packing density of the RF MOS device active areas per unit chip area, a reduction in the output capacitance of the RF MOS device, and an improvement in usable BW of the RF MOS device employed in amplifier circuits.
  • the lateral MOS structure of '104 patent has some drawbacks related to the size and depth of the trench and the process used to deposit the metal layer to fill it. Indeed, as shown in FIG. 2, if a sputtering process is used to deposit the metal into the trench 31 , the width (W) 35 of the trench 31 is greater than 3 microns and its depth (H) 36 is less than 6 microns, the metal sputtered thickness (h) 32 needs to be equal to the depth (H) to totally fill the trench. The planarization of the structure with such thick metal layer (greater than 6 microns) by subsequent processes becomes very difficult.
  • the trench 31 has a width (W) less than (2-3) microns, for the same depth (H) situation, the shadowing effect of the sputtering process will build a metal ledge 37 at the side surface of the trench that prevents the complete trench filling by creating a hole 39 inside the plug.
  • the current etch process technology can remove only up to 1.00 ⁇ layer of metal from the surface.
  • the single “narrow” trench having the width only up to 2.0 ⁇ can be completely filled with metal.
  • a multiple plug lateral LDMOS structure would allow one to minimize the parasitic source resistance and inductance using the same processing technology as in the case of single plug lateral LDMOS structure, and to design an RF LDMOS power amplifier for wireless applications with substantially improved RF performance.
  • the single plug lateral MOS structure of '104 patent has another drawback—it includes only one enhanced drain drift region 22 (of FIGS. 1A and 1B) which leads to a low drain-source breakdown voltage and high hot carrier drift effects because of the relatively high electric fields next to the gate-drain junction.
  • the U.S. Pat. No. 6,271,552 “Lateral RF MOS device with improved Breakdown voltage” discloses a large power output lateral RF MOS structure having two enhanced drain drift regions.
  • the existence of two enhanced drain drift regions allows one to significantly increase the maximum drain-source voltage breakdown thus reducing the hot-carrier vulnerability of the device built on the '552 LDMOS technology.
  • the '552 patent is incorporated herein in its entirety.
  • FIG. 3 depicts an LDMOS structure of the present invention 40 that includes at least one plug region 42 , that is used to connect the body contact region 47 of the LDMOS device to the substrate 58 , and at least one between-conductive-plug region 41 .
  • the LDMOS structure of the present invention 40 also includes at least two drain drift regions 46 and 48 that allows one to increase the threshold voltage thus significantly reducing hot-carrier vulnerability (as fully explained below). Therefore, the present invention RF LDMOS technology allows one to build an RF LDMOS power amplifier for wireless applications with substantially improved RF performance and significantly reduced hot-carrier vulnerability.
  • the drain extension region concentration is designed to have the lowest doping concentration N in the first drain drift region 46 , closest to the gate 52 , with the doping concentration N + of the remaining portion of the drain extension area (the second drain drift region 48 ) increasing towards the drain region 50 .
  • the source plugs 42 are placed within the device structure, between the channel regions.
  • the RF LDMOS structure 40 of present invention has the capability of optimizing performance over other approaches by the selection of how many plugs and/or drain extension areas to use for the desired application.
  • FIGS. 1A and 1B illustrate a prior art single LDMOS plug structure 10 disclosed in the U.S. Pat. No. 5,949,104.
  • the plug 12 connects the source 17 and the body areas (not marked) to the backside 23 through the original epitaxial layer 26 thickness without diffusion.
  • the connection area 14 could be made small comparable to the prior art diffusion area of the '563 patent, thus increasing the density of devices per inch 2 .
  • the prior art lateral RF MOS plug structure 12 (of FIGS. 1A and 1B) was optimized for high frequency applications, such as the cellular and the PCS regions of the RF spectrum in terms of its transconductance g m and the interelectrode capacitances C gs , C gd , and C ds .
  • the transconductance per unit gm was increased by fabricating the device with the smallest plug size that the technology would allow.
  • the reduction of the interelectrode capacitance (mainly C gd and C ds ) affects gain and efficiency.
  • the gate-drain capacitance C gd and the source-drain capacitance C ds are proportional to the gate and drain region areas (including sidewalls).
  • the reduction in C gd capacitance was obtained by minimizing the channel length L and by minimizing the insertion of the drain extension lateral diffusion under the gate.
  • the reduction in C ds capacitance was obtained by utilizing a high resistivity material under the drain portion of the structure and by separating the drain area from the source.
  • a conductive plug region 12 (of FIGS. 1A and 1B) was formed in the source-body region of the semiconductor material 26 .
  • FIG. 3 this is a detailed cross-sectional view of the lateral RF MOS transistor 40 of the present invention having at least one conductive plug region 42 , at least one between-conductive-plug-region 41 having a first conductivity type and having a first between-conductive-plug dopant concentration, and at least two drain drift regions 46 and 48 .
  • the device structure 40 comprises: a semiconductor material comprising an epitaxial layer 56 of a first conductivity type and having an epitaxial layer dopant concentration and a top surface 59 .
  • the epitaxial layer's conductivity type is of P-type, that is the majority carriers are holes.
  • the dopant concentration of the epitaxial layer is P ⁇ , wherein ( ⁇ ) indicates that the dopant concentration of holes P ⁇ in the epitaxial layer 56 is small comparatively with the hole concentration P in the body region 44 (see discussion below).
  • the typical thickness of the epitaxial layer 56 is (3-10) ⁇ .
  • the between-conductive-plug region 41 is of the first conductivity type P and includes between-conductive-plug dopant concentration P.
  • the semiconductor material 56 is of a second (N) conductivity type, has a dopant concentration N ⁇ and includes a top surface 59 .
  • the between-conductive-plug region 41 is of the second conductivity type N and includes between-conductive-plug dopant concentration N.
  • the majority carriers are electrons.
  • a conductive gate 52 overlies a portion of the top surface 59 of the semiconductor material.
  • the gate 52 is insulated from the semiconductor material by a gate oxide layer 54 .
  • the gate oxide layer 54 has dimensions (200-700) ⁇ .
  • the gate 52 comprises a polysilicon gate.
  • the region 46 forms a first enhanced drain drift region of the RF MOS structure.
  • the region 46 is formed completely within the semiconductor material 56 .
  • the first enhanced drain drift region 46 has N conductivity type if the epitaxial layer 56 has P conductivity type. In an alternative embodiment, the first enhanced drain drift region 46 has P conductivity type if the epitaxial layer has N conductivity type.
  • the first enhanced drain drift region 46 has N conductivity type and has a dopant concentration N 1 .
  • the first enhanced drain region 46 has dimensions (0.1-2.5) ⁇ laterally, and about (0.2-0.5) ⁇ vertically.
  • the region 48 forms a second enhanced drain drift region of the RF MOS structure that contacts the first enhanced drain drift region 46 .
  • the region 48 is formed completely within the semiconductor material 56 .
  • the second enhanced drain drift region 48 has N conductivity type if the epitaxial layer has P conductivity type.
  • the second enhanced drain drift region 48 has P conductivity type if the epitaxial layer has N conductivity type.
  • the second enhanced drain drift region 48 has N conductivity type and has a dopant concentration N 2 that is larger than the dopant concentration N 1 of the first enhanced drain region 46 :
  • the dopant concentration N 2 of the second enhanced drain drift region 48 is 3/2 as much as the dopant concentration N 1 of the first enhanced drain drift region 46 :
  • the structure of the lateral RF MOS device 40 (of FIG. 3) of the present invention including two drain drift regions ( 46 and 48 ) allows one to increase the maximum drain drift current density of the device and the drain-to-source breakdown voltage V breakdown of the structure 40 (of FIG. 3) is also increased.
  • the effective electrical field in the drain drift region is strong enough (about 10 kV/cm) to cause at certain critical concentration of carriers N c the avalanche effect of carrier multiplication.
  • the critical carrier concentration N c is related to the breakdown voltage V breakdown , that is defined as the voltage at which the avalanche effect of carrier multiplication takes place.
  • the second drain drift region 48 has the concentration N 2 that is higher than the concentration of the first drain drift region N 1 This results in the redistribution of the critical electrical fields in the source-drain channel and in an increase of the drain-to-source breakdown voltage V breakdown .
  • the maximum current density in the source-drain channel of the device is also increased because the total concentration:
  • N T N 1 +N 2 (4)
  • the second enhanced drain drift region 48 is extended into the semiconductor material 56 at the same depth level as the first enhanced drain drift region 46 .
  • the second enhanced drain drift region 57 is extended into the semiconductor material 56 deeper than the first drain enhanced drift region 46 .
  • a drain region 50 is also formed in the epitaxial layer 56 .
  • the drain region 50 has the N conductivity type, if the epitaxial layer 56 has P conductivity type.
  • the drain region 50 has the P conductivity type, if the epitaxial layer 56 has N conductivity type. If the drain region 50 is of N conductivity type, the drain region 50 has a dopant concentration N drain that is greater than the dopant concentration N 2 of the second drain drift region 48 :
  • the drain region 50 contacts the second enhanced drain drift region 48 .
  • the typical dimensions of the drain region 50 are (0.5-3.0) ⁇ horizontally, and (0.1-0.3) ⁇ vertically.
  • a body region 44 of the RF MOS structure ( 40 of FIG. 3) is also formed in the epi layer 56 .
  • the body region 44 has P conductivity type if the epitaxial layer 56 has P conductivity type.
  • the body region 44 has N conductivity type if the epitaxial layer 56 has N conductivity type.
  • the body region 44 has a dopant concentration P that is at least equal to the dopant concentration P ⁇ of the epitaxial layer 56 .
  • the typical dimensions of the body region 44 are (0.5-1.5) ⁇ horizontally or vertically.
  • the body region 44 includes a source region 45 being of N conductivity type N (if the epitaxial layer has P conductivity type and vice versa) and having a dopant concentration N ++ .
  • the typical dimensions of the source region 45 are (0.5-5.0) ⁇ horizontally.
  • the body region 44 also includes a body contact region 47 being of P conductivity type (if the epitaxial layer has P conductivity type and vice versa) and having a dopant concentration P ++ that is greater than the dopant concentration P of the body region 44 .
  • the typical dimensions of the body contact region 47 are (0.5-3.0) ⁇ vertically or horizontally.
  • the substrate 58 is a highly conductive one and is P-doped with concentration of carriers (0.005-0.01) ⁇ -cm.
  • the plug region 70 comprises at least two conductive plug regions: a first conductive plug region 62 formed in the epi layer 172 , and a second conductive plug region 66 formed in the epi layer 72 .
  • the first conductive plug region 62 contacts the body contact region 78 .
  • the plug region 70 of FIG. 4 further comprises a first between-conductive-plug region 64 formed in the epi layer 72 .
  • the first between-conductive-plug region is of the first conductivity type P and includes a first between-conductive-plug dopant concentration P 1 .
  • the first between-conductive-plug region 64 contacts the first conductive plug region 62 .
  • the second conductive plug region 66 contacts the first between-conductive-plug region 64 .
  • the plug region 70 of FIG. 4 further comprises a second between-conductive-plug region 68 formed in the epi layer 72 .
  • the second between-conductive-plug region 68 is of the first conductivity type P and has a second between-conductive-plug dopant concentration P 2 .
  • the second between-conductive-plug region contacts the second conductive plug region 66 .
  • the first conductive plug region 62 connects the body contact region 78 of the epi layer 72 to a highly conductive substrate 84 of the structure, and the second conductive plug region 66 connects a top surface 82 of the epi layer 72 to the substrate 84 .
  • the conductive plug ( 42 of FIG. 3, and/or 62 of FIG. 4, and/or 66 of FIG. 4) comprises a metal plug or a silicided plug.
  • the silicided plug comprises a tungsten silicide plug, a titanium silicide plug, a cobalt silicide plug, or a platinum silicide plug.

Abstract

A lateral RF MOS transistor with at least one conductive plug structure comprising: (1) a semiconductor material of a first conductivity type having a first dopant concentration and a top surface; (2) a conductive gate overlying and insulated from the top surface of the semiconductor material; (3) at least two enhanced drain drift regions of the second conductivity type of the RF MOS transistor; the first region laying partially underneath the gate; the second enhanced drain drift region contacting the first enhanced drain drift region, the dopant concentration of the second enhanced drain drift region is higher than the dopant concentration of the first enhanced drain drift region; (4) a drain region of the second conductivity type contacting the second enhanced drain drift region; (5) a body region of said RF MOS transistor of the first conductivity type with the dopant concentration being at least equal to the dopant concentration of the semiconductor epi layer; (6) a source region of the second conductivity type located within the body region; (7) a body contact region of the first conductivity type contacting the body region; and (8) a plug region further comprising at least one conductive plug region, and at least one between-conductive-plug region.

Description

  • This is a divisional patent application for the U.S. patent application Ser. No. 10/033,839, filed on Dec. 26, 2001, and entitled “MULTIPLE CONDUCTIVE PLUG STRUCTURE FOR LATERAL RF MOS DEVICES.”[0001]
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0002]
  • The present invention is in the field of lateral RF MOS devices. More specifically, the present invention relates to a lateral MOS structure utilized to build an RF MOS device with an improved hot carrier reliability and improved RF performance. [0003]
  • 2. Discussion of the Prior Art [0004]
  • An LDMOS technology is rapidly becoming the technology of choice for RF power amplification in wireless communication applications. There has been a continuous effort to further improve the device performance based on RF LDMOS technology, including optimization in layout and reduction in the gate resistance. However, the device performance remains limited by the large parasitic feedback capacitance C[0005] rss because the RF output power decreases drastically with the increased parasitic feedback capacitance Crss, and parasitic source resistance and inductance. Thus, the reduction of the parasitic feedback capacitance Crss and parasitic source resistance and inductance are crucial to an RF LDMOS device performance.
  • Another issue is the hot-carrier effects that degrade the performance of an LDMOS device used as an RF power amplifier. Indeed, in such a device, gate and drain may be biased with a high voltage simultaneously. Therefore, the LDMOS device might be forced to operate at high electric field while carrying high current. However, due to the hot-electron injection into the gate oxide, threshold voltage and transconductance change result in the decrease of drain current-carrying capability. Thus, hot-electron effects cause the device gain to decrease and R[0006] Drain-Source to increase thus resulting in output power degradation.
  • A number of structures have been proposed in the past years regarding improvements to the performance of LDMOS devices used in RF amplification for wireless applications. All these prior art structures had in common the minimization of parasitic source resistance and inductance, the increase of drain-source breakdown voltage, the maximization of drain current, and the reduction of hot electron carrier effects. [0007]
  • For instance, in the paper “RF LDMOS with Extreme Low Parasitic Feedback Capacitance and High Hot-Carrier Immunity” given by Shuming Xu, Pangdow Foo, Jianqing Wen, Yong Liu, Fujiang Lin, and Changhong Ren at the International Electron Devices Meeting in Washington, D.C., Dec. 5-8, 1999, a new RF LDMOS was demonstrated with a cost effective process technology. By combining a step LDD and an inherent thermal oxide spacer, the parasitic feedback capacitance was reduced by 40%, achieving a 35% higher output power. The hot-electron resistance was also improved by 70%, allowing power to be obtained with a higher reliability. [0008]
  • However, this approach entails the control of the lateral oxidation of the polysilicon gate finger which is difficult to achieve. A simpler approach is to optimize the depth and concentration of the enhanced drain structures in order to maximize the drain-source breakdown voltage, and to minimize the hot electron effects. [0009]
  • An LDMOS device structure with a plug formed on a partially filled trench has another drawback. Indeed, such a structure does not allow one to substantially planarize the LDMOS device structure. This issue is important because a planarized LDMOS structure can be used to increase the degree of freedom in designing an RF LDMOS amplifier device with the required characteristics. For instance, the substantially planarized LDMOS structure can be used to design an RF LDMOS high power amplifier device with an improved RF gain, improved collector efficiency, and a wider usable bandwidth (BW) as compared with an RF LDMOS devices designed by using a conventional non-planarized LDMOS structure. [0010]
  • What is needed is a substantially filled multiple conductive plug LDMOS structure with a reduced hot carrier vulnerability that would allow one to design an RF LDMOS device with an improved RF performance. [0011]
  • SUMMARY OF THE INVENTION
  • To address the shortcomings of the available art, the present invention provides a substantially planarized multiple conductive plug LDMOS structure with a multiple enhanced drain drift region. The LDMOS structure of the present invention allows one design an RF LDMOS power amplifier for wireless applications with substantially improved RF performance because of significantly reduced hot carrier vulnerability and improved drain-source breakdown voltage. [0012]
  • One aspect of the present invention is directed to a lateral RF MOS transistor with at least one conductive plug structure. [0013]
  • In one embodiment of the present invention, the lateral RF MOS transistor with at least one conductive plug structure comprises: (a) a semiconductor material of the first, P conductivity type, or an epi layer, having a first (epi layer) dopant concentration and a top surface; (b) a conductive gate overlying the top surface of the epi layer and insulated from the epi layer by silicon dioxide; ®) a first enhanced drain drift region of the second, N conductivity type, having a second dopant concentration, formed in the epi layer and extended at a first depth level inside the epi layer; (d) a second enhanced drain drift region of N conductivity type, having a third dopant concentration, formed in the epi layer and extended at a second depth level inside the epi layer; (e) a drain region of N conductivity type, having a drain dopant concentration and formed in the epi layer; (f) a body region of P conductivity type, having a body region dopant concentration, including a first end underlying the conductive gate, formed in the epi layer; (g) a source region of N conductivity type formed in the epi layer, having a source region dopant concentration, located within the body region; (h) a body contact region of P conductivity type, having a body contact region dopant concentration, contacting the body region; and (I) a plug region. In one embodiment, the drain region contacts the second enhanced drain drift region, and the second enhanced drain drift region contacts the first enhanced drain drift region. [0014]
  • In one embodiment of the present invention, the plug region further comprises at least one conductive plug region formed in the epi layer, and at least one between-conductive-plug region of the first, P conductivity type, having a between-conductive-plug dopant concentration formed in the epi layer. The conductive plug region contacts the body contact region of the epi layer, and the between-conductive-plug region contacts the conductive plug region. [0015]
  • In one embodiment of the present invention, the plug region further comprises two conductive plug regions formed in the epi layer, and at least one between-conductive-plug region of P conductivity type formed in the epi layer and located between two conductive plug regions. The first conductive plug region contacts the body contact region of the epi layer. [0016]
  • In one embodiment, both the first conductive plug region and the second conductive plug region connect the body contact region of the epi layer to a highly conductive substrate of the structure. [0017]
  • In one embodiment of the present invention, the dopant concentration of the second enhanced drain drift region is higher than the dopant concentration of the first enhanced drain drift region, and the drain region dopant concentration is higher than the dopant concentration of the second enhanced drain drift region. In one embodiment of the present invention, the body region dopant concentration is at least equal to the dopant concentration of the epi layer, and the body contact region dopant concentration is greater than the body region dopant concentration. [0018]
  • In one embodiment of the present invention, the first (and/or the second) conductive plug comprises: a metal plug, a silicided plug, a tungsten silicide plug, a titanium silicide plug, a cobalt silicide plug, and/or a platinum silicide plug. [0019]
  • BRIEF DESCRIPTION OF DRAWINGS
  • The aforementioned advantages of the present invention as well as additional advantages thereof will be more clearly understood hereinafter as a result of a detailed description of a preferred embodiment of the invention when taken in conjunction with the following drawings. [0020]
  • FIG. 1A depicts a prior art lateral MOS structure having a “narrow” trench filled with a single conductive plug connecting the source region at the chip surface to the backside. [0021]
  • FIG. 1B illustrates a prior art lateral MOS structure having a “narrow” trench filled with a single conductive plug connecting the source region at the chip surface to the substrate. [0022]
  • FIG. 2 shows the “narrow” trench of the prior art lateral MOS in more details. [0023]
  • FIG. 3 illustrates a lateral RF MOS device of the present invention including a plug region including one conductive plug region connecting the body contact region and the substrate, and one between-conductive-plug region. [0024]
  • FIG. 4 shows a lateral RF MOS device of the present invention including a plug region including two conductive plug regions and two between-conductive-plug regions. [0025]
  • DETAILED DESCRIPTION OF THE PREFERRED AND ALTERNATIVE EMBODIMENTS
  • Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention. [0026]
  • The present application incorporates in its entirety the U.S. Pat. No. 5,949,104 “Source Connection Structure for Lateral RF MOS devices”. As depicted in FIG. 1A, the '104 patent discloses a [0027] lateral MOS structure 10 having a single plug 12 connecting the source region 17 at the chip surface 20 to its backside 23 (in one embodiment of '104 patent), or, as depicted in FIG. 1B, to a substrate 28 (in another embodiment of '104 patent). As was stated in '104 patent, the single lateral MOS plug structure allows one to obtain an increase in the packing density of the RF MOS device active areas per unit chip area, a reduction in the output capacitance of the RF MOS device, and an improvement in usable BW of the RF MOS device employed in amplifier circuits.
  • However, the lateral MOS structure of '104 patent has some drawbacks related to the size and depth of the trench and the process used to deposit the metal layer to fill it. Indeed, as shown in FIG. 2, if a sputtering process is used to deposit the metal into the [0028] trench 31, the width (W) 35 of the trench 31 is greater than 3 microns and its depth (H) 36 is less than 6 microns, the metal sputtered thickness (h) 32 needs to be equal to the depth (H) to totally fill the trench. The planarization of the structure with such thick metal layer (greater than 6 microns) by subsequent processes becomes very difficult. If the trench 31 has a width (W) less than (2-3) microns, for the same depth (H) situation, the shadowing effect of the sputtering process will build a metal ledge 37 at the side surface of the trench that prevents the complete trench filling by creating a hole 39 inside the plug.
  • If, on the other hand, the chemical vapor deposit (CVD) and etch back process is performed in order to fill the [0029] trench cavity 34 with metal, one can fill completely only a “narrow” trench 34 with a width W, wherein there is a certain relationship between the width of the “narrow” trench cavity W 35 that can be completely filled with metal, and the depth H of the trench 36. In the present technology, this relationship between the width of the “narrow” trench W and the size H of the trench can be expressed as follows:
  • W<H/2.  (1)
  • However, the current etch process technology can remove only up to 1.00μ layer of metal from the surface. Thus, the single “narrow” trench having the width only up to 2.0μ can be completely filled with metal. [0030]
  • But, there is a long felt need in the field of power RF amplifiers for wireless applications for a lateral LDMOS structure with a trench completely filled with metal, so that the device built on such a structure would have a substantially high source conductivity to demonstrate superior RF performance. For instance, one would need a lateral RF MOS transistor with a “wide” trench, preferably up to 6μ, completely filled with metal, in order to have enough conductivity to substantially decrease the large parasitic source resistance and inductance. The “wide” trench structure can be modeled by using a multiple plug structure approach. Thus, a multiple plug lateral LDMOS structure would allow one to minimize the parasitic source resistance and inductance using the same processing technology as in the case of single plug lateral LDMOS structure, and to design an RF LDMOS power amplifier for wireless applications with substantially improved RF performance. [0031]
  • The single plug lateral MOS structure of '104 patent has another drawback—it includes only one enhanced drain drift region [0032] 22 (of FIGS. 1A and 1B) which leads to a low drain-source breakdown voltage and high hot carrier drift effects because of the relatively high electric fields next to the gate-drain junction.
  • To support a high drain-source breakdown voltage (greater than 70 Volt), the U.S. Pat. No. 6,271,552 “Lateral RF MOS device with improved Breakdown voltage” discloses a large power output lateral RF MOS structure having two enhanced drain drift regions. The existence of two enhanced drain drift regions allows one to significantly increase the maximum drain-source voltage breakdown thus reducing the hot-carrier vulnerability of the device built on the '552 LDMOS technology. The '552 patent is incorporated herein in its entirety. [0033]
  • FIG. 3 depicts an LDMOS structure of the [0034] present invention 40 that includes at least one plug region 42, that is used to connect the body contact region 47 of the LDMOS device to the substrate 58, and at least one between-conductive-plug region 41. The LDMOS structure of the present invention 40 also includes at least two drain drift regions 46 and 48 that allows one to increase the threshold voltage thus significantly reducing hot-carrier vulnerability (as fully explained below). Therefore, the present invention RF LDMOS technology allows one to build an RF LDMOS power amplifier for wireless applications with substantially improved RF performance and significantly reduced hot-carrier vulnerability. Additionally, the drain extension region concentration is designed to have the lowest doping concentration N in the first drain drift region 46, closest to the gate 52, with the doping concentration N+ of the remaining portion of the drain extension area (the second drain drift region 48) increasing towards the drain region 50.
  • The source plugs [0035] 42 are placed within the device structure, between the channel regions. The RF LDMOS structure 40 of present invention has the capability of optimizing performance over other approaches by the selection of how many plugs and/or drain extension areas to use for the desired application.
  • In one prior art structure, disclosed in U.S. Pat. No. 5,155,563 (issued to Motorola), a connection of the source and body regions in the MOS structure to the backside is made through the diffusion of a dopant introduced from the topside of the chip and a metal finger short. However, this diffusion not only moves the topside dopant down and sideways but also moves the substrate dopant up thus reducing the distance between the highly doped substrate interface and the drain area of the device. This diffusion movement of the interface produces an increase of the minimum source-drain capacitance C[0036] ds that can be obtained under a high voltage bias VDS.
  • In another prior art structure disclosed in the U.S. Pat. No. 5,841,166 (issued to Spectrian), the connection between the source and body regions in the MOS structure to backside was made by a sinker contact aligned with the source region and spaced from the width of the channel region. [0037]
  • On the other hand, FIGS. 1A and 1B illustrate a prior art single [0038] LDMOS plug structure 10 disclosed in the U.S. Pat. No. 5,949,104. The plug 12 connects the source 17 and the body areas (not marked) to the backside 23 through the original epitaxial layer 26 thickness without diffusion. The connection area 14 could be made small comparable to the prior art diffusion area of the '563 patent, thus increasing the density of devices per inch2.
  • The usage of a [0039] metal plug 12 of FIG. 1A (and FIG. 1B) takes care of two important prior art technological problems: (1) how to make a good ohmic contact in a small area (2) without long thermal processing cycles. As it is well known in the art, the long thermal processing cycles increase the doping movements thus increasing the source-drain capacitance Cds.
  • The prior art lateral RF MOS plug structure [0040] 12 (of FIGS. 1A and 1B) was optimized for high frequency applications, such as the cellular and the PCS regions of the RF spectrum in terms of its transconductance gm and the interelectrode capacitances Cgs, Cgd, and Cds. The transconductance per unit gm was increased by fabricating the device with the smallest plug size that the technology would allow. The reduction of the interelectrode capacitance (mainly Cgd and Cds) affects gain and efficiency. The gate-drain capacitance Cgd and the source-drain capacitance Cds are proportional to the gate and drain region areas (including sidewalls). Therefore, the reduction in Cgd capacitance was obtained by minimizing the channel length L and by minimizing the insertion of the drain extension lateral diffusion under the gate. The reduction in Cds capacitance was obtained by utilizing a high resistivity material under the drain portion of the structure and by separating the drain area from the source. A conductive plug region 12 (of FIGS. 1A and 1B) was formed in the source-body region of the semiconductor material 26.
  • Referring still to FIG. 3, this is a detailed cross-sectional view of the lateral [0041] RF MOS transistor 40 of the present invention having at least one conductive plug region 42, at least one between-conductive-plug-region 41 having a first conductivity type and having a first between-conductive-plug dopant concentration, and at least two drain drift regions 46 and 48. The device structure 40 comprises: a semiconductor material comprising an epitaxial layer 56 of a first conductivity type and having an epitaxial layer dopant concentration and a top surface 59.
  • In one embodiment, the epitaxial layer's conductivity type is of P-type, that is the majority carriers are holes. The dopant concentration of the epitaxial layer is P[0042] , wherein (−) indicates that the dopant concentration of holes P in the epitaxial layer 56 is small comparatively with the hole concentration P in the body region 44 (see discussion below). The typical thickness of the epitaxial layer 56 is (3-10)μ. In this embodiment, the between-conductive-plug region 41 is of the first conductivity type P and includes between-conductive-plug dopant concentration P.
  • In another embodiment of the present invention, the [0043] semiconductor material 56 is of a second (N) conductivity type, has a dopant concentration N and includes a top surface 59. In this embodiment, the between-conductive-plug region 41 is of the second conductivity type N and includes between-conductive-plug dopant concentration N. In this embodiment, the majority carriers are electrons.
  • A [0044] conductive gate 52 overlies a portion of the top surface 59 of the semiconductor material. The gate 52 is insulated from the semiconductor material by a gate oxide layer 54. The gate oxide layer 54 has dimensions (200-700) Å. In one embodiment, the gate 52 comprises a polysilicon gate.
  • Referring still to FIG. 3, the [0045] region 46 forms a first enhanced drain drift region of the RF MOS structure. The region 46 is formed completely within the semiconductor material 56. In one embodiment, the first enhanced drain drift region 46 has N conductivity type if the epitaxial layer 56 has P conductivity type. In an alternative embodiment, the first enhanced drain drift region 46 has P conductivity type if the epitaxial layer has N conductivity type.
  • In one embodiment, the first enhanced [0046] drain drift region 46 has N conductivity type and has a dopant concentration N1. The first enhanced drain region 46 has dimensions (0.1-2.5)μ laterally, and about (0.2-0.5)μ vertically.
  • In one embodiment, the [0047] region 48 forms a second enhanced drain drift region of the RF MOS structure that contacts the first enhanced drain drift region 46. The region 48 is formed completely within the semiconductor material 56. In one embodiment, the second enhanced drain drift region 48 has N conductivity type if the epitaxial layer has P conductivity type. In another embodiment, the second enhanced drain drift region 48 has P conductivity type if the epitaxial layer has N conductivity type.
  • In one embodiment, the second enhanced [0048] drain drift region 48 has N conductivity type and has a dopant concentration N2 that is larger than the dopant concentration N1 of the first enhanced drain region 46:
  • N1<N2.  (2)
  • In one embodiment, the dopant concentration N[0049] 2 of the second enhanced drain drift region 48 is 3/2 as much as the dopant concentration N1 of the first enhanced drain drift region 46:
  • N 2=3/2N 1  (3)
  • The structure of the lateral RF MOS device [0050] 40 (of FIG. 3) of the present invention including two drain drift regions (46 and 48) allows one to increase the maximum drain drift current density of the device and the drain-to-source breakdown voltage Vbreakdown of the structure 40 (of FIG. 3) is also increased. Indeed, the effective electrical field in the drain drift region is strong enough (about 10 kV/cm) to cause at certain critical concentration of carriers Nc the avalanche effect of carrier multiplication. Thus, the critical carrier concentration Nc is related to the breakdown voltage Vbreakdown, that is defined as the voltage at which the avalanche effect of carrier multiplication takes place.
  • According to (eq. 2), the second [0051] drain drift region 48 has the concentration N2 that is higher than the concentration of the first drain drift region N1 This results in the redistribution of the critical electrical fields in the source-drain channel and in an increase of the drain-to-source breakdown voltage Vbreakdown. The maximum current density in the source-drain channel of the device is also increased because the total concentration:
  • N T =N 1 +N 2  (4)
  • in both drain enhancement regions reduces the resistance of the drain region. [0052]
  • In one embodiment, as shown in FIG. 3, the second enhanced [0053] drain drift region 48 is extended into the semiconductor material 56 at the same depth level as the first enhanced drain drift region 46. In another embodiment, the second enhanced drain drift region 57 is extended into the semiconductor material 56 deeper than the first drain enhanced drift region 46.
  • Referring still to the [0054] structure 40 of FIG. 3 of the RF MOS device of the present invention, a drain region 50 is also formed in the epitaxial layer 56. In one embodiment, the drain region 50 has the N conductivity type, if the epitaxial layer 56 has P conductivity type. In another embodiment, the drain region 50 has the P conductivity type, if the epitaxial layer 56 has N conductivity type. If the drain region 50 is of N conductivity type, the drain region 50 has a dopant concentration Ndrain that is greater than the dopant concentration N2 of the second drain drift region 48:
  • Ndrain>N2>N1.  (5)
  • The [0055] drain region 50 contacts the second enhanced drain drift region 48. The typical dimensions of the drain region 50 are (0.5-3.0)μ horizontally, and (0.1-0.3)μ vertically.
  • Referring still to FIG. 3, a [0056] body region 44 of the RF MOS structure (40 of FIG. 3) is also formed in the epi layer 56. In one embodiment, the body region 44 has P conductivity type if the epitaxial layer 56 has P conductivity type. In another embodiment, the body region 44 has N conductivity type if the epitaxial layer 56 has N conductivity type.
  • In the P conductivity type embodiment, the [0057] body region 44 has a dopant concentration P that is at least equal to the dopant concentration P of the epitaxial layer 56. The typical dimensions of the body region 44 are (0.5-1.5)μ horizontally or vertically.
  • The [0058] body region 44 includes a source region 45 being of N conductivity type N (if the epitaxial layer has P conductivity type and vice versa) and having a dopant concentration N++. The typical dimensions of the source region 45 are (0.5-5.0)μ horizontally.
  • Referring still to FIG. 3, the [0059] body region 44 also includes a body contact region 47 being of P conductivity type (if the epitaxial layer has P conductivity type and vice versa) and having a dopant concentration P++ that is greater than the dopant concentration P of the body region 44. The typical dimensions of the body contact region 47 are (0.5-3.0)μ vertically or horizontally.
  • In one embodiment of the present invention, the [0060] substrate 58 is a highly conductive one and is P-doped with concentration of carriers (0.005-0.01) Ω-cm.
  • In one embodiment of the present invention, as depicted in FIG. 4, the [0061] plug region 70 comprises at least two conductive plug regions: a first conductive plug region 62 formed in the epi layer 172, and a second conductive plug region 66 formed in the epi layer 72. The first conductive plug region 62 contacts the body contact region 78.
  • In one embodiment, the [0062] plug region 70 of FIG. 4 further comprises a first between-conductive-plug region 64 formed in the epi layer 72. In one embodiment, the first between-conductive-plug region is of the first conductivity type P and includes a first between-conductive-plug dopant concentration P1. The first between-conductive-plug region 64 contacts the first conductive plug region 62. The second conductive plug region 66 contacts the first between-conductive-plug region 64.
  • In one embodiment, the [0063] plug region 70 of FIG. 4 further comprises a second between-conductive-plug region 68 formed in the epi layer 72. In one embodiment, the second between-conductive-plug region 68 is of the first conductivity type P and has a second between-conductive-plug dopant concentration P2. The second between-conductive-plug region contacts the second conductive plug region 66.
  • Referring still to FIG. 4, in one embodiment of the present invention, the first [0064] conductive plug region 62 connects the body contact region 78 of the epi layer 72 to a highly conductive substrate 84 of the structure, and the second conductive plug region 66 connects a top surface 82 of the epi layer 72 to the substrate 84.
  • The conductive plug ([0065] 42 of FIG. 3, and/or 62 of FIG. 4, and/or 66 of FIG. 4) comprises a metal plug or a silicided plug. The silicided plug comprises a tungsten silicide plug, a titanium silicide plug, a cobalt silicide plug, or a platinum silicide plug.
  • The foregoing description of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents. [0066]

Claims (21)

What is claimed is:
1. A lateral RF MOS transistor with at least one conductive plug structure comprising:
a semiconductor material of a first conductivity type, said semiconductor material having a first dopant concentration and a top surface;
a conductive gate overlying a portion of and insulated from the top surface of said semiconductor material;
a first region formed completely within said semiconductor material to a first depth level, said first region being of a second conductivity type, and having a second dopant concentration to form a first enhanced drain drift region of said RF MOS transistor;
a second region formed in said semiconductor material to a second depth level, said second region being of said second conductivity type and having a third dopant concentration to form a second enhanced drain drift region of said RF MOS transistor, said second region contacting said first region, said third dopant concentration being higher than said second dopant concentration;
a third region formed in said semiconductor material, said third region being of said second conductivity type and having a fourth dopant concentration greater than said third dopant concentration to form a drain region of said RF MOS transistor, said third region contacting said second region;
a fourth region formed in said semiconductor material, said fourth region being of said first conductivity type and having a fifth dopant concentration to form a body region of said RF MOS transistor, said fifth dopant concentration being at least equal to said first dopant concentration, said fourth region having a first end underlying said conductive gate, any remaining portion of said semiconductor material underlying said gate being of said first conductivity type;
a fifth region formed in said semiconductor material, said fifth region being of said second conductivity type and having a sixth dopant concentration to form a source region of said RF MOS transistor, said fifth region being located within said fourth region;
a sixth region formed in said semiconductor material, said sixth region being of said first conductivity type and having a seventh dopant concentration to form a body contact region of said RF MOS transistor, said seventh dopant concentration being greater than said fifth dopant concentration of said fourth region, said sixth region contacting said fourth region; and
a plug region further comprising:
at least one conductive plug region; and
at least one between-conductive-plug region.
2. The lateral RF MOS transistor of claim 1, wherein said plug region further comprises:
a conductive plug region formed in said semiconductor material; said conductive plug region contacting said body contact region of said semiconductor material; and
a between-conductive-plug region formed in said semiconductor material, said between-conductive-plug region being of said first conductivity type and having a between-conductive-plug dopant concentration; said between-conductive-plug region contacting said conductive plug region.
3. The lateral RF MOS transistor of claim 1, wherein said plug region further comprises:
a first conductive plug region formed in said semiconductor material; said first conductive plug region contacting said body contact region of said semiconductor material;
a between-conductive-plug region formed in said semiconductor material, said between-conductive-plug region being of said first conductivity type and having a between-conductive-plug dopant concentration; said between-conductive-plug region contacting said first conductive plug region; and
a second conductive plug region formed in said semiconductor material;
said second conductive plug region contacting said between-conductive-plug region.
4. The lateral RF MOS transistor of claim 1, wherein said plug region further comprises:
a first conductive plug region formed in said semiconductor material; said first conductive plug region contacting said body contact region of said semiconductor material;
a first between-conductive-plug region formed in said semiconductor material, said first between-conductive-plug region being of said first conductivity type and having a first between-conductive-plug dopant concentration; said first between-conductive-plug region contacting said first conductive plug region;
a second conductive plug region formed in said semiconductor material; said second conductive plug region contacting said first between-conductive-plug region; and
a second between-conductive-plug region formed in said semiconductor material, said second between-conductive-plug region being of said first conductivity type and having a second between-conductive-plug dopant concentration; said second between-conductive-plug region contacting said second conductive plug region.
5. The lateral RF MOS transistor of claim 1, wherein each said conductive plug region connects a lateral surface of said body contact region of said semiconductor material to a highly conductive substrate of said transistor.
6. The lateral RF MOS transistor of claim 3;
wherein said first conductive plug region connects said body contact region of said semiconductor material to a highly conductive substrate of said transistor;
and wherein said second conductive plug region connects a top surface of said semiconductor material to said highly conductive substrate of said transistor.
7. The lateral RF MOS transistor of claim 1, wherein said first conductivity type is a P type.
8. The lateral RF MOS transistor of claim 3, wherein said first conductive plug comprises a metal plug.
9. The lateral RF MOS transistor of claim 3, wherein said second conductive plug comprises a metal plug.
10. The lateral RF MOS transistor of claim 3, wherein said first conductive plug comprises a silicided plug.
11. The lateral RF MOS transistor of claim 3, wherein said second conductive plug comprises a silicided plug.
12. The lateral RF MOS transistor of claim 10, wherein said first conductive plug comprises a tungsten silicide plug.
13. The lateral RF MOS transistor of claim 11, wherein said second conductive plug comprises a tungsten silicide plug.
14. The lateral RF MOS transistor of claim 10, wherein said first conductive plug comprises a titanium silicide plug.
15. The lateral RF MOS transistor of claim 11, wherein said second conductive plug comprises a titanium silicide plug.
16. The lateral RF MOS transistor of claim 10, wherein said first conductive plug comprises a cobalt silicide plug.
17. The lateral RF MOS transistor of claim 11, wherein said second conductive plug comprises a cobalt silicide plug.
18. The lateral RF MOS transistor of claim 10, wherein said first conductive plug comprises a platinum silicide plug.
19. The lateral RF MOS transistor of claim 11, wherein said second conductive plug comprises a platinum silicide plug.
20. The lateral RF MOS transistor of claim 1, said first enhanced drain drift region having said second dopant concentration extended at said first depth level, said second enhanced drain drift region having said third dopant concentration extended at said second depth level, and wherein said second drain drift region is extended into said semiconductor material deeper than said first drain drift region.
21. A semiconductor device, comprising:
a semiconductor substrate of a first conductivity type and having a substrate dopant concentration;
a semiconductor material overlying said substrate, said semiconductor material having a first conductivity type, said semiconductor material having a first dopant concentration and a top surface;
a plurality of transistor disposed upon said top surface of said semiconductor material, at least some of said plurality of transistors having a lateral DMOS structure, including:
a conductive gate overlying a portion of and insulated from the top surface of said semiconductor material;
a first region formed completely within said semiconductor material to a first depth level, said first region being of a second conductivity type, and having a second dopant concentration to form a first enhanced drain drift region of said RF MOS transistor;
a second region formed in said semiconductor material to a second depth level, said second region being of said second conductivity type and having a third dopant concentration to form a second enhanced drain drift region of said RF MOS transistor, said second region contacting said first region, said third dopant concentration being higher than said second dopant concentration;
a third region formed in said semiconductor material, said third region being of said second conductivity type and having a fourth dopant concentration greater than said third dopant concentration to form a drain region of said RF MOS transistor, said third region contacting said second region;
a fourth region formed in said semiconductor material, said fourth region being of said first conductivity type and having a fifth dopant concentration to form a body region of said RF MOS transistor, said fifth dopant concentration being at least equal to said first dopant concentration, said fourth region having a first end underlying said conductive gate, any remaining portion of said semiconductor material underlying said gate being of said first conductivity type;
a fifth region formed in said semiconductor material, said fifth region being of said second conductivity type and having a sixth dopant concentration to form a source region of said RF MOS transistor, said fifth region being located within said fourth region;
a sixth region formed in said semiconductor material, said sixth region being of said first conductivity type and having a seventh dopant concentration to form a body contact region of said RF MOS transistor, said seventh dopant concentration being greater than said fifth dopant concentration of said fourth region, said sixth region contacting said fourth region; and
a plug region further comprising:
at least one conductive plug region; and
at least one between-conductive-plug region.
US10/360,365 2001-12-26 2003-02-08 Multiple conductive plug structure including at least one conductive plug region and at least one between-conductive-plug region for lateral RF MOS devices Expired - Lifetime US6762456B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/360,365 US6762456B1 (en) 2001-12-26 2003-02-08 Multiple conductive plug structure including at least one conductive plug region and at least one between-conductive-plug region for lateral RF MOS devices
PCT/US2004/002278 WO2004073015A2 (en) 2003-02-08 2004-01-27 Multiple conductive plug structure including at least one conductive plug region and at least one between-conductive-plug region for lateral rf mos devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/033,839 US6686627B2 (en) 2001-12-26 2001-12-26 Multiple conductive plug structure for lateral RF MOS devices
US10/360,365 US6762456B1 (en) 2001-12-26 2003-02-08 Multiple conductive plug structure including at least one conductive plug region and at least one between-conductive-plug region for lateral RF MOS devices

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/033,839 Division US6686627B2 (en) 2001-12-26 2001-12-26 Multiple conductive plug structure for lateral RF MOS devices

Publications (2)

Publication Number Publication Date
US20040124462A1 true US20040124462A1 (en) 2004-07-01
US6762456B1 US6762456B1 (en) 2004-07-13

Family

ID=32867942

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/360,365 Expired - Lifetime US6762456B1 (en) 2001-12-26 2003-02-08 Multiple conductive plug structure including at least one conductive plug region and at least one between-conductive-plug region for lateral RF MOS devices

Country Status (2)

Country Link
US (1) US6762456B1 (en)
WO (1) WO2004073015A2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050073003A1 (en) * 2003-10-03 2005-04-07 Olof Tornblad LDMOS transistor
US20100117237A1 (en) * 2008-11-12 2010-05-13 Coolbaugh Douglas D Silicided Trench Contact to Buried Conductive Layer
EP2879185A1 (en) * 2013-11-29 2015-06-03 Nxp B.V. Radio frequency power transistor with a resistor region between a source and a drain contact region and method for manufacturing such a transistor
KR20160101586A (en) * 2015-02-17 2016-08-25 에스케이하이닉스 주식회사 Power integrated device, and electronic device and electronic system having the power integrated device

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7176129B2 (en) * 2001-11-20 2007-02-13 The Regents Of The University Of California Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications
JP2004214575A (en) * 2003-01-09 2004-07-29 Matsushita Electric Ind Co Ltd Semiconductor device
JP5114824B2 (en) * 2004-10-15 2013-01-09 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
TW200741892A (en) 2006-03-02 2007-11-01 Volterra Semiconductor Corp A lateral double-diffused MOSFET (LDMOS) transistor and a method of fabricating
US7999318B2 (en) * 2007-12-28 2011-08-16 Volterra Semiconductor Corporation Heavily doped region in double-diffused source MOSFET (LDMOS) transistor and a method of fabricating the same
CN104282762B (en) * 2014-09-15 2017-06-06 上海华虹宏力半导体制造有限公司 Radio frequency horizontal dual pervasion field effect transistor and preparation method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841166A (en) * 1996-09-10 1998-11-24 Spectrian, Inc. Lateral DMOS transistor for RF/microwave applications

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4890146A (en) * 1987-12-16 1989-12-26 Siliconix Incorporated High voltage level shift semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5841166A (en) * 1996-09-10 1998-11-24 Spectrian, Inc. Lateral DMOS transistor for RF/microwave applications

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050073003A1 (en) * 2003-10-03 2005-04-07 Olof Tornblad LDMOS transistor
US6989567B2 (en) * 2003-10-03 2006-01-24 Infineon Technologies North America Corp. LDMOS transistor
US20100117237A1 (en) * 2008-11-12 2010-05-13 Coolbaugh Douglas D Silicided Trench Contact to Buried Conductive Layer
US8338265B2 (en) 2008-11-12 2012-12-25 International Business Machines Corporation Silicided trench contact to buried conductive layer
US8872281B2 (en) 2008-11-12 2014-10-28 International Business Machines Corporation Silicided trench contact to buried conductive layer
EP2879185A1 (en) * 2013-11-29 2015-06-03 Nxp B.V. Radio frequency power transistor with a resistor region between a source and a drain contact region and method for manufacturing such a transistor
KR20160101586A (en) * 2015-02-17 2016-08-25 에스케이하이닉스 주식회사 Power integrated device, and electronic device and electronic system having the power integrated device
KR102286012B1 (en) * 2015-02-17 2021-08-05 에스케이하이닉스 시스템아이씨 주식회사 Power integrated device, and electronic device and electronic system having the power integrated device

Also Published As

Publication number Publication date
WO2004073015A2 (en) 2004-08-26
US6762456B1 (en) 2004-07-13
WO2004073015A3 (en) 2004-12-02

Similar Documents

Publication Publication Date Title
US6686627B2 (en) Multiple conductive plug structure for lateral RF MOS devices
US6831332B2 (en) Microwave field effect transistor structure
US7335565B2 (en) Metal-oxide-semiconductor device having improved performance and reliability
US6710416B1 (en) Split-gate metal-oxide-semiconductor device
US5949104A (en) Source connection structure for lateral RF MOS devices
US6222233B1 (en) Lateral RF MOS device with improved drain structure
US6444527B1 (en) Method of operation of punch-through field effect transistor
US7138690B2 (en) Shielding structure for use in a metal-oxide-semiconductor device
US6271552B1 (en) Lateral RF MOS device with improved breakdown voltage
US7126193B2 (en) Metal-oxide-semiconductor device with enhanced source electrode
US7061057B2 (en) Laterally diffused MOS transistor having N+ source contact to N-doped substrate
US10510869B2 (en) Devices and methods for a power transistor having a Schottky or Schottky-like contact
US6297533B1 (en) LDMOS structure with via grounded source
US6762456B1 (en) Multiple conductive plug structure including at least one conductive plug region and at least one between-conductive-plug region for lateral RF MOS devices
US6838731B1 (en) Microwave transistor structure having step drain region
EP1058949B1 (en) Rf mos transistor
KR20010102278A (en) Silicon carbide lmosfet with gate break-down protection
US20050139858A1 (en) Lateral double-diffused MOS transistor device
JP2004063922A (en) Semiconductor device
US20020027242A1 (en) Arrangemenet in a power MOS transistor
US20050110083A1 (en) Metal-oxide-semiconductor device having improved gate arrangement

Legal Events

Date Code Title Description
AS Assignment

Owner name: SIRENZA MICRODEVICES, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:D'ANNA, PABLO;YAN, ALAN;REEL/FRAME:014238/0490;SIGNING DATES FROM 20011221 TO 20011222

AS Assignment

Owner name: SIRENZA MICRODEVICES, INC., COLORADO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:XEMOD, INC.;REEL/FRAME:014452/0338

Effective date: 20030808

STCF Information on status: patent grant

Free format text: PATENTED CASE

REMI Maintenance fee reminder mailed
AS Assignment

Owner name: RF MICRO DEVICES, INC., NORTH CAROLINA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SIRENZA MICRODEVICES;REEL/FRAME:020927/0907

Effective date: 20080505

FPAY Fee payment

Year of fee payment: 4

SULP Surcharge for late payment
FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT, TE

Free format text: NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS;ASSIGNOR:RF MICRO DEVICES, INC.;REEL/FRAME:030045/0831

Effective date: 20130319

AS Assignment

Owner name: RF MICRO DEVICES, INC., NORTH CAROLINA

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF THE ASSIGNOR TO SIRENZA MICRODEVICES, INC. PREVIOUSLY RECORDED ON REEL 020927 FRAME 0907. ASSIGNOR(S) HEREBY CONFIRMS THE NAME OF THE ASSIGNEE IS RF MICRO DEVICES, INC.;ASSIGNOR:SIRENZA MICRODEVICES, INC.;REEL/FRAME:030194/0769

Effective date: 20080505

AS Assignment

Owner name: RF MICRO DEVICES, INC., NORTH CAROLINA

Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS (RECORDED 3/19/13 AT REEL/FRAME 030045/0831);ASSIGNOR:BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT;REEL/FRAME:035334/0363

Effective date: 20150326

REMI Maintenance fee reminder mailed
FPAY Fee payment

Year of fee payment: 12

SULP Surcharge for late payment

Year of fee payment: 11

AS Assignment

Owner name: QORVO US, INC., NORTH CAROLINA

Free format text: MERGER;ASSIGNOR:RF MICRO DEVICES, INC.;REEL/FRAME:039196/0941

Effective date: 20160330