US20040173941A1 - Exposed die molding apparatus - Google Patents
Exposed die molding apparatus Download PDFInfo
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- US20040173941A1 US20040173941A1 US10/797,287 US79728704A US2004173941A1 US 20040173941 A1 US20040173941 A1 US 20040173941A1 US 79728704 A US79728704 A US 79728704A US 2004173941 A1 US2004173941 A1 US 2004173941A1
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- Prior art keywords
- circuit package
- molding
- support plate
- cavity plate
- set forth
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present invention relates generally to microelectronic packaging and, more particularly, to a method and apparatus for applying a protective ring about the perimeter of an exposed die face.
- Packaging of electrical circuits is a key element in the technological development of any device containing electrical components.
- Several technologies have been developed to provide a means of mounting these electrical components on a surface such as a printed circuit board (PCB).
- PCB printed circuit board
- Fine pitch surface mount (FPT), pin grid array (PGA), and ball grid array (BGA) are examples of leading surface mount technologies.
- BGA technology offers several advantages over FPT and PGA.
- advantages of BGA are: reduced co-planarity problems, since there are no leads; reduced placement problems; reduced paste printing problems; reduced handling damage; smaller size; better electrical and thermal performance; better package yield; better board assembly yield; higher interconnect density; multi-layer interconnect options; higher IO's for a given footprint; easier extension to multi-chip modules; and faster design-to-production cycle time.
- a BGA semiconductor package generally includes a semiconductor chip mounted on the upper surface of a substrate.
- the semiconductor chip may be electrically coupled to the substrate by bonding wires.
- the substrate contains conductive routing which allows the signals to pass from the semiconductor chip on the top side of the substrate, through the substrate, and to pads on the underside of the substrate.
- a plurality of solder balls are deposited and electrically coupled to the pads on the underside of the substrate to be used as input/output terminals for electrically connecting the substrate to a PCB or other external device.
- the semiconductor chip is often encapsulated in a molding compound.
- vacuum based systems are implemented to inject a molding compound which completely encompasses the chip.
- the overall height of the circuit package will be increased.
- the current system for encapsulating the semiconductor chip implements vacuum ports to seat the film which is used to separate the molding compound from the packaging system after encapsulation is complete. These vacuum ports may become contaminated with the molding compound which is used to encase the semiconductor chip.
- the present invention may address one or more of the problems set forth above.
- the circuit package 10 typically includes a semiconductor chip 20 , such as a memory die.
- the semiconductor chip 20 is mounted on a substrate 30 and electrically coupled to the substrate 30 by bond wires (not shown).
- a molding compound 40 is generally used to encapsulate the semiconductor chip 20 .
- the purpose of the molding compound 40 is to protect the semiconductor chip 20 and the bond wires (not shown) from external elements.
- Solder balls 50 may be deposited on the back side of the substrate 30 so that the circuit package 10 may be electrically coupled to a printed circuit board (PCB) in order to incorporate the circuit package 10 into a system.
- PCB printed circuit board
- FIG. 2 illustrates a method and apparatus for encapsulating a circuit package 10 .
- a bottom support plate 60 is generally made of a rigid substance such as metal.
- the bottom support plate 60 contains a molding cavity 70 which is used to encapsulate the circuit package 10 .
- the bottom support plate 60 also contains vacuum holes 80 which are used to seat a film 90 in the molding cavity 70 .
- the film 90 separates the molding compound from the molding equipment once the semiconductor chip 20 has been encapsulated.
- the circuit package 10 is placed on the support plate 60 so that the edges of the substrate 30 are in contact with the film 90 , and so that the semiconductor chip 20 occupies the molding cavity 70 .
- the semiconductor chip 20 is not in contact with the bottom support plate 60 or the film 90 , but rather is suspended in the molding cavity 70 to be injected with a molding compound.
- a top support plate 100 is generally used to secure the circuit package 10 during the injection process.
- a molding compound such as a resin, is injected into the molding cavity 70 . Once the molding compound solidifies, the circuit package 10 is removed from the molding equipment.
- This method of “die side down” encapsulation described above presents several problems.
- this method of encapsulation adds additional undesirable thickness to the circuit package 10 .
- the overall height increase of the circuit package is generally 100-300 microns.
- FIGS. 3-9 illustrate an exposed die molding apparatus and a method for producing an exposed die molded circuit package.
- FIGS. 3-5 illustrate the manner in which the molding process generally operates. Specifically, FIG. 3 illustrates a partial cross-section of the circuit package 10 mounted in the molding apparatus 25 , in accordance with the present invention.
- the film 95 is brought in contact with the bottom support plate 65 .
- the cavity plate 110 is seated on top of the film 95 .
- the cavity plate 110 contains a molding cavity 75 .
- the depth of the molding cavity 75 is approximately equal to the thickness of the semiconductor chip 20 .
- the semiconductor chip 20 is brought in contact with the film 95 since the walls of the molding cavity 75 are only about as high as the semiconductor chip 20 .
- the cavity plate 110 is constructed such that the molding cavity 75 may receive the semiconductor chip 20 while the substrate 30 is disposed upon the top surface of the cavity plate 110 .
- the raised portion of the bottom support plate 65 is brought in contact with the top surface of the semiconductor chip 20 , with only the film 95 separating the two plates.
- the molding cavity 75 is formed by the molding cavity sidewall 120 which is part of the cavity plate 110 , and the edge of the semiconductor chip 20 , shown as reference number 130 .
- the floor of the molding cavity 75 is formed when the cavity plate 110 is disposed on the film 95 .
- the substrate 30 provides the final containment surface to form the molding cavity 75 .
- the top support plate 100 is disposed upon the cavity plate 110 and the substrate 30 to secure the circuit package 10 during the molding compound injection process.
- FIG. 3 also illustrates a substrate slot 140 .
- the substrate slot 140 is actually a slot which has been cut in the substrate to allow the bond wires from the semiconductor chip 20 to be electrically coupled to the substrate 30 .
- the semiconductor chip 20 is electrically coupled to the substrate 30 by bond wires 150 .
- Exemplary bond wires 150 are illustrated. Because one of the purposes of the molding compound is to protect the electrical connections such as bond wires 150 , the molding compound is advantageously injected about the connections.
- the cavity plate 110 is constructed such that the molding compound will flow through the substrate slot 140 to encapsulate the bond wires 150 .
- the top support plate 105 contains a molding pocket 160 .
- FIG. 4 illustrates the apparatus disclosed in FIG. 3 after the molding compound 170 has been injected into the system.
- the hatch lines in FIG. 4 illustrate where the molding compound 170 has been injected. It is significant to note that the molding compound is not injected onto the top surface of the semiconductor chip 20 . Thus, there is no additional height added to the circuit package 10 .
- the disclosed apparatus 25 does not require a vacuum system to seat the film 95 against the bottom support plate 65 . Because the top surface of the semiconductor chip 20 is disposed directly upon the film 95 with no space left in the molding cavity 75 to allow the top side of the semiconductor chip 20 to be encapsulated, the film 95 will automatically be pressed flat once the cavity plate 110 is disposed upon the bottom support plate 65 . Thus, the vacuum system which was used in the conventional encapsulating machines is no longer utilized to assist in seating the film 95 flush with the bottom support plate 65 to form the top surface of the molding cavity 75 .
- FIG. 5 illustrates the circuit package 10 after the molding compound 170 has solidified, and the circuit package 10 has been ejected.
- the apparatus 25 used to encapsulate the circuit package 10 will be explained in greater detail in FIGS. 6A and 6B.
- the purpose of FIG. 5 is simply to illustrate the completed stage of the encapsulation process.
- FIG. 5 thus contains the same elements as FIGS. 3 and 4.
- the circuit package 10 may be ejected from the encapsulation system.
- the cavity plate 110 is separated from bottom support plate 65 by any suitable means, such as a cavity plate push rod 180 , for example.
- the cavity plate push rod 180 is a rod which may be contained within the bottom support plate 65 during the encapsulation process.
- the cavity plate push rod 180 is extended thereby elevating the cavity plate 110 from its prior position (as shown in FIGS. 3 and 4).
- the film 95 returns to its feed position as will be shown in FIG. 6B (since the cavity plate 110 is no longer forcing the film 95 downwardly into contact with the bottom support plate 65 ).
- the bottom support plate 65 may also contain rail ejection pins 190 which are used to eject an encapsulated circuit package 10 from the cavity plate 110 after the molding injection process is complete.
- FIG. 6A illustrates a top plan view
- FIG. 6B illustrates a side view of a molding apparatus 25
- the apparatus 25 is shown in its ejected position.
- the film 95 is positioned proximate to the bottom support plate 65 .
- the film is held in place during processing by a feed roller 200 and a take up roller 210 .
- the cavity plate push rods 180 and the rail ejection pins 190 are contained within the bottom support plate 65 .
- the cavity plate 110 is thus sitting on top of the film 95 which in turn forces the film 95 downwardly and against the bottom support plate 65 .
- the substrate 30 which is coupled to the semiconductor chip 20 is disposed on the cavity plate 110 .
- the substrate 30 contains a plurality of semiconductor chips 20 . After injection of the molding compound 170 (not shown) and removal from the injection apparatus 25 , the substrate 30 will be cut to provide individual circuit packages 10 .
- the molding compound is injected through a molding compound injection slot 220 .
- the cavity plate 10 is elevated by the cavity plate push rod 180 .
- the substrate 30 is then removed by pushing it out of the cavity plate 110 by means of the rail ejection pins 190 .
- the apparatus 25 will look like the side view shown in FIG. 6B and the partial cross-sectional view shown in FIG. 5.
- top support plate 105 is not illustrated in the present figure. However, it should be understood that the top support plate 105 is also positioned on top of the cavity plate 110 during the injection processing.
- the film 95 may be omitted.
- One of the other purposes of the film 95 may be to account for height differences in circuit packages 10 .
- the film 95 may be comprised of a resilient material which ensures contact despite height variations in substrate packages 10 .
- the bottom cavity plate 65 is comprised of a resilient material, such as composite material, rather than a solid material, such as metal, the film 95 may not be necessary.
- FIG. 7 illustrates a top plan view of the circuit package 10 .
- the molding compound 170 completely surrounds the semiconductor chip 20 .
- the molding compound 170 does not extend to the edge of the substrate 30 .
- the molding compound 170 could be extended to the edge of the substrate 30 or with a different cavity plate fixture the molding compound 170 could extend beyond the edges of the substrate 30 , in such a way so as to contain the substrate 30 completely within the molding compound 170 .
- FIG. 8 illustrates a partial cross-sectional view of the circuit package 10 after the injection process. It can be seen that the molding compound 170 does not extend above the height of the semiconductor chip 20 . Because the semiconductor chip 20 is left with its face exposed, there is no additional height added to the circuit package 10 by the injection processing. Solder balls 50 may be attached to the substrate 30 to couple the circuit package 10 to another substrate or PCB for use in a system. However, it should also be appreciated that other means, such as pins, may be used to electrically couple the circuit package 10 to another substrate or PCB.
- FIG. 9 illustrates a top plan view of the back side of the circuit package 10 .
- solder pads 230 may be disposed upon the back side of the substrate 30 to receive solder balls 50 (not shown) for electrical coupling to a substrate or PCB for use in a system.
- the substrate 30 contains a slot 140 through which the semiconductor chip 20 (not shown) is coupled to the substrate 30 through the use of bond wires (not shown).
- bond wires not shown
Abstract
A method and apparatus for applying a protective ring about the perimeter of an exposed die face. Specifically, a semiconductor chip is coupled to the upper surface of a substrate. The edges of the semiconductor chip are protected by a molding compound which is disposed about the perimeter of the chip and on all or a portion of the substrate. The molding system which is used to apply the protective ring comprises three molding plates and does not require a vacuum-based system to hold the package stationary during the encapsulation process. By not applying a molding compound on the top surface of the semiconductor chip, no height is added to the package.
Description
- The present application is a divisional of U.S. application Ser. No. 09/516,080, filed on Mar. 1, 2000.
- 1. Field of the Invention
- The present invention relates generally to microelectronic packaging and, more particularly, to a method and apparatus for applying a protective ring about the perimeter of an exposed die face.
- 2. Description of the Related Art
- This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
- Packaging of electrical circuits is a key element in the technological development of any device containing electrical components. Several technologies have been developed to provide a means of mounting these electrical components on a surface such as a printed circuit board (PCB). Fine pitch surface mount (FPT), pin grid array (PGA), and ball grid array (BGA) are examples of leading surface mount technologies.
- BGA technology offers several advantages over FPT and PGA. Among the most often cited advantages of BGA are: reduced co-planarity problems, since there are no leads; reduced placement problems; reduced paste printing problems; reduced handling damage; smaller size; better electrical and thermal performance; better package yield; better board assembly yield; higher interconnect density; multi-layer interconnect options; higher IO's for a given footprint; easier extension to multi-chip modules; and faster design-to-production cycle time.
- A BGA semiconductor package generally includes a semiconductor chip mounted on the upper surface of a substrate. The semiconductor chip may be electrically coupled to the substrate by bonding wires. The substrate contains conductive routing which allows the signals to pass from the semiconductor chip on the top side of the substrate, through the substrate, and to pads on the underside of the substrate. A plurality of solder balls are deposited and electrically coupled to the pads on the underside of the substrate to be used as input/output terminals for electrically connecting the substrate to a PCB or other external device.
- To protect the semiconductor chip and bonding wires from external elements such as moisture, dust, or impact, the semiconductor chip is often encapsulated in a molding compound. To encapsulate the semiconductor chip, vacuum based systems are implemented to inject a molding compound which completely encompasses the chip. Disadvantageously, by encasing the entire semiconductor chip in a molding compound, the overall height of the circuit package will be increased. Further, the current system for encapsulating the semiconductor chip implements vacuum ports to seat the film which is used to separate the molding compound from the packaging system after encapsulation is complete. These vacuum ports may become contaminated with the molding compound which is used to encase the semiconductor chip.
- The present invention may address one or more of the problems set forth above.
- One or more specific embodiments of the present invention will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.
- Turning now to the drawings, and referring initially to FIG. 1, a partial cross-sectional view depicting an exemplary encapsulated circuit package generally designated by
reference numeral 10 is illustrated. Thecircuit package 10 typically includes asemiconductor chip 20, such as a memory die. Thesemiconductor chip 20 is mounted on asubstrate 30 and electrically coupled to thesubstrate 30 by bond wires (not shown). Amolding compound 40 is generally used to encapsulate thesemiconductor chip 20. The purpose of themolding compound 40 is to protect thesemiconductor chip 20 and the bond wires (not shown) from external elements.Solder balls 50 may be deposited on the back side of thesubstrate 30 so that thecircuit package 10 may be electrically coupled to a printed circuit board (PCB) in order to incorporate thecircuit package 10 into a system. - FIG. 2 illustrates a method and apparatus for encapsulating a
circuit package 10. Abottom support plate 60 is generally made of a rigid substance such as metal. Thebottom support plate 60 contains amolding cavity 70 which is used to encapsulate thecircuit package 10. Thebottom support plate 60 also containsvacuum holes 80 which are used to seat afilm 90 in themolding cavity 70. Thefilm 90 separates the molding compound from the molding equipment once thesemiconductor chip 20 has been encapsulated. - To encapsulate the
semiconductor chip 20, thecircuit package 10 is placed on thesupport plate 60 so that the edges of thesubstrate 30 are in contact with thefilm 90, and so that thesemiconductor chip 20 occupies themolding cavity 70. Thesemiconductor chip 20 is not in contact with thebottom support plate 60 or thefilm 90, but rather is suspended in themolding cavity 70 to be injected with a molding compound. Atop support plate 100 is generally used to secure thecircuit package 10 during the injection process. During the encapsulation process, a molding compound, such as a resin, is injected into themolding cavity 70. Once the molding compound solidifies, thecircuit package 10 is removed from the molding equipment. - This method of “die side down” encapsulation described above presents several problems. First, many such molding machines do not use a vacuum to seat the
film 90 during this type of molding procedure. Thus, such equipment must be modified to facilitate this type of encapsulation. Second, the vacuum assist which is used to seat thefilm 90 in themolding cavity 70 often creates wrinkles in thefilm 90, which are subsequently transferred into the molding compound and, finally, to the encapsulatedcircuit package 10. Third, this method of encapsulation adds additional undesirable thickness to thecircuit package 10. The overall height increase of the circuit package is generally 100-300 microns. - To address these shortcomings, FIGS. 3-9 illustrate an exposed die molding apparatus and a method for producing an exposed die molded circuit package. FIGS. 3-5 illustrate the manner in which the molding process generally operates. Specifically, FIG. 3 illustrates a partial cross-section of the
circuit package 10 mounted in themolding apparatus 25, in accordance with the present invention. Thefilm 95 is brought in contact with thebottom support plate 65. Thecavity plate 110 is seated on top of thefilm 95. Thecavity plate 110 contains amolding cavity 75. Here, the depth of themolding cavity 75 is approximately equal to the thickness of thesemiconductor chip 20. As thecircuit package 10 is mounted die side down within thecavity plate 110, thesemiconductor chip 20 is brought in contact with thefilm 95 since the walls of themolding cavity 75 are only about as high as thesemiconductor chip 20. Thecavity plate 110 is constructed such that themolding cavity 75 may receive thesemiconductor chip 20 while thesubstrate 30 is disposed upon the top surface of thecavity plate 110. As thecavity plate 110 is disposed upon thefilm 95 the raised portion of thebottom support plate 65 is brought in contact with the top surface of thesemiconductor chip 20, with only thefilm 95 separating the two plates. Thus, themolding cavity 75 is formed by themolding cavity sidewall 120 which is part of thecavity plate 110, and the edge of thesemiconductor chip 20, shown asreference number 130. The floor of themolding cavity 75 is formed when thecavity plate 110 is disposed on thefilm 95. Thesubstrate 30 provides the final containment surface to form themolding cavity 75. Thetop support plate 100 is disposed upon thecavity plate 110 and thesubstrate 30 to secure thecircuit package 10 during the molding compound injection process. - FIG. 3 also illustrates a
substrate slot 140. Thesubstrate slot 140 is actually a slot which has been cut in the substrate to allow the bond wires from thesemiconductor chip 20 to be electrically coupled to thesubstrate 30. In one embodiment, thesemiconductor chip 20 is electrically coupled to thesubstrate 30 bybond wires 150.Exemplary bond wires 150 are illustrated. Because one of the purposes of the molding compound is to protect the electrical connections such asbond wires 150, the molding compound is advantageously injected about the connections. Thus, thecavity plate 110 is constructed such that the molding compound will flow through thesubstrate slot 140 to encapsulate thebond wires 150. To encapsulate thebond wires 150 completely, thetop support plate 105 contains amolding pocket 160. - FIG. 4 illustrates the apparatus disclosed in FIG. 3 after the
molding compound 170 has been injected into the system. The hatch lines in FIG. 4 illustrate where themolding compound 170 has been injected. It is significant to note that the molding compound is not injected onto the top surface of thesemiconductor chip 20. Thus, there is no additional height added to thecircuit package 10. - Significantly, the disclosed
apparatus 25 does not require a vacuum system to seat thefilm 95 against thebottom support plate 65. Because the top surface of thesemiconductor chip 20 is disposed directly upon thefilm 95 with no space left in themolding cavity 75 to allow the top side of thesemiconductor chip 20 to be encapsulated, thefilm 95 will automatically be pressed flat once thecavity plate 110 is disposed upon thebottom support plate 65. Thus, the vacuum system which was used in the conventional encapsulating machines is no longer utilized to assist in seating thefilm 95 flush with thebottom support plate 65 to form the top surface of themolding cavity 75. - FIG. 5 illustrates the
circuit package 10 after themolding compound 170 has solidified, and thecircuit package 10 has been ejected. Theapparatus 25 used to encapsulate thecircuit package 10 will be explained in greater detail in FIGS. 6A and 6B. The purpose of FIG. 5 is simply to illustrate the completed stage of the encapsulation process. FIG. 5 thus contains the same elements as FIGS. 3 and 4. Once themolding compound 170 solidifies, thecircuit package 10 may be ejected from the encapsulation system. Thecavity plate 110 is separated frombottom support plate 65 by any suitable means, such as a cavityplate push rod 180, for example. The cavityplate push rod 180 is a rod which may be contained within thebottom support plate 65 during the encapsulation process. Once the process is complete and themolding compound 170 solidifies, the cavityplate push rod 180 is extended thereby elevating thecavity plate 110 from its prior position (as shown in FIGS. 3 and 4). As thecavity plate 110 is elevated by the cavityplate push rod 180, thefilm 95 returns to its feed position as will be shown in FIG. 6B (since thecavity plate 110 is no longer forcing thefilm 95 downwardly into contact with the bottom support plate 65). Thebottom support plate 65 may also contain rail ejection pins 190 which are used to eject an encapsulatedcircuit package 10 from thecavity plate 110 after the molding injection process is complete. - Turning now to FIGS. 6A and 6B, the molding process and
apparatus 25 can be better explained. FIG. 6A illustrates a top plan view, and FIG. 6B illustrates a side view of amolding apparatus 25. Referring first to the side view of FIG. 6B, theapparatus 25 is shown in its ejected position. As can be seen, thefilm 95 is positioned proximate to thebottom support plate 65. The film is held in place during processing by afeed roller 200 and a take uproller 210. During the injection processing, the cavityplate push rods 180 and the rail ejection pins 190 are contained within thebottom support plate 65. Thecavity plate 110 is thus sitting on top of thefilm 95 which in turn forces thefilm 95 downwardly and against thebottom support plate 65. Thesubstrate 30 which is coupled to thesemiconductor chip 20 is disposed on thecavity plate 110. At this point in the processing, thesubstrate 30 contains a plurality ofsemiconductor chips 20. After injection of the molding compound 170 (not shown) and removal from theinjection apparatus 25, thesubstrate 30 will be cut to provide individual circuit packages 10. - When the
apparatus 25 is in its injection position (as shown in FIGS. 3 and 4), the molding compound is injected through a moldingcompound injection slot 220. Once the molding compound has solidified, thecavity plate 10 is elevated by the cavityplate push rod 180. Thesubstrate 30 is then removed by pushing it out of thecavity plate 110 by means of the rail ejection pins 190. Thus, once the injection process is complete and before thesubstrate 30 is removed from theapparatus 25, theapparatus 25 will look like the side view shown in FIG. 6B and the partial cross-sectional view shown in FIG. 5. As should be evident from these figures, there is no need for a vacuum apparatus to be contained within thebottom support plate 65 to seat thefilm 95 during the injection processing since thecavity plate 10 will force thefilm 95 flat againstbottom support plate 65. For simplicity, thetop support plate 105 is not illustrated in the present figure. However, it should be understood that thetop support plate 105 is also positioned on top of thecavity plate 110 during the injection processing. - In an alternate embodiment, the
film 95 may be omitted. One of the other purposes of thefilm 95 may be to account for height differences in circuit packages 10. To ensure that allsemiconductor chips 20 are seated flush against thebottom support plate 65, thefilm 95 may be comprised of a resilient material which ensures contact despite height variations in substrate packages 10. However, if thebottom cavity plate 65 is comprised of a resilient material, such as composite material, rather than a solid material, such as metal, thefilm 95 may not be necessary. - FIGS. 7, 8 and9 illustrate the separated
circuit package 10 once the injection processing is complete. FIG. 7 illustrates a top plan view of thecircuit package 10. As can be seen, themolding compound 170 completely surrounds thesemiconductor chip 20. In one embodiment, themolding compound 170 does not extend to the edge of thesubstrate 30. However, it should be appreciated that themolding compound 170 could be extended to the edge of thesubstrate 30 or with a different cavity plate fixture themolding compound 170 could extend beyond the edges of thesubstrate 30, in such a way so as to contain thesubstrate 30 completely within themolding compound 170. - FIG. 8 illustrates a partial cross-sectional view of the
circuit package 10 after the injection process. It can be seen that themolding compound 170 does not extend above the height of thesemiconductor chip 20. Because thesemiconductor chip 20 is left with its face exposed, there is no additional height added to thecircuit package 10 by the injection processing.Solder balls 50 may be attached to thesubstrate 30 to couple thecircuit package 10 to another substrate or PCB for use in a system. However, it should also be appreciated that other means, such as pins, may be used to electrically couple thecircuit package 10 to another substrate or PCB. - FIG. 9 illustrates a top plan view of the back side of the
circuit package 10. Again, in one particular embodiment of the present invention,solder pads 230 may be disposed upon the back side of thesubstrate 30 to receive solder balls 50 (not shown) for electrical coupling to a substrate or PCB for use in a system. Also, in this particular embodiment, thesubstrate 30 contains aslot 140 through which the semiconductor chip 20 (not shown) is coupled to thesubstrate 30 through the use of bond wires (not shown). Thus, in this embodiment it may also be desirable to injectmolding compound 170 through theslot 140 to encase the bond wires to protect them from external contacts. It should be appreciated that if thesemiconductor chip 20 is electrically coupled to thesubstrate 30 by some other means, theslot 140 in thesubstrate 30 may not be present and thus nomolding compound 170 will be used in the region shown in FIG. 9. - While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.
Claims (20)
1. A method of molding a circuit package comprising the acts of:
(a) disposing the circuit package on a cavity plate, the circuit package comprising a semiconductor device coupled to a substrate;
(b) disposing the cavity plate on a first support plate;
(c) disposing a second support plate on the cavity plate;
(d) injecting a molding compound into the cavity plate;
(e) separating the second support plate from the cavity plate;
(f) separating the cavity plate from the first support plate; and
(g) separating the circuit package from the cavity plate.
2. The method of molding a circuit package, as set forth in claim 27, wherein act (a) comprises the act of disposing the circuit package on the cavity plate die-side down.
3. The method of molding a circuit package, as set forth in claim 27, wherein act (b) comprises the act of disposing the cavity plate on the first support plate by mechanically moving the cavity plate onto the first support plate.
4. The method of molding a circuit package, as set forth in claim 27, wherein the cavity plate is configured to accept a protruding portion of the circuit package.
5. The method of molding a circuit package, as set forth in claim 30, wherein act (b) comprises the act of disposing the protruding portion of the circuit package upon the first support plate as the cavity plate is disposed upon the first support plate.
6. The method of molding a circuit package, as set forth in claim 27, wherein act (c) comprises the act of disposing the second support plate on the cavity plate by mechanically moving the second support plate onto the cavity plate.
7. The method of molding a circuit package, as set forth in claim 27, wherein act (d) comprises the act of injecting a molding compound into an aperture to create a peripheral ring around the semiconductor device.
8. The method of molding a circuit package, as set forth in claim 33, wherein the molding compound is an insulating material.
9. The method of molding a circuit package, as set forth in claim 33, wherein the molding compound is injected in liquid form.
10. The method of molding a circuit package, as set forth in claim 35, wherein the molding compound is allowed to harden after the injection process.
11. The method of molding a circuit package, as set forth in claim 27, wherein act (f) comprises the act of elevating the cavity support plate with respect to the first support plate by a plurality of cavity plate push rods, the cavity plate push rods controlled to extend from the first support plate.
12. The method of molding a circuit package, as set forth in claim 27, wherein act (g) comprises the act of elevating the circuit package with respect to the cavity support plate by a plurality of rail ejection pins, the rail ejection pins controlled to extend from the first support plate.
13. The method of molding a circuit package, as set forth in claim 27, wherein a film is disposed between the cavity plate and the first support plate.
14. The method of molding a circuit package, as set forth in claim 39, wherein the film is comprised of a resilient material.
15. The method of molding a circuit package, as set forth in claim 27, wherein a film is disposed between the semiconductor device and the first support plate.
16. The method of molding a circuit package, as set forth in claim 41, wherein the film is comprised of a resilient material.
17. The method of molding a circuit package, as set forth in claim 27, wherein the acts are performed on a plurality of circuit packages at once.
18. The method of molding a circuit package, as set forth in claim 43, further comprising the act of singulating the plurality of circuit packages.
19. The method of molding a circuit package, as set forth in claim 27, wherein the acts are performed in the recited order.
20. A circuit package comprising:
a substrate;
a semiconductor chip having a top surface, a bottom surface, and a periphery, the bottom surface being coupled to the substrate;
a peripheral ring of molding compound deposited on the substrate and about the periphery of the semiconductor chip, leaving the top surface of the semiconductor chip uncovered by:
(a) disposing the circuit package on a cavity plate, the circuit package comprising a semiconductor device coupled to a substrate;
(b) disposing the cavity plate on a first support plate;
(c) disposing a second support plate on the cavity plate;
(d) injecting a molding compound into the cavity plate;
(e) separating the second support plate from the cavity plate;
(f) separating the cavity plate from the first support plate; and
(g) separating the circuit package from the cavity plate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/797,287 US20040173941A1 (en) | 2000-03-01 | 2004-03-10 | Exposed die molding apparatus |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/516,080 US6747345B1 (en) | 2000-03-01 | 2000-03-01 | Exposed die molding apparatus |
US10/797,287 US20040173941A1 (en) | 2000-03-01 | 2004-03-10 | Exposed die molding apparatus |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US09/516,080 Division US6747345B1 (en) | 2000-03-01 | 2000-03-01 | Exposed die molding apparatus |
Publications (1)
Publication Number | Publication Date |
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US20040173941A1 true US20040173941A1 (en) | 2004-09-09 |
Family
ID=32326790
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/516,080 Expired - Fee Related US6747345B1 (en) | 2000-03-01 | 2000-03-01 | Exposed die molding apparatus |
US10/797,287 Abandoned US20040173941A1 (en) | 2000-03-01 | 2004-03-10 | Exposed die molding apparatus |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US09/516,080 Expired - Fee Related US6747345B1 (en) | 2000-03-01 | 2000-03-01 | Exposed die molding apparatus |
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US (2) | US6747345B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090321988A1 (en) * | 2008-02-15 | 2009-12-31 | Chipmos Technologies Inc. | Chip packaging process |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8105063B1 (en) * | 2010-08-26 | 2012-01-31 | National Semiconductor Corporation | Three piece mold cavity design for packaging integrated circuits |
CN102856217B (en) | 2011-06-30 | 2018-05-22 | 恩智浦美国有限公司 | For the apparatus and method of molding semiconductor device |
US9934419B2 (en) * | 2016-02-23 | 2018-04-03 | Shenzhen GOODIX Technology Co., Ltd. | Package structure, electronic device and method for manufacturing package structure |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4374080A (en) * | 1981-01-13 | 1983-02-15 | Indy Electronics, Inc. | Method and apparatus for encapsulation casting |
US4980019A (en) * | 1988-09-13 | 1990-12-25 | Intel Corporation | Etch-back process for failure analysis of integrated circuits |
US5391346A (en) * | 1991-11-20 | 1995-02-21 | Rohm Co., Ltd. | Method for making molded photointerrupters |
US5405255A (en) * | 1992-11-24 | 1995-04-11 | Neu Dynamics Corp. | Encapsulaton molding equipment |
US5654877A (en) * | 1991-08-15 | 1997-08-05 | Staktek Corporation | Lead-on-chip integrated circuit apparatus |
US5656549A (en) * | 1996-08-19 | 1997-08-12 | Motorola, Inc. | Method of packaging a semiconductor device |
US5779958A (en) * | 1993-12-22 | 1998-07-14 | Matsushita Electric Industrial Co., Ltd. | Method for packaging electronic device |
US6019588A (en) * | 1995-02-09 | 2000-02-01 | Fico B.V. | Moulding apparatus with compensation element |
US6048483A (en) * | 1996-07-23 | 2000-04-11 | Apic Yamada Corporation | Resin sealing method for chip-size packages |
US6081997A (en) * | 1997-08-14 | 2000-07-04 | Lsi Logic Corporation | System and method for packaging an integrated circuit using encapsulant injection |
US6604281B2 (en) * | 2001-07-11 | 2003-08-12 | Power Mate Technology Co., Ltd. | Circuit board packaging process for preventing electromagnetic interference |
US6676885B2 (en) * | 2000-02-10 | 2004-01-13 | Nec Electronics Corporation | Plural semiconductor devices bonded onto one face of a single circuit board for subsequent batch resin encapsulation of the plural semiconductor devices in a single cavity formed by molding dies |
-
2000
- 2000-03-01 US US09/516,080 patent/US6747345B1/en not_active Expired - Fee Related
-
2004
- 2004-03-10 US US10/797,287 patent/US20040173941A1/en not_active Abandoned
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4374080A (en) * | 1981-01-13 | 1983-02-15 | Indy Electronics, Inc. | Method and apparatus for encapsulation casting |
US4980019A (en) * | 1988-09-13 | 1990-12-25 | Intel Corporation | Etch-back process for failure analysis of integrated circuits |
US5654877A (en) * | 1991-08-15 | 1997-08-05 | Staktek Corporation | Lead-on-chip integrated circuit apparatus |
US5391346A (en) * | 1991-11-20 | 1995-02-21 | Rohm Co., Ltd. | Method for making molded photointerrupters |
US5405255A (en) * | 1992-11-24 | 1995-04-11 | Neu Dynamics Corp. | Encapsulaton molding equipment |
US5779958A (en) * | 1993-12-22 | 1998-07-14 | Matsushita Electric Industrial Co., Ltd. | Method for packaging electronic device |
US6019588A (en) * | 1995-02-09 | 2000-02-01 | Fico B.V. | Moulding apparatus with compensation element |
US6048483A (en) * | 1996-07-23 | 2000-04-11 | Apic Yamada Corporation | Resin sealing method for chip-size packages |
US5656549A (en) * | 1996-08-19 | 1997-08-12 | Motorola, Inc. | Method of packaging a semiconductor device |
US6081997A (en) * | 1997-08-14 | 2000-07-04 | Lsi Logic Corporation | System and method for packaging an integrated circuit using encapsulant injection |
US6676885B2 (en) * | 2000-02-10 | 2004-01-13 | Nec Electronics Corporation | Plural semiconductor devices bonded onto one face of a single circuit board for subsequent batch resin encapsulation of the plural semiconductor devices in a single cavity formed by molding dies |
US6604281B2 (en) * | 2001-07-11 | 2003-08-12 | Power Mate Technology Co., Ltd. | Circuit board packaging process for preventing electromagnetic interference |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090321988A1 (en) * | 2008-02-15 | 2009-12-31 | Chipmos Technologies Inc. | Chip packaging process |
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US6747345B1 (en) | 2004-06-08 |
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Owner name: MICRON TECHNOLOGY, INC., IDAHO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BOLKEN, TODD O.;REEL/FRAME:015092/0871 Effective date: 20000228 |
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