US20040198007A1 - Semiconductor device having a metal silicide layer and method for manufacturing the same - Google Patents
Semiconductor device having a metal silicide layer and method for manufacturing the same Download PDFInfo
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- US20040198007A1 US20040198007A1 US10/823,544 US82354404A US2004198007A1 US 20040198007 A1 US20040198007 A1 US 20040198007A1 US 82354404 A US82354404 A US 82354404A US 2004198007 A1 US2004198007 A1 US 2004198007A1
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
- H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The present invention provides a semiconductor device having a metal silicide layer and a method for forming the metal silicide layer, the semiconductor device having a metal silicide-semiconductor contact structure, wherein the semiconductor device includes a substrate, an insulation layer with an opening, in which a metal silicide layer is formed using a native metal silicide with a first phase and a second phase, upon which a conductive layer is formed. The second phase has a first stoichiometrical composition ratio different from a second stoichiometrical composition ratio of the first phase. A reaction between the metal silicide layer of the first phase and the silicon results in the metal silicide layer of the second phase having high phase stability and low resistance.
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor device and a method for manufacturing the same. More particularly, the present invention relates to a semiconductor device which is formed with a low resistance metal silicide layer having a superior phase stability and to a method for manufacturing the metal silicide layer.
- 2. Description of the Related Art
- As semiconductor devices become more highly integrated, the design rule of a device, such as channel length, an interval between the active areas, a wiring width, a wiring interval, and a contact size of a transistor are scaled-down. Regarding the contact size of a transistor, a silicidation process for forming a metal silicide is carried out in order to obtain a low resistance contact. Reducing the size of the contact causes the thickness uniformity of a suicide layer and the step coverage of the silicide layer to be of inferior quality.
- Conventionally, the metal silicide layer is formed on a bottom of a contact hole or a via hole using an argon sputtering process and an evaporation process using an electronic beam. However, use of those processes results in less step coverage than if a CVD (chemical vapor deposition) process is used. Additionally, it is difficult to uniformly control the thickness of the silicide layer.
- When the metal silicide layer is formed using the CVD process, silicon etching can occur depending on the vacuum levels caused by the source gas which is deposited at a high temperature. In addition, the isotropic deposition feature can cause undesired metal deposition at sidewalls of the contact hole or the via hole. Accordingly, the silicon deposited on the bottom of the contact hole reacts with the metal deposited on the sidewalls of the contact hole. In this case, the silicon is over-consumed, so bulk depletion and voids are generated, which cause contact resistance failure. In addition, the step coverage may be reduced depending on the aspect ratio of the contact hole when the silicide layer is formed using the CVD process.
- U.S. Pat. No. 5,780,929 discloses a method for forming a defect enhanced cobalt silicide layer. According to the disclosure of the above-referenced U.S. patent, a silicon substrate is defected by implanting argon into the silicon substrate without performing a separate heat treatment process. However, it is difficult to defect the silicon substrate properly, so the defection remaining on a surface of the silicon substrate can act as a source of current leakage. In addition, since the resistance is increased due to the argon implanted into the silicon substrate, the resistance reducing effect of a shallow silicide layer is reduced when a shallow junction is formed using the above method.
- On the other hand, as the design rule of the device is scaled down, a margin is required with respect to a short channel effect and a punch-through of the transistor. Accordingly, forming a shallow junction of a source/drain area and reducing the parasitic resistance, such as a sheet resistance and a contact resistance, of the source/drain area are required. For this reason, a self-aligned silicide (hereinafter, referred to as “salicide”) process has been developed, in which the silicide is selectively formed on a surface of a gate and a surface of a source/drain area to reduce the non-resistance of the gate, and the sheet resistance and contact resistance of the source/drain area.
- According to a conventional salicide process, a metal layer is deposited in a sputtering method. Then a first heat-treatment process is carried out to form a metal silicide layer having a first phase. Non-reacted metal layers are selectively removed by a wet etching process. Then, a second heat-treatment process is carried out to form a metal silicide layer having a second phase, which is stable with respect to the resistance and the phase stability as compared with the metal silicide having the first phase. However, the conventional salicide process does not uniformly form a shallow silicide layer having a thickness of less than 400 Å, which is problematic. When a silicide layer having a thickness of greater than 400 Å is formed, the uniformity of thickness and the uniformity of the surface roughness are reduced. Furthermore, the distance between the junction portion and the silicide layer is irregularly formed making it difficult to preserve the junction. For example, if the salicide process is carried out after depositing a cobalt layer having a thickness of greater than 100 Å, the thickness difference of a cobalt disilicide layer (CoSi2) having a thickness of 300 to 400 Å is greater than ±150 Å. In addition, since the heat-treatment process is carried out twice, the high heat budget can cause the agglomeration of the metal silicide layer and lateral over-growing.
- In order to solve the aforementioned problems, a process for forming an epitaxial silicide layer has been suggested. However, this process requires a monocrystalline silicon seed and therefore, is not adapted for the polycrystalline silicon layer. In addition, the vacuum level of the process chamber has to be maintained below 1 E-10 torr in order to obtain reproducibility. Furthermore, the deposition speed and the throughput are reduced; hence, it is not adapted for mass-production.
- In order to solve the aforementioned problems, it is a feature of an embodiment of the present invention to provide a semiconductor device which achieves a low contact resistance by forming an ohmic contact with respect to a semiconductor layer by using a metal silicide thin film.
- Another feature of an embodiment of the present invention is to provide a method for forming a low resistance metal silicide having a high phase stability by using native metal silicide formed at an interfacial area between metal and silicon.
- Still another feature of an embodiment of the present invention is to provide a method for forming a metal silicide layer in a semiconductor device, in which a salicide process can be achieved by using native metal silicide formed at an interfacial area between metal and silicon.
- In an embodiment of the present invention, there is provided a semiconductor device having a metal silicide-semiconductor contact structure, the semiconductor device comprising: a substrate; an insulation layer having an opening formed on the substrate; a metal silicide layer formed in the opening of the insulation layer, by using a native metal silicide having a first phase, the metal silicide layer having a second phase which has a first stoichiometrical composition ratio that is different from a second stoichiometrical composition ratio of the first phase; a conductive layer formed on the metal silicide layer of the second phase, wherein the metal silicide layer is formed between the substrate and the conductive layer and the metal silicide layer has a thickness of less than about 100 Å.
- In another embodiment of the present invention, there is provided a method for forming a metal silicide layer in a semiconductor device comprising: i) providing a substrate; ii) forming an insulation layer on the substrate, the insulation having an opening therein; iii) depositing a metal in the opening of the insulation layer so that a first layer including a native metal silicide layer of a first phase is formed at an interfacial area between the substrate and the deposited metal; iv) selectively removing the first layer while retaining the native metal silicide layer of the first phase; v) forming a second layer made of a conductive material on the native metal silicide layer of the first phase and the insulation layer; and vi) reacting the native metal silicide layer of the first phase with the substrate in order to transform the native metal silicide layer into a metal silicide layer having a second phase which has a first stoichiometrical composition ratio that is different from a second stoichiometrical composition ratio of the first phase.
- In still another embodiment of the present invention, there is, provided a method for forming a metal silicide layer in a semiconductor device comprising: i) providing a substrate having formed thereon a gate oxide film and a gate stack including a conductive material including silicon and having gate sidewall spacers on sides thereof; ii) depositing a metal on the substrate, the gate stack and the gate sidewall spacers, in such a manner that a first layer including a native metal silicide layer of a first phase is formed at an interfacial area between the silicon and the deposited refractory metal; iii) selectively removing the first layer while retaining the native metal silicide layer of the first phase; iv) depositing a first capping layer on a resulting structure; and v) reacting the native metal silicide layer of the first phase with the silicon in order to transform the native metal silicide layer into a metal silicide layer having a second phase which has a first stoichiometrical composition ratio that is different from a second stoichiometrical composition ratio of the first phase and a thickness of less than about 100 Å.
- According to yet another embodiment of the present invention, by using the native metal silicide formed at an interfacial area between the metal and the silicon, the native metal silicide layer is reacted with the silicon by means of a heat-treatment process so that a metal silicide layer with high phase stability and low resistance is obtained. Therefore, a thin metal suicide layer is uniformly formed, and the stepped portion is uniformly coated with the thin metal silicide layer. Additionally, when an embodiment of the present invention is applied to the salicide process, the primary heat-treatment process can be skipped so that the heat budget is reduced. Accordingly, the process is simplified and a shallow junction may be achieved.
- These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.
- The above features and other advantages of the present invention, as well as others, will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which:
- FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention;
- FIGS. 2A to2D are sectional views of a semiconductor device illustrating a method for forming metal silicide according to a first embodiment of the present invention;
- FIGS. 3A to3D are sectional views of a semiconductor device illustrating a method for forming metal silicide according to a second embodiment of the present invention;
- FIGS. 4A to4C are sectional views of a semiconductor device illustrating a method for forming metal silicide according to a third embodiment of the present invention; and
- FIGS. 5A to5D are sectional views of a semiconductor device illustrating a method for forming metal silicide according to a fourth embodiment of the present invention.
- Korean Patent Application No. 2000-55769, filed on Sep. 22, 2000, and entitled: “Semiconductor Device Having a Metal Silicide Layer and Method for Manufacturing the Same,” is incorporated by reference herein in its entirety.
- Hereinafter, preferred embodiments of the present invention will be described in detail with reference to accompanying drawings.
- FIG. 1 is a sectional view of a semiconductor device of an embodiment of the present invention.
- Referring to FIG. 1, an
insulation layer 12 is formed on asemiconductor substrate 10 that is comprised of silicon (Si), silicon germanium (SiGe), silicon-on-insulator (SOI), or silicon-germanium-on-insulator (SGOI). Theinsulation layer 12 has anopening 14 for exposing a semiconductor area, such as a predetermined area of thesemiconductor substrate 10. The semiconductor area is either thesemiconductor substrate 10 or a silicon layer or silicon germanium layer in the form of a crystalline phase or an amorphous phase formed on thesemiconductor substrate 10. - By using native metal silicide of a first phase, which is formed at an interfacial area between metal and silicon, a thin
metal silicide layer 16 is formed on the semiconductor area which is exposed by theopening 14. The thinmetal silicide layer 16 has a second phase having a first stoichiometrical composition ratio that is different from a second stoichiometrical composition ratio of the first phase. Aconductive layer 18 is formed on themetal silicide layer 16 of the second phase thereby forming a metal silicide-semiconductor contact structure. Themetal silicide layer 16 has a thickness of less than about 100 Å and a resistance between about 3 to 20 Ω/□. Theconductive layer 18 is comprised of silicon or silicon germanium in the form of the crystalline phase or the amorphous phase. Preferably, theconductive layer 18 is a semiconductor layer comprised of doped polycrystalline silicon. - According to an embodiment of the present invention, in a contact structure between semiconductor layers including the semiconductor substrate, a metal silicide layer is formed between the semiconductor layers so that an ohmic contact is formed with respect to upper and lower semiconductor layers. In the conventional contact structure, an interfacial characteristic is lowered due to a native oxide film remaining on a surface of a lower semiconductor layer so that the contact resistance is increased up to between about 2,000 and 10,000 Ω. The variation of the contact resistance is also increased. On the contrary, an embodiment of the present invention forms the metal silicide layer between the semiconductor layers, so not only is an ohmic contact with respect to the upper and lower semiconductor layers achieved, but also the interfacial characteristic is improved since the native oxide film formed on the surface of the lower semiconductor layer is replaced with silicide. Accordingly, the contact resistance of the metal silicide-semiconductor contact structure is reduced to less than 1,000 Ω and the contact resistance is uniformly achieved.
- Hereinafter, various embodiments of the present invention for forming a semiconductor device having a metal silicide layer will be described with reference to the accompanying drawings.
- FIGS. 2A to2D are sectional views of a semiconductor device illustrating a method for forming a metal suicide layer in a semiconductor device according to a first embodiment of the present invention.
- Referring to FIG. 2A, a
semiconductor substrate 100 comprising silicon (Si), silicon germanium (SiGe), silicon-on-insulator (SOI), or silicon-germanium-on-insulator (SGOI) is subject to an isolation process so that thesemiconductor substrate 100 is divided into an active area and a field area. Then, agate oxide film 102 and agate stack 106 are formed on thesemiconductor substrate 100. Particularly, thegate oxide film 102 is grown by thermal oxidation, and a highly impurity-dopedpolycrystalline silicon layer 104 is deposited on thegate oxide film 102. The polycrystalline silicon layer is doped by a conventional doping process, such as a diffusing process, an ion implanting process, or an in-situ doping process. After depositing amask layer 105 comprising silicon nitride on thepolycrystalline silicon layer 104, a photo etching process is carried out for patterning themask layer 105 and thepolycrystalline silicon layer 104, thereby forming thegate stack 106. Themask layer 105 increases the shoulder margin when the following self-align contact process is carried out. - Next,
gate sidewall spacers 108 comprising silicon nitride are formed at both sides of thegate stack 106 and a source/drain area 107 is formed on the active area of thesubstrate 100 using an ion implantation process. - Thereafter, an
insulation layer 110 comprising silicon oxide is deposited on an entire surface of the resulting structure. Then, theinsulation layer 100 is partially etched by an anisotropic etching process having an etching selectivity between the silicon oxide film and the silicon nitride film so that anopening 111 for exposing the semiconductor area, that is, the source/drain area 107, is formed. - Referring to FIG. 2B, after performing a wet cleaning process for removing the native oxide film and impurities remaining on a silicon surface, an RF plasma etching for cleaning is carried out in RF sputtering equipment. Then, a
first layer 112 of a metal (refractory metals, novel metals, transition metals are included) which is one selected from the group consisting of cobalt (Co), titanium (Ti), tungsten (W), nickel (Ni), platinum (Pt), hafnium (Hf), and palladium (Pd) is deposited on theopening 111 and theinsulation layer 110, in-situ, to a thickness of greater than 50 Å. As a result, a silicidation reaction between the metal and the silicon occurs at an interfacial surface of thefirst layer 112 and the silicon area (that is, source/drain area 107), so that a nativemetal silicide layer 114 of the first phase is formed to a thickness between about 25-35 Å. In addition, while the nativemetal silicide layer 114 is growing, the impurities remaining at the interfacial surface of the metal and the silicon are removed by the newly created suicide, and the interfacial surface of the metal silicide and the silicon is buried below the initial surface of the silicon area. As a result, a complete metal silicide-silicon contact is formed. - For example, when cobalt is deposited on the silicon substrate to a thickness of 100 Å, a uniform native cobalt monosilicide (CoSi) is stably formed at an interfacial surface between the cobalt layer and the silicon substrate.
- Referring to FIG. 2C, the
first layer 112 is selectively removed while retaining the nativemetal silicide layer 114 by a wet etching process using a chemical having an etching selectivity with respect to thefirst layer 112 and themetal silicide layer 114. Preferably, in the wet etching process, a pan strip is carried out at a temperature of about 65° C. for about 30 minutes without using H2O2, or a sulfuric strip process is carried out at a temperature of about 145° C. for about 20 minutes. - Referring to FIG. 2D, a
second layer 116, preferably a doped polycrystalline silicon layer, is deposited on themetal silicide layer 114 of the first phase and theinsulation layer 110. Thesecond layer 116 comprises silicon or germanium in the form of a crystalline phase or an amorphous phase and is electrically connected to the source/drain area 107 through theopening 111. Then, a rapid thermal process (RTP) is carried out at a temperature of 850° C. for 30 seconds to cause a reaction between themetal silicide layer 114 of the first phase and the silicon thereby transforming themetal silicide layer 114 into ametal silicide layer 115 having a second phase which has a first stoichiometrical composition ratio different from a second stoichiometrical composition ratio of the first phase. For example, if the cobalt monosilicide (CoSi) having a, thickness of about 30 Å is heat-treated, the volume thereof is expanded, so that a cobalt disilicide (CoSi2) having a thickness of less than about 100 Å and a sheet resistance of about 20 Ω/□ is formed. - In the present embodiment, the
second layer 116 is deposited before the heat treatment process is carried out, so a predetermined phase transition occurs in themetal silicide layer 114 of the first phase by the heat budget when the deposition process is carried out. At this time, a silicon source for the phase transition is supplied from both thesemiconductor substrate 100 and thesecond layer 116, so a shallow junction of the source/drain area can be achieved. Besides the heat-treatment process, various kinds of processes can be used to cause a reaction between the metal silicide and the silicon. - Then, a chemical mechanical polishing (CMP) process is performed with respect to the resulting structure formed with the
metal silicide layer 115 of the second phase, so that thesecond layer 116 is removed until the surface of theinsulation layer 110 is exposed in such a manner that thesecond layer 116 remains only in theopening 111. As a result, the contact structure consisting of second (polycrystalline silicon)layer 116—silicide layer 115—semiconductor substrate (that is, source/drain area 107) is obtained. Themetal silicide layer 115 acts as an ohmic contact with respect to upper and lower semiconductor layers and provides a low contact resistance. Thesecond layer 116 can be formed in a plug shape as shown in FIG. 2D, or can be patterned with a predetermined pattern by means of a photo etching process. Thesecond layer 116 reduces the aspect ratio of a contact hole formed thereon. - According to the first embodiment of the present invention, a low resistance metal silicide having a high phase stability is formed by performing the heat treatment process to the native metal silicide thin film which is uniformly formed at the interfacial area of the metal and the silicon. Therefore, a thin metal silicide layer having a uniform thickness may be achieved. In the conventional sputtering method or chemical vapor deposition method for forming metal silicide, the step difference portions are unevenly coated and voids are created. However, the present invention solves the above problems by using an interfacial silicide.
- In addition, according to the first embodiment of the present invention, the contact resistance is reduced by forming an ohmic contact of metal silicide-semiconductor. Furthermore, since the semiconductor layer is deposited before the heat treatment process for the phase transition of metal silicide is carried out, a thin junction is effectively achieved.
- FIGS. 3A to3D are sectional views of a semiconductor device showing a method for forming a metal silicide layer in a semiconductor device according to a second embodiment of the present invention.
- Referring to FIG. 3A, a
field oxide film 201 is formed on asemiconductor substrate 200 by means of an isolation process so that thesemiconductor substrate 200 is divided into an active area and a field area. Then, a MOS transistor (not shown) is formed on the active area of thesubstrate 200 by using a MOS transistor manufacturing process. Thereafter, a first insulation layer (not shown) is deposited on the MOS transistor and thesubstrate 200. The first insulation layer is etched by using a photo etching process thereby exposing the active area. - Next, a silicon or silicon germanium layer, such as a doped polycrystalline silicon layer, in the form of a crystalline phase or an amorphous phase, is deposited on an entire surface of the resulting structure. A
pad layer 202 which makes contact with the active area is formed by patterning the doped polycrystalline silicon layer. Thepad layer 202 can be formed by means of a self-align contact process. - Thereafter, a
second insulation layer 204 is deposited on thepad layer 202 and thesubstrate 200 and abit line stack 206 is formed on thesecond insulation layer 204 by using a bit line fabricating process. Thebit line stack 206 is formed as a mono-layer of the doped polycrystalline silicon layer, or formed as a polycide structure of the doped polycrystalline silicon layer and the metal silicide layer. In addition, thebit line stack 206 includes a bit line capping layer which is made of an insulation material and is formed on thebit line stack 206. - Then, after depositing a
third insulation layer 208 on thebit line stack 206 and thesecond insulation layer 204, thethird insulation layer 208 is planarized by using a reflow process, an etch-back process or a CMP process. Thethird insulation layer 208 is partially etched by using a photo etching process so that anopening 210 for exposing a semiconductor area, that is thepad layer 202, is formed. At this time, theopening 210 can be formed by means of a self-align contact process. - Referring to FIG. 3B, a
first layer 212 of a metal which is selected from the group consisting of cobalt (Co), titanium (Ti), tungsten (W), nickel (Ni), platinum (Pt), hafnium (Hf), and palladium (Pd) is deposited on theopening 210 and thethird insulation layer 208 to a thickness of greater than about 50 Å. As a result, a silicidation reaction between the metal and the silicon occurs at an interfacial surface of the exposedpad layer 202 and thefirst layer 212, so that a nativemetal silicide layer 214 of the first phase is formed to a thickness between about 25-35 Å. For example, when the cobalt is deposited, a native cobalt monosilicide (CoSi) layer is formed at a bottom portion of theopening 210 to a thickness of about 30 Å. - Referring to FIG. 3C, the
first layer 212 is selectively removed while retaining the nativemetal suicide layer 214 of the first phase by a wet etching process using a chemical having an etching selectivity with respect to thefirst layer 212 and themetal silicide layer 214. Preferably, in the wet etching process, a pan strip is carried out at a temperature of about 65° C. for about 30 minutes without using H2O2, or a sulfuric strip is carried out at a temperature of about 145° C. for about 20 minutes. - Referring to FIG. 3D, a
second layer 216 such as a doped polycrystalline silicon layer is deposited on themetal silicide layer 214 of the first phase and thethird insulation layer 208. Thesecond layer 216 comprises silicon or germanium in the form of a crystalline phase or an amorphous phase and is electrically connected to thepad layer 202 through theopening 210. At this time, a predetermined phase transition occurs in themetal silicide layer 214 of the first phase by the heat budget when the deposition process is carried out. - Then, a rapid thermal process (RTP) is carried out at a temperature of about 850° C. for about 30 seconds to cause a reaction between the
metal silicide layer 214 of the first phase and the silicon, thereby transforming themetal silicide layer 214 into ametal silicide layer 215 having a second phase which has a first stoichiometrical composition ratio different from a second stoichiometrical composition ratio of the first phase. For example, if the cobalt monosilicide (CoSi) layer having a thickness of about 30 Å is heat-treated, the volume thereof is expanded, so that a cobalt disilicide (CoSi2) layer having a thickness of less than 100 Å and a sheet resistance of 20 Ω/□ is formed. - Thereafter, a chemical mechanical polishing (CMP) process is performed to remove the
polycrystalline silicon layer 216 such that the surface of thethird insulation layer 208 is exposed so that thepolycrystalline silicon layer 216 remains only in theopening 210. As a result, the contact structure consisting ofpolycrystalline silicon layer 216—metal silicide layer 215—pad layer 202 is obtained. Themetal silicide layer 215 acts as an ohmic contact with respect to upper and lower semiconductor layers. Thepolycrystalline silicon layer 216 can be formed in a plug shape as shown in FIG. 3D, or can be patterned with a storage electrode pattern by means of a photo etching process. - According to the second embodiment of the present invention, with the replacement of the conventional semiconductor-semiconductor structure with the inventive semiconductor-metal silicide-semiconductor ohmic contact structure, interfacial feature is improved and the contact resistance is reduced.
- FIGS. 4A to4C are sectional views of a semiconductor device showing a method for forming a metal silicide layer in a semiconductor device according to a third embodiment of the present invention.
- Referring to FIG. 4A, a device structure (not shown) is formed on a
semiconductor substrate 300 consisting of silicon (Si), silicon germanium (SiGe) and silicon-on-insulator (SOI), or silicon-germanium-on-insulator (SGOI). The device structure includes a transistor, a bit line and a capacitor. - Then an
insulation layer 302 is deposited on the device structure and thesubstrate 300. Thereafter, theinsulation layer 302 is etched to form acontact hole 303 for exposing a semiconductor area, such as a predetermined area of thesemiconductor substrate 300. The semiconductor area exposed through thecontact hole 303 is either thesemiconductor substrate 300 or a silicon layer or silicon germanium layer formed on thesemiconductor substrate 300 in the form of a crystalline phase or an amorphous phase. - Then, a
first layer 304 of a metal which is one selected from the group consisting of cobalt (Co), titanium (Ti), tungsten (W), nickel (Ni), platinum (Pt), hafnium (Hf), and palladium (Pd) is deposited on thecontact hole 303 and theinsulation layer 302 to a thickness of greater than 50 Å. As a result, a silicidation reaction between the metal and the silicon occurs at the bottom of thecontact hole 303, so that a nativemetal silicide layer 306 of a first phase is formed to a thickness between about 25-35 Å. - Referring to FIG. 4B, the
first layer 304 is selectively removed while retaining the nativemetal silicide layer 306 of the first phase by a wet etching process using a chemical having an etching selectivity with respect to thefirst layer 304 and themetal silicide layer 306. Preferably, in the wet etching process, a pan strip is carried out at a temperature of about 65° C. for about 30 minutes without using H2O2, or a sulfuric strip is carried out at a temperature of about 145° C. for about 20 minutes. - Referring to FIG. 4C, a
second layer 308 comprising titanium nitride (TiN) is deposited on themetal silicide layer 306 of the first phase and theinsulation layer 302. Then, a rapid thermal process (RTP) is carried out at a temperature of about 850° C. for about 30 seconds in order to cause a reaction between themetal silicide layer 306 of the first phase and the silicon, thereby transforming themetal silicide layer 306 into ametal silicide layer 307 having a second phase which has a first stoichiometrical composition ratio different from a second stoichiometrical composition ratio of the first phase. Thesecond layer 308 can be made of metallic material instead of titanium nitride (TiN). Thesecond layer 308 acts as a diffusion barrier layer. - Next, a
third layer 310 consisting of metal is deposited on thesecond layer 308 to bury thecontact hole 303. As a result, an ohmic contact structure consisting of thethird layer 310—metal silicide layer 307—semiconductor substrate 300 is obtained. - According to the third embodiment of the present invention, a low resistance metal silicide having a high phase stability can be formed by using a native metal silicide thin film formed at an interfacial surface between a metal layer and a silicon area. Therefore, the metal silicide makes direct contact with the silicon substrate so that an ohmic contact is formed, thereby reducing the contact resistance.
- FIGS. 5A to5D are sectional views of a semiconductor device showing a method for forming a metal silicide layer in a semiconductor device according to a fourth embodiment of the present invention.
- Referring to FIG. 5A, a
semiconductor substrate 400 consisting of silicon (Si), silicon germanium (SiGe) and silicon-on-insulator (SOI), or silicon-germanium-on-insulator (SGOI) is subject to an isolation process so that thesemiconductor substrate 400 is divided into an active area and a field area. Then, agate oxide film 402 is grown on thesemiconductor substrate 400 by means of a thermal oxidation process. Then, a semiconductor material layer, such as a silicon layer or a silicon germanium layer in the form of a crystalline phase or an amorphous phase is deposited on thegate oxide film 402. The semiconductor material layer is patterned by using a photo etching process so that agate structure 404 is formed. Preferably, thegate structure 404 is formed as a highly-impurity doped polycrystalline silicon layer by means of a doping process, such as a diffusing process, an ion implanting process, or an in-situ doping process. In addition, when it is required to form the metal suicide layer only in the source/drain area, a capping insulation layer (not shown) is stacked on an upper surface of thegate structure 404. - Then, after forming
gate sidewall spacers 406 made of silicon oxide film at both sides of thegate stack 404, a source/drain area 408 is formed on the active area of thesemiconductor substrate 400 by using an ion implantation process. In addition, it is possible to form a lightly-doped source/drain area 405 aligned on thegate stack 404 by using the ion implantation process before thegate sidewall spacers 404 are formed on thegate stack 404. - Thereafter, a cleaning process is carried out to remove impurities including particles remaining on the
semiconductor substrate 400 and a native oxide film created on a surface of the silicon area. Then thesemiconductor substrate 400 is conveyed into an RF sputtering chamber. In order to prevent recreation of the native oxide film while thesemiconductor substrate 400 is being conveyed, acobalt layer 410 is deposited in-situ, after performing the RF plasma etching process, on thegate stack 404, thegate sidewall spacers 406, and thesemiconductor substrate 400, to a thickness of about 100 Å. At this time, one of titanium (Ti), tungsten (W), nickel (Ni), platinum (PT), hafnium (Hf), and palladium (Pd) may be selectively used instead of cobalt (Co). - As the
cobalt layer 410 is deposited, the silicidation reaction between silicon and cobalt is generated at an interfacial surface of the exposed silicon area and thecobalt layer 410 so that a cobalt silicide layer of the first phase, that is, a cobalt monosilicide (CoSi)layer 412, is uniformly formed on the upper surface of thegate stack 404 and the upper surface of the source/drain area 408, to a thickness of about 30 Å. At this time, the native silicide layer in the form of a monosilicide may not be achieved if another refractory metal is used instead of cobalt. - Referring to FIG. 5B, the
cobalt layer 410 is selectively removed while retaining thecobalt monosilicide layer 412 by a wet etching process using a chemical having an etching selectivity with respect to cobalt and silicide. Preferably, in the wet etching process, a pan strip is carried out at a temperature of about 65° C. for about 30 minutes without using H2O2, or a sulfuric strip is carried out at a temperature of about 145° C. for about 20 minutes. - Referring to FIG. 5C, a
first capping layer 414 is deposited on thesemiconductor substrate 400 including thecobalt monosilicide layer 412. Thefirst capping layer 414 is made of a metallic compound selected from the group consisting of titanium nitride (TiN), titanium tungsten (TiW), tantalum nitride (TaN), and tungsten nitride (WN). In addition, thefirst capping layer 414 can be made of an insulation material, such as SiN or SiON. Thefirst capping layer 414 prevents the diffusing of cobalt and controls the speed of the silicidation reaction when the following heat treatment process is carried out. - Referring to FIG. 5D, a rapid thermal process (RTP) is carried out at a temperature of about 850° C. for about 30 seconds to cause a reaction between metal silicide and silicon, thereby transforming the phase of the
cobalt monosilicide layer 412 into a cobalt disilicide (CoSi2)layer 415 having a thickness of less than about 100 Å and a sheet resistance of about 20 Ω/. At this time, if another refractory metal is used instead of cobalt, the resulting silicide layer may not be formed in a monosilicide phase. - After removing the
first capping layer 414, an insulation material having an etching selectivity with respect to the cobalt disilicide (CoSi2)layer 415 is deposited on the resulting structure to form asecond capping layer 416. Then a contact hole (not shown) for exposing the source/drain area 408 is formed by partially etching thesecond capping layer 416. - According to the fourth embodiment of the present invention, a uniform and thin metal silicide layer can be obtained by using the native silicidation reaction generated at an interfacial area of metal and silicon. In addition, unlike the conventional silicide forming method, which requires performing the heat treatment process twice to obtain the stable silicide layer, the present invention can obtain the low resistance metal silicide layer with high phase stability by performing the heat treatment process only once. Accordingly, the heat budget is reduced so that the shallow junction can be effectively achieved. Furthermore, according to the present invention, the process is simplified and reproducibility is improved and thereby makes mass production possible.
- In sum, the present invention allows a low resistance metal silicide layer with high phase stability to be obtained by causing a reaction between the native metal silicide layer of the first phase and silicon by means of the heat treatment process in order that a thin metal silicide layer can be uniformly formed. Also, since the present invention uses the native metal silicide layer, the step difference portion can be uniformly coated.
- Furthermore, since the present invention does not require performing the heat treatment process twice, the heat budget is reduced. Accordingly, when the present invention is applied to a salicidation process, a shallow junction is effectively obtained while the process is simplified.
- Preferred embodiments of the present invention have been disclosed herein and, although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for the purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and scope may be made without departing from the spirit and scope of the invention as set forth in the following claims.
Claims (20)
1. A semiconductor device having a metal silicide contact structure, comprising:
a substrate;
an insulation layer having an opening formed on the substrate;
a metal silicide layer formed in the opening of the insulation layer; and
a conductive layer formed on the metal silicide layer,
wherein the metal silicide layer is formed between the substrate and the conductive layer and the metal silicide layer has a thickness of less than about 100 Å.
2. A semiconductor device having a metal silicide contact structure as claimed in claim 1 , wherein the conductive layer is a semiconductor layer.
3. A semiconductor device having a metal silicide contact structure as claimed in claim 1 , wherein the metal silicide layer is formed using a native metal silicide having a first phase and a second phase, the second phase having a first stoichiometrical composition ratio that is different from a second stoichiometrical composition ratio of the first phase.
4. A semiconductor device having a metal silicide contact structure as claimed in claim 1 , wherein the substrate is comprised of a material selected from the group consisting of silicon, silicon germanium, silicon-on-insulator (SOI), and silicon-germanium-on-insulator (SGOI).
5. A semiconductor device having a metal silicide contact structure as claimed in claim 1 , further comprising a silicon layer or a silicon germanium layer in a form of a crystalline phase or an amorphous phase formed on the substrate.
6. A semiconductor device having a metal silicide contact structure as claimed in claim 1 , wherein the conductive layer comprises a silicon layer or a silicon germanium layer in a form of a crystalline phase or an amorphous phase.
7. A semiconductor device having a metal suicide contact structure as claimed in claim 1 , wherein the conductive layer is doped polycrystalline silicon.
8. A semiconductor device having al metal silicide contact structure as claimed in claim 1 , wherein the metal silicide layer has a resistance between about 3 to 20 Ω/□.
9. A semiconductor device having a metal silicide contact structure as claimed in claim 1 , further comprising a gate oxide film formed on the substrate.
10. A semiconductor device having a metal silicide contact structure as claimed in claim 9 , further comprising a gate stack formed on the gate oxide film.
11. A semiconductor device having a metal silicide contact structure as claimed in claim 10 , further comprising gate sidewall spacers formed on the sides of the gate stack.
12. A semiconductor device having a metal silicide contact structure as claimed in claim 9 , further comprising a source/drain area formed on the substrate exposed by the opening in the insulation layer.
13. A semiconductor device having a metal silicide contact structure as claimed in claim 1 , further comprising:
field oxide films formed on the substrate; and
a pad layer formed between the field oxide films and below the metal silicide layer.
14. A semiconductor device having a metal silicide contact structure as claimed in claim 13 , and further comprising:
a second insulation layer formed above the field oxide films and the pad layer;
a bit line stack formed on the second insulation layer; and
a third insulation layer formed on the bit line stack and the second insulation layer.
15. A semiconductor device having a metal silicide contact structure as claimed in claim 1 , wherein the conductive layer is titanium nitride (TiN).
16. A semiconductor device having a metal silicide contact structure as claimed in claim 1 , wherein the conductive layer is a metallic material.
17. A semiconductor device having a metal silicide contact structure as claimed in claim 15 , further comprising a metal layer formed on the conductive layer.
18. A semiconductor device having a metal silicide contact structure, comprising:
a substrate;
a gate oxide film formed on the substrate;
a gate stack formed on the gate oxide film;
a metal silicide layer formed on the substrate and the gate stack; and
a capping layer formed above the metal silicide layer, wherein the metal silicide layer has a thickness less than about 100 Å.
19. A semiconductor device having a metal silicide contact structure as claimed in claim 18 , further comprising:
a source/drain area formed on the substrate;
a lightly-doped source/drain area formed on the substrate between the metal silicide layer formed on the substrate and the gate oxide film; and
gate sidewall spacers formed on sides of the gate stack.
20-43. (Cancelled)
Priority Applications (1)
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US10/823,544 US20040198007A1 (en) | 2000-09-22 | 2004-04-14 | Semiconductor device having a metal silicide layer and method for manufacturing the same |
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KR2000-55769 | 2000-09-22 | ||
KR1020000055769A KR100343653B1 (en) | 2000-09-22 | 2000-09-22 | Semiconductor device with metal silicide layer and method of manufacturing the same |
US09/949,853 US6740587B2 (en) | 2000-09-22 | 2001-09-12 | Semiconductor device having a metal silicide layer and method for manufacturing the same |
US10/823,544 US20040198007A1 (en) | 2000-09-22 | 2004-04-14 | Semiconductor device having a metal silicide layer and method for manufacturing the same |
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US09/949,853 Division US6740587B2 (en) | 2000-09-22 | 2001-09-12 | Semiconductor device having a metal silicide layer and method for manufacturing the same |
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US20040198007A1 true US20040198007A1 (en) | 2004-10-07 |
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US09/949,853 Expired - Lifetime US6740587B2 (en) | 2000-09-22 | 2001-09-12 | Semiconductor device having a metal silicide layer and method for manufacturing the same |
US10/823,544 Abandoned US20040198007A1 (en) | 2000-09-22 | 2004-04-14 | Semiconductor device having a metal silicide layer and method for manufacturing the same |
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US (2) | US6740587B2 (en) |
JP (1) | JP4748408B2 (en) |
KR (1) | KR100343653B1 (en) |
TW (1) | TW513754B (en) |
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Also Published As
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---|---|
KR20020023496A (en) | 2002-03-29 |
US20020036353A1 (en) | 2002-03-28 |
JP2002176010A (en) | 2002-06-21 |
JP4748408B2 (en) | 2011-08-17 |
KR100343653B1 (en) | 2002-07-11 |
TW513754B (en) | 2002-12-11 |
US6740587B2 (en) | 2004-05-25 |
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