US20040201107A1 - Transistor assembly and method for the production thereof - Google Patents

Transistor assembly and method for the production thereof Download PDF

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US20040201107A1
US20040201107A1 US10/487,802 US48780204A US2004201107A1 US 20040201107 A1 US20040201107 A1 US 20040201107A1 US 48780204 A US48780204 A US 48780204A US 2004201107 A1 US2004201107 A1 US 2004201107A1
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film
fact
micro holes
metal layer
semiconductor material
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Rolf Koenenkamp
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Helmholtz Zentrum Berlin fuer Materialien und Energie GmbH
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Hahn Meitner Institut Berlin GmbH
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Publication of US20040201107A1 publication Critical patent/US20040201107A1/en
Priority to US11/327,218 priority Critical patent/US7579281B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/491—Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/50—Forming devices by joining two substrates together, e.g. lamination techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/902—Specified use of nanostructure
    • Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
    • Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device
    • Y10S977/938—Field effect transistors, FETS, with nanowire- or nanotube-channel region

Definitions

  • the invention relates to a transistor arrangement and to a method of its fabrication.
  • the transistor arrangement is constructed such that semi-conductor material is vertically introduced into micro-holes of a film laminate consisting of two plastic films with an interposed metal layer, the semiconductor material being provided with contacts by metalization of the upper and lower surface of the film laminate.
  • the micro holes used are cylindrical ion trace channels which are formed in polymer or polyester films by ion bombardment and a subsequent etching treatment. These ion trace channels may be filled by electrode deposition, precipitation in a chemical bath or by other suitable processes, with connecting semiconductors, or, initially, by a hollow-cylindrical insulation layer followed by a connecting semiconductor.
  • the film laminate into which the semiconductor material is embedded is fabricated by a film being coated with a metal layer, for instance by vaporization, and by a second film connected by an adhesive agent to the metal layer on the surface of the first film. Thereafter, ion bombardment is carried out in an accelerator. Along the ion trace, the ion bombardment results in the formation in the film of amorphous channels of a diameter of a few Angstroms. The ion trace channels thus formed are then sensitized for a subsequent etching treatment in the film which causes micro holes to be formed in the plastic films. Prior to sensitization, a further sensitization may optionally be performed with a chemical sensitizing agent.
  • the method of forming micro holes in films has heretofore been used in connection with a single-layer film and without a metal layer between the layers of film for fabricating micro filters and in other applications. It has not been used, however, for fabricating transistors.
  • the metal layer is removed by a further etching process in the area of the holes.
  • the metal film may be removed sufficiently to extend just to the ion trace channel in the films.
  • the interposed metal layer serves as a gate terminal, and for that reason it should either form a Schottky contact (MESFET), or it should be insulated from the semiconductor (MOSFET) as shown in S.M. Sze, Physics of Semiconductor Devices, Wiley, N.Y., 1981, pp. 312 seq. and pp. 321 seq.
  • semiconductor material may be grown from the edge of the interposed metal layer by electrode deposition to form a MESFET, thus forming a Schottky contact.
  • an insulation layer is initially deposited, for instance by precipitation in a bath, at the interior wall of the entire channel.
  • An insulation layer may also be formed only in the area of the metal layer by chemically or electro-chemically converting, e.g. oxidizing, it from the micro holes. Instead of forming an insulation layer, the metal layer may be removed by etching around the micro hole thus forming an insulating cavity.
  • the semiconductor material is introduced by electrode deposition or by precipitation in a chemical bath. Drain and source contacts are formed by a subsequent metalization of the upper and lower surfaces of the film laminate. It may be necessary to metalize at least one surface of the film laminate prior to the electrode deposition in order to provide the electrode required for the application of a potential during the electrode deposition.
  • By structuring the metalization layer by means of conventional lithographic processes, e.g. in matrix form, it is possible to connect transistors to form transistor units which may be energized together.
  • the formation of transistor area arrangements may be augmented by masking the film laminate before the ion bombardment. Last but not least it is also possible to fabricate individual transistors at a predetermined site by bombarding the film laminate by a controlled ion beam for forming individual ion trace channels.
  • the advantage of the cylindrical vertical arrangement of the transistors is that they are mechanically very sturdy since the film is both flexible and stretchable. Moreover, the organic film material is substantially softer than inorganic transistor material. Consequently, all bending, shearing and pressure forces are wholly absorbed by the film material, thus rendering the characteristic curve of the transistors and other electrical parameters substantially constant, notwithstanding any bending, flexing and tensile forces.
  • the micro holes may be fabricated with diameters as small as 30 nm and since they may be filled with semiconductor material, it is possible to fabricate transistors on the nanometer scale without lithography and without masking technology.
  • the channel length of the transistors is determined by the space charge range of the center gate contact. As a rule, it is substantially smaller than the thickness of the film which determined the distance between source and drain. Accordingly, the transistor is best operated in a depletion mode, see German patent specification 199 16 403 C.
  • the small diameter and the small channel length open the possibilities of operating the transistor in a quantum regime.
  • a film of A 4 size may be used with closely adjacent vertical transistors arrayed as optical pixels with about 1,00 transistors. While the transistors are distributed randomly, the large number of transistors in the pixels nevertheless permits a precise energization of the pixels. At a diameter of the transistors of 150 nm and an average spacing of 500 nm, 1,000 transistors result in a size of pixel of about 20 ⁇ 20 ⁇ m, which constitutes a conventional size.
  • FIG. 1 is a sectional view of a transistor in accordance with the invention.
  • FIG. 2 is a sectional view of a second variant of a transistor
  • FIG. 3 depicts the energy band gap of a transistor in accordance with the invention.
  • a metal layer 2 e.g. Al, Cu, Ag
  • a PET film 1 of 5 ⁇ m thickness
  • the metal surface is then adhesively connected to a second PET film 2 of 5 ⁇ m thickness.
  • ion trace channels For forming ion trace channels, sections of about A 4 size are bombarded in an accelerator with fast ions, preferably krypton or xenon ions, at an energy of several 100 MeV at a density of about 10 8 /cm 2 .
  • the resultant ion trace channels are then pretreated with a sensitizing agent (e.g. dimethyl formamide, pyridine, dioxane) before being etched in a solution of sodium hydroxide (NaOH).
  • a sensitizing agent e.g. dimethyl formamide, pyridine, dioxane
  • NaOH sodium hydroxide
  • the center metal layer is etched (in a solution of sodium hydroxide if it is Al, for instance, in HNO3 if it is CU, etc.) Thereafter, the micro holes 4 are lined, by precipitation in a chemical bath or by another process as described in German patent specification 199 16 403, with an insulation layer 5 of TiO 2 or another oxide.
  • a source contact 6 or a drain contact 7 is fabricated by vapor deposition of platinum on the second surface of the film laminate.
  • the center metal layer 2 constitutes the gate contact.
  • micro holes 4 flaring conically outwardly are formed with a diameter in the area of the gate of about 100 nm.
  • the metal layer consists of aluminum. At its margin, it is electro-chemically oxidized to aluminum oxide 9 at the etched out micro holes 4 so that the need to apply an insulation layer is avoided.
  • FIG. 3 depicts the energy conditions of the electron flow in such a transistor.
  • the gate results in a space charge zone of a length of about 400 nm in which the potential of the CuSNC may be shifted. Since CuSNC is p-conductive, depletion in the channel results in a positive gate potential. When the depletion extends through the entire thickness of the semiconductor cylinder, the conductivity between source and drain is significantly reduced. At a negative gate potential enrichment occurs in the channel. However, since the length of the channel is insignificant relative to the spacing between source and drain, the increase in conductivity between source and drain remains insignificant.

Abstract

A transistor assembly with semiconductor material vertically introduced into micro holes (4) in a pliable a film laminate consisting of two plastic films (1, 3) with a metal layer (2) located therebetween. Said semiconductor material is provided with contacts (6, 7) by metalizing the top side and bottom side of the film laminate. The assembly is very strong by virtue of the fact that the film can be bent and stretched.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The invention relates to a transistor arrangement and to a method of its fabrication. [0002]
  • 2. The Prior Art [0003]
  • For fabricating thin-film transistors it is known to apply semiconductor material on a flexible substrate in a planar arrangement. When mechanical stress is applied to the substrates by bending, shearing or stretching, the thin-film transistors are also subjected to stress which can easily lead to damage of the semiconductor layers or to their separation from the substrate layer. [0004]
    • OBJECT OF THE INVENTION
  • It is an object of the invention to provide for a transistor arrangement and a method of its fabrication, using a flexible substrate wherein mechanical stresses do not result in deterioration of the function of the transistors. [0005]
    • BRIEF SUMMARY OF THE INVENTION
  • In accordance with the invention, the object is accomplished by [the characteristics of [0006] claims 1 and 8. Useful embodiments are the subject of the sub-claims] a transistor arrangement comprising a laminate of at least two layers of plastic film with an interposed metal layer and provided with micro holes filed by a vertically introduced semiconductor material provided at at least one of the upper and lower surfaces of the laminate with at least one electrical contact.
  • Other objects will in part be obvious and will in part appear hereinafter. [0007]
  • Accordingly, the transistor arrangement is constructed such that semi-conductor material is vertically introduced into micro-holes of a film laminate consisting of two plastic films with an interposed metal layer, the semiconductor material being provided with contacts by metalization of the upper and lower surface of the film laminate. [0008]
  • In accordance with the invention, the micro holes used are cylindrical ion trace channels which are formed in polymer or polyester films by ion bombardment and a subsequent etching treatment. These ion trace channels may be filled by electrode deposition, precipitation in a chemical bath or by other suitable processes, with connecting semiconductors, or, initially, by a hollow-cylindrical insulation layer followed by a connecting semiconductor. [0009]
  • The film laminate into which the semiconductor material is embedded is fabricated by a film being coated with a metal layer, for instance by vaporization, and by a second film connected by an adhesive agent to the metal layer on the surface of the first film. Thereafter, ion bombardment is carried out in an accelerator. Along the ion trace, the ion bombardment results in the formation in the film of amorphous channels of a diameter of a few Angstroms. The ion trace channels thus formed are then sensitized for a subsequent etching treatment in the film which causes micro holes to be formed in the plastic films. Prior to sensitization, a further sensitization may optionally be performed with a chemical sensitizing agent. The method of forming micro holes in films has heretofore been used in connection with a single-layer film and without a metal layer between the layers of film for fabricating micro filters and in other applications. It has not been used, however, for fabricating transistors. [0010]
  • Following etching of the polymer films applied to both sides of the metal layer, the metal layer is removed by a further etching process in the area of the holes. For this purpose, the metal film may be removed sufficiently to extend just to the ion trace channel in the films. In the proposed transistor, the interposed metal layer serves as a gate terminal, and for that reason it should either form a Schottky contact (MESFET), or it should be insulated from the semiconductor (MOSFET) as shown in S.M. Sze, Physics of Semiconductor Devices, Wiley, N.Y., 1981, pp. 312 seq. and pp. 321 seq. Where the material combination of metal and semiconductor permits it, semiconductor material may be grown from the edge of the interposed metal layer by electrode deposition to form a MESFET, thus forming a Schottky contact. [0011]
  • For fabricating a MOSFET an insulation layer is initially deposited, for instance by precipitation in a bath, at the interior wall of the entire channel. An insulation layer may also be formed only in the area of the metal layer by chemically or electro-chemically converting, e.g. oxidizing, it from the micro holes. Instead of forming an insulation layer, the metal layer may be removed by etching around the micro hole thus forming an insulating cavity. [0012]
  • After the formation of micro holes from the ion trace channels has been completed, the semiconductor material is introduced by electrode deposition or by precipitation in a chemical bath. Drain and source contacts are formed by a subsequent metalization of the upper and lower surfaces of the film laminate. It may be necessary to metalize at least one surface of the film laminate prior to the electrode deposition in order to provide the electrode required for the application of a potential during the electrode deposition. By structuring the metalization layer by means of conventional lithographic processes, e.g. in matrix form, it is possible to connect transistors to form transistor units which may be energized together. The formation of transistor area arrangements may be augmented by masking the film laminate before the ion bombardment. Last but not least it is also possible to fabricate individual transistors at a predetermined site by bombarding the film laminate by a controlled ion beam for forming individual ion trace channels. [0013]
  • The advantage of the cylindrical vertical arrangement of the transistors is that they are mechanically very sturdy since the film is both flexible and stretchable. Moreover, the organic film material is substantially softer than inorganic transistor material. Consequently, all bending, shearing and pressure forces are wholly absorbed by the film material, thus rendering the characteristic curve of the transistors and other electrical parameters substantially constant, notwithstanding any bending, flexing and tensile forces. [0014]
  • Since the micro holes may be fabricated with diameters as small as 30 nm and since they may be filled with semiconductor material, it is possible to fabricate transistors on the nanometer scale without lithography and without masking technology. The channel length of the transistors is determined by the space charge range of the center gate contact. As a rule, it is substantially smaller than the thickness of the film which determined the distance between source and drain. Accordingly, the transistor is best operated in a depletion mode, see German patent specification 199 16 403 C. The small diameter and the small channel length open the possibilities of operating the transistor in a quantum regime. [0015]
  • Moreover, the possible minute dimensions also yield advantages in respect of integrated control circuits. [0016]
  • Many applications are possible. For use in the field of displays, a film of A[0017] 4 size may be used with closely adjacent vertical transistors arrayed as optical pixels with about 1,00 transistors. While the transistors are distributed randomly, the large number of transistors in the pixels nevertheless permits a precise energization of the pixels. At a diameter of the transistors of 150 nm and an average spacing of 500 nm, 1,000 transistors result in a size of pixel of about 20×20 μm, which constitutes a conventional size.
    •  DESCRIPTION OF THE SEVERAL DRAWINGS
  • The novel features which are considered to be characteristic of the invention are set forth with particularity in the appended claims. The invention itself, however, in respect of its structure, construction and lay-out as well as manufacturing techniques, together with other objects and advantages thereof, will be best understood from the following description of preferred embodiments when read in connection with the appended drawings, in which: [0018]
  • FIG. 1 is a sectional view of a transistor in accordance with the invention; [0019]
  • FIG. 2 is a sectional view of a second variant of a transistor; and [0020]
  • FIG. 3 depicts the energy band gap of a transistor in accordance with the invention.[0021]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The method of fabrication will be explained on the basis of the sectional representation of a single transistor in FIG. 1. Initially, a metal layer [0022] 2 (e.g. Al, Cu, Ag) is applied by vapor deposition on one surface of a PET (polyethylene therephthalate) film 1 of 5 μm thickness. To form a laminate, the metal surface is then adhesively connected to a second PET film 2 of 5 μm thickness.
  • For forming ion trace channels, sections of about A[0023] 4 size are bombarded in an accelerator with fast ions, preferably krypton or xenon ions, at an energy of several 100 MeV at a density of about 108/cm2. The resultant ion trace channels are then pretreated with a sensitizing agent (e.g. dimethyl formamide, pyridine, dioxane) before being etched in a solution of sodium hydroxide (NaOH). Depending upon the etching time, micro holes 4 will result with a diameter between 30 nm and 20 μm will result. Thereafter, the center metal layer is etched (in a solution of sodium hydroxide if it is Al, for instance, in HNO3 if it is CU, etc.) Thereafter, the micro holes 4 are lined, by precipitation in a chemical bath or by another process as described in German patent specification 199 16 403, with an insulation layer 5 of TiO2 or another oxide.
  • This is followed by an electrochemical implantation of p-conductive copper thiocyanate [0024] 8 (CuSCN) in the micro holes 4. The dosage may be changed by adjusting the potential ratios; see C. Rost et al., Appl. Phys. Left. 75, 692 (1999). To apply a potential, one surface of the film laminate is provided with a metal layer of gold which subsequently will constitute a source contact 6 or a drain contact 7. The electro deposition may take place in a conventional potentiostate. A 0.05 molar Cu(BF4)2 solution and 0.025 molar KSCN in ethanol have been found to be suitable at a cathode voltage of −(0.2 to 0.8) V relative to a platinum reference electrode. It has been found to be possible to form hexagonal crystals of <001> or <101> orientation.
  • Following the complete filling of the [0025] micro holes 4 with CuSCN, a source contact 6 or a drain contact 7 is fabricated by vapor deposition of platinum on the second surface of the film laminate. The center metal layer 2 constitutes the gate contact.
  • Another possibility is shown in FIG. 2. As the etching progresses, [0026] micro holes 4 flaring conically outwardly are formed with a diameter in the area of the gate of about 100 nm. The metal layer consists of aluminum. At its margin, it is electro-chemically oxidized to aluminum oxide 9 at the etched out micro holes 4 so that the need to apply an insulation layer is avoided.
  • FIG. 3 depicts the energy conditions of the electron flow in such a transistor. The gate results in a space charge zone of a length of about 400 nm in which the potential of the CuSNC may be shifted. Since CuSNC is p-conductive, depletion in the channel results in a positive gate potential. When the depletion extends through the entire thickness of the semiconductor cylinder, the conductivity between source and drain is significantly reduced. At a negative gate potential enrichment occurs in the channel. However, since the length of the channel is insignificant relative to the spacing between source and drain, the increase in conductivity between source and drain remains insignificant. [0027]

Claims (46)

What is claimed is:
1. A transistor arrangement,
characterized by the fact that semiconductor material is vertically introduced into micro holes (4) of a film laminate consisting of two plastic films (1, 3) with an intermediate metal layer (2), the semiconductor material being provided with contacts (6, 7) by metalization of the upper and lower surface of the film laminate.
2. The transistor arrangement of claim 1,
characterized by the fact that
the film (1, 3) is a polymer film.
3. The transistor arrangement of claim 1,
characterized by the fact that
the film (1, 3) is a polyester film.
4. The transistor arrangement of claim 3,
characterized by the fact that
the film (1, 3) is a PET film.
5. The transistor arrangement of one of the preceding claims,
characterized by the fact that
the film (1, 3) is of a thickness of 2 μm to 30 μm.
6. The transistor arrangement of one of the preceding claims,
characterized by the fact that
the metal layer (2) consists of copper, aluminum or silver.
7. The transistor arrangement of one of the preceding claims,
characterized by the fact that
the semiconductor material is copper thiocyanate (CuSCN).
8. A method of fabricating a transistor arrangement,
characterized by the fact that
a metal layer is embedded between two plastic films, that ion trace channels are introduced into this laminate film by ion bombardment, that the film laminate is subsequently subjected to an etching treatment, that the ion trace channels etched to micro holes are filled with semiconductor material and that by metal coating source or drain contacts are formed on the upper and lower surface of the film laminate.
9. The method of claim 8,
characterized by the fact that
the metal layer between the plastic films is subjected within the micro holes to a special etching treatment.
10. The method of claim 9,
characterized by the fact that
for forming field effect transistors the micro holes are provided with an insulating layer.
11. The method of claim 8 or 9,
characterized by the fact that
for forming field effect transistors the metal layer in the area of the micro holes is etched away to behind the diameter of the micro holes.
12. The method of claim 8 or 9,
characterized by the fact that
for forming field effect transistors the metal layer in the area of the micro holes is electro-chemically oxidized.
13. The method of one of claims 8 to 12,
characterized by the fact that
filling of the micro holes with semiconductor material is carried out by electrode deposition.
14. The method of one of claims 8 to 12,
characterized by the fact that
filling of the micro holes with semiconductor material is carried out by precipitation in a chemical bath.
15. The method of one of claims 8 to 14,
characterized by the fact that
the etching treatment of the ion trace channels results in the formation of micro holes of a diameter between 30 nm and 20 μm.
16. The method of one of claims 8 to 15,
characterized by the fact that
the metal layer is applied to one surface of the plastic foil by vaporization or sputtering.
17. The method of one of claims 8 to 16,
characterized by the fact that
the plastic foil provided with the metal layer and the second plastic film are adhesively connected to each other.
18. The method of one of claims 8 to 17,
characterized by the fact that
the etching of the ion trace channels is carried out with a sodium hydroxide solution.
19. The method of one of claims 8 to 18,
characterized by the fact that
the ion bombardment is carried out at an ion density of 107/cm2 to 109/cm2.
20. The method of one of claims 8 to 19,
characterized by the fact that
the ion bombardment is carried out at an energy of several 100 MeV.
21. The method of one of claims 8 to 20,
characterized by the fact that
that prior to etching of the ion trace channels the film laminate is treated with a sensitizing agent.
22. The method of one of claims 8 to 21,
characterized by the fact that
the prior to metal coating of its upper and lower surface the film laminate is masked.
23. The method of one of claims 8 to 22,
characterized by the fact that
the film laminate is masked prior to ion bombardment.
24. A transistor assembly, comprising:
a film laminate comprising at least first and second adhesively connected superposed layers of pliable film and a metal layer interposed therebetween, the film laminate being provided with a plurality of micro holes;
a semiconductor material provided in the micro holes; and
electrical contacts connected to the semiconductor material and comprising a metalization on at least one outer surface of the film laminate.
25. The transistor assembly of claim 24, wherein micro holes are of a diameter between 30 nm and 20 μm.
26. The transistor assembly of claim 25, wherein the pliable film is a polymeric film.
27. The transistor assembly of claim 26, wherein the polymeric film is a polyester film.
28. The transistor assembly of claim 26, wherein the polyester film is a polyethylene terephthalate film.
29. The transistor assembly of claim 24, wherein the pliable film is of a thickness of between 2 μm and 30 μm.
30. The transistor assembly of claim 24, wherein the metal layer consists of the group selected from copper, aluminum and silver.
31. The transistor assembly of claim 24, wherein the semiconductor material is copper thiocyanate (CuSCN).
32. A method of fabricating a transistor assembly, comprising the steps of:
providing a film laminate comprising first and second layers of pliable film with a metal layer therebetween;
subjecting the film laminate to ion bombardment to provide a plurality of ion trace channels therein;
etching the film laminate to an etching process to convert the ion trace channels to micro holes;
vertically introducing into the micro holes a semiconductor material; and
metal coating at least one of the outer surfaces of the film laminate to provide at least one electrical contact connected to the semiconductor material.
33. The method of claim 32, further comprising the step of subjecting the metal layer between the layers of pliable film to an etching process within the micro holes.
34. The method of claim 33, further comprising the step of lining the micro holes with an insulating layer to form a field effect transistor.
35. The method of claim 34, further comprising the step of etching away the metal layer in the area of the micro holes beyond the diameter of the micro holes to form a field effect transistor.
36. The method of claim 33, further comprising the step of electro-chemically oxidizing the metal layer in the area of the micro holes to form a field effect transistor.
37. The method of claim 32, wherein the step of introducing the semiconductor material is carried out by electrode deposition.
38. The method of claim 32, wherein the step of introducing the semiconductor material is carried out by precipitation in a chemical bath.
39. The method of claim 32, wherein the metal layer is applied to a surface of one plastic film by one of vapor deposition and sputtering.
40. The method of claim 39, further comprising the step of adhesively connecting the pliable film with the metal layer thereon and the other pliable film by adhesion.
41. The method of claim 32, wherein the step of etching for converting the ion trace channels to micro holes is carried out in a solution of sodium hydroxide.
42. The method of claim 32, wherein the step of ion bombardment is carried out at a density of 107/cm2 to 10 9/cm2.
43. The method of claim 32, wherein the step of ion bombardment is carried out at a power of several 100 MeV.
44. The method of claim 40, further comprising the step of subjecting the film laminate to a sensitizing agent prior to etching.
45. The method of claim 32, further comprising the step of masking the film laminate prior to metal coating.
46. The method of claim 32, further comprising the step of masking the film laminate prior to ion bombardment.
US10/487,802 2001-08-27 2002-08-27 Transistor assembly and method for the production thereof Abandoned US20040201107A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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US20060121654A1 (en) 2006-06-08
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WO2003026034A1 (en) 2003-03-27
US7579281B2 (en) 2009-08-25

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