US20040208043A1 - Feram memory device - Google Patents
Feram memory device Download PDFInfo
- Publication number
- US20040208043A1 US20040208043A1 US10/418,734 US41873403A US2004208043A1 US 20040208043 A1 US20040208043 A1 US 20040208043A1 US 41873403 A US41873403 A US 41873403A US 2004208043 A1 US2004208043 A1 US 2004208043A1
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- Prior art keywords
- data
- pins
- memory chip
- reset
- stored
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
Definitions
- the present invention relates to an FeRAM memory chip, as well as to a method of operating such a memory chip.
- FeRAM memory chips are now in common use.
- One beneficial characteristic of these chips is that they are non-volatile, which means that if the power supply to the FeRAM memory chip is removed, the data stored in the device is not deleted. This characteristic is in contrast to certain other memory devices, such as DRAM devices, which forget their data as soon as the power supply is switched off.
- a typical application for a non-volatile memory chip is a RAM memory for a low power device.
- Such devices may have an unreliable power supply, or may be designed to stop drawing power whenever possible, such as when the device is not in use.
- the advantage of providing a low-power device with a non-volatile memory chip as the RAM memory is that, after a power down, any code (e.g. operating system program code or application programs) stored in the non-volatile memory is not deleted. This means that then the device is powered-up again, the system would be in the same state as before the power off. The device does not have to be rebooted for example.
- the overall structure of a known FeRAM memory chip is shown schematically in FIG. 1.
- the device has a number of pins including pins which are referred to in this document as data transfer pins.
- the data transfer pins are for receiving data to be stored and address data indicating where in the memory the data should be stored, and for outputting data stored in the memory cells.
- the pins for receiving the data and addresses (“input pins”) are different pins from the pins which output data (“output pins”).
- output pins the same pins may act as input or as output pins at different times.
- the memory chip shown in FIG. 1 includes two input pins marked as “data” and “address”.
- the pins “data” and “address” respectively receive data to be stored in the device and an address at which that data is to be stored
- the memory chip further includes control pins (not shown), such as a chip enable (CE) pin, or an output enable (OE) pin, for receiving commands.
- CE chip enable
- OE output enable
- the memory chip has an address decoder which includes a word line address decoder (not shown) which uses the address to obtain a word line address (corresponding to a row of the memory array), and a column decoder 1 which uses the address to obtain the column address.
- a word line address decoder not shown
- a column decoder 1 which uses the address to obtain the column address.
- the memory chip further includes for each column a corresponding sense amplifier 3 . Only one of these is shown in FIG. 1 for simplicity.
- the column address selects a sense amplifier 3
- the word line address (row) selects one cell of the corresponding column.
- the sense amplifier 3 is arranged to read data out of the selected cell of the selected column, or to write data to into the selected cell of the selected column, based on the a clock signal received through a clock pin (not shown) of the memory chip and the control signals (e.g. CE, OE).
- the columns are each made up of two chain cell arrays 5 , and the sense amplifiers 3 are shared between those two adjacent chain cell arrays 5 .
- word lines addresses 0 , . . . 255 might be in the left hand chain cell array 5
- word line addresses 256 - 511 might be in the right hand chain cell array 5 .
- many other possible arrangements are known.
- a FeRAM memory chip should include a reset unit for recognising an externally applied reset signal.
- the reset unit is arranged upon recognition of this reset signal to initiate an operation in which at least a portion, and preferably all, of the FeRAM memory is erased.
- the reset unit may be arranged to perform this reset operation as a sequence of reset steps in which respective sections of the memory are reset. In this way, the peak power required to perform the reset operation may be kept to an acceptably low level. A balance can be achieved between the speed of the reset and the power requirement.
- One option is for the memory chip to have a dedicated pin input for receiving a reset signal, so that the reset unit can initiate the reset operation upon measuring that a voltage on this pin reaches a certain level.
- reset unit Another option, which does not require a dedicated pin and therefore which is cheaper to implement, is for the reset unit to be sensitive to a reset signal applied as voltages on one or more pins which are otherwise used for inputting data to the memory chip.
- the reset signal may be that the voltage on one of the input pins is set to a voltage which is not encountered in the usual operation of the chip (e.g. a voltage which is higher than the voltages which are encountered on that input pin when data is transmitted to the memory chip for storage).
- the reset signal may be a pattern of voltages over a period of time which is not encountered in the usual operation of the memory chip, such as a non-standard sequence of voltages on the clock-pin.
- the reset signal may be any “soft entry” command.
- “Soft entry” is a sequence of non-standard clock signals and commands (e.g. a series of “1” and “0”s on selected data pins) applied to the memory chip's data pins.
- the chip according to the present invention may have a soft entry decoder unit for recognising a limited set of commands (e.g. that the voltage power input V DC is the default V DC plus 30 mV) as a reset signal.
- a further aspect of the invention provides a method of using a memory chip as defined above, comprising supplying a reset signal to the memory chip, whereby the reset unit initiates an operation in which at least a portion, and preferably all, of the FeRAM memory is erased.
- a further expression of the invention is a device, such as a low power device, comprising a memory chip as defined above, and a processor operative to store data in the memory chip and retrieve the stored data from the memory chip, the processor further being operative to generate a reset signal and transmit it to the memory chip.
- FIG. 1 shows an access scheme of a known FeRAM device
- FIG. 2 shows an access scheme of a FeRAM device according to the invention.
- FIG. 2 an embodiment of the invention is shown schematically. Elements which correspond to those of the known memory chip shown in FIG. 1 are labelled by the same reference numerals, and these elements have the same construction as in known memory chips.
- the embodiment has an additional pin, for receiving an input signal “reset”, and that the embodiment additionally has a reset unit 7 , which is arranged to receive the “reset” signal and also the “data” and “Addr” signals.
- the memory chip of FIG. 2 shares with the memory chip of FIG. 1 a number of features which are not shown in either diagram, such as pins for receiving commands (e.g. read/write), clock pins, and one or more output pins for outputting stored data when the chip is commanded to do so.
- the output pin(s) may be the same as the input pin(s) which receive the data. That is, these pin(s) have a different function according to whether the memory chip is commanded to read or write data.
- the reset unit 7 is arranged in normal operation to output the signals “data” and “Addr” which it receives, unchanged, respectively to the shared sense amplifier 3 and the column decoder 1 .
- the operation of the shared sense amplifier 3 and the chain cell array 5 is as in the known embodiment.
- the reset unit 7 registers this fact and initiates an operation in which the outputs it sends to the column decoder 1 and the shared sense amplifier 3 are such as to set the values of the data stored in the memory cells to be set to one or more predetermined values (e.g. all set to the same value, i.e. all “0” or all “1”).
- This operation is a sequence of steps, each performed on a respective clock cycle. For example, at each cycle a respective set of banks (word lines) may be opened in parallel, and the predetermined values can be written to the cells.
- the reset signal does not require a dedicated pin.
- the reset cell 7 may be arranged to recognise the reset signal from a pattern of voltage values (applied all at once, or over a period of time) on one or more of the pins through which the FeRAM receives the inputs “data” and/or “Addr” and/or the clock signal (this input is not shown in FIG. 1 or 2 ).
Abstract
Description
- The present invention relates to an FeRAM memory chip, as well as to a method of operating such a memory chip.
- FeRAM memory chips are now in common use. One beneficial characteristic of these chips is that they are non-volatile, which means that if the power supply to the FeRAM memory chip is removed, the data stored in the device is not deleted. This characteristic is in contrast to certain other memory devices, such as DRAM devices, which forget their data as soon as the power supply is switched off.
- A typical application for a non-volatile memory chip is a RAM memory for a low power device. Such devices may have an unreliable power supply, or may be designed to stop drawing power whenever possible, such as when the device is not in use. The advantage of providing a low-power device with a non-volatile memory chip as the RAM memory is that, after a power down, any code (e.g. operating system program code or application programs) stored in the non-volatile memory is not deleted. This means that then the device is powered-up again, the system would be in the same state as before the power off. The device does not have to be rebooted for example.
- Another application of non-volatile memory chips is as simple data storage devices.
- The overall structure of a known FeRAM memory chip is shown schematically in FIG. 1. The device has a number of pins including pins which are referred to in this document as data transfer pins. The data transfer pins are for receiving data to be stored and address data indicating where in the memory the data should be stored, and for outputting data stored in the memory cells. In some memory chips the pins for receiving the data and addresses (“input pins”) are different pins from the pins which output data (“output pins”). However, in other memory chips the same pins may act as input or as output pins at different times.
- The memory chip shown in FIG. 1 includes two input pins marked as “data” and “address”. The pins “data” and “address” respectively receive data to be stored in the device and an address at which that data is to be stored The memory chip further includes control pins (not shown), such as a chip enable (CE) pin, or an output enable (OE) pin, for receiving commands.
- The memory chip has an address decoder which includes a word line address decoder (not shown) which uses the address to obtain a word line address (corresponding to a row of the memory array), and a
column decoder 1 which uses the address to obtain the column address. - The memory chip further includes for each column a
corresponding sense amplifier 3. Only one of these is shown in FIG. 1 for simplicity. The column address selects asense amplifier 3, and the word line address (row) selects one cell of the corresponding column. Thesense amplifier 3 is arranged to read data out of the selected cell of the selected column, or to write data to into the selected cell of the selected column, based on the a clock signal received through a clock pin (not shown) of the memory chip and the control signals (e.g. CE, OE). - As shown in FIG. 1, the columns are each made up of two
chain cell arrays 5, and thesense amplifiers 3 are shared between those two adjacentchain cell arrays 5. For example, word lines addresses 0, . . . 255 might be in the left handchain cell array 5, and word line addresses 256-511 might be in the right handchain cell array 5. However, many other possible arrangements are known. - The present inventors have appreciated that, although non-volatile FeRAM memory devices are certainly useful, there are circumstances in which it is not desirable that the data stored inside the memory should be retained.
- For example, following a system failure, it would be helpful if all system components could be reset into a defined state, rather than simply returning to their state before the system failure. Furthermore, if a low power device experiences an application failure such as a crash, it would be desirable if the data in the memory (which may have led to the crash) is removed, and if the application program itself is erased from the memory. Furthermore, in cases in which the memory chip is used for storage only, a deliberate erasal of the memory may be desirable when the device is used in an environment with only limited operating system capabilities.
- For this reason, the present invention proposes in general terms that a FeRAM memory chip should include a reset unit for recognising an externally applied reset signal. The reset unit is arranged upon recognition of this reset signal to initiate an operation in which at least a portion, and preferably all, of the FeRAM memory is erased.
- The reset unit may be arranged to perform this reset operation as a sequence of reset steps in which respective sections of the memory are reset. In this way, the peak power required to perform the reset operation may be kept to an acceptably low level. A balance can be achieved between the speed of the reset and the power requirement.
- There are various forms which the reset signal may take in different embodiments of the invention.
- One option is for the memory chip to have a dedicated pin input for receiving a reset signal, so that the reset unit can initiate the reset operation upon measuring that a voltage on this pin reaches a certain level.
- Another option, which does not require a dedicated pin and therefore which is cheaper to implement, is for the reset unit to be sensitive to a reset signal applied as voltages on one or more pins which are otherwise used for inputting data to the memory chip.
- For example, the reset signal may be that the voltage on one of the input pins is set to a voltage which is not encountered in the usual operation of the chip (e.g. a voltage which is higher than the voltages which are encountered on that input pin when data is transmitted to the memory chip for storage).
- Alternatively, the reset signal may be a pattern of voltages over a period of time which is not encountered in the usual operation of the memory chip, such as a non-standard sequence of voltages on the clock-pin.
- More generally, the reset signal may be any “soft entry” command. “Soft entry” is a sequence of non-standard clock signals and commands (e.g. a series of “1” and “0”s on selected data pins) applied to the memory chip's data pins. As in some known memory chips, the chip according to the present invention may have a soft entry decoder unit for recognising a limited set of commands (e.g. that the voltage power input VDC is the default VDC plus 30 mV) as a reset signal.
- A further aspect of the invention provides a method of using a memory chip as defined above, comprising supplying a reset signal to the memory chip, whereby the reset unit initiates an operation in which at least a portion, and preferably all, of the FeRAM memory is erased.
- A further expression of the invention is a device, such as a low power device, comprising a memory chip as defined above, and a processor operative to store data in the memory chip and retrieve the stored data from the memory chip, the processor further being operative to generate a reset signal and transmit it to the memory chip.
- Preferred features of the invention will now be described, for the sake of illustration only, with reference to the following figures in which:
- FIG. 1 shows an access scheme of a known FeRAM device; and
- FIG. 2 shows an access scheme of a FeRAM device according to the invention.
- Turning to FIG. 2, an embodiment of the invention is shown schematically. Elements which correspond to those of the known memory chip shown in FIG. 1 are labelled by the same reference numerals, and these elements have the same construction as in known memory chips.
- The differences between the known FeRAM memory chip and the embodiment shown in FIG. 2 are that the embodiment has an additional pin, for receiving an input signal “reset”, and that the embodiment additionally has a
reset unit 7, which is arranged to receive the “reset” signal and also the “data” and “Addr” signals. It should be understood that the memory chip of FIG. 2 shares with the memory chip of FIG. 1 a number of features which are not shown in either diagram, such as pins for receiving commands (e.g. read/write), clock pins, and one or more output pins for outputting stored data when the chip is commanded to do so. Note that in certain embodiments the output pin(s) may be the same as the input pin(s) which receive the data. That is, these pin(s) have a different function according to whether the memory chip is commanded to read or write data. - The
reset unit 7 is arranged in normal operation to output the signals “data” and “Addr” which it receives, unchanged, respectively to the sharedsense amplifier 3 and thecolumn decoder 1. In this case, the operation of the sharedsense amplifier 3 and thechain cell array 5 is as in the known embodiment. - However, if the reset signal is sent to the
reset unit 7, thereset unit 7 registers this fact and initiates an operation in which the outputs it sends to thecolumn decoder 1 and the sharedsense amplifier 3 are such as to set the values of the data stored in the memory cells to be set to one or more predetermined values (e.g. all set to the same value, i.e. all “0” or all “1”). This operation is a sequence of steps, each performed on a respective clock cycle. For example, at each cycle a respective set of banks (word lines) may be opened in parallel, and the predetermined values can be written to the cells. - Although the invention has been described in relation to a single embodiment only, many variations are possible within the scope of the invention as will be clear to a skilled reader. For example, as mentioned above, the reset signal does not require a dedicated pin. Instead the
reset cell 7 may be arranged to recognise the reset signal from a pattern of voltage values (applied all at once, or over a period of time) on one or more of the pins through which the FeRAM receives the inputs “data” and/or “Addr” and/or the clock signal (this input is not shown in FIG. 1 or 2).
Claims (9)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/418,734 US6807084B1 (en) | 2003-04-17 | 2003-04-17 | FeRAM memory device |
CNB2004100327359A CN100354974C (en) | 2003-04-17 | 2004-04-16 | Feram memory device |
DE102004019230A DE102004019230A1 (en) | 2003-04-17 | 2004-04-16 | FeRAM memory device |
SG200402197A SG121882A1 (en) | 2003-04-17 | 2004-04-16 | Feram memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/418,734 US6807084B1 (en) | 2003-04-17 | 2003-04-17 | FeRAM memory device |
Publications (2)
Publication Number | Publication Date |
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US6807084B1 US6807084B1 (en) | 2004-10-19 |
US20040208043A1 true US20040208043A1 (en) | 2004-10-21 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US10/418,734 Expired - Fee Related US6807084B1 (en) | 2003-04-17 | 2003-04-17 | FeRAM memory device |
Country Status (4)
Country | Link |
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US (1) | US6807084B1 (en) |
CN (1) | CN100354974C (en) |
DE (1) | DE102004019230A1 (en) |
SG (1) | SG121882A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI611407B (en) * | 2012-10-23 | 2018-01-11 | 三星電子股份有限公司 | Nonvolatile memory, memory system, computer system, and operating method of nonvolatile memory |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2005025878A (en) * | 2003-07-03 | 2005-01-27 | Toshiba Corp | Semiconductor memory device and its testing method |
KR100672996B1 (en) | 2005-02-07 | 2007-01-24 | 삼성전자주식회사 | Memory apparatus with meta data stored fram |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5539279A (en) * | 1993-06-23 | 1996-07-23 | Hitachi, Ltd. | Ferroelectric memory |
US6370058B1 (en) * | 2000-01-21 | 2002-04-09 | Sharp Kabushiki Kaisha | Non-volatile semiconductor memory device and system LSI including the same |
US6473828B1 (en) * | 1998-07-03 | 2002-10-29 | Nec Corporation | Virtual channel synchronous dynamic random access memory |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5703804A (en) * | 1996-09-26 | 1997-12-30 | Sharp Kabushiki K.K. | Semiconductor memory device |
EP1187140A3 (en) * | 2000-09-05 | 2002-09-11 | Matsushita Electric Industrial Co., Ltd. | Method for driving semiconductor memory |
JP4233205B2 (en) * | 2000-09-28 | 2009-03-04 | シャープ株式会社 | Reset device, semiconductor integrated circuit device, and semiconductor memory device |
-
2003
- 2003-04-17 US US10/418,734 patent/US6807084B1/en not_active Expired - Fee Related
-
2004
- 2004-04-16 CN CNB2004100327359A patent/CN100354974C/en not_active Expired - Fee Related
- 2004-04-16 DE DE102004019230A patent/DE102004019230A1/en not_active Ceased
- 2004-04-16 SG SG200402197A patent/SG121882A1/en unknown
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5539279A (en) * | 1993-06-23 | 1996-07-23 | Hitachi, Ltd. | Ferroelectric memory |
US6473828B1 (en) * | 1998-07-03 | 2002-10-29 | Nec Corporation | Virtual channel synchronous dynamic random access memory |
US6370058B1 (en) * | 2000-01-21 | 2002-04-09 | Sharp Kabushiki Kaisha | Non-volatile semiconductor memory device and system LSI including the same |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI611407B (en) * | 2012-10-23 | 2018-01-11 | 三星電子股份有限公司 | Nonvolatile memory, memory system, computer system, and operating method of nonvolatile memory |
Also Published As
Publication number | Publication date |
---|---|
DE102004019230A1 (en) | 2005-01-27 |
US6807084B1 (en) | 2004-10-19 |
CN100354974C (en) | 2007-12-12 |
CN1542846A (en) | 2004-11-03 |
SG121882A1 (en) | 2006-05-26 |
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