US20040222190A1 - Plasma processing method - Google Patents

Plasma processing method Download PDF

Info

Publication number
US20040222190A1
US20040222190A1 US10/813,012 US81301204A US2004222190A1 US 20040222190 A1 US20040222190 A1 US 20040222190A1 US 81301204 A US81301204 A US 81301204A US 2004222190 A1 US2004222190 A1 US 2004222190A1
Authority
US
United States
Prior art keywords
gas
holes
mask
etching
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/813,012
Inventor
Katsumi Horiguchi
Kenji Yamamoto
Kiyohito Ito
Keiichi Kanno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Assigned to TOKYO ELECTRON LIMITED reassignment TOKYO ELECTRON LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HORIGUCHI, KATSUMI, ITO, KIYOHITO, KANNO, KEIICHI, YAMAMOTO, KENJI
Publication of US20040222190A1 publication Critical patent/US20040222190A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor
    • H01J37/32532Electrodes
    • H01J37/32568Relative arrangement or disposition of electrodes; moving means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching

Abstract

In a plasma processing method, a silicon layer of an object to be processed is etched by using a plasma of a processing gas introduced into an airtight processing chamber through a patterned mask. The processing gas contains a gaseous mixture of HBr, O2 and SiF4 and, additionally, one or both of SF6 gas and NF3 gas; and a gas containing C and F is further added to the processing gas.

Description

    FIELD OF THE INVENTION
  • The present invention relates to a plasma processing method. [0001]
  • BACKGROUND OF THE INVENTION
  • Recently, along with the trend for high density and high integration of semiconductor devices, there has been increased demand for forming holes (or grooves) having a high aspect ratio. Moreover, it is preferable that such a hole has a smooth sidewall approximately perpendicular to a surface of an opening thereof. [0002]
  • A plasma etching is conventionally used in forming holes having a high aspect ratio in a silicon layer, by adopting certain etching conditions exemplified below. [0003]
  • Conventionally, a plasma etching process is carried out by setting the temperature of a lower electrode on which an object to be processed is mounted in a hermetically sealed processing chamber to be not greater than, e.g., 60° C., and the inner pressure thereof to be lower than or equal to 150 mTorr, wherein a gaseous mixture of HBr, NF[0004] 3 and O2 gases or HBr, SF6 and O2 gases is used as a processing gas.
  • U.S. Pat. No. 5,423,941 also discloses a method for performing an etching by using a gaseous mixture of HBr gas, SiF[0005] 4 gas, SF6 gas, and O2 gas containing He gas as a processing gas in an airtightly sealed processing chamber, wherein the pressure in the processing chamber is set to be between 50 and. 150 mTorr and a magnetic field of a magnitude smaller than or equal to 100 Gauss is applied perpendicular to an electric field.
  • In the above etching methods, since HBr gas and/or SiF[0006] 4 gas is included in the processing gas, a protective layer is formed on an inner sidewall of a hole. Accordingly, it is possible to vertically form a hole having an opening diameter smaller than or equal to 1 μm according to the size of a mask.
  • In the aforementioned conventional methods, however, deposits (e.g., SiBr[0007] xOy x and y being the combination ratios) may be accumulated at the openings of the mask. If an opening diameter of the mask is large, such deposits do not affect the etching process. However, when an opening diameter of the mask becomes smaller than or equal to about 0.2 μm, the deposits accumulated at the openings of the mask may present a hampering effect on a fine patterning of the hole.
  • In case the deposits are accumulated at the opening of the mask, the opening diameter becomes narrower and, consequently, an apparent aspect ratio of the hole increases. An increase in the aspect ratio results in a decrement of an etching rate and, further, a deterioration in the throughput. In addition, if the aspect ratio is greater than or equal to, e.g., 50, it becomes difficult to etch a bottom portion of the hole, so that the hole may not attain a designed depth. [0008]
  • SUMMARY OF THE INVENTION
  • It is, therefore, a primary object of the present invention to provide a new and improved plasma processing method capable of forming fine holes (or grooves) of a high aspect ratio in a silicon layer with a high etching rate. [0009]
  • In accordance with the present invention, there is provided a plasma processing method including the step of: etching a silicon layer of an object to be processed by employing a patterned mask and by using a plasma of a processing gas introduced into an airtight processing chamber, the processing gas containing a gaseous mixture in which one or both of SF[0010] 6 gas and NF3 gas are added to HBr gas, O2 gas and SiF4 gas, wherein a gas containing C and F is further added to the processing gas. Due to an effect of the gas containing C and F, deposits are prevented from being accumulated at an opening of the mask and, further, accumulated deposits are removed. Accordingly, it is possible to form a deep hole in a silicon layer even in case a diameter of a opening of the mask is very small.
  • The gas containing C and F may be a gaseous mixture having a combination of one or more gases selected from the group consisting of CF[0011] 4 gas, C4F8 gas, C5F8 gas, C4F6 gas, CHF3 gas and CH2F2 gas.
  • In order to prevent deposits from being accumulated at the opening of the mask or remove accumulated deposits, it is preferable to set the flow rate of the gas containing C and F added to the processing gas to be smaller than or equal to, e.g., 10 sccm. Further, the added amount of the gas containing C and F is preferably controlled according to the material or thickness of the mask or the etched amount of the silicon layer. Furthermore, the patterned mask preferably includes at least an oxide layer containing silicon. [0012]
  • In accordance with the present invention, the addition of the gas containing C and F to the processing gas may be initiated either from the beginning or at a certain stage of the etching process of the silicon layer of the object to be processed and then terminated before or continued until the end of the etching process. The time period of supplying the gas containing C and F is preferably set based on, e.g., the accumulating state of deposits at the opening of the mask and an opening diameter of a hole or an opening width of a groove formed by the etching. Accordingly, deposits are prevented from being accumulated at the opening of the mask. Further, even if the deposits are excessively accumulated thereat, it is possible to appropriately remove the deposits. [0013]
  • Especially, in case the opening diameter of the hole or the opening width of the groove formed by the etching is smaller than or equal to about 0.2 μm, the accumulation of deposits at the opening thereof has been problematic. Since, however, the accumulation of deposits at the opening of the mask is suppressed in accordance with the present invention, it is possible to form deep holes or deep grooves in a silicon layer even in case the opening diameter of the holes or the opening width of the grooves is smaller than or equal to about 0.2 μm. [0014]
  • Further, as used in this specification, 1 mTorr and 1 sccm correspond to (1×10[0015] 3×101325/760) Pa and (1×10−6/60) m3/sec, respectively.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments, given in conjunction with the accompanying drawings, in which: [0016]
  • FIG. 1 shows a schematic cross sectional view illustrating a plasma processing apparatus in accordance with a preferred embodiment of the present invention; [0017]
  • FIG. 2 describes a schematic cross sectional view of an object to be processed before a mask for use in etching a silicon layer is formed; [0018]
  • FIG. 3 provides a schematic cross sectional view of the object to be processed after the mask for use in etching the silicon layer is formed; [0019]
  • FIGS. 4A to [0020] 4C represent schematic cross sectional views of the object to be processed, showing accumulating states of deposits at openings of the mask;
  • FIGS. 5A to [0021] 5C offer schematic cross sectional views of the object to be processed, showing states of holes formed on a silicon layer; and
  • FIG. 6 presents a graph indicating a relationship between an opening diameter of the mask and an etching time.[0022]
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • A preferred embodiment of the plasma processing method in accordance with the present invention will now be described in detail with reference to the accompanying drawings. In the specification and the accompanying drawings, like reference numerals will be given to like parts having substantially the same functions, and redundant description thereof will be omitted. [0023]
  • FIG. 1 is a schematic cross sectional view showing the structure of a [0024] plasma processing apparatus 100 in accordance with a preferred embodiment of the present invention. A processing chamber 102 of the plasma processing apparatus 100 is made of, e.g., aluminum having an alumite processed (anodizing processed) surface covered by a plate member (not shown) made of quartz. Further, the processing chamber 102 is grounded as illustrated in FIG. 1.
  • Disposed inside the [0025] processing chamber 102 is a lower electrode 104 also serving as a susceptor for mounting thereon an object to be processed, e.g., a semiconductor wafer W. The lower electrode 104 can be vertically moved by an elevating shaft (not shown).
  • Formed under a bottom surface of the [0026] lower electrode 104 are a quartz member 105 to be an insulating material and a conductive member 107 being in contact with a bellows 109. The bellows 109 made of, e.g., stainless steel, is in contact with the processing chamber 102. Accordingly, the conductive member 107 is grounded via the bellows 109 and the processing chamber 102. Further, a bellows cover 111 is installed in such a way that it surrounds the quartz member 105, the conductive member 107 and the bellows 109.
  • An [0027] electrostatic chuck 110 connected with a high voltage DC power supply 108 is installed to a mounting surface of the lower electrode 104 on which the object to be processed is mounted. Further, a focus ring 112 is provided around the electrostatic chuck 110.
  • Connected with the [0028] lower electrode 104 via a matching unit 116 is a dual system of a high frequency power supply, i.e., a first high frequency power supply 118 and a second high frequency power supply 138. The frequency of a power outputted from the first high frequency power supply 118 (hereinafter, referred to as a first frequency) is set to be higher than that from the second high frequency power supply 138 (hereinafter, referred to as a second frequency). Accordingly, in the plasma processing apparatus 100, dual high frequency power is applied to the lower electrode 104 and each frequency power is controlled independently. Consequently, it is possible to avoid a phenomenon in which sidewalls of the holes formed on the object to be processed are eroded into a curved shape, i.e., the so-called bowing phenomenon, thereby providing holes having comparatively appropriate shapes.
  • It is preferable to set the first frequency to be greater than or equal to, e.g., 27.12 MHz. Especially, in case a magnetic field is not generated in a processing space, it is preferable to set the first frequency to be greater than or equal to 27.12 MHz. On the other hand, in case a [0029] magnet 130 and the like are provided to generate a magnetic field in the processing space, the first frequency can be set at 13.56 MHz, as will be further described later. This is because the density of a plasma can be increased to augment an etching rate of silicon by the magnetic field. In this case, the second frequency is preferably set at, e.g., 3.2 MHz.
  • Provided at a top portion of the [0030] processing chamber 102 is an upper electrode 124 grounded therethrough. Further, formed at the upper electrode 124 is a plurality of gas inlet holes 126 for introducing a processing gas. Each of the gas inlet holes 126 is connected with a gas supply source (not shown), and the processing gas is introduced into a processing space 122 via the gas inlet holes 126.
  • Provided outside the [0031] processing chamber 102 is a magnet 130 for generating a horizontal magnetic field to the processing space 122. Due to the magnet 130, a magnetic field of a magnitude of 170 Gauss is generated at a central portion of the object to be processed in the processing space 122. In case the magnitude of the magnetic field generated by the magnet 130 is greater than or equal to 170 Gauss, a high frequency power supply may be configured to provide a single high frequency of, e.g., 13.56 MHz.
  • Installed at a lower portion of the [0032] processing chamber 102 is an exhaust opening 128 connected with an exhaust system (not shown) such as a vacuum pump and the like. Due to such configuration, an inner space of the processing container 102 can be maintained at a certain vacuum level.
  • Hereinafter, operation of the [0033] plasma processing apparatus 100 will be described with reference to FIGS. 1 and 2. FIG. 2 shows a schematic cross sectional view of an object to be processed 200 before being etched.
  • As the object to be processed [0034] 200, a semiconductor wafer W having a diameter of, e.g., 200 mm, is used. As shown in FIG. 2, formed on a surface of the semiconductor wafer W is a resist layer 202 on which holes having a diameter of 150 nm are patterned by a photolithography process. Further, a silicon dioxide film layer (SiO2 film) 204, e.g., a CVD oxide film, having a thickness ranging from about 700 to 2200 nm is formed beneath the resist layer 202. Furthermore, a silicon nitride film layer (SiN film) 206 having a thickness of about 200 nm is formed beneath the silicon dioxide film layer 204. In some cases, a silicon dioxide film layer (SiO2 film) having a thickness smaller than or equal to a few nm may be formed as a gate insulating film between the silicon nitride film layer 206 and a silicon (Si) layer 210.
  • An etching process is performed on the above-described object to be processed [0035] 200 by using the resist layer 202 as a mask, to thereby provide patterning of the silicon dioxide film layer 204 and the silicon nitride film layer 206. Thereafter, the resist layer 202 is removed, as illustrated in FIG. 3. The silicon dioxide film layer 204 and the silicon nitride film layer 206 serve as a mask for etching the silicon layer 210.
  • Next, the object to be processed [0036] 300 having as the mask the silicon dioxide film layer 204 and the silicon nitride film layer 206 that are patterned in a predetermined shape is loaded into the processing chamber 102 via a loading/unloading opening (not shown) and then mounted on the lower electrode 104. After the processing chamber 102 is evacuated through the exhaust opening 128 by using the vacuum pump (not shown), a processing gas is introduced from the gas supply source (not shown) into the processing chamber 102 via the gas inlet holes 126.
  • As for the processing gas, a gaseous mixture in which CF[0037] 4 gas is added to HBr gas, NF3 gas, SiF4 gas and O2 gas is used. Further, it is possible to use SF6 gas instead of NF3 gas. The flow rate of each gas in the processing gas is controlled as follows: HBr gas ranging from 100 to 600 sccm; O2 gas, from 1 to 60 sccm; SiF4 gas, from 2 to 50 sccm; SF6 gas, from 1 to 60 sccm; NF3 gas, from 2 to 80 sccm; and CF4 gas, from 5 to 50 sccm.
  • By controlling the flow rate of the processing gas at a predetermined value, the pressure in the [0038] processing chamber 102 can be set under a predetermined level, e.g., 200 mTorr, while setting the temperature of each unit at a predetermined temperature. Moreover, the first high frequency power having the first frequency is applied from the first high frequency power supply 118 to the lower electrode 104 via the matching unit 116 and, at the same time, the second high frequency power having the second high frequency is applied from the second frequency power supply 138 thereto via the matching unit 116.
  • As described above, the first frequency is preferably chosen to be greater than or equal to 27.12 MHz. Therefore, the first frequency involved herein is set to be 40.0 MHz. In the meantime, the second frequency is set to be 3.2 MHz. In addition, the output power of the first high [0039] frequency power supply 118 is controlled at a value ranging, e.g., from 400 to 600 W, and that of the second high frequency power supply 138 is controlled at a value ranging, e.g., from 100 to 800 W.
  • By supplying the high frequency powers having different frequencies of the dual system to the [0040] lower electrode 104, the dissociation of the processing gas is facilitated and, therefore, the silicon layer 210 can be etched more efficiently.
  • When the [0041] plasma processing apparatus 100 is ready as described above, the etching process is performed on an object to be processed 300. The object to be processed 300 is etched by using the silicon dioxide film layer 204 and the silicon nitride film layer 206 (hereinafter, referred to as ‘mask material’ together) as the mask material, thereby forming holes on the silicon layer 210, as illustrated in FIG. 3.
  • Hereinafter, plasma etching conditions in accordance with this embodiment will be described with reference to Table 1. Table 1 lists the etching conditions applied to a case where holes having a diameter of 0.15 μm (design value) are formed in the [0042] silicon layer 210. Temperatures of the upper electrode 124, an inner wall of the processing chamber 102 and the lower electrode 104 are commonly set at 80° C., 60° C. and 120° C., respectively.
    TABLE 1
    Pressure at backside Etch-
    Power (W) Processing gas of substrate (Torr) ing
    Pressure 40.0 3.2 flow rate (sccm) Central Peripheral time
    Step (mTorr) HHz MHZ HBr NF3 CF4 SiF4 O2 portion portion (sec)
    BT 50 400 100 150 2.5 0 0 1 13 15 10
    S1 125 700 500 220 32 0 0 14 13 15 60
    S2 200 600 500 270 35 0 0 3 10 15 20
    S3 200 600 800 270 35 0 10 18 10 15 240
    S4 200 600 800 270 35 10 10 18 10 15 240
  • The plasma etching method (plasma processing method) in accordance with this embodiment includes a plurality of steps, as shown in Table 1. [0043]
  • First of all, a breakthrough (BT) step is performed to remove a silicon dioxide film layer generated due to a natural oxidation on a surface of the [0044] silicon layer 210 to be etched (see FIG. 3).
  • Next, a first step S[0045] 1 is performed to form holes having, e.g., a funnel shape, wherein a large inner diameter is provided at an upper portion and a small inner diameter is provided at a lower portion. In order to form such shaped holes during the first step, the silicon layer 210 is etched such that the diameter of the holes becomes smaller as the etching progresses in the depth direction. At this time, the depth of the hole is, e.g., 1.5 μm. The first step S1 can be divided into a number of steps and different etching conditions can be applied to each step. In such a case, it is possible to form holes having more conformal shapes to design values.
  • Thereafter, a second step S[0046] 2, a third step S3 and a fourth step S4 are performed to further etch the silicon layer 210. After going through these steps, the holes formed in the silicon layer 210 can have a depth determined by the design value. As can be seen from Table 1, different etching conditions are applied to second, third and fourth steps S2, S3 and S4. By forming the holes while varying the etching conditions as described above, it is possible to obtain holes having a final shape corresponding to the design value.
  • As a result of performing the aforementioned steps, the holes each having a predetermined diameter and depth are formed in the object to be processed [0047] 300.
  • In case of forming fine holes in the [0048] silicon layer 210, the etching rate of silicon is deteriorated as the holes grow toward a lower portion of the silicon layer 210. Therefore, in the plasma etching method in accordance with this embodiment, the output of the high frequency power supply 138 is increased during the latter steps of the etching process, i.e., the third and the fourth steps S3 and S4. Accordingly, the ion energy in the plasma increases such that the etching rate at a lower deep portion of the silicon layer 210 can be prevented from being deteriorated. Further, during the third and the fourth steps S3 and S4, the flow rate of O2 gas is increased to accelerate an accumulation of a protective layer at a top portion of the mask material. As a result, a high etching selectivity can be obtained. Furthermore, it is preferable that the timing of increasing the output power of the high frequency power supply 138 be substantially equal to that of increasing the flow rate of O2 gas.
  • Hereinafter, deposits accumulated at the openings of the mask material during the etching process of the [0049] silicon layer 210 will be described with reference to FIGS. 4A to 4C.
  • In the plasma etching method in accordance with this embodiment, a gaseous mixture in which CF[0050] 4 gas is added to HBr gas, NF3 gas (or SF6 gas), SiF4 gas and O2 gas is used as the processing gas. Among them, HBr gas or SiF4 gas in particular contributes to the forming of a protective layer on inner walls of the holes. Since the protective layer is formed on the inner walls of the holes, it is possible in this embodiment to vertically and highly precisely form fine holes having an opening diameter of 0.15 μm (design value) in the silicon layer 210, as defined in the mask.
  • However, as the etching for forming holes in the [0051] silicon layer 210 progresses, deposits (e.g., SiBrxOy, x and y being combination ratios) become excessively accumulated on the opening portions of the mask.
  • FIG. 4A shows a schematic cross sectional view of the object to be processed (a lower portion of the [0052] silicon layer 210 is omitted), when the third step S3 is completed, i.e., 330 seconds after the start of the etching process. Formed in the silicon layer 210 are holes 210 a and 210 b at this point not reaching a final depth thereof. Further, since the etching has been performed for 330 seconds, the silicon dioxide film layer 204 that used to have a thickness of DO before the etching has a reduced thickness of Da (the remaining amount of silicon dioxide film layer mask), as measured with respect to shoulder portions at the entrance of the holes.
  • Additionally, as illustrated in FIG. 4A, [0053] deposits 310 are accumulated at the openings of the mask. Accordingly, the opening diameter Ra1 103 nm of the mask is narrower than the uppermost opening diameter Ra2 133 nm of the holes 210 a and 210 b.
  • FIG. 4B represents a schematic cross sectional view of the object to be processed (a lower portion of the [0054] silicon layer 210 is omitted) when the entire etching process has been completed by finishing the fourth step S4, i.e., 570 seconds after the start of the etching process. The etching process has been continuously performed on the silicon layer 210 for 240 seconds since the object to be processed reached the state illustrated in FIG. 4A and, accordingly, the thickness of the shoulder portion of the silicon dioxide film layer 204 formed at the entrance of the holes is reduced from Da to Db.
  • As shown in FIG. 4B, the [0055] deposits 310 are accumulated at the openings of the mask even after the entire etching process has been completed. However, the amount of the accumulated deposits 310 is small, and the opening diameter Rb1 127 nm of the mask that is measured when the entire etching process has been completed is wider than the opening diameter Ra1 103 nm of the mask that is measured when 330 seconds has passed since the start of the etching process.
  • Under the etching conditions in accordance with this embodiment, during the fourth step S[0056] 4, CF4 gas is introduced into the processing chamber 102. Due to the CF4 gas, accumulation of deposits at the openings of the mask is suppressed. Hereinafter, effects of the CF4 gas will be described in detail.
  • FIG. 4C shows as in FIG. 4B, a schematic cross sectional view of the object to be processed obtained after the entire etching process has been completed by finishing the fourth step S[0057] 4, i.e., 570 seconds after the start of the etching process. However, the object to be processed illustrated in FIG. 4C is different from that shown in FIG. 4B in that the etching process of FIG. 4C is performed thereon by using a processing gas that does not contain CF4 gas. Specifically, during the etching process of the object to be processed shown in FIG. 4b, CF4 gas having a flow rate of 10 sccm was introduced into the processing chamber 102 in the fourth step S4 (see Table 1). On the other hand, while the object to be processed illustrated in FIG. 4C is etched, CF4 gas is not introduced into the processing chamber 102 during any steps of the etching process.
  • In other words, the difference between the etching conditions applied for obtaining the object to be processed illustrated in FIG. 4B and those for the object to be processed shown in FIG. 4C is whether or not the CF[0058] 4 gas is introduced into the processing chamber 102. As clearly can be seen by comparing FIG. 4B to FIG. 4C, there is a big difference in the amount of accumulated deposits between the case where the CF4 gas is added to the processing gas and the case where the CF4 gas is not added thereto.
  • In case the CF[0059] 4 gas is not added to the processing gas, the amount of the accumulated deposits 310 increases during a latter part of the etching process in which the holes are deeply formed. As a result, when the etching process is completed, the opening diameter Rc1 of the mask becomes very narrow, i.e., 108 nm, as shown in FIG. 4C.
  • On the other hand, in case the CF[0060] 4 gas is added to the processing gas, the amount of the deposits 310 accumulated at the openings of the mask is small, as illustrated in FIG. 4B when the entire etching process is completed. Moreover, the opening diameter Rb1 127 nm of the mask is wider than the opening diameter Rc1 108 nm of the mask that is measured in case the processing gas does not contain the CF4 gas. This means that in case the CF4 gas is added to the processing gas, while the silicon layer 210 is being etched during the latter part of the etching process in which the holes are deeply formed, the opening diameter of the mask is large.
  • On the other hand, the uppermost [0061] opening diameter Rb2 140 nm of the holes 210 a and 210 b which is measured in case the CF4 gas is added to the processing gas, is not considerably different from the uppermost opening diameter Rc2 139 nm of the holes 210 a and 210 b which is measured in case the CF4 gas is not added to the processing gas. That is, even if the CF4 gas is added to the processing gas, the inner diameter of the holes formed in the silicon layer 210 is not enlarged to thereby form appropriately shaped holes.
  • However, the thicknesses Db and Dc of the silicon [0062] dioxide film layer 204 formed at the entrance of the holes become different between the two cases where the CF4 gas is added and not added to the processing gas. By comparing FIG. 4B with FIG. 4C, it can be seen that the etching rate of the silicon dioxide film layer 204 included in the mask material increases in case the CF4 gas is added to the processing gas. Therefore, it is preferable to control the timing of introducing the CF4 gas into the processing chamber 102 and the flow rate thereof so that the silicon dioxide film layer 204 can remain at least until the etching process for forming holes on the silicon layer 210 is completed. The timing of introducing the CF4 gas into the processing chamber 102 and the flow rate thereof will be described later.
  • Hereinafter, the shapes of the holes formed on the [0063] silicon layer 210 by etching the silicon layer 210 under the etching conditions described in Table 1 will be described with reference to FIGS. 5A to 5C.
  • FIG. 5A corresponding to FIG. 4A depicts the shapes of the [0064] holes 210 a and 210 b formed in the depth direction when 330 seconds has passed since the beginning of the etching process. Further, FIG. 5B corresponding to FIG. 4B describes the shapes of the holes 210 a and 210 b formed in the depth direction when the entire etching process has been completed by finishing the fourth step S4 where the CF4 gas is introduced into the processing chamber 102, i.e., when 570 seconds has passed since the beginning, of the etching process. Furthermore, FIG. 5C corresponding to FIG. 4C indicates the shapes of the holes 210 a and 210 b formed in the depth direction when the entire etching process has been completed without introducing the CF4 gas into the processing chamber 102, i.e., 570 seconds after the beginning of the etching process. Additionally, in order to show the accurate shapes of the holes, FIGS. 5A to 5C represent the schematic cross sectional views of the objects to be processed that were cleaned by using a liquid chemical, e.g., hydrofluoric acid. Accordingly, protective layers formed on inner walls of the holes during the etching process or deposits accumulated at the openings of the mask material are not illustrated therein.
  • As shown in FIG. 5A, when 330 seconds has passed since the beginning of the etching process, the depth Dsa of the [0065] holes 210 a and 210 b reaches 5.37 μm. Besides, at this point, the uppermost opening diameter Rat of the holes 210 a and 210 b is 162 nm, and the diameter Rab of a bottom portion of the holes 210 a and 210 b is 127 nm.
  • When the etching process (the fourth step S[0066] 4) has been performed on the silicon layer 210 for 240 seconds after reaching the state shown in FIG. 5A obtained 330 seconds after the beginning of the etching process, the depth Dsb of the holes 210 a and 210 b reaches 7.81 μm, as shown in FIG. 5B. During the fourth step S4, the CF4 gas is introduced into the processing chamber 102.
  • In case the CF[0067] 4 gas is not introduced thereinto during the fourth step S4, the depth Dsc of the holes 210 a and 210 b merely reaches 7.65 μm, as illustrated in FIG. 5C.
  • As clearly can be seen by comparing FIG. 5B with FIG. [0068] 5C, the depth of the holes formed in the silicon layer 210 becomes different between the cases where the CF4 gas is added or not added to the processing gas. Such difference originates from the difference in the amounts of the deposits 310 accumulated at the openings of the mask.
  • As illustrated in FIG. 4C, in case the CF[0069] 4 gas is not added to the processing gas, the deposits 310 are excessively accumulated at the openings of the mask, thereby narrowing the opening diameter Rc1 of the mask. As a result, an apparent aspect ratio of the holes 210 a and 210 b being formed increases. Herein, the “apparent aspect ratio” is defined as “a depth of the holes/the opening diameter Rc1 of the mask”.
  • If the apparent aspect ratio increases, the etching is rate near a bottom portion of the [0070] holes 210 a and 210 b is remarkably deteriorated during the latter part of the etching process where the holes are deeply formed. Thus, it may be difficult to obtain a designed depth.
  • As shown in FIG. 4B, by adding the CF[0071] 4 gas to the processing gas, accumulation of deposits 310 at the openings of the mask is suppressed, thereby enlarging the opening diameter Rb1 of the mask. Accordingly, it is possible to avoid the deterioration of the etching rate near the bottom portion of the holes 210 a and 210 b during the latter part of the etching process where the holes are deeply formed, so that the desired depth of the holes can be obtained. In case the CF4 gas is added to the processing gas during the fourth step S4, the etching rate of the silicon layer 210 during the fourth step S4 is 610 nm/min, which is a favorable value in comparison with the etching rate of the silicon layer 210, i.e., 570 mm/min, that is measured in case the CF4 gas is not added to the processing gas.
  • Further, in case the CF[0072] 4 gas is added to the processing gas (FIG. 5B), the uppermost opening diameter Rbt of the holes 210 a and 210 b is 171 nm, and the diameter Rbb at the bottom of the holes 210 a and 210 b is 137 nm. On the other hand, in case the CF4 gas is not added to the processing gas (FIG. 5C), the uppermost opening diameter Rct of the holes 210 a and 210 b is 168 nm, and the diameter Rcb at the bottom of the holes 210 a and 210 b is 135 nm. In other words, even if the CF4 gas is added to the processing gas, the inner diameter of the holes formed on the silicon layer 210 is not enlarged.
  • Hereinafter, the timing of introducing CF[0073] 4 gas into the processing chamber 102 and the flow rate thereof will be described.
  • Table 2 indicates relationships between the flow rate of CF[0074] 4 gas introduced into the processing chamber 102 and the etching rate and the in-surface uniformity (uniformity of the etching rate in surface of a semiconductor wafer) of the silicon dioxide layer 204 of the mask material.
    TABLE 2
    CF4 gas flow rate Etching rate In-surface
    (sccm) (nm/min) uniformity (%)
    0 55.5 ±8.2
    5 70.4 ±15.9
    10 79.3 ±15.9
    30 117.6 ±9.6
    50 153.8 ±16.7
  • If the flow rate of CF[0075] 4 gas introduced into the processing chamber increases, the etching rate of the silicon dioxide layer 204 also increases. Meanwhile, values of the in-surface uniformity are nearly constant regardless of variations in the flow rates of CF4 gas. Therefore, it is preferable to set the flow rate of CF4 gas mainly considering the etching rate. Specifically, the flow rate thereof is controlled such that the silicon dioxide film layer 204 in the mask material is not completely consumed before the etching process for forming holes is completed. For example, it is preferable to control the flow rate of CF4 gas within the range from about 5 to about 50 sccm. Under the etching conditions in accordance with the preferred embodiment, the flow rate of CF4 gas is controlled to be maintained at about 10 sccm, as illustrated in Table 1.
  • Hereinafter, the timing of introducing the CF[0076] 4 gas into the processing chamber 102 and the period thereof in accordance with the preferred embodiment will be described with reference to FIG. 6. The period of introducing CF4 gas into the processing chamber 102 (the period of adding CF4 gas to the processing gas) can be set from the beginning to the end of the etching process, from the beginning to an intermediate stage of the etching process, or from a certain stage to the end of the etching process. Moreover, the CF4 gas can be introduced into the processing container 102 during a predetermined time period in the etching process. The timing of introducing CF4 gas into the processing container 102 and the period thereof are preferably determined based on the opening diameter or the depth of the holes 210 a and 210 b formed by the etching, the thickness of the silicon dioxide film layer 204 in the mask material, the types of the processing gas and the like.
  • The timing of introducing the CF[0077] 4 gas into the processing chamber 102 and the period thereof in the preferred embodiment will now be described. FIG. 6 shows a relationship between an etching time for forming the holes 210 a and 210 b in the silicon layer 210 and an opening diameter of the mask.
  • Referring to FIG. 6, there are illustrated a circle “◯” indicating an opening diameter of the mask, which is measured when the CF[0078] 4 gas is not added to the processing gas; a square “□” representing an opening diameter of the mask, which is measured when the CF4 gas is added to the processing gas from the beginning of the fourth step S4, i.e., 330 seconds after the beginning of the etching process; and a triangle “Δ” presenting an opening diameter of the mask, which is measured in case the CF4 gas is added to the processing gas from 90 seconds after the beginning of the etching process, i.e., in the middle of the third step S3. The introducing timing of CF4 gas represented by the square “□” in FIG. 6 corresponds to the etching conditions illustrated in Table 1.
  • According to the result represented by the circles “◯” in FIG. 6, a large amount of deposits is accumulated at the openings of the mask during a period spanning from 90 to 330 seconds of the etching time. After 330 seconds has passed since the beginning of the etching process, the amount of newly accumulated deposits is small. During the period spanning from 90 to 330 seconds of the etching time, the depth of the [0079] holes 210 a and 210 b is shallow yet whereas the etching rate of the silicon layer 210 is high, so that a large amount of deposits is considered to be accumulated at the openings of the mask.
  • Therefore, CF[0080] 4 gas can be added to the processing gas from 90 seconds after the beginning of the etching process (or from the beginning of the etching process) till 330 seconds after the beginning of the etching process (or to the end of the etching process), as plotted by the triangle “Δ” instead of the square “□” representing the timing of introducing CF4 gas corresponding to the etching conditions of Table 1. In this case, it is possible to suppress the accumulation of deposits itself at the openings of the mask.
  • Further, as plotted by the squares “□”, the deposits accumulated at the openings of the mask are etched and removed by the CF[0081] 4 gas that is added to the processing gas since 330 seconds after the beginning of the etching process when the amount of newly accumulated deposits at the openings of the mask becomes negligible.
  • By adding the CF[0082] 4 gas to the processing gas, the opening diameter of the mask is enlarged by about 20 nm in comparison with the case where the CF4 gas is not added thereto. Moreover, by controlling the timing of adding the CF4 gas to the processing gas, the effect of suppressing the accumulation of deposits at the openings of the mask and/or an effect of removing the deposits accumulated thereat can be achieved.
  • The timing of adding the CF[0083] 4 gas to the processing gas is preferably set when the opening diameter of the mask becomes narrow (e.g., smaller than or equal to about 110 nm) so as to deteriorate the etching rate of the silicon layer 210 or when deposits are excessively accumulated at the openings of the mask. Furthermore, it is preferable to set the timing of stopping the addition of CF4 gas to the processing gas to coincide with the time when the accumulation of the deposits at the openings of the mask is stopped substantially (e.g., 330 seconds after the beginning of the etching process). Moreover, it is also possible to continuously add the CF4 gas until the end of the etching process. In this case, however, the flow rate of CF4 gas should be controlled at an appropriate value such that, especially, the silicon dioxide film layer 204 is not completely consumed.
  • As described above, in accordance with the plasma etching method of the preferred embodiment, an appropriate amount of CF[0084] 4 gas is added to the processing gas having a mixture of HBr gas, NF3 gas (or SF6 gas), SiF4 gas and O2 gas at an appropriate timing. Due to an effect of the CF4 gas, the accumulation of deposits at the openings of the mask is suppressed and, further, accumulated deposits can be removed. Accordingly, it is possible to form deep holes in the silicon layer 210 even in case the diameter of the openings of the mask is very small.
  • Although the present invention has been described with respect to the preferred embodiments where holes are formed in a silicon layer by the etching, the present invention can be applied to a case where grooves are formed in a silicon layer. Similar effects can be obtained when forming either grooves or holes in a wafer, e.g., a silicon layer. Further, in case the grooves are formed in the wafer, an opening diameter of the aforementioned holes corresponds to an opening width of the grooves. [0085]
  • The preferred embodiments of the present invention have been described where the CF[0086] 4 gas is added to the processing gas. However, in lieu of the CF4 gas, a CF-based gas such as C4F8 gas, C5F8 gas and C4F6 gas and the like or CHF-based gas such as CHF3 gas, CH2F2 gas and the like can be added to the processing gas. Similar effects of preventing deposits from being accumulated at the openings of the mask material can be obtained by employing any of the aforementioned gases.
  • In addition, although the plasma etching method in accordance with the preferred embodiments of the invention uses a processing gas containing either the SF[0087] 6 gas or the NF3 gas, the present invention is not limited thereto. Even if a processing gas containing both the SF6 gas and the NF3 gas is used, similar effects can be obtained.
  • While the invention has been shown and described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes and modification may be made without departing from the spirit and scope of the invention as defined in the following claims. [0088]

Claims (8)

What is claimed is:
1. A plasma processing method comprising the step of:
etching a silicon layer of an object to be processed by employing a patterned mask and by using a plasma of a processing gas introduced into an airtight processing chamber, containing a gaseous mixture of HBr, O2 and SiF4 and, additionally, one or both of SF6 and NF3,
wherein a gas containing C and F is further added to the processing gas.
2. The plasma processing method of claim 1, wherein the gas containing C and F is one or more gases selected from the group consisting of CF4, C4F8, C5F8, C4F6, CHF3 and CH2F2.
3. The plasma processing method of claim 1, wherein the gas containing C and F is added to the processing gas in a middle of the etching step.
4. The plasma processing method of claim 3, wherein the gas containing C and F is continuously added to the processing gas until the end of the etching step.
5. The plasma processing method of claim 1, wherein the gas containing C and F is added to the processing gas for a period of time during the etching step.
6. The plasma processing method of claim 1, wherein the timing of starting to add the gas containing C and F to the processing gas is determined according to the opening diameter of holes or the opening width of grooves formed by the etching step.
7. The plasma processing method of claim 1, wherein the opening diameter of holes or the opening width of grooves formed by the etching step is smaller than or equal to about 0.2 μm.
8. The plasma processing method of claim 1, wherein the patterned mask includes at least an oxide layer containing silicon.
US10/813,012 2003-03-31 2004-03-31 Plasma processing method Abandoned US20040222190A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003-096631 2003-03-31
JP2003096631A JP4184851B2 (en) 2003-03-31 2003-03-31 Plasma processing method

Publications (1)

Publication Number Publication Date
US20040222190A1 true US20040222190A1 (en) 2004-11-11

Family

ID=33408627

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/813,012 Abandoned US20040222190A1 (en) 2003-03-31 2004-03-31 Plasma processing method

Country Status (2)

Country Link
US (1) US20040222190A1 (en)
JP (1) JP4184851B2 (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060128093A1 (en) * 2004-12-15 2006-06-15 Keiichi Takenaka Method of manufacturing semiconductor device
US20070197041A1 (en) * 2006-02-17 2007-08-23 Tokyo Electron Limited Processing method and plasma etching method
WO2009085672A2 (en) * 2007-12-21 2009-07-09 Lam Research Corporation Fabrication of a silicon structure and deep silicon etch with profile control
US20100105208A1 (en) * 2008-10-23 2010-04-29 Lam Research Corporation Silicon etch with passivation using chemical vapor deposition
US20100105209A1 (en) * 2008-10-23 2010-04-29 Lam Research Corporation Silicon etch with passivation using plasma enhanced oxidation
US20130344702A1 (en) * 2011-03-04 2013-12-26 Tokyo Electron Limited Method of etching silicon nitride films
US20140213060A1 (en) * 2013-01-29 2014-07-31 Chia-Ling Kao Method of patterning a low-k dielectric film
US20160322230A1 (en) * 2015-04-30 2016-11-03 Tokyo Electron Limited Etching method and etching apparatus
CN110021524A (en) * 2017-12-27 2019-07-16 东京毅力科创株式会社 Engraving method
TWI685014B (en) * 2015-04-30 2020-02-11 日商東京威力科創股份有限公司 Etching method and etching device
DE102020103408A1 (en) 2020-01-17 2021-07-22 Taiwan Semiconductor Manufacturing Co., Ltd. WAFER ETCHING PROCESS AND METHOD OF IT

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006135029A (en) * 2004-11-04 2006-05-25 Sharp Corp Dry etching device
JP4512529B2 (en) * 2005-07-15 2010-07-28 住友精密工業株式会社 Etching method and etching apparatus
JP4653603B2 (en) * 2005-09-13 2011-03-16 株式会社日立ハイテクノロジーズ Plasma etching method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5423941A (en) * 1992-11-18 1995-06-13 Nippondenso Co., Ltd. Dry etching process for semiconductor
US6531068B2 (en) * 1998-06-12 2003-03-11 Robert Bosch Gmbh Method of anisotropic etching of silicon
US6743727B2 (en) * 2001-06-05 2004-06-01 International Business Machines Corporation Method of etching high aspect ratio openings
US6833079B1 (en) * 2000-02-17 2004-12-21 Applied Materials Inc. Method of etching a shaped cavity

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5423941A (en) * 1992-11-18 1995-06-13 Nippondenso Co., Ltd. Dry etching process for semiconductor
US6531068B2 (en) * 1998-06-12 2003-03-11 Robert Bosch Gmbh Method of anisotropic etching of silicon
US6833079B1 (en) * 2000-02-17 2004-12-21 Applied Materials Inc. Method of etching a shaped cavity
US6743727B2 (en) * 2001-06-05 2004-06-01 International Business Machines Corporation Method of etching high aspect ratio openings

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060128093A1 (en) * 2004-12-15 2006-06-15 Keiichi Takenaka Method of manufacturing semiconductor device
US20070197041A1 (en) * 2006-02-17 2007-08-23 Tokyo Electron Limited Processing method and plasma etching method
US7902078B2 (en) * 2006-02-17 2011-03-08 Tokyo Electron Limited Processing method and plasma etching method
TWI469211B (en) * 2007-12-21 2015-01-11 Lam Res Corp Fabrication of a silicon structure and deep silicon etch with profile control
WO2009085672A2 (en) * 2007-12-21 2009-07-09 Lam Research Corporation Fabrication of a silicon structure and deep silicon etch with profile control
US20090184089A1 (en) * 2007-12-21 2009-07-23 Lam Research Corporation Fabrication of a silicon structure and deep silicon etch with profile control
WO2009085672A3 (en) * 2007-12-21 2009-09-03 Lam Research Corporation Fabrication of a silicon structure and deep silicon etch with profile control
US9865472B2 (en) 2007-12-21 2018-01-09 Lam Research Corporation Fabrication of a silicon structure and deep silicon etch with profile control
US9330926B2 (en) 2007-12-21 2016-05-03 Lam Research Corporation Fabrication of a silicon structure and deep silicon etch with profile control
US20100105208A1 (en) * 2008-10-23 2010-04-29 Lam Research Corporation Silicon etch with passivation using chemical vapor deposition
US20100105209A1 (en) * 2008-10-23 2010-04-29 Lam Research Corporation Silicon etch with passivation using plasma enhanced oxidation
US8598037B2 (en) 2008-10-23 2013-12-03 Lam Research Corporation Silicon etch with passivation using plasma enhanced oxidation
US9018098B2 (en) 2008-10-23 2015-04-28 Lam Research Corporation Silicon etch with passivation using chemical vapor deposition
US8173547B2 (en) 2008-10-23 2012-05-08 Lam Research Corporation Silicon etch with passivation using plasma enhanced oxidation
US20130344702A1 (en) * 2011-03-04 2013-12-26 Tokyo Electron Limited Method of etching silicon nitride films
US20140213060A1 (en) * 2013-01-29 2014-07-31 Chia-Ling Kao Method of patterning a low-k dielectric film
US8987139B2 (en) * 2013-01-29 2015-03-24 Applied Materials, Inc. Method of patterning a low-k dielectric film
US20160322230A1 (en) * 2015-04-30 2016-11-03 Tokyo Electron Limited Etching method and etching apparatus
US9865471B2 (en) * 2015-04-30 2018-01-09 Tokyo Electron Limited Etching method and etching apparatus
TWI685014B (en) * 2015-04-30 2020-02-11 日商東京威力科創股份有限公司 Etching method and etching device
CN110021524A (en) * 2017-12-27 2019-07-16 东京毅力科创株式会社 Engraving method
DE102020103408A1 (en) 2020-01-17 2021-07-22 Taiwan Semiconductor Manufacturing Co., Ltd. WAFER ETCHING PROCESS AND METHOD OF IT
US11177137B2 (en) 2020-01-17 2021-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer etching process and methods thereof

Also Published As

Publication number Publication date
JP4184851B2 (en) 2008-11-19
JP2004304029A (en) 2004-10-28

Similar Documents

Publication Publication Date Title
US9960031B2 (en) Plasma processing apparatus and plasma processing method
JP4579611B2 (en) Dry etching method
US7186661B2 (en) Method to improve profile control and N/P loading in dual doped gate applications
US11380551B2 (en) Method of processing target object
US7682980B2 (en) Method to improve profile control and N/P loading in dual doped gate applications
JP2019533910A (en) Removal method for high aspect ratio structures
WO2011125605A1 (en) Mask pattern formation method and manufacturing method for semiconductor device
US20130344702A1 (en) Method of etching silicon nitride films
US20060021704A1 (en) Method and apparatus for etching Si
US8609549B2 (en) Plasma etching method, plasma etching apparatus, and computer-readable storage medium
US20040222190A1 (en) Plasma processing method
US20080020583A1 (en) Plasma etching method and computer-readable storage medium
US10886138B2 (en) Substrate processing method and substrate processing apparatus
US20070287297A1 (en) Plasma etching method, plasma processing apparatus, control program and computer readable storage medium
US8298960B2 (en) Plasma etching method, control program and computer storage medium
US11043391B2 (en) Etching method and etching processing apparatus
US7667281B2 (en) Method for hard mask CD trim
US20030235993A1 (en) Selective etching of low-k dielectrics
KR20000049010A (en) Plasma etching method
WO2003056617A1 (en) Etching method and plasma etching device
US7604750B2 (en) Method for fabricating semiconductor device
US10651077B2 (en) Etching method
US11201062B2 (en) Method and apparatus for processing a substrate
US10438774B2 (en) Etching method and plasma processing apparatus
JP2002134472A (en) Etching method, etching apparatus, and method of manufacturing semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: TOKYO ELECTRON LIMITED, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HORIGUCHI, KATSUMI;YAMAMOTO, KENJI;ITO, KIYOHITO;AND OTHERS;REEL/FRAME:015171/0735

Effective date: 20040323

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION