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Número de publicaciónUS20040232407 A1
Tipo de publicaciónSolicitud
Número de solicitudUS 10/391,126
Fecha de publicación25 Nov 2004
Fecha de presentación17 Mar 2003
Fecha de prioridad20 Dic 1999
También publicado comoUS6461918, US6534825, US7625793, US20020190282, US20060024890
Número de publicación10391126, 391126, US 2004/0232407 A1, US 2004/232407 A1, US 20040232407 A1, US 20040232407A1, US 2004232407 A1, US 2004232407A1, US-A1-20040232407, US-A1-2004232407, US2004/0232407A1, US2004/232407A1, US20040232407 A1, US20040232407A1, US2004232407 A1, US2004232407A1
InventoresDaniel Calafut
Cesionario originalFairchild Semiconductor Corporation
Exportar citaBiBTeX, EndNote, RefMan
Enlaces externos: USPTO, Cesión de USPTO, Espacenet
Power MOS device with improved gate charge performance
US 20040232407 A1
Resumen
A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor with an improved gate structure. The gate structure includes a first portion of a first conductivity type for creating electron flow from the source to the drain when a charge is applied to the gate. The gate structure includes a second portion of a second conductivity type having a polarity that is opposite a polarity of the first conductivity type, for decreasing a capacitance charge under the gate. A second structure for decreasing a capacitance under the gate includes an implant region in the semiconductor substrate between a channel region, where the implant region is doped to have a conductivity opposite the channel region.
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Reclamaciones(24)
What is claimed is:
1. A method of fabricating a gate structure of a DMOS device, comprising the steps of:
forming a polysilicon gate on a portion of a semiconductor substrate;
implanting a dopant of a first conductivity type into the polysilicon gate;
masking the polysilicon gate to define an alternation region within the gate; and
implanting a dopant of a second conductivity type into the alternation region, where the second conductivity type has an electrical polarity opposite a polarity of the first conductivity type.
2. The method of claim 1, wherein the step of forming a polysilicon gate further comprises the steps of:
growing a dielectric layer on the semiconductor substrate;
depositing a polysilicon layer on the dielectric layer; and
masking the polysilicon layer to define a polysilicon gate.
3. The method of claim 1, wherein the step of implanting a dopant of a second conductivity type further comprises diffusing the dopant of the second conductivity type to drive the dopant to an outer boundary of the alternation region.
4. The method of claim 1, wherein the polarity of the first conductivity type is n-type and the polarity of the second conductivity type is p-type.
5. The method of claim 1, wherein the polysilicon gate overlies a channel region in the semiconductor substrate and extends at least partially over a source formed in the substrate, and wherein an extent of the alternation region corresponds to a boundary between the channel region and an accumulation area.
6. A gate of a semiconductor device, comprising:
a polysilicon gate structure overlying a channel region in a semiconductor substrate and extending at least partially over a source formed in the substrate adjacent the channel region, the polysilicon gate structure having a first portion being of a first conductivity type and a second portion being of a second conductivity type defining an alternation region.
7. The device as in claim 6, wherein an extent of the alternation region substantially corresponds to a boundary between the channel region and an accumulation area in the semiconductor substrate.
8. The device as in claim 6, wherein an electrical polarity of the first conductivity type is opposite an electrical polarity of the second conductivity type.
9. The device as in claim 8, wherein the first portion of the polysilicon gate is doped with n-type impurities.
10. The device as in claim 9, wherein the second portion of the polysilicon gate is doped with p-type impurities.
11. The device as in claim 10, wherein the p-type impurities are boron ions, and wherein the n-type impurities are ions selected from the group comprised of arsenic and phosphorous.
12. The device as in claim 6, further comprising a polycide layer disposed over the polysilicon gate structure.
13. A method of fabricating a gate structure of a DMOS device, comprising the steps of:
forming a trench in a semiconductor substrate;
lining the trench with a dielectric layer;
forming a first polysilicon gate portion to an intermediate depth of the trench;
implanting a dopant of a first conductivity type into the first gate portion;
forming a second polysilicon gate portion in the trench over the first gate structure to a level substantially equal to a top surface of the silicon substrate; and
implanting a dopant of a second conductivity type into the second gate portion.
14. The method of claim 13, further comprising the steps of:
etching away an intermediate portion of the second polysilicon gate portion down to the first polysilicon gate portion; and
forming a polycide strap layer over the first polysilicon gate layer in the intermediate portion and on opposite side walls of the second polysilicon gate portion.
15. The method of claim 14, further comprising the step of depositing a conductive material in the intermediate portion to the level substantially equal to the top surface of the silicon substrate.
16. A composite gate structure in a trench transistor, comprising:
a trench extending a selected depth from a top surface of a semiconductor substrate;
a conformal dielectric layer lining the trench;
a first gate portion disposed over the dielectric layer and extending from the bottom to an intermediate depth of the trench, the first gate portion having a first conductivity type; and
a second gate portion disposed over the first gate portion and the dielectric layer, and extending from the intermediate depth to the top surface, the second gate portion having a second conductivity type that is of an opposite polarity from the first conductivity type.
17. The gate structure of claim 16, further comprising a polycide layer disposed on two side portions of the second gate portion, and over a mid-portion of the first gate portion.
18. The gate structure of claim 16, wherein the first conductivity type is p-type and the second conductivity type is n-type.
19. The gate structure of claim 16, wherein the first gate portion is formed by implanting a dopant of the first conductivity type into polysilicon comprising the first gate portion.
20. The gate structure of claim 16, wherein the second gate portion is formed by implanting a dopant of the second conductivity type into polysilicon comprising the second gate portion.
21. The gate structure of claim 17, wherein the two side portions of the second gate portion are formed by etching away a mid-portion of the second gate portion.
22. The gate structure of claim 16, wherein the intermediate depth substantially corresponds to a boundary between a source region and an epitaxial layer in the substrate.
23. A semiconductor device, comprising:
a channel region of a first conductivity type formed by diffusing a dopant of the first conductivity type into a substrate having a second conductivity type;
a gate dielectric disposed on the substrate; and
an implant region of a second conductivity type formed by diffusing a dopant of the first conductivity type under the gate dielectric, the second conductivity type having a polarity opposite a polarity of the first conductivity type.
24. The semiconductor device of claim 23, wherein the gate dielectric conforms to a trench in the substrate.
Descripción
BACKGROUND OF THE INVENTION

[0001] The present invention relates to field-effect transistors, in particular double-diffused metal-oxide-semiconductor (“DMOS”) transistors, and their method of manufacture.

[0002] A DMOS transistor is a type of field-effect transistor (“FET”) that can be used as a power transistor, that is, a transistor that is used to switch or control relatively large amounts of electrical power compared to a transistor that might be used in a logic circuit application. Power transistors might operate between 1-1000 volts, or higher, and might carry from several tenths of an amp to several amps of current, or higher. Power MOSFETs are designed to operate under conditions that would destroy conventional MOSFETs, or accelerate their failure.

[0003] Design of DMOS transistors presents challenges over other conventional MOS transistor devices, in particular relating to the structure of the channel and drain regions. FIGS. 1 and 2 illustrate a conventional trench DMOS transistor 100 and planar DMOS transistor 200, respectively. FIG. 1 shows a semiconductor substrate 102 with a trench 110 formed to a predetermined depth into the substrate. At the bottom of the substrate is an n+ drain region 120. Above the drain is an epitaxial layer 125 doped to a lighter degree of the same conductivity as the drain region. Overlying the epitaxial region is a channel region 105 implanted with a dopant having a polarity that is opposite the substrate and epitaxial regions. As illustrated in FIG. 1, the dopant profile ranges from a lesser degree to a greater degree away from the trench, to where a concentration of dopant forms a body region.

[0004] Formed near the surface of the substrate on either side of the trench are source regions 130, implanted with a dopant of the same conductivity type as the drain. Source and drain regions of the transistor shown in FIG. 1 are illustrated as n+, the channel region as p−, and a body region as p+. It should be readily apparent to a person skilled in the art that the polarity of the conductivity type for the transistor structure could be reversed. A dielectric layer 112 lines the trench. Filling the trench over the dielectric layer is a gate 114, which is typically made of polysilicon material doped to a similar conductivity type as the source and drain regions.

[0005] In operation, a charge applied to the gate creates a channel for electron migration across a channel 132 alongside the trench between the sources 130 and the epitaxial region 125, and flowing to the drain 120. The charge applied to the gate also forms an accumulation area 134 in the epitaxial layer under the trench, where electrons accumulate.

[0006]FIG. 2 illustrates a conventional planar DMOS transistor 200 fabricated on a semiconductor substrate 202. An n+ drain region lies at the bottom of the substrate. Overlying the drain is an n− epitaxial layer 225. Source regions 230 are formed of an implant of n+ dopants into an area just below the top surface of the substrate. Surrounding each source region underneath are P-type channel regions 205, which form a channel 232 between the source and the epitaxial layer. At least partially overlying each source region is a dielectric layer 212. Coextensively overlying the dielectric layer is a polysilicon gate 214 implanted with dopants of the same conductivity type as the source regions.

[0007] A charge applied to the gate causes electrons to flow from the sources, across the channels to the epitaxial region, and then down to the drain. Because of the uniform charge on the gate, an accumulation of electrons forms at the surface in the epitaxial layer just below the gate, between the channel regions, in an accumulation area 234.

[0008] An important design issue for both trench and planar DMOS transistors is the gate charge required to drive the gate of the MOSFET to a specific voltage. FIG. 3 illustrates an ideal gate charge curve for a conventional DMOS transistor. In a particular range, denoted as the Miller Q range, additional charge on the gate is insufficient to overcome certain parasitic capacitance that arise during operation. Several important ones of the parasitic capacitance are labeled in FIGS. 1 and 2. A capacitance between the gate and the source, Cgs, forms in the area where the gate overlaps the source. A gate-to-drain capacitance, Cgd, forms between the gate and the accumulation region, where electrons accumulate as a current path is formed from the channel region to the drain.

[0009] The capacitance Cgd is also known as the “Miller capacitance.” The Miller capacitance is an effective build-up of capacitative charge which must be overcome in order to bias the transistor to a particular voltage, as shown in FIG. 3. Increasing the gate charge has adverse effects. Transistor switching speed is significantly reduced where a larger gate charge is required. Further, the failure rate of transistors subject to higher gate charge is increased. Thus, it is desired to minimize the Miller capacitance over a range of charge, so as to reduce the gate charge and enhance transistor switching speed, efficiency, and improve failure rates.

[0010] One method of reducing the Miller capacitance is shown in U.S. Pat. No. 5,879,994, which describes a process and structure to apply a non-uniform gate dielectric layer, where a thicker oxide is applied over the accumulation area, and a thinner oxide is formed over the inversion channel area. The extra-thick oxide, or “terrace oxide” over the region where the Miller capacitance occurs, has some limitations. First, for planar DMOS transistors, alignment of the terrace oxide is difficult to achieve, and adds significantly to the costs of manufacturing the devices. Being easily misaligned, transistors formed with a terrace oxide have substantially lower yields. The difficulty with which to build a nonuniform dielectric layer exists in trench DMOS structures as well.

[0011] An alternative approach for reducing the Miller capacitance begins by considering voltage-dependent capacitance characteristics of MOS devices under various gate bias conditions. FIG. 4 shows a well-known CV curve for a conventional MOS device. At the extremes of the applied gate voltage |Vg|, the capacitance value maintains a constant value that depends only on the thickness of the dielectric (assumed to be SiO2, although not limited herein as such). This is due to a layer of mobile charge, at the extreme points on the curve, which causes the interface between the dielectric and the silicon substrate to effectively become a second plate of a capacitor.

[0012] As the gate voltage approaches a value known as the “flat band” voltage, as viewed from the accumulation side, the capacitance begins to decrease until a point called the “threshold” voltage is reached. This point is reached when the mobile charge distribution near the SiO2—Si interface transitions from accumulation to inversion. Beyond the threshold voltage Vt, the area immediately around the SiO2—Si interface is said to be inverted and there is again a layer of mobile charge, albeit of opposite polarity. In this range the MOS capacitance is limited by the gate oxide thickness.

[0013] Close to the threshold Vt, there is a point Cmin that represents the lowest value of capacitance for a given gate bias voltage in conventional MOS devices. However, a novel DMOS structure could be made so as to shift Cmin to as near the Vgs value range for the Miller region shown in FIG. 3. This would lower the capacitance within the Miller range, and effectively decrease the range of charge needed to overcome the Miller capacitance.

SUMMARY OF THE INVENTION

[0014] The present invention provides a method of fabricating a gate structure of a DMOS device. The fabrication method includes the steps of forming a polysilicon gate on a portion of a semiconductor substrate, implanting a dopant of a first conductivity type into the polysilicon gate, masking the polysilicon gate to define an alternation region within the gate, and implanting a dopant of a second conductivity type into the alternation region, where the second conductivity type has an electrical polarity opposite a polarity of the first conductivity type.

[0015] In another embodiment, the present invention provides a gate of a semiconductor device that includes a polysilicon gate structure overlying a channel region in a semiconductor substrate and extending at least partially over a source formed in the substrate adjacent the channel region. The polysilicon gate structure has a first portion being of a first conductivity type and a second portion being of a second conductivity type defining an alternation region. The second conductivity type has a polarity that is opposite a polarity of the first conductivity type.

[0016] In yet another embodiment, the present invention provides a method of fabricating a gate structure of a trench-type DMOS device. The method includes the steps of forming a trench in a semiconductor substrate, lining the trench with a dielectric layer, and forming a first polysilicon gate portion to an intermediate depth of the trench. The method further includes the steps of implanting a dopant of a first conductivity type into the first gate portion, forming a second polysilicon gate portion in the trench over the first gate structure to a level substantially equal to a top surface of the silicon substrate, and implanting a dopant of a second conductivity type into the second gate portion.

[0017] In still yet another embodiment, the present invention provides a composite gate structure in a trench transistor. The composite gate structure includes a trench extending a selected depth from a top surface of a semiconductor substrate, a conformal dielectric layer lining the trench, a first gate portion disposed over the dielectric layer and extending from the bottom to an intermediate depth of the trench, the first gate portion having a first conductivity type, and a second gate portion disposed over the first gate portion and the dielectric layer, and extending from the intermediate depth to the top surface, the second gate portion having a second conductivity type that is of an opposite polarity from the first conductivity type.

[0018] In still yet another embodiment, the present invention provides a semiconductor device having a channel region of a first conductivity type formed by diffusing a dopant of the first conductivity type into a substrate having a second conductivity type, a gate dielectric disposed on the substrate, and an implant region of a second conductivity type formed by diffusing a dopant of the second conductivity type under the gate dielectric, the second conductivity type having a polarity opposite a polarity of the first conductivity type.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019]FIG. 1 is a simplified cross section of a conventional trench DMOS transistor;

[0020]FIG. 2 is a simplified cross section of a conventional planar DMOS transistor;

[0021]FIG. 3 shows a gate charge-gate voltage (QV) curve for conventional MOS devices;

[0022]FIG. 4 is a capacitance-voltage curve (CV) for conventional MOS devices;

[0023]FIG. 5 is a simplified cross section of a trench DMOS transistor according to the present invention;

[0024]FIG. 6 is a simplified cross section of a planar DMOS transistor according to the present invention;

[0025]FIG. 7 is a simplified cross section of a trench DMOS transistor according to an alternative embodiment of the invention; and

[0026]FIG. 8 is a simplified cross section of a planar DMOS transistor according to an alternative embodiment of the invention.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS

[0027] The present invention provides a composite gate structure and methods of manufacture. The composite gate structure lowers gate to drain overlap capacitance and enhances switching speed and efficiency.

[0028]FIG. 5 is a simplified cross section of a trench DMOS transistor 300 according to an embodiment of the present invention. This example illustrates a n− channel device, however, it is understood that the invention could be applied to an p− channel device. The DMOS transistor is fabricated on an n+ silicon substrate 320 that serves as the drain of the DMOS transistor. An n− epitaxial layer 325 is grown on the substrate. A p− channel region 332 and a p+ body region 305 is formed over the n− epitaxial layer, which is considered part of the “substrate” for purposes of this description. The p− channel region and p+ body region are formed by implanting and diffusing dopants of a p-type conductivity.

[0029] A trench 310 is formed into the substrate to a predetermined depth, extending into the n− epitaxial layer. N+ source regions are implanted and diffused into both the p+ body region and the p− channel region, as well as adjacent to opposing sides of the trench at the top surface of the substrate. A gate oxide 312 is deposited over the walls of the trench, and a composite gate structure 311 fills the trench over the gate oxide.

[0030] According to the present invention, the gate structure is initially formed of a first portion 340, deposited into the trench, preferably from the bottom of the trench to a depth substantially corresponding to a depth of the n− epitaxial layer. According to one embodiment of the invention, the first portion is a polysilicon grown in the trench, and a p-type dopant is implanted directly into the trench into the polysilicon. The first portion is doped with a sufficient amount of implant to minimize the capacitance in the accumulation area for a certain predetermined voltage, such as 1 volt.

[0031] A second portion 350 of the gate structure is grown on top of the first portion. As illustrated in FIG. 5, the second portion is preferably etched in the middle down to the first portion. A conformal polycide layer 345 is then deposited over sides of the second portions and the top of the first portion. The polycide layer acts to short out the second portion, which would otherwise be floating, or basically cuts the portion in half to divide it into two isolated cells. An insulator 355 is then formed over the polycide layer in the trench, as well as over the top of the trench and at least partially extending over the source regions on the surface of the substrate. In a preferred embodiment, the insulator is boro-phospho silicon glass (BPSG), but also may be any material exhibiting generally nonconductive properties, such as silicon dioxide (SiO2). A metal layer 360 is formed on the top of the substrate and over the insulator, to provide electrical contact to the source regions.

[0032]FIG. 6 is a simplified cross section of a planar DMOS transistor 400 according to an embodiment of the present invention. The DMOS transistor is illustrated in FIG. 6 to show the composite gate structure in an n-channel transistor, but it is understood the invention could equally be applied to a p-channel transistor by reversing most of the polarities of the portions of the transistor.

[0033] An n+ region 420 serves as the drain of the planar DMOS transistor, just as in the trench case. An n− epitaxial layer 425 is grown on the n+ region. A p− channel region 405 and a p+ body region 407 are formed in the substrate in the epitaxial layer, and defining an accumulation area in the epitaxial layer therebetween. The channel and body regions are doped according to a predetermined doping profile that need not be further explained here. N+ source regions 430 are implanted and diffused into each of both the channel region and body region, as well as laterally under a gate structure 414. A gate oxide 412 is grown over the p-channel regions and the accumulation area.

[0034] The gate structure is formed over the gate oxide, preferably of a deposited and etched polysilicon layer. In a preferred embodiment, the polysilicon gate structure is implanted with a dopant of a first conductivity type to yield a polarity of n+. The gate structure is then masked, and a dopant of a second coductivity type, having a polarity that is opposite to the polarity of the first conductivity type, such as p+, for example, is implanted into the masked area. The p+ implanted material is then driven by diffusion to extend over an area with edges that substantially correspond to the extent of the accumulation area in the substrate.

[0035] The gate structure is then overlaid with an insulator 455, as discussed above. A metal layer 460 is then formed over the insulator and extended to the source regions 430, to provide electrical contact to the source regions. In operation, a charge applied to the gate will cause the greatest current flow between the sources through the channels, while charge in the accumulation area is repelled by the opposing polarity of the second conductivity type formed above it. In this way, the capacitative charge built up in the accumulation area is minimized within a given range of current.

[0036] In exemplary preferred embodiments of either the trench or planar DMOS structures, the n-type portion of the gate structure is formed by implanting ions of either arsenic or phosphorous into the polysilicon. The p-type portion of the gate structure is preferably formed by implanting ions of boron into the polysilicon. It should be understood, however, that other dopants may be implanted into the gate structure of the present invention to produce the desired conductivity profile, as described above with reference to FIGS. 5 and 6.

[0037] The present invention mitigates a build up of charge in the accumulation area proximate the gate structure of a DMOS transistor cell. In an alternative embodiment, as illustrated in FIGS. 7 and 8, the present invention provides an implant region into the epitaxial layer just underneath the gate between channel regions of two transistor cells. The alternative embodiment of the invention is adaptable to both the trench and planar configurations.

[0038] With reference to FIG. 7, there is illustrated a simplified cross section of a trench DMOS transistor 500, showing only the improved structure of the present invention. The DMOS transistor includes a trench 510 formed into a semiconductor substrate as described above in detail. At the bottom of the trench, in the area of the epitaxial layer where the accumulation area is formed, as shown in FIG. 1, an implant area 520 is formed as a lightly doped region. The implant area has a cross-sectional profile that surrounds the bottom of the trench at least within the n− epitaxial layer.

[0039] The implant area may be formed in one of several ways. Once the trench is formed, n-type ions may be implanted directly into the bottom of the trench, in a zero-angle ion implant step. Once implanted, the device is subjected to a drive step to diffuse the n-type ions out from the trench into the epitaxial layer. The drive step is preferably accomplished by annealing the transistor, then driving it at approximately 900-1500 degrees F, to diffuse the ion atoms. The resultant implant area preferably exhibits a Gaussian profile concentration, with the heaviest concentration of n-type ion. Or, the drive step can include multiple implant steps, until a desired implant profile is achieved.

[0040]FIG. 8 illustrates an implant area 620 in a planar DMOS transistor 600, to counteract the adverse effects of the Miller capacitance near a gate structure 614 of the transistor. The implant area is formed by an ion implant of n-type atoms into the accumulation area, between channel regions 632 underlying the n+ source regions. The implant area is preferably formed by masking an area of the semiconductor substrate surface, after p-type implant to form the channels. Then, the n-type material is implanted into the masked area. Next, the implant is driven to a desired profile, preferably extending to each channel region. The n-type material should have a higher density at the surface of the substrate. After the implant area is formed, the gate structure may be formed by employing conventional fabrication techniques.

[0041] While the above is a complete description of specific embodiments of the present invention, various modifications, variations, and alternatives may be employed. For example, although a silicon is given as an example of a substrate material, other materials may be used. The invention is illustrated for a two-transistor cell DMOS FET, but it could be applied to other DMOS structures, such as a multi-cell array of DMOS transistors on a single substrate. Similarly, implantation is given as an example of providing dopants to the substrate, but other doping methods, such as a gas or topical dopant source may be used to provide dopants for diffusion, depending on the appropriate mask being used. These and other alternatives may appear to those skilled in the art; hence, the scope of this invention should not be limited to the embodiments described, but are instead defined by the following claims.

Citas de patentes
Patente citada Fecha de presentación Fecha de publicación Solicitante Título
US3497777 *11 Jun 196824 Feb 1970Stanislas TesznerMultichannel field-effect semi-conductor device
US3564356 *24 Oct 196816 Feb 1971Tektronix IncHigh voltage integrated circuit transistor
US4003072 *1 Nov 197411 Ene 1977Sony CorporationSemiconductor device with high voltage breakdown resistance
US4011105 *15 Sep 19758 Mar 1977Mos Technology, Inc.Field inversion control for n-channel device integrated circuits
US4324038 *24 Nov 198013 Abr 1982Bell Telephone Laboratories, IncorporatedMethod of fabricating MOS field effect transistors
US4326332 *28 Jul 198027 Abr 1982International Business Machines Corp.Method of making a high density V-MOS memory array
US4445202 *2 Nov 198124 Abr 1984International Business Machines CorporationElectrically switchable permanent storage
US4568958 *3 Ene 19844 Feb 1986General Electric CompanyInversion-mode insulated-gate gallium arsenide field-effect transistors
US4579621 *25 Jun 19841 Abr 1986Mitsubishi Denki Kabushiki KaishaSelective epitaxial growth method
US4636281 *13 Jun 198513 Ene 1987Commissariat A L'energie AtomiqueProcess for the autopositioning of a local field oxide with respect to an insulating trench
US4638344 *15 Abr 198220 Ene 1987Cardwell Jr Walter TJunction field-effect transistor controlled by merged depletion regions
US4639761 *25 Oct 198527 Ene 1987North American Philips CorporationCombined bipolar-field effect transistor resurf devices
US4801986 *3 Abr 198731 Ene 1989General Electric CompanyVertical double diffused metal oxide semiconductor VDMOS device with increased safe operating area and method
US4821095 *12 Mar 198711 Abr 1989General Electric CompanyInsulated gate semiconductor device with extra short grid and method of fabrication
US4823176 *3 Abr 198718 Abr 1989General Electric CompanyVertical double diffused metal oxide semiconductor (VDMOS) device including high voltage junction exhibiting increased safe operating area
US4824793 *12 Nov 198725 Abr 1989Texas Instruments IncorporatedMethod of making DRAM cell with trench capacitor
US4893160 *13 Nov 19879 Ene 1990Siliconix IncorporatedMethod for increasing the performance of trenched devices and the resulting structure
US4914058 *29 Dic 19873 Abr 1990Siliconix IncorporatedGrooved DMOS process with varying gate dielectric thickness
US4990463 *29 Jun 19895 Feb 1991Kabushiki Kaisha ToshibaMethod of manufacturing capacitor
US4992390 *6 Jul 198912 Feb 1991General Electric CompanyTrench gate structure with thick bottom oxide
US5079608 *6 Nov 19907 Ene 1992Harris CorporationPower MOSFET transistor circuit with active clamp
US5105243 *25 Ago 198914 Abr 1992Kabushiki Kaisha ToshibaConductivity-modulation metal oxide field effect transistor with single gate structure
US5188973 *30 Abr 199223 Feb 1993Nippon Telegraph & Telephone CorporationMethod of manufacturing SOI semiconductor element
US5275961 *16 Jul 19924 Ene 1994Texas Instruments IncorporatedMethod of forming insulated gate field-effect transistors
US5275965 *25 Nov 19924 Ene 1994Micron Semiconductor, Inc.Trench isolation using gated sidewalls
US5281548 *28 Jul 199225 Ene 1994Micron Technology, Inc.Plug-based floating gate memory
US5294824 *31 Jul 199215 Mar 1994Motorola, Inc.High voltage transistor having reduced on-resistance
US5298761 *16 Jun 199229 Mar 1994Nikon CorporationMethod and apparatus for exposure process
US5300447 *29 Sep 19925 Abr 1994Texas Instruments IncorporatedMethod of manufacturing a minimum scaled transistor
US5300452 *27 Oct 19925 Abr 1994U.S. Philips CorporationMethod of manufacturing an optoelectronic semiconductor device
US5389815 *20 Abr 199314 Feb 1995Mitsubishi Denki Kabushiki KaishaSemiconductor diode with reduced recovery current
US5405794 *14 Jun 199411 Abr 1995Philips Electronics North America CorporationMethod of producing VDMOS device of increased power density
US5488010 *10 May 199430 Ene 1996International Business Machines CorporationMethod of fabricating sidewall charge-coupled device with trench isolation
US5592005 *31 Mar 19957 Ene 1997Siliconix IncorporatedPunch-through field effect transistor
US5593909 *6 Jun 199514 Ene 1997Samsung Electronics Co., Ltd.Method for fabricating a MOS transistor having an offset resistance
US5595927 *17 Mar 199521 Ene 1997Taiwan Semiconductor Manufacturing Company Ltd.Method for making self-aligned source/drain mask ROM memory cell using trench etched channel
US5597765 *17 Abr 199528 Ene 1997Siliconix IncorporatedMethod for making termination structure for power MOSFET
US5605852 *18 May 199525 Feb 1997Siliconix IncorporatedMethod for fabricating high voltage transistor having trenched termination
US5616945 *13 Oct 19951 Abr 1997Siliconix IncorporatedMultiple gated MOSFET for use in DC-DC converter
US5623152 *21 Nov 199522 Abr 1997Mitsubishi Denki Kabushiki KaishaInsulated gate semiconductor device
US5705409 *28 Sep 19956 Ene 1998Motorola Inc.Method for forming trench transistor structure
US5710072 *2 May 199520 Ene 1998Siemens AktiengesellschaftMethod of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells
US5714781 *26 Abr 19963 Feb 1998Nippondenso Co., Ltd.Semiconductor device having a gate electrode in a grove and a diffused region under the grove
US5717237 *17 Jun 199610 Feb 1998Taiwan Semiconductor Manufacturing Company, Ltd.PN junction floating gate EEPROM, flash EPROM device
US5719409 *6 Jun 199617 Feb 1998Cree Research, Inc.Silicon carbide metal-insulator semiconductor field effect transistor
US5744372 *1 Jun 199528 Abr 1998National Semiconductor CorporationFabrication of complementary field-effect transistors each having multi-part channel
US5877528 *3 Mar 19972 Mar 1999Megamos CorporationStructure to provide effective channel-stop in termination areas for trenched power transistors
US5879971 *28 Sep 19959 Mar 1999Motorola Inc.Trench random access memory cell and method of formation
US5879994 *15 Abr 19979 Mar 1999National Semiconductor CorporationSelf-aligned method of fabricating terrace gate DMOS transistor
US5894157 *27 Jun 199413 Abr 1999Samsung Electronics Co., Ltd.MOS transistor having an offset resistance derived from a multiple region gate electrode
US5895951 *5 Abr 199620 Abr 1999Megamos CorporationMOSFET structure and fabrication process implemented by forming deep and narrow doping regions through doping trenches
US5895952 *21 Ago 199620 Abr 1999Siliconix IncorporatedTrench MOSFET with multi-resistivity drain to provide low on-resistance
US5897343 *30 Mar 199827 Abr 1999Motorola, Inc.Method of making a power switching trench MOSFET having aligned source regions
US5897360 *17 Oct 199727 Abr 1999Nec CorporationManufacturing method of semiconductor integrated circuit
US6011298 *31 Dic 19964 Ene 2000Stmicroelectronics, Inc.High voltage termination with buried field-shaping region
US6015727 *8 Jun 199818 Ene 2000Wanlass; Frank M.Damascene formation of borderless contact MOS transistors
US6020250 *1 Abr 19981 Feb 2000International Business Machines CorporationStacked devices
US6034415 *8 Abr 19997 Mar 2000Xemod, Inc.Lateral RF MOS device having a combined source structure
US6037202 *18 Jul 199714 Mar 2000Motorola, Inc.Method for growing an epitaxial layer of material using a high temperature initial growth phase and a low temperature bulk growth phase
US6037628 *30 Jun 199714 Mar 2000Intersil CorporationSemiconductor structures with trench contacts
US6037632 *5 Nov 199614 Mar 2000Kabushiki Kaisha ToshibaSemiconductor device
US6040600 *11 Ago 199721 Mar 2000Mitsubishi Denki Kabushiki KaishaTrenched high breakdown voltage semiconductor device
US6048772 *4 May 199811 Abr 2000Xemod, Inc.Method for fabricating a lateral RF MOS device with an non-diffusion source-backside connection
US6049108 *28 Ago 199711 Abr 2000Siliconix IncorporatedTrench-gated MOSFET with bidirectional voltage clamping
US6051488 *14 Ene 199818 Abr 2000Fairchild Korea Semiconductor, Ltd.Methods of forming semiconductor switching devices having trench-gate electrodes
US6168983 *5 Feb 19992 Ene 2001Power Integrations, Inc.Method of making a high-voltage transistor with multiple lateral conduction layers
US6168996 *20 Ago 19982 Ene 2001Hitachi, Ltd.Method of fabricating semiconductor device
US6171935 *24 May 19999 Ene 2001Siemens AktiengesellschaftProcess for producing an epitaxial layer with laterally varying doping
US6174773 *27 Ago 199916 Ene 2001Fuji Electric Co., Ltd.Method of manufacturing vertical trench misfet
US6174785 *18 Jun 199816 Ene 2001Micron Technology, Inc.Method of forming trench isolation region for semiconductor device
US6184545 *14 Sep 19986 Feb 2001Infineon Technologies AgSemiconductor component with metal-semiconductor junction with low reverse current
US6184555 *30 Ene 19976 Feb 2001Siemens AktiengesellschaftField effect-controlled semiconductor component
US6188104 *27 Mar 199813 Feb 2001Samsung Electronics Co., LtdTrench DMOS device having an amorphous silicon and polysilicon gate
US6188105 *1 Abr 199913 Feb 2001Intersil CorporationHigh density MOS-gated power device and process for forming same
US6190978 *16 Abr 199920 Feb 2001Xemod, Inc.Method for fabricating lateral RF MOS devices with enhanced RF properties
US6191447 *28 May 199920 Feb 2001Micro-Ohm CorporationPower semiconductor devices that utilize tapered trench-based insulating regions to improve electric field profiles in highly doped drift region mesas and methods of forming same
US6194741 *3 Nov 199827 Feb 2001International Rectifier Corp.MOSgated trench type power semiconductor with silicon carbide substrate and increased gate breakdown voltage and reduced on-resistance
US6198127 *19 May 19996 Mar 2001Intersil CorporationMOS-gated power device having extended trench and doping zone and process for forming same
US6201279 *22 Oct 199913 Mar 2001Infineon Technologies AgSemiconductor component having a small forward voltage and high blocking ability
US6204097 *1 Mar 199920 Mar 2001Semiconductor Components Industries, LlcSemiconductor device and method of manufacture
US6207994 *5 Feb 199927 Mar 2001Power Integrations, Inc.High-voltage transistor with multi-layer conduction region
US6222229 *14 Jun 199924 Abr 2001Cree, Inc.Self-aligned shield structure for realizing high frequency power MOSFET devices with improved reliability
US6222233 *4 Oct 199924 Abr 2001Xemod, Inc.Lateral RF MOS device with improved drain structure
US6337499 *17 Ago 19988 Ene 2002Infineon Technologies AgSemiconductor component
US6346464 *27 Jun 200012 Feb 2002Kabushiki Kaisha ToshibaManufacturing method of semiconductor device
US6346469 *3 Ene 200012 Feb 2002Motorola, Inc.Semiconductor device and a process for forming the semiconductor device
US6351018 *26 Feb 199926 Feb 2002Fairchild Semiconductor CorporationMonolithically integrated trench MOSFET and Schottky diode
US6353252 *28 Jul 20005 Mar 2002Kabushiki Kaisha ToshibaHigh breakdown voltage semiconductor device having trenched film connected to electrodes
US6359308 *24 Jul 200019 Mar 2002U.S. Philips CorporationCellular trench-gate field-effect transistors
US6362112 *8 Nov 200026 Mar 2002Fabtech, Inc.Single step etched moat
US6362505 *27 Jul 200026 Mar 2002Siemens AktiengesellschaftMOS field-effect transistor with auxiliary electrode
US6534825 *14 Ago 200218 Mar 2003Fairchild Semiconductor CorporationPower MOS device with improved gate charge performance
US6677641 *17 Oct 200113 Ene 2004Fairchild Semiconductor CorporationSemiconductor structure with improved smaller forward voltage loss and higher blocking capability
US6683346 *7 Mar 200227 Ene 2004Fairchild Semiconductor CorporationUltra dense trench-gated power-device with the reduced drain-source feedback capacitance and Miller charge
US20020009832 *19 Ene 200124 Ene 2002Blanchard Richard A.Method of fabricating high voltage power mosfet having low on-resistance
US20020014658 *4 May 20017 Feb 2002Blanchard Richard A.High voltage power mosfet having low on-resistance
US20030060013 *24 Sep 199927 Mar 2003Bruce D. MarchantMethod of manufacturing trench field effect transistors with trenched heavy body
US20040031987 *19 Mar 200319 Feb 2004Ralf HenningerMethod for fabricating a transistor configuration including trench transistor cells having a field electrode, trench transistor, and trench configuration
US20050017293 *28 May 200427 Ene 2005Infineon Technologies AgSemiconductor component
Citada por
Patente citante Fecha de presentación Fecha de publicación Solicitante Título
US765232631 May 200626 Ene 2010Fairchild Semiconductor CorporationPower semiconductor devices and methods of manufacture
US773287627 Feb 20088 Jun 2010Fairchild Semiconductor CorporationPower transistor with trench sinker for contacting the backside
US777266826 Dic 200710 Ago 2010Fairchild Semiconductor CorporationShielded gate trench FET with multiple channels
US785541515 Feb 200821 Dic 2010Fairchild Semiconductor CorporationPower semiconductor devices having termination structures and methods of manufacture
US785904711 Nov 200828 Dic 2010Fairchild Semiconductor CorporationShielded gate trench FET with the shield and gate electrodes connected together in non-active region
US79360082 May 20083 May 2011Fairchild Semiconductor CorporationStructure and method for forming accumulation-mode field effect transistor with improved current capability
Clasificaciones
Clasificación de EE.UU.257/40, 257/E29.154, 257/E29.257, 257/E29.152, 257/E29.04
Clasificación internacionalH01L29/78, H01L29/08, H01L29/49
Clasificación cooperativaH01L29/4983, H01L29/4933, H01L29/4236, H01L29/0878, H01L29/42376, H01L29/0847, H01L29/7802, H01L29/7813, H01L29/4916
Clasificación europeaH01L29/423D2B5T, H01L29/49C, H01L29/49F, H01L29/08E2D4C, H01L29/78B2, H01L29/78B2T