US20040241926A1

US20040241926A1 - Contactless mask progammable rom

Info

Publication number: US20040241926A1
Application number: US10/477,880
Authority: US
Inventors: Jhyy-Cheng Liou; Chin-Hsi Lin
Original assignee: Solid State System Co Ltd
Current assignee: Solid State System Co Ltd
Priority date: 2002-08-26
Filing date: 2002-08-26
Publication date: 2004-12-02
Also published as: US20050127454A1; WO2004019408A1; WO2004019372A2; AU2003226597A1; WO2004019372A3; AU2002328180A1; US7227232B2; AU2003226597A8

Abstract

A contactless mask programmable read-only memory (Mask ROM) is described, comprising a plurality of word lines extending in row direction and a plurality of diffusions arranged in rows and columns in a substrate. In the Mask ROM, two rows of diffusions are separated by a word line. Two adjacent diffusions in the same column, the word line between the two diffusions, and the substrate between the two diffusions together constitute a memory cell. The memory cells include a plurality of first memory cells and a plurality of second memory cells. The channel length, the gate oxide width or the channel dopant concentration of the first memory cells is different from that of the second memory cells, such that the threshold voltage of the first memory cells is substantially different from that of the second memory cells.

Description

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a semiconductor device. More particularly, the present invention relates to a contactless mask programmable read-only memory (Mask ROM).

2. Description of Related Art

Read-only memory (ROM) is a type of non-volatile memory, which can retain data as disconnected from power supply and is therefore used to store permanent data, such as booting data of computer systems.

In order to simplify the fabricating processes and to increase the integration of ROM devices, various ROM structures are proposed based on shared diffusion and integration of the coding process and the contact process. Some conventional ROM devices are described below.

FIG. 1 illustrates a top view of a contact ROM in the prior art.

Refer to FIG. 1, the

contact ROM

100 comprises rows and columns of MOS-type memory cells, wherein two adjacent memory cells in the same column constitute a cell pair 102 that is isolated by field isolation 104. The memory cells in the same row are controlled by a word line 106, and the memory cells in the same column are located under a bit line 108. The two memory cells in a cell pair 102 share a source 110 between the two drains 112 thereof, while the sources 110 of the cell pairs 102 in the same row are electrically connected to a ground line 114. In the contact ROM 100, a plurality of contacts 116 are selectively formed on the drains 112 of the memory cells as data codes, wherein the contacts in the same column are connected to a bit line 108.

During a reading operation of the contact ROM, the

selected word line

106 is biased to high level. If the drain 112 of the selected memory cell has a contact 116 thereon electrically connecting with the selected bit line 108, a current can be conducted from the selected bit line 108 to the ground line 114 connecting with the source 110 of the selected memory cell. Otherwise, no current is detected. In other words, the data is stored as a contact pattern. However, since the field isolation 104 is formed between two rows of cell pairs 102 and contacts 116 are formed on the drains 112, the area of the memory array is large and the device integration is low.

FIG. 2 illustrates a top view of an implant programmable ROM in the prior art.

Refer to FIG. 2, the implant

programmable ROM

200 comprises rows and columns of MOS-type memory cells 201. The memory cells in the same row are controlled by a word line 202 and every two rows of memory cells 201 are coupled to a ground line 204, while two columns of memory cells 201 are separated by isolation 203. A memory cell 201 shares a source 206 with one adjacent memory cell in the same column, and shares a drain 208 with the other adjacent memory cell in the same column. The sources 206 of the memory cells 201 in the same row are connected to a ground line 204, and the drains 208 of the memory cells 201 in the same column are electrically connected to a bit line 210 via contacts 212. The implant programmable ROM 200 is programmed by selectively implanting ions into the channel regions under the word lines 202 to make the selected channel regions 214 have a higher threshold voltage (V_T). During the reading operation of the implant programmable ROM, the selected word line 202 is biased to high level. If the channel region of the selected memory cell 201 is not implanted, the channel can be switched on and an On-current can be detected, otherwise the channel cannot be switched on and the channel current is extremely small.

As compared with the

contact ROM

100 in FIG. 1, the implant programmable ROM 200 is more compact because the isolation between rows of memory cells is omitted and a drain 208 is shared by two memory cells 201 like a source 206. However, since an additional mask is needed for selectively implanting the channel regions of the memory cells 201, the fabricating process is more complex. Moreover, in consideration of the lateral area necessary for forming the contacts 212, the degree of area reduction of the drain region 208 is limited and the memory array cannot be further miniaturized.

FIG. 3 illustrates a top view of a Metal ROM in the prior art.

Refer to FIG. 3, the

Metal ROM

300 has a NAND (NOT AND) structure and comprises rows and columns of MOS-type memory cells. The memory cells in the same row are controlled by a word line 302 and four continuous memory cells in the same column are grouped as a memory string 304. In a memory string 304, the diffusion 305 of one terminal memory cell is electrically connected to a ground line 306, and the diffusion 305 of the other terminal memory cell is coupled to a bank select transistor 308. The bank select transistor 308 is coupled to a bit line 320 parallel to the memory string 304 via a contact 322. The source and the drain of a memory cell, i.e., the two diffusions 305 of a memory cell, are both shared by adjacent cells.

The Metal ROM is programmed by selectively forming

local interconnects

326 each connecting the two diffusions 305 of a selected memory cell. If a memory cell has a local interconnect 326 formed thereon like memory cell C1 does, the memory cell is always electrically conductible and acts like a depletion-type MOS devices, otherwise the memory cell is in the enhanced mode like memory cell C2 is. During a reading operation, the selected bit line 320 is coupled to a certain voltage level, the selected word line 302 is coupled to low level, and the unselected word lines 302 and the gate 340 of the bank select transistor 308 are coupled to high level. Thus, the bank select transistor 308 and all of the unselected memory cells in the same memory string 304 are switched on. Consequently, if the selected memory cell has a local interconnect 326 formed thereon, a current can be conducted through it and can be detected, otherwise no current is detected. The Metal ROM is more compact than the contact ROM, but the memory area in the Metal ROM cannot be further reduced because local interconnects must be formed on the diffusions 305 (sources and drains).

SUMMARY OF THE INVENTION

Accordingly, this invention provides a contactless mask programmable ROM that has a smaller memory array for increasing device integration.

A Mask ROM of this invention comprises a plurality of word lines extending in row direction and a plurality of MOS-type memory cells. A memory cell in one column shares its diffusions with two adjacent memory cells in the same column, and the two terminal memory cells in the same column are coupled to a first voltage source and a second voltage source, respectively. The first voltage source and the second voltage source are, for example, a bit line and ground, respectively. The memory cells include a plurality of first memory cells and a plurality of second memory cells. The first memory cells have a first channel length (word line width) and a first threshold voltage, and the second memory cells have a second channel length (word line width) that is smaller than the first one and is small enough to cause short channel effect. The second memory cells thus have a second threshold voltage substantially lower than the first threshold voltage. In addition, the difference between the first threshold voltage and the second threshold voltage is sufficiently large, so that a reading voltage can be set between the two to identify the type (first or second) of the selected memory cell during a reading operation. The type of the selected memory cell corresponds to the data value (0 or 1) stored in it.

In another Mask ROM of this invention, the first memory cells have a first channel dopant concentration to cause a first threshold voltage. The second memory cells have a second channel dopant concentration lower than the first one to cause a second threshold voltage substantially lower than the first threshold voltage. This can be done by performing a threshold voltage adjusting implantation to selected (first) memory cells with a patterned photoresist layer as a mask, which is formed with a photo-mask. In addition, the difference between the first threshold voltage and the second threshold voltage is sufficiently large, so that a reading voltage can be set between the two to identify the type (first or second) of the selected memory cell during a reading operation.

In still another Mask ROM of this invention, the first memory cells have a first gate dielectric thickness to cause a first threshold voltage. The second memory cells have a second gate dielectric thickness smaller than the first one to cause a second threshold voltage substantially lower than the first threshold voltage. The difference between the first threshold voltage and the second threshold voltage is sufficiently large, so that a reading voltage can be set between the two to identify the type (first or second) of the selected memory cell during a reading operation.

As mentioned above, in the contactless Mask ROM of this invention, the data value stored in a memory cell corresponds to the channel length, the gate dielectric thickness or the channel dopant concentration thereof, and no contact is formed on the diffusion regions. Therefore, the Mask ROM of this invention is more compact than those in the prior art.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings, [0021]
FIG. 1 illustrates a top view of a contact ROM in the prior art; [0022]
FIG. 2 illustrates a top view of an implant programmable ROM in the prior art; [0023]
FIG. 3 illustrates a top view of a Metal ROM in the prior art; [0024]
FIG. 4A illustrates a contactless Mask ROM according to a first embodiment of this invention, and FIG. 4B illustrates the equivalent circuit of the contactless Mask ROM; [0025]
FIG. 5 plots the threshold voltage with respect to the channel length; [0026]
FIG. 6 illustrates a top view of a contactless Mask ROM according to a second or third embodiment of this invention; [0027]
FIG. 7 illustrates the contactless Mask ROM of the second embodiment in FIG. 6 in a cross-sectional view along line VII-VII′; and [0028]
FIG. 8 illustrates the contactless Mask ROM of the third embodiment in FIG. 6 in a cross-sectional view along line VII-VII′.[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment [0030]
FIG. 4A illustrates a contactless Mask ROM according to a first embodiment of this invention, and FIG. 4B illustrates the equivalent circuit of the contactless Mask ROM. Meanwhile, FIG. 5 plots the threshold voltage with respect to the channel length in order to explain this embodiment. [0031]
Refer to FIGS. 4A and 4B, the [0032] contactless Mask ROM 400 comprises a plurality of word lines 420 extending in row direction, and rows and columns of diffusions 440 in a substrate (not shown) like a P-type substrate. The word lines 420 comprise a material such as doped polysilicon, and the diffusions 440 contain N-type dopants, for example. In the contactless Mask ROM 400, two columns of diffusions 440 are separated by isolation 410. Two rows of diffusions 440 are separated by a word line 420, and the two terminal diffusions 440 in each column of diffusions 440 are coupled to a bit line (BL_n) and ground, respectively. In addition, two adjacent diffusions 440 in the same column, the word line 420 between the two diffusions 440, and the substrate (not shown) between the two diffusions 440 together constitute a MOS-type memory cell C_s/C_n. Accordingly, two columns of memory cells C_s/C_nare separated by the isolation 410.
The word lines [0033] 420 over the memory cells C_nare not narrowed, and the memory cells C_nhave a first channel length and a first threshold voltage. The word lines 420 over the memory cells C_sare narrowed to create a second channel length small enough to cause short channel effect, so the memory cells C_shave a second threshold voltage substantially lower than the first threshold voltage, as shown in FIG. 5. The difference between the first threshold voltage and the second threshold voltage is sufficiently large, so that a reading voltage can be set between the two to identify the type (first or second) of the selected memory cell during a reading operation. The type of the selected memory cell corresponds to the data value (0 or 1) stored in it.
Second Embodiment [0034]
FIG. 6 illustrates a contactless Mask ROM according to the second embodiment of this invention, and FIG. 7 illustrates the contactless Mask ROM in a cross-sectional view along the line VII-VII′. [0035]
Refer to FIGS. 6 and 7, the [0036] contactless Mask ROM 600 comprises a plurality of word lines 620 extending in row direction and rows and columns of diffusions 640 in a substrate 602, wherein each word line 620 is isolated from the substrate 602 by a gate oxide layer 660. The word lines 620 comprise a material such as doped polysilicon, and the diffusions 640 contain N-type dopants, for example. In the contactless Mask ROM 600, two columns of diffusions 640 are separated by isolation 610. Two rows of diffusions 640 are separated by a word line 620, and the two terminal diffusions 640 in each column of diffusions 640 are coupled to a bit line (BL_n) and ground, respectively. In addition, two adjacent diffusions 640 in the same column, the word line 620 between the two diffusions 640, and the substrate 602 between the two diffusions 640 together constitute a MOS-type memory cell.
Refer to FIGS. 6 and 7 again, the memory cells C[0037] _hhave a raised channel dopant concentration, as indicated by the numeral 608, to cause a first threshold voltage. The other memory cells have a lower channel dopant concentration, i.e., an original channel dopant concentration, to cause a second threshold voltage. The higher channel dopant concentration is made by, for example, conducting a threshold voltage adjusting implantation process, wherein a photo-mask is used to form a patterned photoresist layer exposing selected memory cells and an implantation is then performed to adjust the threshold voltages of the selected memory cells. In addition, the difference between the first threshold voltage and the second threshold voltage is sufficiently large, so that a reading voltage can be set between the two to identify the type (first or second) of the selected memory cell during a reading operation. The type of the selected memory cell corresponds to the data value (0 or 1) stored in it.
Third Embodiment [0038]
FIG. 6 also illustrates a contactless Mask ROM according to the third embodiment of this invention, and FIG. 8 illustrates the contactless Mask ROM in a cross-sectional view along the line VII-VII′. [0039]
Refer to FIGS. 6 and 8, the [0040] contactless Mask ROM 800 comprises a plurality of word lines 820 extending in row direction and rows and columns of diffusions 840 in a substrate 802. The word lines 820 comprise a material such as doped polysilicon, and the diffusions 840 contain N-type dopants, for example. In the contactless Mask ROM 800, two columns of diffusions 840 are separated by isolation 810. Two rows of diffusions 840 are separated by a word line 820, and the two terminal diffusions 840 in each column of diffusions 840 are coupled to a bit line (BL_n) and ground, respectively. In addition, two adjacent diffusions 840 in the same column, the word line 820 between the two diffusions 840, and the substrate 802 between the two diffusions 840 together constitute a MOS-type memory cell.
Refer to FIG. 8, the memory cells C[0041] _hhave a gate oxide layer 860 b with a first thickness to cause a first threshold voltage. The other memory cells have a gate oxide layer 860 a with a second thickness smaller than the first thickness to cause a second threshold voltage substantially lower than the first threshold voltage. The difference between the first threshold voltage and the second threshold voltage is sufficiently large, so that a reading voltage can be set between the two to identify the type (first or second) of the selected memory cell during a reading operation. The type of the selected memory cell corresponds to the data value (0 or 1) stored in it.
Moreover, the two gate oxide layers [0042] 860 a and 860 b can be formed with a method that has been used in a CMOS /Logic process supporting dual power supply product, e.g., a 3 v/5 v application. For example, the substrate regions corresponding to the gate oxide layers 860 a are implanted with nitrogen ions before gate oxide formation, so as to inhibit the growth of the gate oxide layers 860 a. On the other hand, the substrate regions corresponding to the gate oxide layers 860 b are implanted with fluorine ions before gate oxide formation, so as to enhance the growth of the gate oxide layers 860 b.
As mentioned above, the Mask ROM in the second embodiment can be programmed by performing a selective threshold voltage adjusting implantation, while that in the third embodiment is programmed by adjusting the gate oxide thickness. The method using threshold voltage adjusting implantation and the method adjusting the gate oxide thickness both need an additional mask. However, the mask for forming a gate dielectric layer with different thickness is ready for a CMOS /Logic process that supports dual power supply product, e.g., a 3 v/5 v application, while the additional mask needed for adjusting the threshold voltage should be designed from the beginning. [0043]
Reading Operation of the Mask ROM: [0044]
The reading operation of the mask ROM according to the preferred embodiment of this invention is described below. Refer to FIG. 4B, for example, when the memory cell C[0045] _scorresponding to word line WL1 and bit line BL1 is being read, the selected word line WL1 is coupled to low level and the unselected world lines are coupled to high level. The low level is between the lower (second) threshold voltage and the higher (first) threshold voltage, and the high level is higher than the first threshold voltages and therefore is capable of switching on the unselected memory cells in the same column. Since the memory cell C_scorresponding to word line WL1 and bit line BL1 has the second (smaller) channel length and therefore has the second (lower) threshold voltage, it can be switched on by the low level voltage to allow a current from BL1 to ground.
On the other hand, when the memory cell C[0046] _ncorresponding to word line WL2 and bit line BL1 is being read, WL2 is coupled to low level, and the unselected world lines are coupled to high level to switch on the unselected memory cells in the same column. Since the memory cell C_nhas the first (larger) channel length and therefore has the first (higher) threshold voltage, it cannot be switched on by the low-level voltage. Consequently, the current from BL₁to ground is extremely small. Therefore, by detecting the magnitude of the current from BL₁to ground, the type of the selected memory cell and the corresponding data value (0 or 1) can be determined.
Moreover, the method for reading the contactless Mask ROM illustrated in FIG. 6˜[0047] 8 is similar to the aforementioned one, wherein the memory cells C_hare taken as C_nand the other cells are taken as C_s.
As mentioned above, in the contactless Mask ROM of this invention, the value of the data stored in a memory cell corresponds to the channel length, the gate dielectric thickness or the channel dopant concentration, and no contact is formed on the diffusion regions. Therefore, the Mask ROM of this invention is more compact than those in the prior art. [0048]
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents. [0049]

Claims

What is claimed is:

1. A contactless mask programmable read-only memory (Mask ROM), comprising a plurality of word lines extending in a row direction and a plurality of MOS-type memory cells, wherein

two terminal memory cells in one column are coupled to a first voltage source of a first level and a second voltage source of a second level, respectively, wherein the second level is different from the first level; and

the memory cells include a plurality of first memory cells and a plurality of second memory cells, wherein a first threshold voltage of the first memory cells is substantially different from a second threshold voltage of the second memory cells, such that a type (first or second) of a selected memory cell can be identified during a reading operation.

2. The contactless Mask ROM of claim 1, wherein a second channel length of the second memory cells is smaller than a first channel length of the first memory cells and is small enough to cause short channel effect, such that the second threshold voltage of the second memory cells is substantially lower than the first threshold voltage of the first memory cells.

3. The contactless Mask ROM of claim 1, wherein a second channel dopant concentration of the second memory cells is lower than a first channel dopant concentration of the first memory cells, such that the second threshold voltage of the second memory cells is substantially lower than the first threshold voltage of the first memory cells.

4. The contactless Mask ROM of claim 1, wherein a second gate dielectric thickness of the second memory cell is smaller than a first gate dielectric thickness of the first memory cells, such that the second threshold voltage of the second memory cells is substantially lower than the first threshold voltage of the first memory cells.

5. The contactless Mask ROM of claim 1, wherein the first voltage source comprises a bit line.

6. The contactless Mask ROM of claim 5, wherein the second voltage source comprises ground.

7. The contactless Mask ROM of claim 1, wherein two columns of memory cells are separated by an isolation layer.

8. The contactless Mask ROM of claim 1, wherein the word lines comprises doped polysilicon.

9. The contactless Mask ROM of claim 1, wherein the substrate is a P-type substrate and diffusions of the MOS-type memory cells are of N-type.

10. A contactless mask programmable read-only memory (Mask ROM), comprising:

a plurality of word lines extending in a row direction; and

a plurality of diffusions arranged in rows and columns in a substrate, wherein

two rows of diffusions are separated by a word line;

two adjacent diffusions in the same column, the word line between the two diffusions, and the substrate between the two diffusions together constitute a memory cell, and a plurality of memory cells are thus defined; and

the memory cells include a plurality of first memory cells and a plurality of second memory cells, wherein a second channel length of the second memory cells is smaller than a first channel length of the first memory cells and is small enough to cause short channel effect, such that a second threshold voltage of the second memory cells is substantially lower than a first threshold voltage of the first memory cells and a type (first or second) of a selected memory cell can be identified during a reading operation.

11. The contactless Mask ROM of claim 10, wherein one terminal diffusion in a column of diffusions is coupled to a bit line.

12. The contactless Mask ROM of claim 11, wherein the other terminal diffusion in the column of diffusions is coupled to ground.

13. The contactless Mask ROM of claim 10, wherein two columns of diffusions are separated by an isolation layer.

14. A contactless mask programmable read-only memory (Mask ROM), comprising:

a plurality of word lines extending in a row direction; and

a plurality of diffusions arranged in rows and columns in a substrate, wherein

two rows of diffusions are separated by a word line;

two terminal diffusions in each column of diffusions are coupled to a voltage and ground, respectively;

two adjacent diffusions in the same column, the word line between the two diffusions, and the substrate between the two diffusions together constitute a memory cell, so that a plurality of memory cells are defined; and

the memory cells include a plurality of first memory cells and a plurality of second memory cells, wherein a second channel dopant concentration of the second memory cells is lower than a first channel dopant concentration of the first memory cells, such that a second threshold voltage of the second memory cells is substantially lower than a first threshold voltage of the first memory cells and a type (first or second) of a selected memory cell can be identified during a reading operation.

15. The contactless Mask ROM of claim 14, wherein one terminal diffusion in a column of diffusions is coupled to a bit line.

16. The contactless Mask ROM of claim 15, wherein the other terminal diffusion in the column of diffusions is coupled to ground.

17. The contactless Mask ROM of claim 14, wherein two columns of diffusions are separated by an isolation layer.

18. A contactless mask programmable read-only memory (Mask ROM), comprising:

a plurality of word lines extending in a row direction; and

a plurality of diffusions arranged in rows and columns in a substrate, wherein

two rows of diffusions are separated by a word line;

the memory cells include a plurality of first memory cells and a plurality of second memory cells, wherein a second gate dielectric thickness of the second memory cells is smaller than a first gate dielectric thickness of the first memory cells, such that a second threshold voltage of the second memory cells is substantially lower than a first threshold voltage of the first memory cells and a type (first or second) of a selected memory cell can be identified during a reading operation.

19. The contactless Mask ROM of claim 18, wherein one terminal diffusion in a column of diffusions is coupled to a bit line.

20. The contactless Mask ROM of claim 19, wherein the other terminal diffusion in the column of diffusions is coupled to ground.