US20040241940A1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- US20040241940A1 US20040241940A1 US10/885,865 US88586504A US2004241940A1 US 20040241940 A1 US20040241940 A1 US 20040241940A1 US 88586504 A US88586504 A US 88586504A US 2004241940 A1 US2004241940 A1 US 2004241940A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/318—Inorganic layers composed of nitrides
- H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
Definitions
- the present invention relates to a method for fabricating a semiconductor device. Particularly, the present invention relates to a method for fabricating a semiconductor device, in which a plug is involved.
- the lower electrode of the capacitor is fabricated in various configurations, such as, cylindrical structures, stacked structures, pin structures, or concave structures. These structures allow the effective area of the lower electrode of the capacitor to be maximized within limited areas.
- a transistor including a word line and bit line is formed on a semiconductor substrate, and then, a capacitor contact plug is formed for connecting the capacitor to the transistor. Then a lower electrode is connected to the capacitor contact plug, thereby forming a polysilicon plug (PP) structure.
- the PP structure is known to be suitable for fabricating a high density semiconductor devices.
- FIG. 1 illustrates the layout of a conventional semiconductor device.
- a word line (WL) and a bit line (BL) are formed on a semiconductor substrate 11 in a mutually crossing structure.
- a storage node contact plug (SNC) is formed on a region of semiconductor substrate 11 where the word line and the bit line cross each other.
- FIGS. 2A to 2 D are cross-sectional views taken along dashed line A-A′ of FIG. 1 showing the conventional fabricating method for a semiconductor device.
- a capacitor over bit line (COB) structure is formed.
- FIG. 2A As shown in FIG. 2A, on semiconductor substrate 11 on which a transistor (not illustrated) including a word line and a source/drain has been formed, there is deposited a first interlayer insulating film 12 . Then a flattening process is performed.
- first interlayer insulating film 12 is selectively etched to form a contact hole so as to expose a relevant portion (source or drain) of semiconductor substrate 11 . Then a first polysilicon plug 13 is buried into the contact hole.
- first polysilicon plug 13 In an alternative method for fabricating first polysilicon plug 13 , polysilicon is deposited on the entire surface including the word line, and then, etching is performed in a line pattern. Then, a first interlayer insulating film 12 is deposited, and then chemical-mechanical polishing is performed until a surface of the word line is exposed, thereby completing the process.
- first polysilicon plug 13 is the contact plug which will be contacted to the bit line and the storage node contact. In the drawing, there is illustrated only the portion to which the storage node contact is to be contacted.
- a second interlayer insulating film 14 is deposited on first interlayer insulating film 12 in which the first polysilicon plug has been buried, and then, a flattening process is performed. Then a plurality of bit lines 15 are formed at certain gaps on second interlayer insulating film 14 .
- spacers 16 are formed on both of the sidewalls of bit lines 15 .
- a third interlayer insulating film 17 is deposited on the entire surface including bit line 15 , and then, a flattening process is performed.
- a barrier nitride film 18 and a buffer oxide film 19 are then sequentially formed on flattened third interlayer insulating film 17 .
- a storage node contact mask 20 is formed on buffer oxide layer 19 by using a photoresist film.
- first buffer oxide film 19 and barrier nitride film 18 are etched using storage node contact mask 20 .
- Third interlayer insulating film 17 and second interlayer insulating film 14 are also etched to form a storage node contact hole 21 to expose the surface of first polysilicon plug 13 between bit lines 15 (referred to as “self-aligned contact” below). Then, storage node contact mask 20 is removed.
- a polysilicon film is deposited on the entire surface including storage node contact hole 21 , and then, the polysilicon film is etched back to form a second polysilicon plug 22 (referred to as “storage node contact plug” below) which is vertically contacted with first polysilicon plug 13 .
- an oxide film 23 (referred to as “capacitor oxide film” below), a hard mask 24 and a reflection preventing mask 25 are sequentially deposited on buffer oxide film 20 including storage node contact plug 22 .
- Oxide film 23 determines the height and the shape of the storage node.
- a storage node mask (not illustrated) is formed on reflection preventing film 25 by using a photoresist film. Reflection preventing film 25 , hard mask 24 and capacitor oxide film 23 are etched by utilizing the storage node mask to form a concave part 26 so as to expose a surface of storage node contact plug 22 .
- the storage node mask is removed, and then, a storage node 27 is formed only in concave part 26 .
- Prominences, such as meta-stable polysilicon (MPS) 28 are grown.
- the process of forming storage node 27 and MPS 28 is performed in the following manner. First, without isolating the cells from each other, MPS 28 is grown on the surface of storage node 27 .
- Storage node 27 is isolated by performing a chemical-mechanical polishing. Or, alternatively, storage node 27 is first isolated, and then, MPS 28 is grown on its surface. Then, a dielectric node 29 and a plate node 30 are sequentially deposited on the entire surface including isolated storage nodes 27 .
- the buffer oxide film is also etched during etching of the capacitor oxide film.
- the storage node contact plug protrudes above the barrier nitride film (Section B by about 1000 ⁇ (refer to the portion B of FIG. 3 a ).
- the area of the storage node is decreased.
- FIG. 3B if a misalignment occurs during the process of forming the storage node mask, a bridge is formed between the storage node and an adjacent storage node contact plug (Section B′ of FIG. 3B).
- the chemical-mechanical polishing is performed for isolating the storage node after forming the MPS, and thus, the MPS grains are broken. Further, the broken pieces of the grains are not completely removed during a subsequent wet wash process, and therefore, the broken pieces remain buried within the storage node.
- This method may overcome the breaking of the MPS grains during the chemical-mechanical polishing.
- an MPS seed will be partly grown on the uppermost non-crystalline silicon layer of the storage node (which is the lower electrode) during the growing of the MPS (this will be called “out-growing” below).
- the gaps between the storage nodes are narrowed, or in a worst case, bridges are formed between the nodes, thereby generating double-bit defects.
- An aspect related to the present invention provides a method for fabricating a semiconductor device in which there can be prevented the formation of bridges between storage nodes and storage node contact plugs and between bit lines and the storage node contact plugs due to a misalignment in the masking process.
- Another aspect related to the present invention provides a method for fabricating a capacitor in which MPS growing can be carried out on the uppermost surface of the storage node, and the formation of bridges between the storage nodes during the MPS out-growing can be inhibited.
- Another aspect related to the present invention provides a method for fabricating a capacitor in which the reduction of the area of the storage node due to the exposure of the storage node contact plug after an etch of the capacitor oxide film can be inhibited.
- a method for fabricating a contact plug includes the steps of forming an insulating film on a semiconductor substrate; selectively etching the insulating film to form a contact hole so as to expose the semiconductor substrate; forming a spacer on a side wall of the contact hole; and plugging a conductive film into the contact hole.
- a method for fabricating a capacitor according to the present invention includes the steps of forming a first insulating film on a semiconductor substrate, and forming a contact plug through the first insulating film; sequentially forming an etch barrier film and a second insulating film upon the first insulating film; sequentially etching the second insulating film and the etch barrier film to form an opening part so as to expose the contact plug; forming a conductive film on the second insulating film and on the opening part; selectively etching the conductive film, with the conductive film being over-etched relative to the second insulating film, so as to form a storage node within the opening part; forming prominences on a surface of the storage node; and sequentially forming a dielectric film and a plate node upon the storage node.
- a method for fabricating a semiconductor device includes the steps of forming a first insulating film on a semiconductor substrate; forming a plurality of bit lines on the first insulating film; forming a contact hole through the first insulating film between the bit lines to reach the semiconductor substrate; forming a spacer on a side wall of the contact hole; forming a first contact plug, the first contact plug being buried into the contact hole to reach the semiconductor substrate; sequentially forming an etch barrier film and a second insulating film on the first insulating film and upon the first contact plug; sequentially etching the second insulating film and the etch barrier film to form an opening part so as to expose the first contact plug; forming a first conductive film on an entire surface (including the opening part); selectively etching the first conductive film, with the first conductive film being over-etched relative to the second insulating film, so as to form a storage node within the opening part; and sequentially
- FIG. 1 is a plan view of a conventional general semiconductor device
- FIGS. 2A to 2 D are cross-sectional views showing a conventional fabricating method for a semiconductor device
- FIG. 3A illustrates an effect of a projection in a storage node contact plug formed by a conventional method
- FIG. 3B illustrates the formation of a short circuit between a storage node and an adjacent storage node contact plug by a conventional method
- FIGS. 4A to 4 D are cross-sectional views showing a contact plug fabrication method according to the present invention.
- FIGS. 5A to 5 J are cross-sectional views showing a semiconductor device fabrication method according to the present invention.
- FIG. 6 illustrates a semiconductor device which is fabricated according to the present invention.
- FIG. 7 illustrates a semiconductor device which is fabricated according to the present invention.
- FIGS. 4 a to 4 d are cross-sectional views showing a contact plug fabrication method in one aspect related to the present invention.
- a word line 42 is formed on a semiconductor substrate 41 , with a gate oxide film (not illustrated) involved therein. Then an ion implantation is performed on semiconductor substrate 41 and on the both sides of word line 42 , thereby forming an LDD (lightly doped drain) junction 43 . Then a spacer insulating film is deposited on the entire surface including word line 42 .
- word line spacer 44 contacts both of the sidewalls of word line 42 .
- an ion implantation is performed using word line spacer 44 and word line 42 as a mask to form a source/drain 45 which is electrically connected to LDD junction 43 .
- interlayer insulating film (ILD) 46 is deposited and flattened. Then, a contact mask 47 is formed on interlayer insulating film 46 by using a photoresist film.
- interlayer insulating film 46 is etched by using contact mask 47 to form a contact hole 49 exposing relevant portions of source/drain 45 . Then, contact mask 47 is removed. A nitride film 48 is then deposited on the entire surface including contact hole 49 .
- the nitride film 48 is etched away to form a nitride film spacer 48 a on the inside wall of contact hole 49 .
- Nitride film spacer 48 a is formed to a thickness ranging from 100 ⁇ to 200 ⁇ , and during the etching of the nitride film, an over-etching of 30% is performed, so that any residual nitride film on the source/drain can be removed.
- a conductive material for the plug is deposited on interlayer insulating film 46 including contact hole 49 in which nitride film spacer 48 a has been formed. Then an etch-back or a chemical-mechanical polishing is performed to form a plug 49 a which is buried in contact hole 49 .
- the conductive material for the plug is one or more material selected from a group consisting of: polysilicon, tungsten (W), tungsten silicide (W-silicide), TiN, TiAlN, TaSiN, TiSiN, TaN, TaAlN, TiSi and TaSi.
- the conductive film for the plug is deposited by applying a method selected from a group consisting of a chemical vapor deposition method (CVD), a physical vapor deposition method (PVD), and an atomic layer deposition method (ALD).
- CVD chemical vapor deposition method
- PVD physical vapor deposition method
- ALD atomic layer deposition method
- a low pressure chemical vapor deposition method LP-CVD
- RTP rapid thermal process
- the nitride spacer is formed on the inside wall of the contact hole prior to the formation of the plug, and therefore, even if a misalignment occurs during the contact mask process, any current leakage between the plug and the bit line can be inhibited.
- FIG. 5A to 5 H are cross-sectional views showing the semiconductor device fabricating method in another aspect related to the present invention.
- a semiconductor substrate 51 on which a transistor has been formed and which includes a word line spacer 52 a , a word line 52 , and a source/drain 53 of an LDD junction structure 53 a the following process steps are performed. That is, a first interlayer insulating film 54 is deposited, and then, a contact mask (not illustrated) is formed on first interlayer insulating film 54 by using a photoresist film. Then, first interlayer insulating film 54 is etched using the contact mask to form a contact hole thereby exposing source/drain 53 .
- a first conductive film for the plug is deposited on the entire surface, and the first conductive film is selectively removed by etching or chemical-mechanical polishing until the surface of first interlayer insulating film 54 is exposed, thereby forming a first contact plug 55 .
- first contact plug 55 contacts a bit line and a storage node contact, which are to be formed later. In the drawing, only the portion where the storage node contact is to be contacted is illustrated.
- a second interlayer insulating film 56 is formed on the entire surface, and then, a bit line 57 with a bit line spacer 57 a is formed on second interlayer insulating film 56 , bit line 57 crosses word line 52 .
- a contact hole is formed prior to the formation of bit line 57 , exposing the surface of first contact plug 55 .
- a bit line contact (not illustrated) may be formed to make bit line 57 contact semiconductor substrate 51 .
- a third interlayer insulating film 58 is formed on the entire surface including bit line 57 .
- a storage node contact mask (not illustrated) is then formed on third interlayer insulating film 58 by using a photoresist film.
- Third interlayer insulating film 58 a and second interlayer insulating film 56 are etched to form a contact hole for a storage node contact plug, thereby exposing the surface of first contact plug 55 between bit line 57 and word line 52 .
- first nitride film 59 is thoroughly etched to form a nitride film spacer 60 on the sidewalls of contact hole 58 a , and then, a second conductive film 61 is deposited on the entire surface including nitride film spacer 60 .
- an over-etching of 30% is performed during the thorough etching of first nitride film 59 which is formed by using tungsten or polysilicon.
- a low pressure chemical vapor deposition method (LP-CVD) or a rapid thermal process (RTP) is employed, with a doping concentration preferably of 2 ⁇ 10 20 atoms/cc or more of phosphorus (P).
- second conductive film 61 is etched back to form a second contact plug 62 (referred to as “storage node plug’ below) which is vertically connected to first contact plug 55 .
- a second nitride film 63 is formed on third interlayer insulating film 58 including storage node contact plug 62 .
- second nitride film 63 serves as an etch barrier during a dry etch and a wet etch performed on a capacitor oxide film later.
- Second nitride film 63 is deposited to a thickness ranging from 200 ⁇ to 800 ⁇ by employing a low pressure chemical vapor deposition method (LP-CVD), a plasma chemical vapor deposition method (PE-CVD), or a rapid thermal process (RTP).
- LP-CVD low pressure chemical vapor deposition method
- PE-CVD plasma chemical vapor deposition method
- RTP rapid thermal process
- a capacitor oxide film 64 , a hard mask 65 and a reflection preventing film 66 are sequentially deposited on second nitride film 63 , with capacitor oxide film 64 determining the height and shape of the storage node.
- Capacitor oxide film 64 is deposited to a desired thickness by utilizing plasma enhanced tetraethyl orthosilicate (PE-TEOS) or phosphosilicate glass (PSG). Generally, in the case where a wiring process of 0.16 ⁇ m or less is utilized, there is required a deposition thickness of 12,000 ⁇ or more for capacitor oxide film 64 , so that a capacitance of 25 fF/cell or more (the area for the storage node) can be obtained.
- PE-TEOS plasma enhanced tetraethyl orthosilicate
- PSG phosphosilicate glass
- a doped or undoped polysilicon is deposited to have a thickness ranging from 500 ⁇ to 2000 ⁇ at a temperature of 500° C. to 650° C.
- reflection preventing film 66 an inorganic material (such as SiON) or organic material is deposited or coated to have a thickness ranging from 300 ⁇ to 1000 ⁇ , so that the forthcoming masking process may be performed easily.
- an inorganic material such as SiON
- organic material is deposited or coated to have a thickness ranging from 300 ⁇ to 1000 ⁇ , so that the forthcoming masking process may be performed easily.
- a storage node mask 67 is formed on reflection preventing film 66 by using a photoresist film. Reflection preventing film 66 , hard mask 65 , and capacitor oxide film 64 are etched by utilizing storage node mask 67 .
- the photoresist film i.e., storage node mask 67 is stripped.
- reflection preventing film 66 which is made of a material similar to that of the photoresist film is removed simultaneously.
- second nitride film 63 which has been exposed upon etching capacitor oxide film 64 , is etched by using residual hard mask 65 as the etch mask (after removing reflection preventing film 66 ). Thus a concave part 64 a is formed to expose the surface of storage node contact plug 62 .
- second nitride film 63 is over-etched by 10% to 50%, thereby completely exposing the surface of storage node contact plug 62 .
- a light dry etching is carried out using oxygen (O 2 ) plasma, so that the foreign materials on the surface of storage node contact plug 62 can be removed once more, thereby decreasing the boundary resistance between the storage node and storage node contact plug 62 .
- residual hard mask 65 is removed in such a manner that an entire etch-back is carried out, thereby making the residual hard mask remain on the cell regions and on the peripheral circuit regions.
- a third conductive film 68 is deposited on the entire surface including concave part 64 a , and then, a photoresist film 69 is deposited to have a thickness ranging from 0.5 ⁇ m to 1 . 5 ⁇ m on the entire surface including third conductive film 68 . Then, an etch-back is carried out to expose the upper face of third conductive film 68 , and thus, photoresist film 69 remains only in the concave part.
- third conductive film 68 (not shown) is etched back to form a storage node 70 within concave part 64 a , and then, residual photoresist film 69 is removed.
- third conductive film 68 is formed into the storage node 70 .
- Third conductive film 68 comprises one or more materials selected from the group consisting of: a silicon-based material such as a doped polysilicon (D-poly Si) and a doped non-crystalline silicon; metals such as TiN, TaN, W, WN, Ru, Ir, and Pt; metal oxides such as RuO 2 and IrO 2 ; and WSi.
- a silicon-based material such as a doped polysilicon (D-poly Si) and a doped non-crystalline silicon
- metals such as TiN, TaN, W, WN, Ru, Ir, and Pt
- metal oxides such as RuO 2 and IrO 2
- WSi metal oxides
- One example of a doping process is a thermal doping that is performed under a phosphorus gas atmosphere ranging from 1% to 5% PH 3 /N 2 or PH 3 /H 3 , 50 sccm to 2000 sccm.
- the thermal doping is performed at a low temperature of 600 ⁇ 50° C. for 30 to 120 minutes under a pressure ranging from 1 to 100 Torr within an electric furnace.
- a second example of the doping is a plasma glow discharge that is performed with an radio frequency (RF) power of ranging from 100 W to 500 W for 30 to 120 seconds under a PH 3 atmosphere.
- RF radio frequency
- a third example of the doping is the rapid thermal process (RTP) in which a radiation heat is utilized at a temperature ranging from 750° C. to 950° C. for 30 to 120 seconds under a PH 3 atmosphere.
- RTP rapid thermal process
- a wet cleaning is performed in order to remove organic and metallic components and naturally formed oxide films, so that the doping effect can be maximized.
- the wet cleaning is performed in two stages. That is, a first stage is performed with a sulfuric acid solution, and a second stage is performed with a fluoric acid solution.
- a dielectric film 72 is formed on storage node 70 on which MPS 71 has been formed, and then, a plate node 73 is formed upon dielectric film 72 , thereby completing the concave capacitor of the present invention.
- plate node 73 is formed of the same material as that of storage node 70 . That is, it is formed with one or more material selected from the group consisting of: a silicon-based material such as a doped polysilicon (D-poly Si) and a doped non-crystalline silicon; metals such as TiN, TaN, W, WN, Ru, Ir and Pt; and metal oxides such as RuO 2 and IrO 2 .
- a silicon-based material such as a doped polysilicon (D-poly Si) and a doped non-crystalline silicon
- metals such as TiN, TaN, W, WN, Ru, Ir and Pt
- metal oxides such as RuO 2 and IrO 2 .
- a doped polysilicon film can be stacked as a shock-absorbing layer, so that structural stability can be obtained, and so that the life expectancy of TiN can be extended by protecting against thermal and electrical shocks.
- storage node 70 may be formed in a three-dimensional shape such as double or triple structures including a cylindrical structure as illustrated in FIG. 6, with prominences, such as MPS, being added.
- Dielectric film 72 may consist of a ferroelectric film or a high dielectric constant film selected from the group consisting of: Ta 2 O 5 ; STO (SrTiO 3 ); BST ((BaSr)TiO 3 ); PZT ((Pb) (Zr, Ti)O 3 ); PLZT((Pb, La) (Zr, Ti)O 3 ); BTO (BaTiO 3 ); PMN (Pb(Ng1 ⁇ 3Nb2 ⁇ 3)O 3 ); SBTN ((Sr,Bi)(Ta, Nb) 2 O 9 ); SBT ((Sr, Bi)Ta 2 O 9 ); BLT ((Bi, La)Ti 3 O 12 ); BT (BaTiO 3 ); ST (SrTiO 3 ); and PT (PbTiO 3 ).
- FIG. 6 illustrates the semiconductor device fabricated according to another aspect related to the present invention.
- the process is performed in the same manner as that of the process illustrated in FIGS. 5A-5H up to the formation of dielectric film 72 .
- capacitor oxide film 64 is wet-removed to make only storage node 70 remain.
- dielectric film 72 and plate node 73 are deposited, thereby forming a cylindrical capacitor.
- FIG. 7 illustrates the semiconductor device fabricated according to another aspect related to the present invention. Referring to FIG. 7, the process is performed in the same manner as that of the process illustrated in FIG. 5A-5H, except that a nitride film spacer 74 is formed on the wall of each of contact holes 54 a and 58 a for first and second contact plugs 55 and 62 .
- nitride film spacers 60 and 74 are formed on the walls of contact holes 54 a and 58 a prior to depositing first and second contact plugs 55 and 62 . Accordingly, even if a misalignment occurs during the contact masking process, any current leakage can be prevented between first contact plug 55 and word line 52 and between second contact plug 62 and bit line 57 .
- the dielectric film consists of a ferroelectric film or a high dielectric constant film selected from the group consisting of: Ta 2 O 5 ; STO (SrTiO 3 ); BST ((BaSr)TiO 3 ); PZT ((Pb) (Zr, Ti)O 3 ), PLZT ((Pb, La) (Zr, Ti)O 3 ); BTO (BaTiO 3 ); PMN (Pb(Ng1 ⁇ 3Nb2 ⁇ 3)O 3 ); SBTN ((Sr,Bi)(Ta, Nb) 2 O 9 ); SBT ((Sr, Bi)Ta 2 O 9 ); BLT ((Bi, La)Ti 3 O 12 ); BT (BaTiO 3 ); ST (SrTiO 3 ); and PT (PbTiO 3 ).
- Dielectric film 72 is deposited by applying one method selected from among a metal organic deposition method, a zol gel method, a spin-on method, a chemical deposition method (CVD), an atomic layer deposition method (ALD); and a physical vapor deposition method (PVD).
- a metal organic deposition method e.g., a metal organic deposition method, a zol gel method, a spin-on method, a chemical deposition method (CVD), an atomic layer deposition method (ALD); and a physical vapor deposition method (PVD).
- CVD chemical deposition method
- ALD atomic layer deposition method
- PVD physical vapor deposition method
- Storage node 70 and plate node 73 are formed with one material selected from the group consisting of: a silicon-based material such as a doped polysilicon (D-poly Si) and a doped non-crystalline silicon; metals such as TiN, TaN, W, WN, Ru, Ir and Pt; metal oxides such as RuO 2 and IrO 2 ; and WSi.
- a silicon-based material such as a doped polysilicon (D-poly Si) and a doped non-crystalline silicon
- metals such as TiN, TaN, W, WN, Ru, Ir and Pt
- metal oxides such as RuO 2 and IrO 2
- WSi a silicon-based material selected from the group consisting of: a silicon-based material such as a doped polysilicon (D-poly Si) and a doped non-crystalline silicon
- metals such as TiN, TaN, W, WN, Ru, Ir and Pt
- metal oxides such as RuO 2
- plate node 73 is formed with TiN
- a doped polysilicon film can be stacked, so that structural stability can be obtained, and the life expectancy of TiN can be extended by protecting against thermal and electrical shocks.
- a three-dimensional shape such as double or triple structures including a cylindrical structure, with prominences, such as the MPS being added.
- the present invention is applicable not only to capacitors connected to a source/drain, but also to capacitors connected to a conductive layer such as a gate electrode. Further, it can be applied not only to a capacitor over bit line (COB) structure, but also to a capacitor under bit line (CUB) structure of semiconductor devices.
- COB capacitor over bit line
- CUB capacitor under bit line
- an etch-back is performed for isolating the storage nodes from each other, and then, MPS is formed, so that the formation of any bridge between storage nodes can be inhibited, thereby preventing any electrical defects such as double-bit defects.
Abstract
A method for fabricating a semiconductor device is disclosed. A spacer is formed on the sidewall of the contact hole in which a storage node contact plug is buried. An etch barrier film and an insulating film are sequentially formed after the formation of the storage node contact plug. The insulating film and the etch barrier film are sequentially etched to form an opening part. Then a storage node is formed within the opening part which has been formed by an etching. Then prominences are formed on the surface of the storage node.
Description
- Priority is claimed from Republic of Korea Patent Application No. 2001-56742 filed Sep. 14, 2001, the entire contents of which are incorporated herein.
- The present invention relates to a method for fabricating a semiconductor device. Particularly, the present invention relates to a method for fabricating a semiconductor device, in which a plug is involved.
- As semiconductor devices undergo increases in component density and miniaturization, in order to increase speed, the area occupied by capacitors in semiconductor devices is decreased. As semiconductor devices undergo increases in component density and miniaturization, capacitors have to retain minimum values of capacitance.
- In order to establish the capacitance of the capacitor, the lower electrode of the capacitor is fabricated in various configurations, such as, cylindrical structures, stacked structures, pin structures, or concave structures. These structures allow the effective area of the lower electrode of the capacitor to be maximized within limited areas.
- In another method of establishing the capacitance of the capacitor, materials having a high dielectric constant, such as barium strontium titanate (BST), or Ta2O5, are used in the capacitor. If a dielectric material such as BST or Ta2O5 is used, the upper and lower electrodes of the capacitor are made of platinum (Pt), ruthenium (Ru) or TiN because of considerations of electrical properties.
- Particularly, where the lower electrode of the capacitor is fabricated using the metals mentioned above, a transistor including a word line and bit line is formed on a semiconductor substrate, and then, a capacitor contact plug is formed for connecting the capacitor to the transistor. Then a lower electrode is connected to the capacitor contact plug, thereby forming a polysilicon plug (PP) structure. The PP structure is known to be suitable for fabricating a high density semiconductor devices.
- FIG. 1 illustrates the layout of a conventional semiconductor device. As shown in FIG. 1, a word line (WL) and a bit line (BL) are formed on a
semiconductor substrate 11 in a mutually crossing structure. On a region ofsemiconductor substrate 11 where the word line and the bit line cross each other, is formed a storage node contact plug (SNC) to which a storage node will be contacted. - FIGS. 2A to2D are cross-sectional views taken along dashed line A-A′ of FIG. 1 showing the conventional fabricating method for a semiconductor device. Here, a capacitor over bit line (COB) structure is formed.
- As shown in FIG. 2A, on
semiconductor substrate 11 on which a transistor (not illustrated) including a word line and a source/drain has been formed, there is deposited a first interlayerinsulating film 12. Then a flattening process is performed. - Then, first
interlayer insulating film 12 is selectively etched to form a contact hole so as to expose a relevant portion (source or drain) ofsemiconductor substrate 11. Then afirst polysilicon plug 13 is buried into the contact hole. - In an alternative method for fabricating
first polysilicon plug 13, polysilicon is deposited on the entire surface including the word line, and then, etching is performed in a line pattern. Then, a firstinterlayer insulating film 12 is deposited, and then chemical-mechanical polishing is performed until a surface of the word line is exposed, thereby completing the process. - Here,
first polysilicon plug 13 is the contact plug which will be contacted to the bit line and the storage node contact. In the drawing, there is illustrated only the portion to which the storage node contact is to be contacted. - Next, a second
interlayer insulating film 14 is deposited on first interlayerinsulating film 12 in which the first polysilicon plug has been buried, and then, a flattening process is performed. Then a plurality ofbit lines 15 are formed at certain gaps on secondinterlayer insulating film 14. - Then,
spacers 16 are formed on both of the sidewalls ofbit lines 15. A third interlayerinsulating film 17 is deposited on the entire surface includingbit line 15, and then, a flattening process is performed. Abarrier nitride film 18 and abuffer oxide film 19 are then sequentially formed on flattened third interlayerinsulating film 17. A storagenode contact mask 20 is formed onbuffer oxide layer 19 by using a photoresist film. - As shown in FIG. 2B, first
buffer oxide film 19 andbarrier nitride film 18 are etched using storagenode contact mask 20. Thirdinterlayer insulating film 17 and secondinterlayer insulating film 14 are also etched to form a storagenode contact hole 21 to expose the surface offirst polysilicon plug 13 between bit lines 15 (referred to as “self-aligned contact” below). Then, storagenode contact mask 20 is removed. - As shown in FIG. 2C, a polysilicon film is deposited on the entire surface including storage
node contact hole 21, and then, the polysilicon film is etched back to form a second polysilicon plug 22 (referred to as “storage node contact plug” below) which is vertically contacted withfirst polysilicon plug 13. - Then, an oxide film23 (referred to as “capacitor oxide film” below), a hard mask 24 and a
reflection preventing mask 25 are sequentially deposited onbuffer oxide film 20 including storagenode contact plug 22.Oxide film 23 determines the height and the shape of the storage node. - A storage node mask (not illustrated) is formed on
reflection preventing film 25 by using a photoresist film.Reflection preventing film 25, hard mask 24 andcapacitor oxide film 23 are etched by utilizing the storage node mask to form aconcave part 26 so as to expose a surface of storagenode contact plug 22. - As shown in FIG. 2D, the storage node mask is removed, and then, a
storage node 27 is formed only inconcave part 26. Prominences, such as meta-stable polysilicon (MPS) 28, are grown. - The process of forming
storage node 27 andMPS 28 is performed in the following manner. First, without isolating the cells from each other,MPS 28 is grown on the surface ofstorage node 27.Storage node 27 is isolated by performing a chemical-mechanical polishing. Or, alternatively,storage node 27 is first isolated, and then, MPS 28 is grown on its surface. Then, adielectric node 29 and aplate node 30 are sequentially deposited on the entire surface includingisolated storage nodes 27. - In the above described conventional technique, the buffer oxide film is also etched during etching of the capacitor oxide film. As show in FIG. 3A, the storage node contact plug protrudes above the barrier nitride film (Section B by about 1000 Å (refer to the portion B of FIG. 3a). As a result, the area of the storage node is decreased. Particularly as shown in FIG. 3B, if a misalignment occurs during the process of forming the storage node mask, a bridge is formed between the storage node and an adjacent storage node contact plug (Section B′ of FIG. 3B).
- Further, when forming the storage node plug, if a misalignment occurs during the contact mask process, then a current leakage occurs between the bit line and the storage node contact plug. This current leakage affects the yield of the self-aligned contact etching (SAC). Particularly, in the 0.13 μm semiconductor product group, in which a fine wiring width is applied, this phenomenon has more serious consequences.
- Further, in the above described conventional technique, the chemical-mechanical polishing (CMP) is performed for isolating the storage node after forming the MPS, and thus, the MPS grains are broken. Further, the broken pieces of the grains are not completely removed during a subsequent wet wash process, and therefore, the broken pieces remain buried within the storage node.
- Thus, in the dielectric medium which is deposited by the chemical vapor deposition method (CVD), an increases in the leakage current in the capacitor occurs. An increase in leakage current may also be caused by due a stepped difference cladding of the upper electrode. Further, if the MPS pieces are buried between the storage nodes, then a bridge is formed, thereby generating double-bit defects.
- The effects of chemical-mechanical polishing carried out after the formation of the MPS is overcome by the method described herein. That is, the storage nodes are isolated from each other by performing a chemical-mechanical polishing, and then, the MPS is grown on the surface of the storage node.
- This method may overcome the breaking of the MPS grains during the chemical-mechanical polishing. However, an MPS seed will be partly grown on the uppermost non-crystalline silicon layer of the storage node (which is the lower electrode) during the growing of the MPS (this will be called “out-growing” below). As a result, either the gaps between the storage nodes are narrowed, or in a worst case, bridges are formed between the nodes, thereby generating double-bit defects.
- An aspect related to the present invention provides a method for fabricating a semiconductor device in which there can be prevented the formation of bridges between storage nodes and storage node contact plugs and between bit lines and the storage node contact plugs due to a misalignment in the masking process.
- Another aspect related to the present invention provides a method for fabricating a capacitor in which MPS growing can be carried out on the uppermost surface of the storage node, and the formation of bridges between the storage nodes during the MPS out-growing can be inhibited.
- Another aspect related to the present invention provides a method for fabricating a capacitor in which the reduction of the area of the storage node due to the exposure of the storage node contact plug after an etch of the capacitor oxide film can be inhibited.
- In one aspect related to the present invention, a method for fabricating a contact plug according to the present invention includes the steps of forming an insulating film on a semiconductor substrate; selectively etching the insulating film to form a contact hole so as to expose the semiconductor substrate; forming a spacer on a side wall of the contact hole; and plugging a conductive film into the contact hole.
- In another aspect of the present invention, a method for fabricating a capacitor according to the present invention includes the steps of forming a first insulating film on a semiconductor substrate, and forming a contact plug through the first insulating film; sequentially forming an etch barrier film and a second insulating film upon the first insulating film; sequentially etching the second insulating film and the etch barrier film to form an opening part so as to expose the contact plug; forming a conductive film on the second insulating film and on the opening part; selectively etching the conductive film, with the conductive film being over-etched relative to the second insulating film, so as to form a storage node within the opening part; forming prominences on a surface of the storage node; and sequentially forming a dielectric film and a plate node upon the storage node.
- In still another aspect of the present invention, a method for fabricating a semiconductor device according to the present invention includes the steps of forming a first insulating film on a semiconductor substrate; forming a plurality of bit lines on the first insulating film; forming a contact hole through the first insulating film between the bit lines to reach the semiconductor substrate; forming a spacer on a side wall of the contact hole; forming a first contact plug, the first contact plug being buried into the contact hole to reach the semiconductor substrate; sequentially forming an etch barrier film and a second insulating film on the first insulating film and upon the first contact plug; sequentially etching the second insulating film and the etch barrier film to form an opening part so as to expose the first contact plug; forming a first conductive film on an entire surface (including the opening part); selectively etching the first conductive film, with the first conductive film being over-etched relative to the second insulating film, so as to form a storage node within the opening part; and sequentially forming a dielectric film and a plate node upon the storage node.
- Additional aspects related to the present invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Certain aspect related to the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
- The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several aspects related to the present invention and together with the description, serve to explain the principles of the invention.
- FIG. 1 is a plan view of a conventional general semiconductor device;
- FIGS. 2A to2D are cross-sectional views showing a conventional fabricating method for a semiconductor device;
- FIG. 3A illustrates an effect of a projection in a storage node contact plug formed by a conventional method;
- FIG. 3B illustrates the formation of a short circuit between a storage node and an adjacent storage node contact plug by a conventional method;
- FIGS. 4A to4D are cross-sectional views showing a contact plug fabrication method according to the present invention;
- FIGS. 5A to5J are cross-sectional views showing a semiconductor device fabrication method according to the present invention;
- FIG. 6 illustrates a semiconductor device which is fabricated according to the present invention; and
- FIG. 7 illustrates a semiconductor device which is fabricated according to the present invention.
- Reference will now be made in detail to various aspects related to the present invention, examples of which are illustrated in the accompanying drawings. The present invention will be described in detail referring to the attached drawings in such a manner that the present invention can be easily carried out by those ordinarily skilled in the art. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
- FIGS. 4a to 4 d are cross-sectional views showing a contact plug fabrication method in one aspect related to the present invention.
- As shown in FIG. 4A, a
word line 42 is formed on asemiconductor substrate 41, with a gate oxide film (not illustrated) involved therein. Then an ion implantation is performed onsemiconductor substrate 41 and on the both sides ofword line 42, thereby forming an LDD (lightly doped drain)junction 43. Then a spacer insulating film is deposited on the entire surface includingword line 42. - Then, the spacer insulating film is etched back to form a
word line spacer 44.Word line spacer 44 contacts both of the sidewalls ofword line 42. Then an ion implantation is performed usingword line spacer 44 andword line 42 as a mask to form a source/drain 45 which is electrically connected toLDD junction 43. - Then, on
semiconductor substrate 41 on whichword line 42 and source/drain 45 have been formed, an interlayer insulating film (ILD) 46 is deposited and flattened. Then, acontact mask 47 is formed oninterlayer insulating film 46 by using a photoresist film. - As shown in FIG. 4B,
interlayer insulating film 46 is etched by usingcontact mask 47 to form acontact hole 49 exposing relevant portions of source/drain 45. Then, contactmask 47 is removed. Anitride film 48 is then deposited on the entire surface includingcontact hole 49. - As shown in FIG. 4C, the
nitride film 48 is etched away to form anitride film spacer 48 a on the inside wall ofcontact hole 49.Nitride film spacer 48 a is formed to a thickness ranging from 100 Å to 200 Å, and during the etching of the nitride film, an over-etching of 30% is performed, so that any residual nitride film on the source/drain can be removed. - As shown in FIG. 4D, a conductive material for the plug is deposited on interlayer insulating
film 46 includingcontact hole 49 in which nitridefilm spacer 48 a has been formed. Then an etch-back or a chemical-mechanical polishing is performed to form aplug 49 a which is buried incontact hole 49. - The conductive material for the plug is one or more material selected from a group consisting of: polysilicon, tungsten (W), tungsten silicide (W-silicide), TiN, TiAlN, TaSiN, TiSiN, TaN, TaAlN, TiSi and TaSi. The conductive film for the plug is deposited by applying a method selected from a group consisting of a chemical vapor deposition method (CVD), a physical vapor deposition method (PVD), and an atomic layer deposition method (ALD).
- In the case of deposition of the polysilicon as the conductive material for the plug, a low pressure chemical vapor deposition method (LP-CVD) or a rapid thermal process (RTP) is performed, and thus, a doped polysilicon is deposited in which phosphorus atoms of 2×1020 atoms/cc or more are doped.
- In the above aspect related to the present invention, the nitride spacer is formed on the inside wall of the contact hole prior to the formation of the plug, and therefore, even if a misalignment occurs during the contact mask process, any current leakage between the plug and the bit line can be inhibited.
- FIG. 5A to5H are cross-sectional views showing the semiconductor device fabricating method in another aspect related to the present invention. As shown in FIG. 5A, on a
semiconductor substrate 51 on which a transistor has been formed and which includes aword line spacer 52 a, aword line 52, and a source/drain 53 of anLDD junction structure 53 a, the following process steps are performed. That is, a firstinterlayer insulating film 54 is deposited, and then, a contact mask (not illustrated) is formed on firstinterlayer insulating film 54 by using a photoresist film. Then, firstinterlayer insulating film 54 is etched using the contact mask to form a contact hole thereby exposing source/drain 53. Then, a first conductive film for the plug is deposited on the entire surface, and the first conductive film is selectively removed by etching or chemical-mechanical polishing until the surface of firstinterlayer insulating film 54 is exposed, thereby forming afirst contact plug 55. - In this case,
first contact plug 55 contacts a bit line and a storage node contact, which are to be formed later. In the drawing, only the portion where the storage node contact is to be contacted is illustrated. - A second
interlayer insulating film 56 is formed on the entire surface, and then, abit line 57 with abit line spacer 57 a is formed on secondinterlayer insulating film 56,bit line 57crosses word line 52. Alternatively, a contact hole is formed prior to the formation ofbit line 57, exposing the surface offirst contact plug 55. Thus a bit line contact (not illustrated) may be formed to makebit line 57contact semiconductor substrate 51. - Next, a third
interlayer insulating film 58 is formed on the entire surface includingbit line 57. A storage node contact mask (not illustrated) is then formed on thirdinterlayer insulating film 58 by using a photoresist film. Thirdinterlayer insulating film 58 a and secondinterlayer insulating film 56 are etched to form a contact hole for a storage node contact plug, thereby exposing the surface offirst contact plug 55 betweenbit line 57 andword line 52. - In this step, during the etching of second and third
interlayer insulating films first contact plug 55. Then, afirst nitride film 59 is deposited on the entire surface includingcontact hole 58 a. - As shown in FIG. 5B,
first nitride film 59 is thoroughly etched to form anitride film spacer 60 on the sidewalls ofcontact hole 58 a, and then, a secondconductive film 61 is deposited on the entire surface includingnitride film spacer 60. - In this step, an over-etching of 30% is performed during the thorough etching of
first nitride film 59 which is formed by using tungsten or polysilicon. In the case where the polysilicon is used, a low pressure chemical vapor deposition method (LP-CVD) or a rapid thermal process (RTP) is employed, with a doping concentration preferably of 2×1020 atoms/cc or more of phosphorus (P). - As shown in FIG. 5C, second
conductive film 61 is etched back to form a second contact plug 62 (referred to as “storage node plug’ below) which is vertically connected tofirst contact plug 55. Then, asecond nitride film 63 is formed on thirdinterlayer insulating film 58 including storagenode contact plug 62. - In this step,
second nitride film 63 serves as an etch barrier during a dry etch and a wet etch performed on a capacitor oxide film later.Second nitride film 63 is deposited to a thickness ranging from 200 Å to 800 Å by employing a low pressure chemical vapor deposition method (LP-CVD), a plasma chemical vapor deposition method (PE-CVD), or a rapid thermal process (RTP). - As shown in FIG. 5D, a
capacitor oxide film 64, ahard mask 65 and areflection preventing film 66 are sequentially deposited onsecond nitride film 63, withcapacitor oxide film 64 determining the height and shape of the storage node. -
Capacitor oxide film 64 is deposited to a desired thickness by utilizing plasma enhanced tetraethyl orthosilicate (PE-TEOS) or phosphosilicate glass (PSG). Generally, in the case where a wiring process of 0.16 μm or less is utilized, there is required a deposition thickness of 12,000 Å or more forcapacitor oxide film 64, so that a capacitance of 25 fF/cell or more (the area for the storage node) can be obtained. - Further, for
hard mask 65, a doped or undoped polysilicon is deposited to have a thickness ranging from 500 Å to 2000 Å at a temperature of 500° C. to 650° C. - Further, to form
reflection preventing film 66, an inorganic material (such as SiON) or organic material is deposited or coated to have a thickness ranging from 300 Å to 1000 Å, so that the forthcoming masking process may be performed easily. - Then, a
storage node mask 67 is formed onreflection preventing film 66 by using a photoresist film.Reflection preventing film 66,hard mask 65, andcapacitor oxide film 64 are etched by utilizingstorage node mask 67. - In this step, in order to make
second nitride film 63 serve as an etch barrier during etching ofcapacitor oxide film 64, there should be adopted an etch selectivity ratio of 5:1 to 20:1 betweencapacitor oxide film 64 andsecond nitride film 63. - As shown in FIG. 5E, the photoresist film, i.e.,
storage node mask 67 is stripped. In this step,reflection preventing film 66 which is made of a material similar to that of the photoresist film is removed simultaneously. - Then,
second nitride film 63, which has been exposed upon etchingcapacitor oxide film 64, is etched by using residualhard mask 65 as the etch mask (after removing reflection preventing film 66). Thus aconcave part 64 a is formed to expose the surface of storagenode contact plug 62. In this step,second nitride film 63 is over-etched by 10% to 50%, thereby completely exposing the surface of storagenode contact plug 62. - After etching of
second nitride film 63, a light dry etching is carried out using oxygen (O2) plasma, so that the foreign materials on the surface of storage node contact plug 62 can be removed once more, thereby decreasing the boundary resistance between the storage node and storagenode contact plug 62. - As shown in FIG. 5F, residual
hard mask 65 is removed in such a manner that an entire etch-back is carried out, thereby making the residual hard mask remain on the cell regions and on the peripheral circuit regions. - Then, a third
conductive film 68 is deposited on the entire surface includingconcave part 64 a, and then, aphotoresist film 69 is deposited to have a thickness ranging from 0.5 μm to 1.5 μm on the entire surface including thirdconductive film 68. Then, an etch-back is carried out to expose the upper face of thirdconductive film 68, and thus,photoresist film 69 remains only in the concave part. - As shown in FIG. 5G, without removing
residual photoresist film 69, third conductive film 68 (not shown) is etched back to form astorage node 70 withinconcave part 64 a, and then,residual photoresist film 69 is removed. - In this step, third
conductive film 68 is formed into thestorage node 70. Thirdconductive film 68 comprises one or more materials selected from the group consisting of: a silicon-based material such as a doped polysilicon (D-poly Si) and a doped non-crystalline silicon; metals such as TiN, TaN, W, WN, Ru, Ir, and Pt; metal oxides such as RuO2 and IrO2; and WSi. In the case where polysilicon is used forstorage node 70, the polysilicon is etched by only 300 Å to 1000 Å when formingstorage node 70. - Thus, when forming
storage node 70, etching results in more etching on the polysilicon due to the selection ratio between the capacitor oxide film and the polysilicon of the first conductive film, with the result that the capacitor oxide film protrudes up. Then, prominences, such asMPS 71, are grown on the surface ofstorage node 70. - As shown in FIG. 5H, after the growing of
MPS 71, a doping is performed under a P (phosphorus)-containing atmosphere. In this step, when a negative bias is supplied, a P depletion region is formed to reduce capacitance. In order to prevent this phenomenon, the doping process is performed. - One example of a doping process is a thermal doping that is performed under a phosphorus gas atmosphere ranging from 1% to 5% PH3/N2 or PH3/H3, 50 sccm to 2000 sccm. In this case, the thermal doping is performed at a low temperature of 600±50° C. for 30 to 120 minutes under a pressure ranging from 1 to 100 Torr within an electric furnace.
- A second example of the doping is a plasma glow discharge that is performed with an radio frequency (RF) power of ranging from 100 W to 500 W for 30 to 120 seconds under a PH3 atmosphere.
- A third example of the doping is the rapid thermal process (RTP) in which a radiation heat is utilized at a temperature ranging from 750° C. to 950° C. for 30 to 120 seconds under a PH3 atmosphere.
- As shown in FIG. 51, a wet cleaning is performed in order to remove organic and metallic components and naturally formed oxide films, so that the doping effect can be maximized. The wet cleaning is performed in two stages. That is, a first stage is performed with a sulfuric acid solution, and a second stage is performed with a fluoric acid solution.
- As shown in FIG. 5J, a
dielectric film 72 is formed onstorage node 70 on whichMPS 71 has been formed, and then, aplate node 73 is formed upondielectric film 72, thereby completing the concave capacitor of the present invention. - In this step,
plate node 73 is formed of the same material as that ofstorage node 70. That is, it is formed with one or more material selected from the group consisting of: a silicon-based material such as a doped polysilicon (D-poly Si) and a doped non-crystalline silicon; metals such as TiN, TaN, W, WN, Ru, Ir and Pt; and metal oxides such as RuO2 and IrO2. - In the case where
plate node 73 is formed with TiN, a doped polysilicon film can be stacked as a shock-absorbing layer, so that structural stability can be obtained, and so that the life expectancy of TiN can be extended by protecting against thermal and electrical shocks. - In order to ensure the capacitance,
storage node 70 may be formed in a three-dimensional shape such as double or triple structures including a cylindrical structure as illustrated in FIG. 6, with prominences, such as MPS, being added. -
Dielectric film 72 may consist of a ferroelectric film or a high dielectric constant film selected from the group consisting of: Ta2O5; STO (SrTiO3); BST ((BaSr)TiO3); PZT ((Pb) (Zr, Ti)O3); PLZT((Pb, La) (Zr, Ti)O3); BTO (BaTiO3); PMN (Pb(Ng⅓Nb⅔)O3); SBTN ((Sr,Bi)(Ta, Nb)2O9); SBT ((Sr, Bi)Ta2O9); BLT ((Bi, La)Ti3O12); BT (BaTiO3); ST (SrTiO3); and PT (PbTiO3). - FIG. 6 illustrates the semiconductor device fabricated according to another aspect related to the present invention. Referring to FIG. 6, the process is performed in the same manner as that of the process illustrated in FIGS. 5A-5H up to the formation of
dielectric film 72. However, prior to the formation ofdielectric film 72,capacitor oxide film 64 is wet-removed to makeonly storage node 70 remain. Then,dielectric film 72 andplate node 73 are deposited, thereby forming a cylindrical capacitor. - FIG. 7 illustrates the semiconductor device fabricated according to another aspect related to the present invention. Referring to FIG. 7, the process is performed in the same manner as that of the process illustrated in FIG. 5A-5H, except that a
nitride film spacer 74 is formed on the wall of each of contact holes 54 a and 58 a for first and second contact plugs 55 and 62. - That is,
nitride film spacers first contact plug 55 andword line 52 and betweensecond contact plug 62 and bitline 57. - In the processes illustrated in FIGS. 6 and 7, the dielectric film consists of a ferroelectric film or a high dielectric constant film selected from the group consisting of: Ta2O5; STO (SrTiO3); BST ((BaSr)TiO3); PZT ((Pb) (Zr, Ti)O3), PLZT ((Pb, La) (Zr, Ti)O3); BTO (BaTiO3); PMN (Pb(Ng⅓Nb⅔)O3); SBTN ((Sr,Bi)(Ta, Nb)2O9); SBT ((Sr, Bi)Ta2O9); BLT ((Bi, La)Ti3O12); BT (BaTiO3); ST (SrTiO3); and PT (PbTiO3).
-
Dielectric film 72 is deposited by applying one method selected from among a metal organic deposition method, a zol gel method, a spin-on method, a chemical deposition method (CVD), an atomic layer deposition method (ALD); and a physical vapor deposition method (PVD). -
Storage node 70 andplate node 73 are formed with one material selected from the group consisting of: a silicon-based material such as a doped polysilicon (D-poly Si) and a doped non-crystalline silicon; metals such as TiN, TaN, W, WN, Ru, Ir and Pt; metal oxides such as RuO2 and IrO2; and WSi. - Particularly, in the case where
plate node 73 is formed with TiN, a doped polysilicon film can be stacked, so that structural stability can be obtained, and the life expectancy of TiN can be extended by protecting against thermal and electrical shocks. - In order to ensure the capacitance, there may be formed a three-dimensional shape such as double or triple structures including a cylindrical structure, with prominences, such as the MPS being added.
- The present invention is applicable not only to capacitors connected to a source/drain, but also to capacitors connected to a conductive layer such as a gate electrode. Further, it can be applied not only to a capacitor over bit line (COB) structure, but also to a capacitor under bit line (CUB) structure of semiconductor devices.
- According to the present invention as described above, even if a misalignment occurs during a storage node masking process, any current leakage can be inhibited between bit lines and storage node contact plugs.
- Further, an etch-back is performed for isolating the storage nodes from each other, and then, MPS is formed, so that the formation of any bridge between storage nodes can be inhibited, thereby preventing any electrical defects such as double-bit defects.
- Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
Claims (6)
1. A method for fabricating a contact plug, comprising:
forming an insulating film on a semiconductor substrate;
selectively etching the insulating film to form a contact hole so as to expose the semiconductor substrate;
forming a spacer on a side wall of the contact hole; and
depositing a conductive film into the contact hole.
2. The method as claimed in claim 1 , wherein forming the spacer comprises:
forming a nitride film on an entire surface including the contact hole; and
thoroughly etching the nitride film to form the spacer.
3. The method as claimed in claim 2 , wherein the nitride film is deposited to a thickness ranging from 100 Å to 200 Å.
4. The method as claimed in claim 1 , wherein forming the contact hole comprises over-etching the insulating film by 30%.
5. The method as claimed in claim 1 , wherein the conductive film is formed with one or more materials selected from a group comprising polysilicon, aluminum, molybdenum, and tungsten.
6-22. (Cancelled)
Priority Applications (1)
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US10/885,865 US20040241940A1 (en) | 2001-09-14 | 2004-07-08 | Method for fabricating semiconductor device |
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KR10-2001-0056742A KR100418573B1 (en) | 2001-09-14 | 2001-09-14 | Method for fabricating semiconductor device |
KR2001-56742 | 2001-09-14 | ||
US10/238,637 US6777305B2 (en) | 2001-09-14 | 2002-09-11 | Method for fabricating semiconductor device |
US10/885,865 US20040241940A1 (en) | 2001-09-14 | 2004-07-08 | Method for fabricating semiconductor device |
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US10/238,637 Division US6777305B2 (en) | 2001-09-14 | 2002-09-11 | Method for fabricating semiconductor device |
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US10/238,637 Expired - Lifetime US6777305B2 (en) | 2001-09-14 | 2002-09-11 | Method for fabricating semiconductor device |
US10/885,865 Abandoned US20040241940A1 (en) | 2001-09-14 | 2004-07-08 | Method for fabricating semiconductor device |
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US20050042835A1 (en) * | 2003-08-19 | 2005-02-24 | International Business Machines Corporation | Metal-insulator-metal capacitor and method of fabricating same |
US6949457B1 (en) * | 2004-01-21 | 2005-09-27 | Kla-Tencor Technologies Corporation | Barrier enhancement |
US20060017118A1 (en) * | 2004-07-21 | 2006-01-26 | Park Je-Min | Semiconductor device having spacer pattern and method of forming the same |
US20060141699A1 (en) * | 2004-12-28 | 2006-06-29 | Hynix Semiconductor Inc. | Method for fabricating semiconductor memory device |
US20060183319A1 (en) * | 2003-02-22 | 2006-08-17 | Ju-Bum Lee | Method for manufacturing a semiconductor device |
US20070082492A1 (en) * | 2005-10-12 | 2007-04-12 | Samsung Electronics Co., Ltd. | Semiconductor memory device and method of fabricating the same |
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Citations (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5521121A (en) * | 1995-04-03 | 1996-05-28 | Taiwan Semiconductor Manufacturing Company | Oxygen plasma etch process post contact layer etch back |
US5597756A (en) * | 1995-06-21 | 1997-01-28 | Micron Technology, Inc. | Process for fabricating a cup-shaped DRAM capacitor using a multi-layer partly-sacrificial stack |
US5597754A (en) * | 1995-05-25 | 1997-01-28 | Industrial Technology Research Institute | Increased surface area for DRAM, storage node capacitors, using a novel polysilicon deposition and anneal process |
US6010942A (en) * | 1999-05-26 | 2000-01-04 | Vanguard International Semiconductor Corporation | Post chemical mechanical polishing, clean procedure, used for fabrication of a crown shaped capacitor structure |
US6146968A (en) * | 1998-12-09 | 2000-11-14 | Taiwan Semiconductor Manufacturing Corp. | Method for forming a crown capacitor |
US6153510A (en) * | 1997-02-27 | 2000-11-28 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same, and semiconductor memory device and method for manufacturing the same |
US6163047A (en) * | 1999-07-12 | 2000-12-19 | Vanguard International Semiconductor Corp. | Method of fabricating a self aligned contact for a capacitor over bitline, (COB), memory cell |
US6165840A (en) * | 1998-04-29 | 2000-12-26 | Samsung Electronics Co., Ltd. | Method for fabricating a DRAM cell capacitor including forming first multilayer insulator, forming conductive plug, forming second insulator, and etching second and first insulators to form the storage node |
US6184081B1 (en) * | 1999-10-08 | 2001-02-06 | Vanguard International Semiconductor Corporation | Method of fabricating a capacitor under bit line DRAM structure using contact hole liners |
US6214689B1 (en) * | 1998-03-02 | 2001-04-10 | Samsung Electronics Co., Ltd. | Apparatus for manufacturing semiconductor device, method of manufacturing capacitor of semiconductor device thereby, and resultant capacitor |
US6218260B1 (en) * | 1997-04-22 | 2001-04-17 | Samsung Electronics Co., Ltd. | Methods of forming integrated circuit capacitors having improved electrode and dielectric layer characteristics and capacitors formed thereby |
US6225160B1 (en) * | 1999-04-20 | 2001-05-01 | United Microelectronics, Corp. | Method of manufacturing bottom electrode of capacitor |
US6228700B1 (en) * | 1999-09-03 | 2001-05-08 | United Microelectronics Corp. | Method for manufacturing dynamic random access memory |
US6232175B1 (en) * | 1999-10-08 | 2001-05-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing double-recess crown-shaped DRAM capacitor |
US6232178B1 (en) * | 1998-11-11 | 2001-05-15 | Nec Corporation | Method for manufacturing capacitive element |
US6274426B1 (en) * | 1999-02-25 | 2001-08-14 | Taiwan Semiconductor Manufacturing Company | Self-aligned contact process for a crown shaped dynamic random access memory capacitor structure |
US6348709B1 (en) * | 1999-03-15 | 2002-02-19 | Micron Technology, Inc. | Electrical contact for high dielectric constant capacitors and method for fabricating the same |
US6436763B1 (en) * | 2000-02-07 | 2002-08-20 | Taiwan Semiconductor Manufacturing Company | Process for making embedded DRAM circuits having capacitor under bit-line (CUB) |
US6562679B2 (en) * | 2000-08-28 | 2003-05-13 | Hynix Semiconductor, Inc. | Method for forming a storage node of a capacitor |
US20030092277A1 (en) * | 2001-10-02 | 2003-05-15 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating semiconductor device |
US6717202B2 (en) * | 1998-09-04 | 2004-04-06 | Renesas Technology Corp. | HSG semiconductor capacitor with migration inhibition layer |
US6852579B2 (en) * | 1996-05-30 | 2005-02-08 | Hitachi, Ltd. | Method of manufacturing a semiconductor integrated circuit device |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20000027785A (en) * | 1998-10-29 | 2000-05-15 | 김영환 | Method of forming capacitor for semiconductor device |
KR100296915B1 (en) * | 1998-12-30 | 2001-08-07 | 박종섭 | Method of manufacturing capacitor of semiconductor device _ |
JP2001053246A (en) | 1999-06-02 | 2001-02-23 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
KR100334393B1 (en) * | 1999-06-30 | 2002-05-03 | 박종섭 | Fabricating method for semiconductor device |
KR100309077B1 (en) | 1999-07-26 | 2001-11-01 | 윤종용 | Triple metal 1t/1c ferroelectric capacitor and method for fabricating thereof |
JP2001053249A (en) | 1999-08-05 | 2001-02-23 | Tokyo Electron Ltd | Semiconductor device and manufacture thereof |
KR20010046152A (en) * | 1999-11-10 | 2001-06-05 | 박종섭 | Method of fabrication capacitor in high capacity of memory device |
KR20010046663A (en) * | 1999-11-15 | 2001-06-15 | 윤종용 | method of forming buried contact hole for use in capacitor lower electrode semiconductor memory device |
KR20010063777A (en) * | 1999-12-24 | 2001-07-09 | 박종섭 | Method for manufacturing semiconductor device |
KR20010068611A (en) * | 2000-01-07 | 2001-07-23 | 박종섭 | Capacitor forming method |
-
2001
- 2001-09-14 KR KR10-2001-0056742A patent/KR100418573B1/en active IP Right Grant
-
2002
- 2002-09-11 US US10/238,637 patent/US6777305B2/en not_active Expired - Lifetime
-
2004
- 2004-07-08 US US10/885,865 patent/US20040241940A1/en not_active Abandoned
Patent Citations (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5521121A (en) * | 1995-04-03 | 1996-05-28 | Taiwan Semiconductor Manufacturing Company | Oxygen plasma etch process post contact layer etch back |
US5597754A (en) * | 1995-05-25 | 1997-01-28 | Industrial Technology Research Institute | Increased surface area for DRAM, storage node capacitors, using a novel polysilicon deposition and anneal process |
US5597756A (en) * | 1995-06-21 | 1997-01-28 | Micron Technology, Inc. | Process for fabricating a cup-shaped DRAM capacitor using a multi-layer partly-sacrificial stack |
US6852579B2 (en) * | 1996-05-30 | 2005-02-08 | Hitachi, Ltd. | Method of manufacturing a semiconductor integrated circuit device |
US6153510A (en) * | 1997-02-27 | 2000-11-28 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same, and semiconductor memory device and method for manufacturing the same |
US6218260B1 (en) * | 1997-04-22 | 2001-04-17 | Samsung Electronics Co., Ltd. | Methods of forming integrated circuit capacitors having improved electrode and dielectric layer characteristics and capacitors formed thereby |
US20040033662A1 (en) * | 1997-04-22 | 2004-02-19 | Seung-Hwan Lee | Integrated circuit capacitors having doped HSG electrodes |
US6214689B1 (en) * | 1998-03-02 | 2001-04-10 | Samsung Electronics Co., Ltd. | Apparatus for manufacturing semiconductor device, method of manufacturing capacitor of semiconductor device thereby, and resultant capacitor |
US6165840A (en) * | 1998-04-29 | 2000-12-26 | Samsung Electronics Co., Ltd. | Method for fabricating a DRAM cell capacitor including forming first multilayer insulator, forming conductive plug, forming second insulator, and etching second and first insulators to form the storage node |
US6717202B2 (en) * | 1998-09-04 | 2004-04-06 | Renesas Technology Corp. | HSG semiconductor capacitor with migration inhibition layer |
US6232178B1 (en) * | 1998-11-11 | 2001-05-15 | Nec Corporation | Method for manufacturing capacitive element |
US6146968A (en) * | 1998-12-09 | 2000-11-14 | Taiwan Semiconductor Manufacturing Corp. | Method for forming a crown capacitor |
US6274426B1 (en) * | 1999-02-25 | 2001-08-14 | Taiwan Semiconductor Manufacturing Company | Self-aligned contact process for a crown shaped dynamic random access memory capacitor structure |
US6348709B1 (en) * | 1999-03-15 | 2002-02-19 | Micron Technology, Inc. | Electrical contact for high dielectric constant capacitors and method for fabricating the same |
US6225160B1 (en) * | 1999-04-20 | 2001-05-01 | United Microelectronics, Corp. | Method of manufacturing bottom electrode of capacitor |
US6010942A (en) * | 1999-05-26 | 2000-01-04 | Vanguard International Semiconductor Corporation | Post chemical mechanical polishing, clean procedure, used for fabrication of a crown shaped capacitor structure |
US6163047A (en) * | 1999-07-12 | 2000-12-19 | Vanguard International Semiconductor Corp. | Method of fabricating a self aligned contact for a capacitor over bitline, (COB), memory cell |
US6228700B1 (en) * | 1999-09-03 | 2001-05-08 | United Microelectronics Corp. | Method for manufacturing dynamic random access memory |
US6232175B1 (en) * | 1999-10-08 | 2001-05-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing double-recess crown-shaped DRAM capacitor |
US6184081B1 (en) * | 1999-10-08 | 2001-02-06 | Vanguard International Semiconductor Corporation | Method of fabricating a capacitor under bit line DRAM structure using contact hole liners |
US6436763B1 (en) * | 2000-02-07 | 2002-08-20 | Taiwan Semiconductor Manufacturing Company | Process for making embedded DRAM circuits having capacitor under bit-line (CUB) |
US6562679B2 (en) * | 2000-08-28 | 2003-05-13 | Hynix Semiconductor, Inc. | Method for forming a storage node of a capacitor |
US20030092277A1 (en) * | 2001-10-02 | 2003-05-15 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating semiconductor device |
Cited By (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100090223A1 (en) * | 1999-04-06 | 2010-04-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US8541844B2 (en) * | 1999-04-06 | 2013-09-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20110254068A1 (en) * | 1999-04-06 | 2011-10-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US7977750B2 (en) * | 1999-04-06 | 2011-07-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20060183319A1 (en) * | 2003-02-22 | 2006-08-17 | Ju-Bum Lee | Method for manufacturing a semiconductor device |
US7335589B2 (en) * | 2003-02-22 | 2008-02-26 | Samsung Electronics Co., Ltd. | Method of forming contact via through multiple layers of dielectric material |
US6964908B2 (en) * | 2003-08-19 | 2005-11-15 | International Business Machines Corporation | Metal-insulator-metal capacitor and method of fabricating same |
US20050042835A1 (en) * | 2003-08-19 | 2005-02-24 | International Business Machines Corporation | Metal-insulator-metal capacitor and method of fabricating same |
US6949457B1 (en) * | 2004-01-21 | 2005-09-27 | Kla-Tencor Technologies Corporation | Barrier enhancement |
US20060017118A1 (en) * | 2004-07-21 | 2006-01-26 | Park Je-Min | Semiconductor device having spacer pattern and method of forming the same |
US20060141699A1 (en) * | 2004-12-28 | 2006-06-29 | Hynix Semiconductor Inc. | Method for fabricating semiconductor memory device |
US20070082492A1 (en) * | 2005-10-12 | 2007-04-12 | Samsung Electronics Co., Ltd. | Semiconductor memory device and method of fabricating the same |
US7763542B2 (en) * | 2005-10-12 | 2010-07-27 | Samsung Electronics Co., Ltd. | Semiconductor memory device and method of fabricating the same |
US8581352B2 (en) | 2006-08-25 | 2013-11-12 | Micron Technology, Inc. | Electronic devices including barium strontium titanium oxide films |
US9202686B2 (en) | 2006-08-25 | 2015-12-01 | Micron Technology, Inc. | Electronic devices including barium strontium titanium oxide films |
US7534711B2 (en) * | 2006-12-15 | 2009-05-19 | Semiconductor Manufacturing International (Shanghai) Corporation | System and method for direct etching |
US20080146030A1 (en) * | 2006-12-15 | 2008-06-19 | Semiconductor Manufacturing International (Shanghai) Corporation | System and method for direct etching |
US7781336B2 (en) * | 2007-05-04 | 2010-08-24 | Hynix Semiconductor, Inc. | Semiconductor device including ruthenium electrode and method for fabricating the same |
US20100276804A1 (en) * | 2007-05-04 | 2010-11-04 | Jin-Hyock Kim | Semiconductor device including ruthenium electrode and method for fabricating the same |
US20080272490A1 (en) * | 2007-05-04 | 2008-11-06 | Hynix Semiconductor Inc. | Semiconductor device including ruthenium electrode and method for fabricating the same |
US8120180B2 (en) * | 2007-05-04 | 2012-02-21 | Hynix Semiconductor Inc. | Semiconductor device including ruthenium electrode and method for fabricating the same |
TWI456633B (en) * | 2007-05-04 | 2014-10-11 | Hynix Semiconductor Inc | Semiconductor device including ruthenium electrode and method for fabricating the same |
US20140120710A1 (en) * | 2010-12-15 | 2014-05-01 | SK Hynix Inc. | Semiconductor device with buried gate and method for fabricating the same |
US8975173B2 (en) * | 2010-12-15 | 2015-03-10 | SK Hynix Inc. | Semiconductor device with buried gate and method for fabricating the same |
Also Published As
Publication number | Publication date |
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KR20030023970A (en) | 2003-03-26 |
US20030054634A1 (en) | 2003-03-20 |
US6777305B2 (en) | 2004-08-17 |
KR100418573B1 (en) | 2004-02-11 |
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