US20050006747A1 - Chip mounting substrate, first level assembly, and second level assembly - Google Patents
Chip mounting substrate, first level assembly, and second level assembly Download PDFInfo
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- US20050006747A1 US20050006747A1 US10/911,363 US91136304A US2005006747A1 US 20050006747 A1 US20050006747 A1 US 20050006747A1 US 91136304 A US91136304 A US 91136304A US 2005006747 A1 US2005006747 A1 US 2005006747A1
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- lands
- mounting base
- level
- level assembly
- substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
A chip mounting substrate comprising: a mounting base defined by a first surface and a second surface opposite to the first surface; a plurality of first lands disposed on the first surface, being classified into first and second groups of the first lands; and a plurality of second lands disposed on the second surface so as to face to the first lands, being classified into first and second groups of the second lands.
Description
- This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. P2002-062893, filed on Mar. 8, 2002; the entire contents of which are incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a semiconductor device packaging technology, more specifically to a chip mounting substrate, a first level assembly using the chip mounting substrate, and a second level assembly using the first level assembly.
- 2. Description of the Related Art
- The increase in density and the progress in large-scale integration have continued in semiconductor integrated circuits. Especially in DRAM, thin and small package such as ball grid array (BGA) package has been widely used. In a conventional BGA package, a plurality of connection electrodes are disposed in a lower surface of a rectangular-shaped mounting base, the substrate is defined by the lower surface and an upper surface opposite to the lower surface. The connection electrodes include: a power supply terminal to which a power supply potential is supplied; an ground terminal to which an ground potential is supplied; a selection signal input terminal to which a selection signal of a semiconductor chip is fed; an input and output terminal to which an input is fed or from which output signal is provided; an address terminal to which an address signal is fed; and the like. A chip mounting area is assigned on the upper surface of the mounting base. A semiconductor chip is fixed to the chip mounting area by using an adhesive or the like. Tape-shaped thin film is used as the mounting base.
- Recently, high-density packaging is required in semiconductor packaging technology. The packaging area can be reduced by a configuration such that if conventional thin-type semiconductor packages are stacked. However, connection electrodes for superimposing the plurality of semiconductor packages are not provided in the thin-type semiconductor packages. Especially, in the case where plural packages using a BGA tape are stacked, it is not possible to superimpose the packages since the lands for connecting a lower level package with an upper level package are not provided. Therefore, it has been difficult to realize high-density packaging in thin-type semiconductor packages such as a BGA package.
- A chip mounting substrate comprising: a mounting base defined by a first surface and a second surface opposite to the first surface; a plurality of first lands disposed on the first surface, being classified into first and second groups of the first lands; and a plurality of second lands disposed on the second surface so as to face to the first lands, being classified into first and second groups of the second lands.
- A first level assembly comprising: a mounting base defined by a first surface and a second surface opposite to the first surface; a plurality of first lands disposed on the first surface, being classified into first and second groups of the first lands; a plurality of second lands disposed on the second surface so as to face to the first lands, being classified into first and second groups of the second lands; a plurality of straight connection paths embedded in the mounting base so as to connect the first group of the first lands with the first group of the second lands just above the first group of the first lands; and a semiconductor chip mounted on a chip mounting area assigned adjacent to the second lands on the second surface.
- A second level assembly comprising: a packaging board defined by a first surface assigning a substrate mounting area; a plurality of connection terminals disposed on the substrate mounting area; a plurality of signal terminals disposed around the substrate mounting area on the first surface of the packaging board; a plurality of signal wiring connected to the connection terminals and the signal terminals; a plurality of packaging balls disposed on the connection terminals, respectively; a mounting base disposed above the substrate mounting area, the mounting base being defined by a first surface and a second surface opposite to the first surface having a plurality of first lands disposed on the first surface, the first lands being classified into first and second groups of the first lands, a plurality of second lands disposed so as to face to the plurality of first lands on the second surface, the second lands being classified into first and second groups of the second lands, and a plurality of straight connection paths embedded in the mounting base so as to connect the first group of the first lands with the first group of the second lands just above the first group of the first lands; and a semiconductor chip mounted on a chip mounting area assigned adjacent to the second lands on the second surface.
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FIG. 1 is a perspective view showing an example of a first level assembly according to a first embodiment of the present invention. -
FIG. 2 is an example of a sectional view seen from the I-I line inFIG. 1 . -
FIG. 3 is an example of a sectional view seen from the II-II line inFIG. 1 -
FIG. 4 is an example of a bottom view of the first level assembly shown inFIG. 1 . -
FIG. 5 is a view showing an example of a connection configuration of chip connection wiring from the first lands to pads of the first level assembly according to the first embodiment of the present invention. -
FIG. 6 is a perspective view showing an example of a first level assembly according to a first modification of the first embodiment. -
FIG. 7 is a perspective view showing an example of a first level assembly according to a second modification of the first embodiment. -
FIG. 8 is a perspective view showing an example of a first level assembly according to a third modification of the first embodiment. -
FIG. 9 is a perspective view showing an example of a first level assembly having a two-level constitution according to a second embodiment of the present invention. -
FIG. 10 is an example of a sectional view seen from the line III-III inFIG. 9 -
FIG. 11 is a perspective view showing an example of a first level assembly having a three-level stacked structure according to a modification of the second embodiment of the present invention. -
FIG. 12 is an example of a sectional view seen from the line IV-IV inFIG. 11 . -
FIG. 13 is a perspective view showing an example of a mounting substrate of a second level assembly according to a third embodiment of the present invention. -
FIG. 14 is a perspective view showing an example of a packaging state of the second level assembly inFIG. 13 . - Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified. Generally, and as it is conventional in the representation of semiconductor devices, it will be appreciated that the various drawings are not drawn to scale from one figure to another nor inside a given figure, and in particular that the layer thicknesses are arbitrarily drawn for facilitating the reading of the drawings. In the following descriptions, numerous details are set forth such as specific signal values, etc. to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details.
- The assembly of levels of electronic devices is classified into several packaging levels in a hierarchy. A first level assembly in the hierarchy indicates an assembly in which a semiconductor chip is mounted on a mounting base and the like. For example, FIGS. 1 to 12 show the
first level assemblies second level assembly 400 as shown inFIG. 14 . A third level assembly indicates an assembly in which the second level assembly is mounted on a motherboard or the like. - (First Embodiment)
- The
first level assembly 100 according to a first embodiment of the present invention encompasses, as shown inFIGS. 1 and 2 : amounting base 1A which is defined by a first surface and a second surface opposite to the first surface;first lands second lands first lands holes mounting base 1A, so that some of thefirst lands second lands first lands Joint balls first lands second lands first lands mounting base 1A. In the center of the second surface of themounting base 1A, achip mounting area 2A is assigned adjacent to thesecond lands chip mounting area 2A with an adhesive and the like. - As shown in
FIG. 2 , as to thefirst lands power supply terminal 7 a, afirst ground terminal 7 b, a first interlevel connection terminal 7 c, a first intrasubstrate connection terminal 7 d, a first input andoutput terminal 7 e, and afirst address terminal 7 f can be assigned on the first surface of themounting base 1A. A powersupply joint ball 5 a, aground joint ball 5 b, a inter leveljoint ball 5 c, an intrasubstrate joint ball 5 d, an input andoutput joint ball 5 e, and an addressjoint ball 5 f are respectively connected to the firstpower supply terminal 7 a, thefirst ground terminal 7 b, the first interlevel connection terminal 7 c, the first intrasubstrate connection terminal 7 d, the first input andoutput terminal 7 e, and thefirst address terminal 7 f. Furthermore, other than the powersupply joint ball 5 a, theground joint ball 5 b, the interlevel joint ball 5 c, the intrasubstrate joint ball 5 d, the input andoutput joint ball 5 e, and the addressjoint ball 5 f, a write terminal joint ball and the like, which are not shown in the drawing are included as the joint balls. The firstpower supply terminal 7 a, thefirst ground terminal 7 b, the first input andoutput terminal 7 e, and thefirst address terminal 7 f (the first group of the first lands) are electrically connected to thesecond lands holes mounting base 1A. - Through-
holes holes level connection terminal 7 c is electrically connected to asemiconductor chip 3A by wiring provided in themounting base 1A, which is not shown in the drawing. The first intrasubstrate connection terminal 7 d (the second group of the first lands) is connected to a second interlevel connection terminal 4 c (the second group of the second lands) on the second surface detoured intra substrate connection wiring in a bent through-hole 9 (bent connection path), which has a stair-step shape and is embedded in themounting base 1A. Note that, a second interlevel connection terminal 4 c is not connected to thesemiconductor chip 3A mounted on the mountingbase 1A, nor to the otherfirst lands - An second intra
substrate connection terminal 4 d is provided on the second surface which is opposite to the first intrasubstrate connection terminal 7 d for intra substrate connection in the mountingbase 1A interposed therebetween. The second intrasubstrate connection terminal 4 d is not connected to any through-holes substrate connection terminal 4 d is also not connected to thesemiconductor chip 3A. InFIG. 2 , the second interlevel connection terminal 4 c and the second intrasubstrate connection terminal 4 d are disposed adjacent to each other, however, it is not always necessary for both terminals to be disposed adjacent to each other. That is, the second interlevel connection terminal 4 c or the second intrasubstrate connection terminal 4 d may be formed in the positions of other second lands, which are not shown in the cross section ofFIG. 2 . - As shown in
FIG. 3 , the outer periphery of thesemiconductor chip 3A is covered with achip passivating film 8. Thechip passivating film 8 is provided to prevent damage to thesemiconductor chip 3A at the time of conveying and packaging thefirst level assembly 100. Thischip passivating film 8 is implemented by insulating materials such as resin. - As shown in
FIG. 4 , awindow 41 is provided in the center of the mountingbase 1A. In thewindow 41, thesemiconductor chip 3A is exposed, which is disposed on the second surface of the mountingbase 1A. A plurality ofpads semiconductor chip 3A, and those pads are respectively connected to thefirst lands chip connection wiring FIG. 4 is thefirst level assembly 100 called a center pad, however, other pad disposition can be employed as long as thepads semiconductor chip 3A are respectively connectable to thefirst lands FIG. 4 , the first intrasubstrate connection terminal 7 d is insulated from thesemiconductor chip 3A and the other connection terminals. - As shown in
FIG. 5 , second wiring layers 42 a and 42 s are embedded in the mountingbase 1A. That is, the mountingbase 1A has three metal wiring layers. Specifically, the metal wiring layers include: afirst wiring layer 45 provided in the first surface; athird wiring layer 46 provided in the second surface; and the second wiring layers 42 a and 42 s embedded between the first surface and the second surface. For example, the power supplyjoint ball 5 a is connected to the through-hole 6 a from the firstpower supply terminal 7 a, and further connected to the embeddedpad 43 a through the secondchip connection wiring 42 a in the second wiring layer provided in the mountingbase 1A. Similar to the power supplyjoint ball 5 a, thejoint ball 5 s is connected to the embeddedpad 43 s through the secondchip connection wiring 42 s in the through-hole 6 s from afirst land 7 s. - The mounting
base 1A shown in FIGS. 1 to 5 employs a fan-out type substrate. That is, the size of the mountingbase 1A is larger than that of thechip mounting area 2A. A thin tape such as a BGA tape is used as the mountingbase 1A. As to thesemiconductor chip 3A, for example, silicon having a thickness of about 0.28 to 0.45 mm can be employed. As to thesecond lands first lands joint balls first lands second lands first lands base 1A. The first lands 7 a, 7 b, 7 c, . . . , 7 f, . . . may be embedded in the first surface of the mountingbase 1A. - As described above, according to the
first level assembly 100 of the first embodiment of the present invention, thefirst lands second lands base 1A. Accordingly, plural thin-type mounting bases 1A such as BGA tape can be stacked into a multi chip module (MCM). Moreover, for thefirst level assemblies 100 shown in FIGS. 1 to 5, all lands on the same surface have the same size. Therefore, when thefirst level assembly 100 is mounted on the packaging substrate, or when pluralfirst level assemblies 100 are stacked, for example, damage to the lands can be prevented, which is caused by applying high pressure to certain lands. A non-connection state of certain lands can be also prevented because lands are all the same size. Therefore, according to thefirst level assembly 100 shown in FIGS. 1 to 5, the mounting substrate capable of high-density packaging, and thefirst level assembly 100 using the mounting substrate can be provided. - (Modification 1-1)
- In the
first level assembly 101 according to a first modification of the first embodiment of the present invention, as shown inFIG. 6 , the plurality ofsecond lands base 1A where thechip mounting area 2A is disposed on. Thejoint balls base 1A so as to correspond accordingly to thesecond lands FIG. 6 . The constitution of other components is similar to that in thefirst level assembly 100 shown in the first embodiment. Since thefirst level assembly 101 shown inFIG. 6 also includes the first lands and the second lands on the first surface and the second surface of the thin-type mounting base 1A, respectively, the thin-typefirst level assemblies 101 is implemented by BGA tape, can be mounted in high density being stacked in multiple levels. - (Modification 1-2)
- In the
first level assembly 102 according to a second modification of the first embodiment of the present invention, as shown inFIG. 7 , thesecond lands base 1A. The opposing side is a blank space. Thejoint balls base 1A. Corresponding accordingly, thesecond lands joint balls FIG. 7 are connected to thejoint balls first level assembly 102 shown inFIG. 7 , the thin-type first level assemblies can be mounted in high density by being stacked in multiple levels, such as thefirst level assembly 100 of the first embodiment. - (Modification 1-3)
- In the
first level assembly 103 according to a third modification of the first embodiment of the present invention, as shown inFIG. 8 , aheat sink 11 is disposed so as to surround the circumference of thesemiconductor chip 3A mounted on the second surface of the mountingbase 1A. Theheat sink 11 is used a metal such as aluminum. Thefirst level assembly 103 shown inFIG. 8 can diseminate heat efficiently, which is generated from thesemiconductor chip 3A, efficiently. Accordingly, when the plurality of first level assemblies are stacked in multiple levels, damage to thefirst level assembly 103 can be prevented by diseminating the heat efficiently, which is generated from semiconductor chips, efficiently. - (Second Embodiment)
- As shown in
FIGS. 9 and 10 , in thefirst level assembly 200 according to a second embodiment of the present invention, a third surface of aupper level assembly 31 is disposed so as to face to a second surface of afirst level assembly 30. That is, thefirst level assembly 200 as shown inFIGS. 9 and 10 further includes: a upperlevel mounting base 1B defined by the third surface and a fourth surface opposite to the third surface; upper level first lands 17 a, 17 b, 17 c, . . . , 17 f, . . . disposed on the third surface; and upper level second lands 14 a, 14 b, 14 c, . . . , 14 f, . . . disposed so as to face to the upper level first lands 17 a, 17 b, 17 c, . . . , 17 f, . . . respectively on the fourth surface. Second through-holes level mounting base 1B, so that some of the upper level first lands 17 a, 17 b, 17 c, . . . , 17 f, . . . are connected to some of the upper level second lands 14 a, 14 b, 14 e, . . . , 14 f, . . . which are just above the some offirst lands Joint balls first level assembly 31. The upper level second lands 14 a, 14 b, 14 c, . . . , 14 f, . . . and the upper level first lands 17 a, 17 b, 17 c, . . . , 17 f, . . . are aligned along two sets of two lines are disposed, on opposing the sides of a square that defined the periphery on thesecond mounting base 2A. In the center of the fourth surface of theupper level assembly 31, an upper levelchip mounting area 2B is assigned adjacent to the upper level second lands 14 a, 14 b, 14 c, . . . , 14 f, . . . . A upperlevel semiconductor chip 3B as an upper level chip is fixed to the secondchip mounting area 2B with an adhesive or the like. Note that, since a fan-out type substrate is used inFIG. 9 , the upper level second lands 14 a, 14 b, 14 c, . . . , 14 f, . . . of theupper level assembly 31 are not disposed in the positions just above thefirst semiconductor chip 3A of thefirst level assembly 30. - As shown in
FIG. 10 , apower supply terminal 17 a, a ground terminal 17 b, a input andoutput terminal 17 e, and anaddress terminal 17 f of the upper level assembly 31(the first group of the upper level first lands) are respectively connected to the upper level second lands 14 a, 14 b, 14 e, and 14 f (the first group of the upper level second lands) on the fourth surface of theupper mounting base 1B, by the second through-holes level mounting base 1B. - A first inter
level connection terminal 17 c is electrically connected to the upperlevel semiconductor chip 3B by wiring, provided in the upperlevel mounting base 1B. The first intrasubstrate connection terminal 17 d (the second group of the upper level first lands) is connected to an interlevel connection terminal 14 c (the second group of the upper level first lands) on the fourth surface of thesecond mounting base 1B by a second bent through-hole 19 (bent connection path), which has a stair-step shape and is provided in thesecond mounting base 1B. The second interlevel connection terminal 14 c is not connected to the upperlevel semiconductor chip 3B, nor to the other upper level second lands 14 a, 14 b, 14 c, . . . , 14 f, . . . . - The first inter
level connection terminal 17 c of theupper level assembly 31 works as a selection signal input terminal of the upperlevel semiconductor chip 3B. That is, the first interlevel connection terminal 17 c connected to the upperlevel semiconductor chip 3B is connected to the second interlevel connection terminal 4 c of thefirst level assembly 30 through the inter leveljoint ball 15 c, and is further connected to the first intrasubstrate connection terminal 7 d and the intra substratejoint ball 5 d by the bent through-hole 9. Accordingly, it is possible to operate the upperlevel semiconductor chip 3B of theupper level assembly 31 independent of thefirst level assembly 30 by feeding the selection signal from the intra substratejoint ball 5 d of thefirst level assembly 30. A description of the other components is omitted because those components have the same constitution as that of the components in FIGS. 1 to 5. - As described above, according to the
first level assembly 200 of the second embodiment of the present invention, The thinner assembly can be made since the plate-shapedfirst level assembly 30 and theupper level assembly 31 are implemented by the BGA tape or the like, are stacked in two levels. In addition, assuming that each of thefirst level assembly 30 and theupper level assembly 31 are semiconductor recording devices, the recording capacitance of two first level assemblies can be obtained in an area required for one first assembly, by stacking thefirst level assembly 30 and theupper level assembly 31 longitudinally, whereby the recording capacitance can be increased. For example, as thefirst level assembly 30 and theupper level assembly 31 shown inFIG. 9 , a DRAM, a flash memory, a SRAM, a mixed memory logic and the like are applicable. In addition, as shown inFIG. 10 , since the first interlevel connection terminal 7 c connected to thefirst semiconductor chip 3A of thefirst level assembly 30, and the first interlevel connection terminal 17 c connected to the upperlevel semiconductor chip 3B of theupper level assembly 31 function as chip selection terminals independent of the other terminals, it is possible to operate thefirst level assembly 30 and theupper level assembly 31 independently. As described in the first embodiment, all of thesecond lands first lands first level assembly 30, and the upper level second lands 14 a, 14 b, 14 c, . . . , 14 f., and the upper level first lands 17 a, 17 b, 17 c, . . . , 17 f . . . of theupper level assembly 31 have the same topology and the same shape. Accordingly, when thefirst level assembly 30 and theupper level assembly 31 are mounted in a stacked manner, theupper level assembly 31 can adhere to thefirst level assembly 30 without being conscious of the third surface and the fourth surface of thesecond mounting base 1B. Therefore, it is possible to achieve an improvement in the packaging operation efficiency. - Note that, as shown in
FIG. 10 , when thefirst level assemblies 100 to 103 shown in FIGS. 1 to 5 are stacked in two levels, at least one or more of the second intrasubstrate connection terminal 4 d and the first intrasubstrate connection terminal 17 d are included in thesecond lands first level assembly 30 and the upper level first lands 17 a, 17 b, 17 c, . . . , 17 f, . . . of theupper level assembly 31. When thefirst level assemblies 100 to 103 are stacked in three levels, as shown inFIG. 11 , at least two or more of the first lands for upper and lower connection, and the second lands for upper and lower connection are included in the same position of the respectiveupper level assembly 32 disposed in the uppermost level, theupper level assembly 31 disposed in the middle level, and thefirst level assembly 30 disposed in the lowermost level. When the first level assemblies are stacked in n levels (n is a natural number that is 2 or more), (n−1) of the first intra substrate connection terminals, and (n−1) of the second intra substrate connection terminals are included, respectively. - When the
first level assembly 30 and theupper level assembly 31 are stacked as thefirst level assembly 200 shown inFIG. 9 , the sum of the thickness of thesecond lands first semiconductor chip 3A for avoiding the compression of thefirst semiconductor chip 3A in the lower level. For example, in the semiconductor module shown inFIG. 10 , assuming that the thickness of each of thefirst semiconductor chip 3A and the upperlevel semiconductor chip 3B is about 0.3 mm, the thickness of thesecond lands first lands semiconductor chip 3A and the upperlevel semiconductor chip 3B each having a thickness of 0.28 to 0.48 mm, and the BGA tape having the thickness of about 190 mm is usable, the BGA tape being used as thefirst mounting base 1A, and thesecond mounting base 1B. The BGA tape to be employed is one with an adhesive part of 50 mm, an insulation film of 75 mm, copper wiring of 15 mm, nickel wiring of 2 mm, gold wiring of 0.2 mm and an insulation film of 30 mm. - (Modification 2-1)
- A structure will be described in which the
first level assemblies 100 are stacked in three levels. As shown inFIGS. 11 and 12 , the third surface of theupper level assembly 31 including thesecond mounting base 1B is disposed so as to face to the second surface of thefirst level assembly 30. Furthermore, a fifth surface of theupper level assembly 32 including a upperlevel mounting base 1C as the upper level mounting base is disposed so as to face to the fourth surface of theupper level assembly 31. - As shown in
FIG. 12 , the firstfirst lands first level assembly 30 are respectively connected to thejoint balls second lands holes upper level assembly 31 connected to thejoint balls holes Joint balls upper level assembly 32 are respectively connected to the upper level second lands 14 a, 14 b, 14 f, and 14 g. Third first lands 27 a, 27 b, 27 f, and 27 g, which are connected to thejoint balls b second lands holes level connection terminal 7 c is electrically connected to thefirst semiconductor chip 3A by wiring, which is provided in thefirst mounting base 1A and is not shown in the drawing. The first intrasubstrate connection terminal 7 d is connected to the first second interlevel connection terminal 4 c of the second surface through the first bent through-hole 9 provided in thefirst mounting base 1A. The second lower surface connection dedicated terminal 17 c, which is connected to the first second interlevel connection terminal 4 c through thejoint ball 15 c, is electrically connected to the upperlevel semiconductor chip 3B by wiring which is provided in thesecond mounting base 1B and is not shown in the drawing. The first intrasubstrate connection terminal 7 e is connected to the first upper surface connectiondedicated terminal 4 d by the first bent through-hole 9 b provided in thefirst mounting base 1A. The second first intrasubstrate connection terminal 17 d, which is connected to the first upper surface connectiondedicated terminal 4 d through thejoint ball 15 d, is connected to the second upper surface connection dedicated terminal 14 c by a second bent through-hole 19 a (bent connection path) provided in thesecond mounting base 1B. The third first interlevel connection terminal 27 c, which is connected to the second upper surface connection dedicated terminal 14 c through thejoint ball 25 c, is electrically connected to thethird semiconductor chip 3C by wiring, which is provided in the upperlevel mounting base 1C and is not shown in the drawing. The first intrasubstrate connection terminal 17 e is connected to the second intrasubstrate connection terminal 14 d by the bent through-hole 19 b (bent connection path) provided in the upperlevel mounting base 1B. A first intrasubstrate connection terminal 27 d, which is connected to the second intrasubstrate connection terminal 14 d through thejoint ball 25 d, is connected to a second interlevel connection terminal 24 c by a third bent through-hole 29 a (bent connection path) provided in the upperlevel mounting base 1C. A third first intrasubstrate connection terminal 27 e, which is connected to the second intrasubstrate connection terminal 14 e through thejoint ball 25 e, is connected to a second interlevel connection terminal 24 c by a bent through-hole 29 b (bent connection path) embedded in the upperlevel mounting base 1C. The first second intrasubstrate connection terminal 4 e, the second intrasubstrate connection terminal 14 e, and the second intrasubstrate connection terminal 24 e are not connected to thesemiconductor chip 3A, the upperlevel semiconductor chip 3B, and the upperlevel semiconductor chip 3C. Note that, the upper level second lands 14 a, 14 b, 14 c, . . . , 14 g, . . . , thejoint balls first level assembly 200 shown inFIGS. 9 and 10 . - According to the
first level assembly 300 shown inFIG. 11 , since thefirst level assembly 30, theupper level assembly 31, and theupper level assembly 32, which is implemented by the BGA tape and the like, are stacked in three levels, the volume of the assembly can be made smaller. In addition, the first interlevel connection terminal 7 c, and the first intrasubstrate connection terminal first level assembly 30, theupper level assembly 31, and theupper level assembly 32, whereby it is possible to operate thefirst level assembly 30, theupper level assembly 31, and theupper level assembly 32 independently. - (Third Embodiment)
- A
second level assembly 400 according to a third embodiment of the present invention includes, as shown inFIGS. 13 and 14 : apackaging substrate 50 defined by a first surface having a firstsubstrate mounting area 51A;first connection terminals substrate mounting area 51A of the first surface;signal terminals substrate mounting area 51A;first signal wiring first connection terminals signal terminals first level assembly 56 which is disposed in the firstsubstrate mounting area 51A. - The
packaging substrate 50 further includes a secondsubstrate mounting area 51B on the first surface thereof. In a secondsubstrate mounting area 51B,second connection terminals second connection terminals signal terminals first level assembly 57 is disposed in the secondsubstrate mounting area 51B. - On the
first level assemblies first level assemblies 100 to 103, 200, and 300 shown in FIGS. 1 to 12 can be mounted. InFIG. 14 , in the firstsubstrate mounting area 51A, thefirst level assembly 56 having the same constitution as that of thefirst level assembly 200 is disposed. In the secondsubstrate mounting area 51B, thefirst level assembly 57 having the same constitution as that of thefirst level assembly 100 shown inFIG. 1 is disposed. Thefirst level assembly 57 includes: the first mountingbase 30 as a second mounting base; first lands which are disposed on the first surface of the first mountingbase 30, not shown inFIG. 14 ; and thesecond lands second lands semiconductor chip 3A as the second semiconductor chip is disposed. As shown inFIG. 14 , packaging substratejoint balls first level assembly 56 are disposed on thefirst connection terminals substrate mounting substrate 51A. The first lands of the mountingbase 30 of thefirst level assembly 56, which is not shown inFIG. 14 , are connected so as to be in contact with the packaging substratejoint balls joint balls base 30, which are not shown in the drawing. Then, the first lands are disposed so as to be in contact with thejoint balls base 31 as in the upper surface mounting base, which is not shown inFIG. 14 . - On the
second connection terminals substrate mounting area 51B as the second substrate mounting area, the packaging substratejoint balls first level assembly 57 are disposed. The first lands of the mountingbase 30 of thefirst level assembly 57, which are not shown inFIG. 14 are connected so as to be in contact with the assembling substratejoint balls - In the
first connection terminals substrate mounting area 51A, for example, included are: anADD terminal 51 a for supplying the address signal; an input andoutput terminal 51 b for supplying the input and output signal;chip selection terminals GND terminal 51 e; and aVDD terminal 51 f and the like. TheADD terminal 51 a, the input andoutput terminal 51 b, thechip selection terminals GND terminal 51 e, and theVDD terminal 51 f receive signals from theADD signal terminal 53 a, an input andoutput terminal 53 b, chipselection signal terminals GND signal terminal 53 e, and a VDD signal terminal 53 f. Thesecond connection terminals substrate mounting area 51B include: the ADD terminal 511 a for supplying the address signal; the input andoutput terminal 511 b for supplying the input and output signal; thechip selection terminals -
- the
VDD terminal 511 f, and the like. The ADD signal 511 a, the input andoutput terminal 511 b, thechip selection terminals VDD terminal 511 f receive signals from theADD signal terminal 53 a connected to thefirst signal wiring output signal terminal 53 b, the chipselection signal terminals GND signal terminal 53 e and the VDD signal terminal 53 f. Thesignal terminals ADD signal terminal 53 a, the input andoutput terminal 53 b, the chipselection signal terminals GND signal terminal 53 e and the VDD signal terminal 53 f.
- the
- According to the
second level assembly 400 of the third embodiment of the present invention, the thin-typefirst level assembly 57 using the BGA tape and the like, and thefirst level assembly 56 in which thefirst level assemblies 57 are stacked in multiple levels can be mounted onto one piece of thepackaging substrate 50. The operation of thefirst level assembly 30 and theupper level assembly 31 of thefirst level assembly 56 can be performed independently by the chipselection signal terminals - Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing form the scope thereof.
Claims (12)
1-20. (canceled)
21. A semiconductor device, comprising:
a first mounting base defined by a first surface and second surface opposite to the first surface, the first surface having a first mounting area and a plurality of first lands, the second surface having a plurality of second lands opposite to the first lands, and each of the first lands are electrically connected to one of the second lands via a first through-hole, respectively;
a first semiconductor chip mounted on the first mounting area having a plurality of first pads electrically connected to the second lands, respectively;
a second mounting base mounted on the first mounting base having a same size as the first mounting base defined by a third surface and fourth surface opposite to the third surface, the third surface having a second mounting area and a plurality of third lands, the fourth surface having a plurality of fourth lands opposite to the third lands, each of third lands is electrically connected to one of the fourth lands via a second through-hole, respectively, each of fourth lands is electrically connected to one of the first lands via a first joint ball, respectively, and
a second semiconductor chip mounted on the second mounting area having a plurality of second pads electrically connected to the first lands via the fourth lands, respectively.
22. The semiconductor device of claim 21 , wherein a distance between the first surface and the fourth surface is longer than the distance between the first surface and an upper surface of the first semiconductor chip.
23. The semiconductor device of claim 21 , wherein the first and the second mounting base are BGA tapes.
24. The semiconductor device of claim 21 , wherein the first semiconductor chip is mounted in a face down configuration on the first chip mounting area.
25. The semiconductor device of claim 21 , further comprising:
a first heat sink contacted to the first semiconductor chip.
26. The semiconductor device of claim 21 , wherein the first lands are provided in the form of matrix over the remaining area of the first mounting area on the first surface.
27. The semiconductor device of claim 21 , wherein the first lands are aligned along a plurality of lines on one side of a square defining a periphery of the first mounting base.
28. The semiconductor device of claim 21 , wherein the first joint ball is made from solder.
29. The semiconductor device of claim 21 , further comprising:
a third mounting base mounted on the second mounting base having same size as the first mounting base defined by a fifth surface and sixth surface opposite to the fifth surface, the fifth surface having a third mounting area and a plurality of fifth lands, the sixth surface having a plurality of sixth lands opposite to the fifth lands, each of the fifth lands is electrically connected to one of the sixth lands via a third through-hole, respectively, each of sixth lands is electrically connected to the first lands via a second joint ball, respectively; and a third semiconductor chip mounted on the third mounting area.
30. The semiconductor device of claim 21 , further comprising:
a packaging board having a plurality of terminals; and
a plurality of packaging balls disposed on the terminals,
wherein the terminals are connected to the second lands via the packaging balls.
31. The semiconductor device of claim 21 , further comprising:
a packaging board having a substrate mounting area;
a plurality of connection terminals disposed on the substrate mounting area;
a plurality of signal terminals disposed around the substrate mounting area on the packaging board;
a plurality of signal wiring connected to the connection terminals and the signal terminals;
a plurality of packaging balls disposed on the connection terminals, respectively, wherein the second lands are connected to the connection terminals via the packaging balls.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/911,363 US20050006747A1 (en) | 2002-03-08 | 2004-08-03 | Chip mounting substrate, first level assembly, and second level assembly |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002062893A JP2003264260A (en) | 2002-03-08 | 2002-03-08 | Semiconductor chip mounting substrate, semiconductor device, semiconductor module, and semiconductor device mounting substrate |
JPP2002-062893 | 2002-03-08 | ||
US10/382,020 US6791193B2 (en) | 2002-03-08 | 2003-03-05 | Chip mounting substrate, first level assembly, and second level assembly |
US10/911,363 US20050006747A1 (en) | 2002-03-08 | 2004-08-03 | Chip mounting substrate, first level assembly, and second level assembly |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/382,020 Continuation US6791193B2 (en) | 2002-03-08 | 2003-03-05 | Chip mounting substrate, first level assembly, and second level assembly |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050006747A1 true US20050006747A1 (en) | 2005-01-13 |
Family
ID=29196435
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US10/382,020 Expired - Fee Related US6791193B2 (en) | 2002-03-08 | 2003-03-05 | Chip mounting substrate, first level assembly, and second level assembly |
US10/911,363 Abandoned US20050006747A1 (en) | 2002-03-08 | 2004-08-03 | Chip mounting substrate, first level assembly, and second level assembly |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US10/382,020 Expired - Fee Related US6791193B2 (en) | 2002-03-08 | 2003-03-05 | Chip mounting substrate, first level assembly, and second level assembly |
Country Status (2)
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US (2) | US6791193B2 (en) |
JP (1) | JP2003264260A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080136020A1 (en) * | 2006-04-26 | 2008-06-12 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
US20100252933A1 (en) * | 2002-04-12 | 2010-10-07 | Renesas Technology Corporation | Semiconductor device |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW569416B (en) * | 2002-12-19 | 2004-01-01 | Via Tech Inc | High density multi-chip module structure and manufacturing method thereof |
US20050170609A1 (en) * | 2003-12-15 | 2005-08-04 | Alie Susan A. | Conductive bond for through-wafer interconnect |
US7608534B2 (en) | 2004-06-02 | 2009-10-27 | Analog Devices, Inc. | Interconnection of through-wafer vias using bridge structures |
JP4424420B2 (en) * | 2005-04-18 | 2010-03-03 | 株式会社村田製作所 | Electronic component module |
US7826243B2 (en) * | 2005-12-29 | 2010-11-02 | Bitmicro Networks, Inc. | Multiple chip module and package stacking for storage devices |
DE102006003377B3 (en) * | 2006-01-24 | 2007-05-10 | Infineon Technologies Ag | Semiconductor chip and electronic component has chip(s) integrated into chip housing with four sets of conductive leads connected both to external contacts and to upper and lower housing surfaces |
US20080087979A1 (en) * | 2006-10-13 | 2008-04-17 | Analog Devices, Inc. | Integrated Circuit with Back Side Conductive Paths |
US20080237823A1 (en) * | 2007-01-11 | 2008-10-02 | Analog Devices, Inc. | Aluminum Based Bonding of Semiconductor Wafers |
KR101179268B1 (en) * | 2010-08-05 | 2012-09-03 | 에스케이하이닉스 주식회사 | Semiconductor package with chip selection by through-vias |
CN103107153B (en) * | 2011-11-15 | 2016-04-06 | 精材科技股份有限公司 | Wafer encapsulation body and forming method thereof |
JP2018032141A (en) | 2016-08-23 | 2018-03-01 | 東芝メモリ株式会社 | Semiconductor device |
Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5216278A (en) * | 1990-12-04 | 1993-06-01 | Motorola, Inc. | Semiconductor device having a pad array carrier package |
US5506756A (en) * | 1994-01-25 | 1996-04-09 | Intel Corporation | Tape BGA package die-up/die down |
US5521435A (en) * | 1993-12-13 | 1996-05-28 | Fujitsu Limited | Semiconductor device and a fabrication process thereof |
US5640048A (en) * | 1994-07-11 | 1997-06-17 | Sun Microsystems, Inc. | Ball grid array package for a integrated circuit |
US5734201A (en) * | 1993-11-09 | 1998-03-31 | Motorola, Inc. | Low profile semiconductor device with like-sized chip and mounting substrate |
US5798564A (en) * | 1995-12-21 | 1998-08-25 | Texas Instruments Incorporated | Multiple chip module apparatus having dual sided substrate |
US5835355A (en) * | 1997-09-22 | 1998-11-10 | Lsi Logic Corporation | Tape ball grid array package with perforated metal stiffener |
US5895231A (en) * | 1996-10-29 | 1999-04-20 | Lg Semicon Co., Ltd. | External terminal fabrication method for semiconductor device package |
US6020629A (en) * | 1998-06-05 | 2000-02-01 | Micron Technology, Inc. | Stacked semiconductor package and method of fabrication |
US6078506A (en) * | 1997-02-13 | 2000-06-20 | Nec Corporation | Tape-ball grid array type semiconductor device having reinforcement plate with slits |
US6303997B1 (en) * | 1998-04-08 | 2001-10-16 | Anam Semiconductor, Inc. | Thin, stackable semiconductor packages |
US6313522B1 (en) * | 1998-08-28 | 2001-11-06 | Micron Technology, Inc. | Semiconductor structure having stacked semiconductor devices |
US6381141B2 (en) * | 1998-10-15 | 2002-04-30 | Micron Technology, Inc. | Integrated device and method for routing a signal through the device |
US6388333B1 (en) * | 1999-11-30 | 2002-05-14 | Fujitsu Limited | Semiconductor device having protruding electrodes higher than a sealed portion |
US6479758B1 (en) * | 2000-01-21 | 2002-11-12 | Kabushiki Kaisha Toshiba | Wiring board, semiconductor package and semiconductor device |
US6555917B1 (en) * | 2001-10-09 | 2003-04-29 | Amkor Technology, Inc. | Semiconductor package having stacked semiconductor chips and method of making the same |
US6686656B1 (en) * | 2003-01-13 | 2004-02-03 | Kingston Technology Corporation | Integrated multi-chip chip scale package |
US6798049B1 (en) * | 1999-08-24 | 2004-09-28 | Amkor Technology Inc. | Semiconductor package and method for fabricating the same |
-
2002
- 2002-03-08 JP JP2002062893A patent/JP2003264260A/en active Pending
-
2003
- 2003-03-05 US US10/382,020 patent/US6791193B2/en not_active Expired - Fee Related
-
2004
- 2004-08-03 US US10/911,363 patent/US20050006747A1/en not_active Abandoned
Patent Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5216278A (en) * | 1990-12-04 | 1993-06-01 | Motorola, Inc. | Semiconductor device having a pad array carrier package |
US5734201A (en) * | 1993-11-09 | 1998-03-31 | Motorola, Inc. | Low profile semiconductor device with like-sized chip and mounting substrate |
US5521435A (en) * | 1993-12-13 | 1996-05-28 | Fujitsu Limited | Semiconductor device and a fabrication process thereof |
US5506756A (en) * | 1994-01-25 | 1996-04-09 | Intel Corporation | Tape BGA package die-up/die down |
US5640048A (en) * | 1994-07-11 | 1997-06-17 | Sun Microsystems, Inc. | Ball grid array package for a integrated circuit |
US5798564A (en) * | 1995-12-21 | 1998-08-25 | Texas Instruments Incorporated | Multiple chip module apparatus having dual sided substrate |
US5895231A (en) * | 1996-10-29 | 1999-04-20 | Lg Semicon Co., Ltd. | External terminal fabrication method for semiconductor device package |
US6078506A (en) * | 1997-02-13 | 2000-06-20 | Nec Corporation | Tape-ball grid array type semiconductor device having reinforcement plate with slits |
US5835355A (en) * | 1997-09-22 | 1998-11-10 | Lsi Logic Corporation | Tape ball grid array package with perforated metal stiffener |
US6303997B1 (en) * | 1998-04-08 | 2001-10-16 | Anam Semiconductor, Inc. | Thin, stackable semiconductor packages |
US6020629A (en) * | 1998-06-05 | 2000-02-01 | Micron Technology, Inc. | Stacked semiconductor package and method of fabrication |
US6313522B1 (en) * | 1998-08-28 | 2001-11-06 | Micron Technology, Inc. | Semiconductor structure having stacked semiconductor devices |
US6381141B2 (en) * | 1998-10-15 | 2002-04-30 | Micron Technology, Inc. | Integrated device and method for routing a signal through the device |
US6798049B1 (en) * | 1999-08-24 | 2004-09-28 | Amkor Technology Inc. | Semiconductor package and method for fabricating the same |
US6388333B1 (en) * | 1999-11-30 | 2002-05-14 | Fujitsu Limited | Semiconductor device having protruding electrodes higher than a sealed portion |
US6479758B1 (en) * | 2000-01-21 | 2002-11-12 | Kabushiki Kaisha Toshiba | Wiring board, semiconductor package and semiconductor device |
US6555917B1 (en) * | 2001-10-09 | 2003-04-29 | Amkor Technology, Inc. | Semiconductor package having stacked semiconductor chips and method of making the same |
US6686656B1 (en) * | 2003-01-13 | 2004-02-03 | Kingston Technology Corporation | Integrated multi-chip chip scale package |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100252933A1 (en) * | 2002-04-12 | 2010-10-07 | Renesas Technology Corporation | Semiconductor device |
US7986041B2 (en) * | 2002-04-12 | 2011-07-26 | Renesas Electronics Corporation | Semiconductor device |
US20080136020A1 (en) * | 2006-04-26 | 2008-06-12 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
US7652375B2 (en) * | 2006-04-26 | 2010-01-26 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
US20100087058A1 (en) * | 2006-04-26 | 2010-04-08 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
US8030201B2 (en) | 2006-04-26 | 2011-10-04 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
US20040046262A1 (en) | 2004-03-11 |
US6791193B2 (en) | 2004-09-14 |
JP2003264260A (en) | 2003-09-19 |
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