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Número de publicaciónUS20050029618 A1
Tipo de publicaciónSolicitud
Número de solicitudUS 10/934,969
Fecha de publicación10 Feb 2005
Fecha de presentación3 Sep 2004
Fecha de prioridad30 Ene 2001
También publicado comoUS6818513, US8829641, US20040132252, US20110014764
Número de publicación10934969, 934969, US 2005/0029618 A1, US 2005/029618 A1, US 20050029618 A1, US 20050029618A1, US 2005029618 A1, US 2005029618A1, US-A1-20050029618, US-A1-2005029618, US2005/0029618A1, US2005/029618A1, US20050029618 A1, US20050029618A1, US2005029618 A1, US2005029618A1
InventoresBruce Marchant
Cesionario originalMarchant Bruce D.
Exportar citaBiBTeX, EndNote, RefMan
Enlaces externos: USPTO, Cesión de USPTO, Espacenet
Structure and method of forming a dual-trench field effect transistor
US 20050029618 A1
Resumen
A field effect transistor includes a semiconductor region of a first conductivity type and a well region of a second conductivity type over the semiconductor region. A source region of the first conductivity type is in an upper portion of the well region. A gate trench is adjacent to the source region. The gate trench extends through the well region and terminates within an upper half of the semiconductor region. A stripe trench extends through the well region and terminates within a lower half of the semiconductor region. The stripe trench is filled with a semiconductor material of the second conductivity type such that: (i) the filled stripe trench is contiguous with the well region, and (ii) the semiconductor material of the second conductivity type forms a PN junction with the semiconductor region.
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Reclamaciones(26)
1. A field effect transistor comprising:
a semiconductor region of a first conductivity type having a thickness defined by the distance between upper and lower surfaces of the semiconductor region;
a well region of a second conductivity type over the semiconductor region;
a source region of the first conductivity type in an upper portion of the well region;
a gate trench adjacent to the source region, the gate trench extending through the well region and terminating within an upper half of the semiconductor region; and
a stripe trench extending through the well region and terminating within a lower half of the semiconductor region at a depth above the bottom surface of the semiconductor region, the stripe trench being filled with a semiconductor material of the second conductivity type such that: (i) the filled stripe trench is contiguous with the well region, and (ii) the semiconductor material of the second conductivity type forms a PN junction with the semiconductor region.
2. The field effect transistor of claim 1 wherein the depth at which the trip trench terminates is substantially near the bottom surface of the semiconductor region.
3. The field effect transistor of claim 2 wherein the gate trench terminates at a depth substantially near an interface between the semiconductor region and the well region.
4. The field effect transistor of claim 1 wherein the gate trench comprises a gate dielectric lining the trench sidewalls and a gate electrode comprising polysilicon at least partially filling the gate trench so as to overlap the source region along the vertical dimension.
5. The field effect transistor of claim 1 wherein the semiconductor region is an epitaxial layer extending over a substrate.
6. The field effect transistor of claim 1 wherein the stripe trench extends substantially deeper in the semiconductor region than does the gate trench.
7. The field effect transistor of claim 1 wherein the stripe trench terminates within a portion of the semiconductor region having a lower boundary which coincides with the lower surface of the semiconductor region and an upper boundary which is above the lower surface of the semiconductor region by a distance equal to one-third of the thickness of the semiconductor region.
8. The field effect transistor of claim 1 wherein the stripe trench is completely filled with the semiconductor material of the second conductivity type.
9. A field effect transistor comprising:
a semiconductor region of a first conductivity type having a thickness defined by the distance between upper and lower surfaces of the semiconductor region;
a well region of a second conductivity type over the semiconductor region;
a plurality of gate trenches each extending through the well region and terminating within an upper half of the semiconductor region;
a plurality of source regions of the first conductivity type in an upper portion of the well region, the plurality of source regions flanking the sides of the plurality of gate trenches; and
a plurality of stripe trenches each extending through the well region and terminating within a lower half of the semiconductor region at a depth above the bottom surface of the semiconductor region, each stripe trench being filled with a semiconductor material of the second conductivity type such that: (i) the filled stripe trench is contiguous with the well region, and (ii) the semiconductor material of the second conductivity type forms a PN junction with the semiconductor region.
10. The field effect transistor of claim 9 wherein the depth at which the plurality of stripe trenches terminate is substantially near a bottom surface of the semiconductor region.
11. The field effect transistor of claim 10 wherein the plurality of gate trenches terminate at a depth substantially near an interface between the semiconductor region and the well region.
12. The field effect transistor of claim 9 wherein each of the plurality of gate trenches comprises:
a gate dielectric lining the trench sidewalls; and
a gate electrode comprising polysilicon at least partially filling the gate trench so as to overlap source regions flanking each side of the gate trench.
13. The field effect transistor of claim 9 wherein the semiconductor region is an epitaxial layer extending over a substrate.
14. The field effect transistor of claim 9 wherein the plurality of stripe trenches extend substantially deeper into the semiconductor region than do the gate trenches.
15. The field effect transistor of claim 9 wherein the plurality of stripe trenches terminate within a portion of the semiconductor region having a lower boundary which coincides with the lower surface of the semiconductor region and an upper boundary which is above the lower surface of the semiconductor region by a distance equal to one-third of the thickness of the semiconductor region.
16. The field effect transistor of claim 9 wherein the plurality of stripe trenches are spaced from one another and extend to such depth within the semiconductor region that upon applying a reverse voltage across a junction between the well region and the semiconductor region a substantial portion of the entire semiconductor region, including those portions of the semiconductor region between adjacent stripe trenches, becomes depleted of charge carriers.
17. The field effect transistor of claim 10 wherein each of the plurality of stripe trenches is completely filled with the semiconductor material of the second conductivity type.
18. A method of forming a field effect transistor comprising:
forming a well region in a semiconductor region of a first conductivity type, the well region being of a second conductivity type and having an upper surface and a lower surface;
forming a plurality of gate trenches extending into the semiconductor region to a depth below the lower surface of the well region;
forming a plurality of stripe trenches extending through the well region and into the semiconductor region to a depth below that of the plurality of gate trenches, the plurality of stripe trenches being laterally spaced from one or more of the plurality of gate trenches; and
at least partially filling the plurality of stripe trenches with a semiconductor material of the second conductivity type such that the semiconductor material of the second conductivity type forms a PN junction with a portion of the semiconductor region.
19. The method of claim 18 wherein the plurality of stripe trenches extend into the semiconductor region parallel to a current flow through the semiconductor region when the field effect transistor is in an on state.
20. The method of claim 18 wherein the plurality of stripe trenches are completely filled with the semiconductor material of the second conductivity type using selective epitaxial growth.
21. The method of claim 18 wherein the semiconductor material of the second conductivity type lines the sidewalls of the plurality of stripe trenches, the method further comprising:
forming a dielectric material within the plurality of stripe trenches such that each stripe trench becomes substantially completely filled with the combination of the semiconductor material of the second conductivity type and the dielectric material.
22. The method of claim 18 wherein the plurality of stripe trenches are formed after forming the plurality of gate trenches and the well region.
23. The method of claim 18 wherein the semiconductor region is an epitaxial layer of the first conductivity type in which the well region is formed, the epitaxial layer having a thickness defined by the spacing between an upper surface and a lower surface of the epitaxial layer, wherein the plurality of stripe trenches extend into the epitaxial layer and terminate at a depth between one-half the thickness of the epitaxial layer and the lower surface of the epitaxial layer.
24. The method of claim 18 wherein the semiconductor region has a thickness defined by the vertical distance between an upper surface and a lower surface of the semiconductor region, the plurality of stripe trenches terminating within a portion of the semiconductor region having a lower boundary which coincides with the lower surface of the semiconductor region and an upper boundary which is above the lower surface of the semiconductor region by a distance equal to one-third of the thickness of the semiconductor region.
25. The method of claim 20 further comprising forming source regions in the well region.
26. The method of claim 25 wherein the semiconductor region comprises an epitaxial layer and a substrate both of the first conductivity type, the substrate forming a drain contact region, the method further comprising:
forming the epitaxial layer over the substrate, the well region being formed in the epitaxial layer, and the plurality of stripe trenches and gate trenches extending into and terminating within the epitaxial layer.
Descripción
    CROSS-REFERENCES TO RELATED APPLICATIONS
  • [0001]
    This application is a continuation of U.S. application Ser. No. 10/741,464, filed Dec. 18, 2003, which is a division of U.S. Pat. No. 6,713,813 issued Mar. 30, 2004, which disclosures are incorporated herein by reference for all purposes.
  • BACKGROUND OF THE INVENTION
  • [0002]
    Embodiments of the invention relate to field effect transistors such as MOSFET (metal oxide semiconductor field effect transistor) devices and methods for making field effect transistors.
  • [0003]
    Power MOSFET devices are well known and are used in many applications. Exemplary applications include automotive electronics, portable electronics, power supplies, and telecommunications. One important electrical characteristic of a power MOSFET device is its drain-to-source on-state resistance (RDS(on)), which is defined as the total resistance encountered by a drain current. RDS(on) is proportional to the amount of power consumed while the MOSFET device is on. In a vertical power MOSFET device, this total, resistance is composed of several resistive components including an inversion channel resistance (“channel resistance”), a starting substrate resistance, an epitaxial portion resistance and other resistances. The epitaxial portion is typically in the form of a layer and may be referred to as an “epilayer”. RDS(on) can be reduced in a MOSFET device by reducing the resistance of one or more of these MOSFET device components.
  • [0004]
    Reducing RDS(on) is desirable. For example, reducing RDS(on) for a MOSFET device reduces its power consumption and also cuts down on wasteful heat dissipation. The reduction of RDS(on) for a MOSFET device preferably takes place without detrimentally impacting other MOSFET characteristics such as the maximum breakdown voltage (BVDSS) of the device. At the maximum breakdown voltage, a reverse-biased epilayer/well diode in a MOSFET breaks down resulting in significant and uncontrolled current flowing between the source and drain.
  • [0005]
    It is also desirable to maximize the breakdown voltage for a MOSFET device without increasing RDS(on). The breakdown voltage for a MOSFET device can be increased, for example, by increasing the resistivity of the epilayer or increasing the thickness of the epilayer. However, increasing the epilayer thickness or the epilayer resistivity undesirably increases RDS(on).
  • [0006]
    It would be desirable to provide for a MOSFET device with a high breakdown voltage and a low RDS(on). Embodiments of the invention address this and other problems.
  • BRIEF SUMMARY OF THE INVENTION
  • [0007]
    Embodiments of the invention are directed to dual-trench field effect transistors and methods of manufacture. In one embodiment, a semiconductor region of a first conductivity type has a thickness defined by the distance between upper and lower surfaces of the semiconductor region. A well region of a second conductivity type is over the semiconductor region. A source region of the first conductivity type is in an upper portion of the well region. A gate trench is adjacent to the source region. The gate trench extends through the well region and terminates within an upper half of the semiconductor region. A stripe trench extends through the well region and terminates within a lower half of the semiconductor region. The stripe trench is filled with a semiconductor material of the second conductivity type such that: (i) the filled stripe trench is contiguous with the well region, and (ii) the semiconductor material of second conductivity type forms a PN junction with the semiconductor region.
  • [0008]
    Another embodiment of the invention is directed to a method of forming a field effect transistor. A well region is formed in a semiconductor region of a first conductivity type. The well region is of a second conductivity type and has an upper surface and a lower surface. A plurality of gate trenches are formed which extend into the semiconductor region to a depth below the lower surface of the well region. A plurality of stripe trenches are formed which extend deeper into the semiconductor region than the plurality of gate trenches. The plurality of stripe trenches is laterally spaced from one or more of the plurality of gate trenches. The plurality of stripe trenches are at least partially filled with a semiconductor material of the second conductivity type such that the semiconductor material of the second conductivity type forms a PN junction with a portion of the semiconductor region.
  • [0009]
    These and other embodiments of the invention are described in greater detail below with reference to the appended drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0010]
    FIGS. 1(a) to 1(f) show schematic cross-sectional views of a conventional vertical trench MOSFET device. The figures show vertically expanding depletion regions as increasing reverse bias voltages are applied.
  • [0011]
    FIGS. 1(a) to 1(f) show schematic cross-sectional views of a conventional vertical trench MOSFET device. The figures show vertically expanding depletion regions as increasing reverse bias voltages are applied.
  • [0012]
    FIGS. 2(a) to 2(f) show schematic cross-sectional views of a vertical trench MOSFET device according to an embodiment of the invention. The figures show horizontally expanding depletion regions as increasing reverse bias voltages are applied.
  • [0013]
    FIGS. 3(a) to 3(f) show schematic cross sectional views of a vertical trench MOSFET device according to an embodiment of the invention. The figures show horizontally expanding depletion regions as increasing reverse bias voltages are applied.
  • [0014]
    FIG. 4 is a bar graph illustrating the various resistive components making up RDS(on) in various MOSFET devices with different breakdown voltage ratings.
  • [0015]
    FIG. 5 is a graph comparing reverse IV curves for conventional trench MOSFET devices with a reverse IV curve for a trench MOSFET device according to an embodiment of the invention.
  • [0016]
    FIG. 6 is a graph showing reverse IV curves for trench MOSFET devices with different P− stripe depths. The curves show the effect of varying P− stripe depths on BVDSS.
  • [0017]
    FIG. 7 is a graph showing reverse IV curves for trench MOSFET devices with different P− stripe widths. The curves show the effect of varying P− stripe widths on BVDSS.
  • [0018]
    FIGS. 8(a) to 8(d) are cross-sectional views illustrating a method for forming a MOSFET device according to an embodiment of the invention.
  • [0019]
    FIG. 8(e) shows a cross-sectional view of a MOSFET device with a stripe having a P− lining and a dielectric inner portion.
  • DETAILED DESCRIPTION OF THE INVENTION
  • [0020]
    The present inventor has found that the resistance of the epilayer in a MOSFET becomes an increasingly significant component of RDS(on) for increasing MOSFET voltage breakdown ratings. For example, computer simulations have indicated that for a 30 volt N-channel trench MOSFET device, the epilayer resistance is about 30% or more of the total specific RDS(on). In another example, for a 200 V N-channel trench MOSFET device, the epilayer resistance is about 75 to 90% of the total specific RDS(on). Thus, for higher voltage applications in particular, it would be desirable to reduce the resistance of the epilayer and thus reduce RDS(on) for a corresponding MOSFET device. The reduction of RDS(on) preferably takes place without degrading the breakdown voltage characteristics of the MOSFET device.
  • [0021]
    The present inventor has found that the resistance of the epilayer in a MOSFET becomes an increasingly significant component of RDS(on) for increasing MOSFET voltage breakdown ratings. For example, computer simulations have indicated that for a 30 volt N-channel trench MOSFET device, the epilayer resistance is about 30% or more of the total specific RDS(on). In another example, for a 200 V N-channel trench MOSFET device, the epilayer resistance is about 75 to 90% of the total specific RDS(on). Thus, for higher voltage applications in particular, it would be desirable to reduce the resistance of the epilayer and thus reduce RDS(on) for a corresponding MOSFET device. The reduction of RDS(on) preferably takes place without degrading the breakdown voltage characteristics of the MOSFET device.
  • [0022]
    Many numerical examples are provided to illustrate embodiments of the invention. It is to be understood that numerical examples such as breakdown voltage, RDS(on), etc. are provided herein for illustrative purposes only. These and other numbers or values in the application may vary significantly or insignificantly depending upon the specific semiconductor fabrication process used and, in particular, with future advances in semiconductor processing.
  • [0023]
    Under normal operation, the maximum breakdown voltage (BVDSS) of a trench or planar DMOSFET (double diffused metal oxide semiconductor field effect transistor) is obtained by forming a depletion region at a junction between the epilayer and a well region of opposite conductivity type as the epilayer. The depletion region is formed by applying a reverse bias voltage across the junction. At the breakdown voltage, the reverse-biased epilayer/well diode breaks down and significant current starts to flow. Current flows between the source and drain by an avalanche multiplication process while the gate and the source are shorted together.
  • [0024]
    The formation of depletion regions in a conventional trench MOSFET device can be described with reference to FIGS. 1(a) to 1(f). These figures show schematic cross-sectional views of a conventional vertical trench MOSFET device. Each cross-section shows a plurality of gate structures 45 at a major surface of a semiconductor substrate 29. The semiconductor substrate 29 comprises an N− epilayer 32 and a drain region 31. In FIG. 1(a), N+ source regions, P− wells, and P+ body regions are shown. In order to clearly illustrate the horizontal depletion effect, N+ source regions and P+ body regions are not shown in FIGS. 1(b) to 1(f), 2(a) to 2(f), and 3(a) to 3(f).
  • [0025]
    In this example, the N− epilayer 32 has a resistivity of about 5.0 ohm-cm and an epilayer dopant concentration, Nd(epi), of about 1×1015 cm−3. The thickness of the N− epilayer 32 is about 20 microns. The device also has an “effective” epilayer thickness (sometimes referred to as “effective epi”) of about 16.5 microns. The effective epilayer thickness is the thickness of the epilayer after taking into account any up diffusion of atoms from the N+ drain region 31 and the formation of regions such as doped regions (e.g., P− wells) in the semiconductor substrate 29. For example, the effective epilayer thickness can be substantially equal to the distance between the bottom of a P+ body or a P− well and the endpoint of any up-diffused donors in the N− epilayer 32 from the N+ substrate 31. The effective epilayer for the device may also include the drift region for the device.
  • [0026]
    Each of the FIGS. 1(a) to 1(f) also shows the maximum electric field established (“Emax”) as different reverse bias voltages are applied. As shown in the figures, as the reverse bias voltage is increased, Emax also increases. If Emax exceeds the critical electric field for a given dopant concentration, avalanche breakdown occurs. Consequently, Emax is desirably less than the critical electric field.
  • [0027]
    FIGS. 1(a) to 1(f) respectively show how the depletion region 50 expands as increasing reverse bias voltages of 0V, 10V, 50V, 100V, 200V, and 250V are applied to the conventional trench MOSFET device. As shown in the figures, as greater reverse bias voltages are applied, the depletion region 50 spreads “vertically” in a direction from the P-well/epilayer interface to the N+ drain region 31. This vertical growth of the depletion region forces the trade-off between lower RDS(on) and higher BVDSS in conventional trench MOSFET devices.
  • [0028]
    The present invention provides an improved MOSFET device wherein the depletion region initially spreads “horizontally” as higher reverse bias voltages are applied. In embodiments of the invention, a number of additional (and preferably deep) trenches are formed in the semiconductor substrate. These deep trenches are eventually used to form stripes that induce the formation of a horizontally spreading depletion region. The stripes comprise a material of the opposite type conductivity to the epilayer. For example, the stripes may comprise a P type material (e.g., a P, P+, or P− silicon) while the epilayer may comprise an N type material. Individual stripes may be present between adjacent gate structures and can extend from the major surface of the semiconductor substrate and into the epilayer. The stripes can also extend any suitable distance into the epilayer. For example, in some embodiments, the stripes extend all the way to the epilayer/drain region interface. The presence of the stripes allows the use of a lower resistance epilayer without exceeding the critical electric field. As will be explained in greater detail below, RDS(on) can be reduced without detrimentally affecting other MOSFET device characteristics such as the breakdown voltage.
  • [0029]
    FIGS. 2(a) to 2(f) illustrate an embodiment of the invention. These figures illustrate how a depletion region spreads as greater reverse bias voltages are applied. The gate bias voltages applied in the examples shown in FIGS. 2(a) to 2(f) are 0V, 1V, 2V, 10V, 200V, and 250V. Like the conventional trench MOSFET device shown in FIGS. 1(a) to 1(f), each of the cross-sections of FIGS. 2(a) to 2(f) include a plurality of trench gate structures 45 and a N-epilayer 32. The N− epilayer 32 is present in a semiconductor substrate 29.
  • [0030]
    However, in FIGS. 2(a) to 2(f), a plurality of trenches forming stripes 35 (e.g., P stripes) of the opposite conductivity type as the N− epilayer 32 are respectively disposed between adjacent gate structures 45. In this example, the stripes 35 comprise a P type material. As shown in FIGS. 2(a) to 2(c), as greater reverse bias voltages are applied, the depletion region 50 initially spreads “horizontally” away from the sides of the stripes 35. The regions between adjacent stripes 35 are quickly depleted of charge carriers as the depletion region 32 expands from the side-surfaces of adjacent stripes 35. After the regions between adjacent stripes 35 are depleted of charge carriers, the depletion region 50 spreads vertically in a direction from the ends of the stripes 35 towards the N+ drain region 31. The epilayer 32 in the embodiment is depleted of charge carriers much more quickly than when depletion initially occurs in a “vertical” manner (e.g., as shown in FIGS. 1(a) to 1(f)). As illustrated in FIG. 2(c) (reverse bias voltage=2V) and FIG. 1(e) (reverse bias voltage=200 V), the depletion region 50 is similar in area with significantly less applied voltage (2V compared to 200 V).
  • [0031]
    FIGS. 3(a) to 3(f) show cross sections of another MOSFET device according to another embodiment of the invention. In these figures, like elements are denoted by like numerals in prior figures. However, unlike the MOSFET devices described in prior figures, the epilayer 50 in the MOSFET device shown in FIGS. 3(a) to 3(f) has a resistivity of about 0.6 ohm-cm, a dopant concentration (Nd) of about 1×1016 cm−3, a thickness of about 16 microns, and an effective epilayer thickness of about 12.5 microns.
  • [0032]
    FIGS. 3(a) to 3(f) respectively show how the depletion region 50 changes at reverse bias voltages of 0V, 10V, 50V, 100V, 200V, and 250V. Like the MOSFET device embodiment shown in FIGS. 2(a) to 2(f), the depletion region 50 initially spreads “horizontally” as higher reverse bias voltages are applied. Also, in this example, the maximum electric field (Emax) at each of these applied reverse bias voltages does not exceed the critical field for avalanche breakdown for the stated dopant concentration. Consequently, a high breakdown voltage (e.g., 250 V) can be obtained while using a thinner and lower resistivity. The thinner and lower resistivity epilayer advantageously results in a lower resistance epilayer and thus, a reduced RDS(on) value. The dimensions and doping level in the stripes 35 are adjusted to balance the total charge in the stripes with the total charge in the epilayer depletion region 50.
  • [0033]
    As noted above, as the breakdown voltage ratings for MOSFET devices increase, the epilayer resistance becomes a significantly increasing component of the total specific RDS(on). For example, FIG. 4 shows a bar graph illustrating some components of RDS(on) for a number of N-channel MOSFET devices with different breakdown voltage ratings. Bar (a) represents the RDS(on) for a control N-channel 30 V MOSFET device at 500 A. Bars (b) to (f) refer to conventional trench N-channel MOSFET devices with respective breakdown voltages of 60, 80, 100, 150, and 200 V. As is clearly evident in FIG. 4, as the breakdown voltage increases, the epilayer resistance has a greater impact on RDS(on). For example, in the conventional 200 V N-channel MOSFET device example, the epilayer resistance constitutes over 90% of the total specific RDS(on). In contrast, in the 30 V N-channel MOSFET example, the epilayer resistance has a significantly lower impact on RDS(on).
  • [0034]
    In embodiments of the invention, the epilayer resistance can be lowered by incorporating trenched stripes in the epilayer. This reduces RDS(on) as compared to a similar conventional MOSFET device with a similar breakdown voltage rating. For example, bar (g) in FIG. 4 shows the improvement provided for a trench MOSFET device according to an exemplary embodiment of the invention. As shown, the epilayer resistance can be significantly reduced when using trenched stripes having the opposite conductivity of the epilayer in a MOSFET device. As shown at bar (g), the total specific RDS(on) for a 200 V trench N-channel MOSFET device is less than 1.4 milliohm-cm2. In contrast, for a conventional 200 V N-channel trench MOSFET without the stripes of the opposite conductivity, the total specific RDS(on) is about 7.5 milliohm-cm2. Accordingly, these exemplary embodiments of the invention can exhibit a greater than 5-fold reduction in RDS(on) than conventional trench MOSFET devices.
  • [0035]
    FIGS. 5 to 11 show graphs of reverse IV curves for MOSFET devices according to embodiments of the invention.
  • [0036]
    FIG. 5 is a graph showing reverse IV curves for conventional trench MOSFET devices and a MOSFET device according to an embodiment of the invention. FIG. 5 shows IV curves 500, 502 for two MOSFET devices without P− stripes. The first curve 500 is for a MOSFET device with an epilayer resistance of 0.8 milliohm-cm and an epilayer thickness of 15 microns. The second curve 502 is for a MOSFET device with an epilayer resistivity of 4.6 milliohm-cm and an epilayer thickness of 19.5 microns. As expected, the MOSFET device with the thicker epilayer and higher resistance has a higher breakdown voltage.
  • [0037]
    An IV curve 504 for an embodiment of the invention is also shown in FIG. 5. This exemplary embodiment has an epilayer resistance of about 0.8 ohm-cm, an epilayer thickness of about 15 microns and a P− stripe about 12 microns deep. As shown by the IV curve 504, this device embodiment has a relatively thin epilayer and a relatively low epilayer resistivity (and therefore a low RDS(on)). It also has a breakdown voltage approaching 220 V. The breakdown voltage is comparable to the breakdown voltage exhibited by a conventional MOSFET device having a thicker and more resistive epilayer.
  • [0038]
    FIG. 6 shows reverse IV curves for MOSFET devices according to embodiments of the invention. The curves show the effect of varying the P− stripe depth on BVDSS. In these devices, the epilayer has a resistance of about 0.8 ohm-cm and a thickness of about 13 microns. The P− stripe width is about 1.0 microns. The dopant concentration in the P− stripe is about 2.2×1016 cm−3. The P− stripe depth was varied at about 8, 10, and 12, microns. The IV curves for these variations show that the breakdown voltage increases as the depth of the P− stripes is increased.
  • [0039]
    FIG. 7 shows reverse IV curves for MOSFET devices according to embodiments of the invention. The curves show the effect of P− stripe width variations on BVDSS. In this example, the devices have an epilayer resistance of about 0.8 ohm-cm and a thickness of about 13 microns. The P− stripe depth is about 10 microns, and the dopant concentration in the P− stripe is about 2.2×1016 cm−3. IV curves for P− stripes with widths of about 0.8, 1.0, and 1.2 microns are shown. The IV curves show that the breakdown voltage is higher when the width of the P− stripes is equal to 1 micron.
  • [0040]
    Embodiments of the present invention can be applied to both trench and planar MOSFET technologies. However, trench MOSFET devices are preferred as they advantageously occupy less space than planar MOSFET devices. In either case, the breakdown voltage of the device may be from about 100 to about 400 volts in some embodiments. For illustrative purposes, a method of manufacturing a MOSFET device according to the present invention is described below in the context of a trenched gate process.
  • [0041]
    A detailed drawing of a power trench MOSFET device according to an embodiment of the invention is shown in FIG. 8(d). The power trench MOSFET device comprises a semiconductor substrate 29 having a drain region 31 and an N− epitaxial portion 32 proximate the drain region 31. The semiconductor substrate 29 may comprise any suitable semiconductor material including Si, GaAs, etc. The drift region for the MOSFET device may be present in the epitaxial portion 32 of the semiconductor substrate 29. A plurality of gate structures 45 are proximate the major surface 28 of the semiconductor substrate 29, and each gate structure 45 comprises a gate electrode 43 and a dielectric layer 44 on the gate electrode 43. A plurality of N+ source regions 36 are formed in the semiconductor substrate 29. Each N+ source region 36 is adjacent to one of the gate structures 45 and is formed in a plurality of P− well regions 34, which are also formed in the semiconductor substrate 29. Each P− well region 34 is disposed adjacent to one of the gate structures 45. A contact 41 for the source regions 36 is present on the major surface 28 of the semiconductor substrate 29. The contact 41 may comprise a metal such as aluminum. For purposes of clarity, other components which may be present in a MOSFET device (e.g., a passivation layer) may not be shown in FIG. 8(d).
  • [0042]
    In FIG. 8(d), a trenched P− stripe 35 is present in the semiconductor substrate 29. A plurality of P− stripes 35 may be respectively disposed between adjacent gate structures 45 when the gate structures 45 form an array of gate structures 45. The P− stripe 35 shown in FIG. 8(d) is disposed between adjacent gate structures 45. As shown, the P− stripe 35 shown in the figure is generally vertical and is oriented generally perpendicular to the orientation of the semiconductor substrate 29. The P− stripe 35 extends past the gate structures 45 and may penetrate most of the N− epitaxial portion 32. The N− epitaxial portion 32 in this embodiment surrounds the bottom and sides of the P− stripe 35. The dopant concentration at the sides and below the P− stripe 35 may be similar in this embodiment. Preferably, the P− stripe 35 has generally parallel sidewalls and a generally flat bottom. If the sidewalls are generally parallel, thin P− stripes 35 can be present between adjacent gate structures 45. The pitch between gate structures 45 can be minimized consequently resulting in MOSFET arrays of reduced size. In exemplary embodiments of the invention, the gate structure 45 (or gate electrode) pitch may be less than about 10 microns (e.g., between about 4 to about 6 microns). The width of the P− stripes 35 may be less than about 2 or 3 microns (e.g., between about 1 and about 2 microns).
  • [0043]
    The stripe trenches in embodiments of the invention are filled or lined with a material of the opposite doping to the epitaxial portion in the semiconductor substrate. An embodiment of this type is shown in FIG. 8(e) and is described in greater detail below. If the stripe is lined with a material of the opposite conductivity type as the epitaxial portion, the stripe may comprise an inner dielectric portion and an outer semiconductor layer of the opposite conductivity type as the epitaxial portion. For example, the inner dielectric portion may comprise silicon oxide or air while the outer semiconductor layer may comprise P or N type epitaxial silicon.
  • [0044]
    The presence of the doped stripes may also be used as a heavy body to improve the ruggedness of the formed device. For example, like the presence of a P type heavy body in the epilayer, the presence of P− stripes penetrating the epilayer is believed to stabilize voltage variations in the device, thus increasing the device's reliability.
  • [0045]
    Suitable methods for forming the inventive power trench MOSFET devices can be described with reference to FIGS. 8(a) to 8(d).
  • [0046]
    With reference to FIG. 8(a), a structure including a semiconductor substrate 29 is provided. The semiconductor substrate 29 may comprise an N+ drain region 31 and an N-epitaxial portion 32. Gate trenches 30 are formed proximate a major surface 28 of the semiconductor substrate 29. These gate trenches 30 may be formed by using, for example, anisotropic etching methods well known in the art. After the gate trenches 30 are formed, gate structures 45 are formed within the gate trenches 30 using methods well known in the art. Each gate structure 45 comprises a dielectric layer 44 and a gate electrode 43. The gate electrode 43 may comprise polysilicon and the dielectric layer 44 may comprise silicon dioxide.
  • [0047]
    Source regions, well regions, and other structures may also be formed in the semiconductor substrate 29 after or before forming the gate structures 45. With reference to FIG. 8(b), P− well regions 34 are formed in the semiconductor substrate 29 and then N+ source regions 36 are formed in the semiconductor substrate 29. Conventional ion implantation or conventional diffusion processes may be used to form these regions. In this example, these doped regions are formed after the formation of the gate structures 45.
  • [0048]
    Additional details regarding the formation of well regions, gate structures, source regions, and heavy bodies are present in U.S. patent application Ser. No. 08/970,221 entitled “Field Effect Transistor and Method of Its Manufacture”, by Brian Sze-Ki Mo, Duc Chau, Steven Sapp, Izak Bencuya, and Dean Edward Probst. This application is assigned to the same assignee as the assignee of the present application and the application is herein incorporated by reference in its entirety for all purposes.
  • [0049]
    In preferred embodiments, after the source regions, well regions, and/or gate structures are formed, one or more stripe trenches 30 are formed in the semiconductor substrate 29. For example, after the P− well regions 34, the N+ source regions 36, and the gate structures 45 are formed, the stripe trench 30 shown in FIG. 8(c) may be formed, e.g., by an anisotropic etching process. The formed stripe trench 30 extends from the major surface 28 of the semiconductor substrate 29. It may extend any suitable distance past the gate structures 45 to the interface between the epitaxial portion 32 and the drain region 31. Preferably, the stripe trench 30 (and also the stripe material disposed therein) terminates at a depth which is between half the thickness of the N− epitaxial portion 32 and the full thickness of the epitaxial portion 32. For example, the stripe trench 30 may extend to the interface between the epitaxial portion 32 and the drain region 31.
  • [0050]
    After the stripe trench 30 is formed, as shown in FIG. 8(d), a stripe 35 is formed in the stripe trench 30. The stripe 35 comprises a material of the second conductivity type. In embodiments of the invention, the material of the second conductivity type is an epitaxial material such as epitaxial P type silicon (e.g., P, P+, P− silicon). The stripe trenches 30 may be filled using any suitable method including a selective epitaxial growth (SEG) process. For example, the trenches 30 may be filled with epitaxial silicon with doping occurring in-situ.
  • [0051]
    The material of the second conductivity type may completely fill the stripe trench 30 as shown in FIG. 8(d) or may line the stripe trench 35 as shown in FIG. 8(e). In FIG. 8(e), like numerals designate like elements as in FIG. 8(d). However, in this embodiment, the stripe 35 comprises a P− layer 35(a) and an inner dielectric material 35(b). The P− layer 35(a) may be deposited in the formed stripe trench first, and then the dielectric material 35(b) may be deposited to fill the enclosure formed by the P− layer 35(a). Alternatively, the inner dielectric material may be formed by oxidizing the P− layer 35(a). The dielectric material 35(b) may comprise a material such as silicon dioxide or air.
  • [0052]
    Other suitable methods which can be used to form doped epitaxial stripes of material in a trench are described in U.S. patent application Ser. No. 09/586,720 entitled “Method of Manufacturing A Trench MOSFET Using Selective Growth Epitaxy”, by Gordon Madsen and Joelle Sharp. This application is assigned to the same assignee as the present invention and is incorporated by reference herein in its entirety for all purposes.
  • [0053]
    As noted, the stripe trench 30 and the stripes 35 of a second conductivity type are preferably formed after at least one of the source regions 36, the gate structures 45, and the well regions 34 are formed. By forming the stripes 35 after the formation of these device elements, the stripes 35 are not subjected to the high temperature processing used to form the gate structures 45 or the P− well regions 34. For example, the high temperature processing (e.g., ion implantation, high temperature drives) used to form the P− well regions can last as long as 1 to 3 hours at high temperatures (e.g., greater than 1100° C.). The formation of the P− stripes 35 in the semiconductor substrate 29, on the other hand, does not detrimentally affect previously formed gate structures 45, P− well regions 34, or the N+ source regions 36. Forming these device elements before forming the P− stripes 35 reduces the likelihood that the P− stripes 35 in the epilayer will diffuse and lose their shape due to extended high temperature processing. If this occurs, the width of the P− stripes 35 may not be uniform down the P− stripe 35 and may decrease the effectiveness of the formed device. For example, dopant from a laterally enlarged P− stripe 35 could diffuse into the channel region of the MOSFET device thereby influencing the threshold voltage characteristics of the MOSFET device. Moreover, wider P− stripes can result in a larger gate structure 45 pitch, thus increasing the size of a corresponding array of gate structures 45.
  • [0054]
    After the P− stripes 35 are formed, additional layers of material may be deposited. Additional layers may include a metal contact layer 41 and a passivation layer (not shown). These additional layers may be formed by any suitable method known in the art.
  • [0055]
    Although a number of specific embodiments are shown and described, embodiments of the invention are not limited thereto. For example, embodiments of the invention have been described with reference to N type semiconductors, P− stripes, etc. It is understood that the invention is not limited thereto and that the doping polarities of the structures shown and described could be reversed. Also, although P− stripes are mentioned in detail, it is understood that the stripes used in embodiments of the invention may be P or N type. The stripes or other device elements may also have any suitable acceptor or donor concentration (e.g., +, ++, −, −−, etc.).
  • [0056]
    The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding equivalents of the features shown and described, or portions thereof, it being recognized that various modifications are possible within the scope of the invention claimed. Moreover, any one or more features of any embodiment of the invention may be combined with any one or more other features of any other embodiment of the invention, without departing from the scope of the invention.
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Clasificaciones
Clasificación de EE.UU.257/500, 257/E29.066
Clasificación internacionalH01L29/78, H01L21/336, H01L29/06, H01L29/10
Clasificación cooperativaH01L29/1095, H01L29/7813, H01L29/0634
Clasificación europeaH01L29/78B2T, H01L29/06B2B3R2, H01L21/336B2T