US20050042809A1 - Bottom gate-type thin-film transistor and method for manufacturing the same - Google Patents
Bottom gate-type thin-film transistor and method for manufacturing the same Download PDFInfo
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- US20050042809A1 US20050042809A1 US10/946,037 US94603704A US2005042809A1 US 20050042809 A1 US20050042809 A1 US 20050042809A1 US 94603704 A US94603704 A US 94603704A US 2005042809 A1 US2005042809 A1 US 2005042809A1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
Definitions
- the interlayer insulating film is in direct contact with the semiconductor layer; the ion stopper does not intervene.
- This structure can prevent the back channel phenomenon caused by impurities contained in the interlayer insulating film. Therefore, manufacturing variations among bottom gate-type thin-film transistors can be reduced.
- Step 1 the length of the gate electrode 2 p is extended by 10%.
- Step 4 the resist mask 7 is shortened by 10%.
- Such a process allows the channel length of the produced TFT to be equal to that in the prior art. In such a condition, with the resist mask 7 not aligned with gate electrode 2 P and as long as the shift is less than 10% of the channel length, the TFT does not erroneously operate.
Abstract
In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper (55) is removed. The ion stopper (55) does not remain in the interlayer insulating film (8) lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper (55), and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer (4). The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 1018 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.
Description
- 1. Field of the Invention
- The present invention relates to a thin-film transistor (TFT) and to a method of manufacturing the same. Particularly, the present invention relates to a method of manufacturing a bottom gate-type thin-film transistor in which the gate electrode is disposed on the side of the substrate rather than the side of the semiconductor layer.
- 2. Description of Related Art
- In active matrix-type liquid crystal displays (LCDS) or organic electroluminescence (EL) displays, a substrate is generally used in which drive circuits and TFTs for selecting a pixel are formed on a transparent insulating substrate made of material such as glass. In order to form semiconductor elements on the transparent substrate, it is impossible to implement a high temperature process and to diffuse impurities into the transparent substrate. This differs from the case where the silicon substrate is used. Hence, when semiconductor elements are formed on a glass substrate, an approach different from the method of forming semiconductor elements on a silicon substrate must be employed.
- One conventional method of forming bottom gate-type TFTs on a glass substrate will be described below. Referring to
FIGS. 1A to 1E, a P-channel TFT is depicted on the right side while an N-channel TFT is depicted on the left side. - Step 1: As shown in
FIG. 1A , a conductive film of a refractory (high-melting point) metal such as chromium is formed on theglass substrate 51. The conductive film is etched in a predetermined pattern to form agate electrode 52. Next, a gate insulating film 63, which is a laminated structure of a silicon dioxide and a silicon nitride, is formed covering thegate electrodes 52, and then asemiconductor layer 54 of a silicon, and anion stopper 55 of a silicon dioxide are sequentially formed. - Step 2: As shown in
FIG. 1B , a photoresist film is coated over the entire intermediate structure. Light is illuminated onto the photoresist film from the side of thesubstrate 51. Using thegate electrode 52 as a mask, the photoresist film is exposed to light and developed to form aresist mask 56. N-type impurities are implanted or doped at a low concentration into thesemiconductor layer 54 while theresist mask 56 and theion stopper 55 are used as a mask. Thus, an N− region is formed. Since theresist mask 56 is formed, with thegate electrode 52 acting as a mask, the N− region is self-aligned with thegate electrode 52. - Step 3: As shown in
FIG. 1C , aresist mask 57 is formed to completely cover the P-channel TFT and is slightly larger than thegate electrode 52 of the N-channel TFT. N-type impurities are heavily implanted into thesemiconductor layer 54 to form an N+ region. Thus, an LDD (lightly Doped Drain) structure can be obtained. - Step 4: As shown in
FIG. 1D , theresist mask 57 is removed. Aresist mask 58 is newly formed to cover the N-channel TFT. Next, P-type impurities are doped into thesemiconductor layer 54, with the ion stopper 55 acting as a mask, to form a P+ region. Because theion stopper 55 is formed to act as a mask for thegate electrode 52, the P+ region is aligned with thegate electrode 52. - Step 5: As shown in
FIG. 1E , an interlayerinsulating film 59 formed of a laminated structure of silicon dioxide and silicon nitride is formed all over the intermediate structure. At this point, because theinterlayer insulating film 59 is integrated with theion stopper 55, the boundary becomes unclear. Next, contact holes are opened in theinterlayer insulating film 59 at predetermined positions. Thereafter, thesource electrodes 60 and thedrain electrodes 60 are formed to complete the TFTs. - As described above, in
Step 4, the P-type impurities are doped while theion stopper 55 is used as a mask. At the same time, the P-type impurities are doped into thesemiconductor layer 54 and thestopper 55. - However, there is variation in the operational characteristics of bottom gate-type thin-film transistor produced through the above-described process. It is considered that variations in the TFT characteristics are caused by an occurrence of back channel. It has also been considered that such back channel results from other wire layer or electrodes disposed above the
semiconductor layer 54 via the thick insulating layer formed of at least theion stopper 55 and theinterlayer insulating film 59. However, the characteristics of the bottom gate-type thin-film transistor vary over the expected effect of a back channel caused by such the conductive layer. Reduction in variation of characteristics resulting from the back channel, regardless of root cause, has long been desired in the field. - An object of the present invention is to provide a method of manufacturing a bottom gate-type thin film transistor in which variations in characteristics can be reduced.
- Another object of the present invention is to provide a bottom gate-type thin film transistor produced by the above-described method.
- The present invention is made to solve the above-described problems. According to the present invention a bottom gate-type thin-film transistor comprises a gate electrode formed on a transparent insulating substrate; a gate insulating film overlying the gate electrode; and a semiconductor layer formed on the gate insulating film, the semiconductor layer having source and drain regions doped with impurities, and a channel region; an interlayer insulating film is formed on the semiconductor layer; and in said interlayer insulating film, a region in a vicinity of at least an interface between at least the channel region in the semiconductor layer and the interlayer insulating film has an impurity concentration of 1018 atom/cc or less.
- The present applicant has studied variations in characteristic of a bottom gate-type thin-film transistor produced according to conventional methods. As a result, the present inventors found out that impurities in the
interlayer insulating film 59 covering the channel region of the TFT induce back channel, thus influencing the characteristic variations. Conventionally, for example, as shown inFIG. 1D , P-type impurities are doped into thesemiconductor layer 54 to form a P-channel TFT while the ion stopper 55 acts as a mask. The impurity concentration is set to a sufficiently heavy value to form the source region and the drain region in thesemiconductor layer 54. P-type impurities such as boron or N-type impurities such as phosphorus and arsenic are heavily doped into even theion stopper 55. The impurities are heavily doped into theinterlayer insulating film 59 and reside therein. The remaining impurities cause variations in the gate threshold of the TFT. - According to the present invention, a region of said interlayer insulating film at least in the vicinity of the interface between the interlayer insulating film and the channel region of the semiconductor layer, the doping concentration of impurities for activating the semiconductor layer is set to 1018 atoms/cc or less. Because this configuration suppresses the occurrence of back channel resulting from the impurities contained in the interlayer insulating film, variations in the TFT characteristics can be decreased.
- In another aspect of the present invention, a bottom gate-type thin-film transistor comprises a gate electrode formed on a transparent insulating substrate; a gate insulating film overlying the gate electrode; a semiconductor layer formed on the gate insulating film, the semiconductor layer having a source and a drain region, impurities being doped, and a channel region; and an interlayer insulating film formed on the semiconductor layer, wherein both the interlayer insulating film and the semiconductor layer are in direct contact each other and are disposed above the gate electrode.
- As described above, in the bottom gate-type thin-film transistor according to the present invention, the interlayer insulating film is in direct contact with the semiconductor layer; the ion stopper does not intervene. This structure can prevent the back channel phenomenon caused by impurities contained in the interlayer insulating film. Therefore, manufacturing variations among bottom gate-type thin-film transistors can be reduced.
- According to another aspect of the invention, a method for manufacturing a bottom gate-type thin-film transistor on a transparent insulating substrate comprises the steps of forming a gate electrode on a transparent substrate; forming a gate insulating film on the gate electrode; forming a semiconductor layer on the gate insulating film; forming a mask on the semiconductor layer corresponding to the gate electrode; doping impurities selectively into the semiconductor layer, using the mask; and forming an interlayer insulating film on the semiconductor layer, after removal of the mask.
- According to the present invention, a bottom gate-type thin-film, which has characteristics identical to that of the prior art, can be easily produced without forming the problematic stopper insulating film which leads to decreases in characteristic.
- Moreover, before formation of the mask, a native oxide film may be formed on the semiconductor layer. After removal of the mask, residue of the mask may be removed together with the native oxide film.
- Moreover, a dilute hydrofluoric acid may be used to remove the native oxide film.
- As described above, the resist mask can be removed together with the native oxide film such that it will not remain between the semiconductor layer and the interlayer insulating film. As a result, a bottom gate-type thin-film transistor with excellent characteristics can be produced.
- These and other objects, features, and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the attached drawings, in which:
-
FIGS. 1A, 1B , 1C, 1D, and 1E are cross sectional views each illustrating a conventional method for manufacturing a bottom gate-type thin film transistor; -
FIG. 2A, 2B , 2C, 2D, and 2E are cross sectional views each illustrating a method for manufacturing a bottom gate-type thin film transistor, according to a preferred embodiment of the present invention; -
FIG. 3 is an enlarged cross-sectional view explaining a resist mask removal step; and -
FIGS. 4A and 4B are cross sectional views each illustrating a method for manufacturing a bottom gate-type thin film transistor, according to an embodiment of the present invention. -
FIG. 5 is a diagram showing variations in the threshold voltages in a TFT having an ion stopper (conventional TFT) and a TFT with no ion stopper (present invention). - A first embodiment according to the present invention will be explained below by referring to the attached drawings.
- Step 1: As shown in
FIG. 2A , a refractory metal such as chromium is sputtered on aglass substrate 1 to form a conductive film of a thickness of 1000 Å to 2000 Å. The conductive film is etched in a predetermined pattern to form a gate electrode 2 (2N, 2P). At this time, thegate electrode 2P of a P-channel TFT is formed to be about 10% larger than theconventional gate electrode 52 in the channel length direction. Next, agate insulating film 3 having a thickness of 1000 Å to 2000 Å is formed over thegate electrode 2 by chemical vapor deposition (CVD). Thegate insulating film 3 has a laminated structure of a silicon dioxide and a silicon nitride. Next, asemiconductor layer 4 of a non-crystalline silicon or a polycrystalline silicon being a crystallized non-crystalline silicon is formed to be a thickness of 300 Å to 500 Å. The non-crystalline silicon is formed through CVD and is crystallized through the excimer laser anneal (ELA) into a polycrystalline silicon. - Step 2: A photoresist is applied over the entire surface of the intermediate structure. The photoresist layer is exposed to ultraviolet radiation illuminated from the side of the
substrate 1 and then developed, with thegate electrode 2 acting as a mask. Thus, a resistmask 5 is formed as shown inFIG. 2B . Next, N-type impurities are lightly doped at a concentration of about 1014 atoms/cc into thesemiconductor layer 4 to form the N− region while the resistmask 5 acts as a mask. Because thegate electrode 2 acts as a mask during formation of the resistmask 5, the N− region is self-aligned with thegate electrode 2. - Step 3: As shown in
FIG. 2C , a photoresist is applied over the entire surface of the intermediate structure. A resistmask 6 is formed using a mask (not shown). The resistmask 6 completely covers the P-channel TFT and is somewhat larger than thegate electrode 2N of the N-channel TFT. N-type impurities are heavily doped into thesemiconductor layer 4 to form an N+ region. Thus, the source region and the drain region are formed as an LDD structure. - Step 4: As shown in
FIG. 2D , a resistmask 7 is formed so as to cover the N-channel TFT. The resistmask 7 is 10% shorter than thegate electrode 2 of the P-channel TFT in the channel length direction. P-type impurities such as boron are doped into thesemiconductor layer 4 to form a source region and a drain region, while thephotoresist mask 7 is used as a mask. - Step 5: As shown in
FIG. 2E , the resistmask 7 is removed. Thereafter, using a CVP process, aninterlayer insulating film 8 of silicon dioxide is formed at a thickness of 4000 Å to 5000 Å all over the surface of the intermediate structure. Next, contact holes are formed at predetermined positions on theinterlayer insulating film 8. Then, asource electrode 9 and adrain electrode 9 are formed. Finally, a TFT is produced. - According to the present embodiment, in the doping process into the
semiconductor layer 4, P-type impurities are doped into the resistmask 7 simultaneously with doping into thesemiconductor layer 4. However, the resistmask 7 is removed and is not present in the completed TFT. In other words, immediately above thegate electrode 2, thesemiconductor layer 4 and theinterlayer insulating film 2 are in direct contact and are not separated by theion stopper 55. In contrast to cases where theion stopper 55 is not removed, the concentration of impurities contained in the insulating film immediately above thegate electrode 2 of the semiconductor layer 4 (that is, on the channel region 4 c of the semiconductor layer 4) is less than 1018 atoms/cc. This helps prevents occurrence of the back channel phenomenon. As a result, bottom-gate thin-film transistors with stable operational characteristics can be produced at high manufacturing yields. - In
Step 1, the length of the gate electrode 2 p is extended by 10%. InStep 4, the resistmask 7 is shortened by 10%. Such a process allows the channel length of the produced TFT to be equal to that in the prior art. In such a condition, with the resistmask 7 not aligned withgate electrode 2P and as long as the shift is less than 10% of the channel length, the TFT does not erroneously operate. - The
semiconductor layer 4 acts as the channel 4 c in the operation of the TFT. It is very important to better the interface between thesemiconductor layer 4 and theinterlayer insulating film 8. Conventionally, theion stopper 55 is piled up immediately after the formation of thesemiconductor layer 4 and has a role of protecting the interface of thesemiconductor layer 4. In contrast, according to the manufacturing method of the present invention, the resistmask 7 formed directly on thesemiconductor layer 4 must be removed after formation. Because residue of the resistmask 7 may contain doped impurities, it should be carefully ensured that no residue of the resistmask 7 is left on thesemiconductor layer 4. Because physical properties of the resistmask 7 such as dielectric constant differ from those of theinterlayer insulating film 8, any residue adversely affects the operation characteristics of a TFT and causes variations in operation characteristics.FIG. 3 is an enlarged cross-sectional view illustrating the state immediately after the resistmask 7 is removed from above thesemiconductor layer 4. Before the formation of the resistmask 7, a very thinnative oxide film 4 a, on the order of 10 Å to several tens of Å, is formed on the surface of thesemiconductor layer 4. When exposed to the atmosphere, thesemiconductor layer 4 reacts with the oxygen in the air, such that native oxide is formed in a very short time. A minute amount of thereside 7 a of the resistmask 7 may remain on thenative oxide film 4 a. When thenative oxide film 4 a is removed using, for example, a dilute hydrofluoric acid (DHF) of 1% to 5%, theresidue 7 a of the resistmask 7 is simultaneously removed. - During solution cleaning in accordance with etching in the lift-off method, solution remaining on the glass substrate may react with the substrate and cause dimming. This method is therefore not usually used when thin film transistors are formed on a glass substrate. The present embodiment employs the so-called spin etcher method, in which the glass substrate is spun a predetermined number of revolutions to spread a dilute hydrofluoric acid over the glass substrate. The spin etcher spins away, or scatters, the dilute hydrofluoric acid on the surface of the substrate and prevents the dilute hydrofluoric acid from invading the back of the substrate, thereby preventing dimming.
- Moreover, in the lift-off method, immersion of the substrate into a buffered hydrofluoric acid prepared by mixing a hydrofluoric acid and an ammonium fluoride with an acetic acid may be considered. However, in this method a great deal of time is required to completely remove the resist mask. Moreover, immersing the substrate in the buffered hydrofluoric acid for the time period during which the native oxide film is completely removed may cause the substrate to be eroded. For that reason, with the lift-off method, use of the spin etcher is preferable.
- Next, a second preferred embodiment of the present invention will be described.
- In this embodiment, steps 1 to 3 are identical to those in the first embodiment and their explanation will not be repeated.
- Step 4: A photoresist is coated over the entire surface of the intermediate structure. The photoresist is subjected to the exposure process and the development process while the
mask 20 covers the N-channel TFT. Thus, the resistmask 21 is formed to cover the N-channel TFT while the P-channel TFT is exposed. - Step 5: Next, a photoresist is coated over the entire surface of the intermediate structure. The photoresist is exposed and developed from the side of the
substrate 1 while thegate electrode 2 is used as a mask. The resistmask 22 is self-aligned with thegate electrode 2P of the P-channel TFT. Using the resistmask 22 as a mask, P-type impurities are doped into thesemiconductor layer 4. - Step 6: After removal of the resist
masks interlayer insulating film 8, thesource electrode 9 and thedrain electrode 9 are formed in accordance with thestep 5 in the first embodiment. Thus, a TFT is produced. - In this second preferred embodiment, the resist
film 22 is also removed as described in the first embodiment. The region which neighbors the channel of theinterlayer insulating film 8 formed on thesemiconductor layer 4 constructing the TFT contains impurities in a concentration of less than 1018 atoms/cc, thereby preventing the occurrence of the back channel phenomenon. As a result, a bottom gate-type thin-film transistor with stable operation characteristics can be manufactured at high manufacturing yields. - Particularly, according to the present embodiment, because impurities can be doped in a self-alignment state into the
gate electrode 2P of the P-channel TFT, the N-channel gate electrode 2N and the P-channel gate electrode 2P can be made to have the same size. When the conventional manufacturing method is converted to the manufacturing method in the present invention, no design changes are required. As a result, the present invention has an additional advantage in that the manufacturing method can be easily implemented. On the contrary, because the resistmask 21 formed on the N-channel is exposed twice, the photoresist is cured excessively. As a result, the hardened photoresist cannot be perfectly removed with the same remover and in the same amount of time as those applied in other steps. Hence, a solution having a concentration higher than that of the solution used in other steps, or immersion of the substrate in the solution for a longer time, is required. - Referring to
FIG. 5 , characteristic variations are compared between a conventional bottom gate type TFT in which an ion stopper remains formed in an interlayer insulating film and a bottom gate type TFT according to the present invention in which an interlayer insulating film is formed after removal of an ion stopper so that, in its final form, the TFT does not include an ion stopper. As shown inFIG. 5 , with regard to the conventional bottom gate type TFF with an ion stopper, values of a threshold voltage (on voltage) Vth of sample P-channel type TFTs are distributed over a wide range between −3.8V to −1.8V. In order to achieve reliable on-off control for the TFT having such characteristic variations, it is necessary to set, for example, the absolute value of the gate voltage to a very high value. On the other hand, with regard to the bottom gate type TFT without an ion stopper as in the present invention, values of a threshold voltage Vth of the sample P-channel type TFTs are distributed only in a narrow range (−2.8V to −1.8V), and most voltage values for the samples are the same, as shown inFIG. 5 . As can be expected from the above, when a region into which impurities are highly doped, such as an ion stopper, resides on the channel region, even in the insulting film, of the bottom gate type TFT, back channel or the like inevitably occurs, resulting in significant deterioration of the TFT characteristics. According to the present invention, such variations in TFT characteristics can be significantly reduced, so that the TFT can be controlled with high accuracy by application of a minimum gate voltage.
Claims (3)
1. A bottom gate-type thin-film transistor, comprising:
a gate electrode formed on a transparent insulating substrate;
a gate insulating film overlying said gate electrode;
a semiconductor layer formed on said gate insulating film, said semiconductor layer having a source region and a drain region doped with impurities, and a channel region; and
an interlayer insulating film formed on said semiconductor layer, wherein
in said interlayer insulating film, a region in a vicinity of at least an interface between at least said channel region in said semiconductor layer has an impurity concentration of 1018 atom/cc or less.
2. A bottom gate-type thin-film transistor, comprising:
a gate electrode formed on a transparent insulating substrate;
a gate insulating film overlying said gate electrode;
a semiconductor layer formed on said gate insulating film, said semiconductor layer having a source region, and a drain region, impurities being doped and a channel region; and
an interlayer insulating film formed on said semiconductor layer, wherein
both said interlayer insulating film and said semiconductor layer are in direct contact with each other and are disposed above said gate electrode.
3-5. (Canceled)
Priority Applications (1)
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US10/946,037 US20050042809A1 (en) | 2000-11-07 | 2004-09-21 | Bottom gate-type thin-film transistor and method for manufacturing the same |
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JP2000338708A JP2002141514A (en) | 2000-11-07 | 2000-11-07 | Bottom-gate thin-film transistor and its manufacturing method |
JP2000-338708 | 2000-11-07 | ||
US10/008,389 US6815272B2 (en) | 2000-11-07 | 2001-11-06 | Bottom gate-type thin-film transistor and method for manufacturing the same |
US10/946,037 US20050042809A1 (en) | 2000-11-07 | 2004-09-21 | Bottom gate-type thin-film transistor and method for manufacturing the same |
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US10/008,389 Division US6815272B2 (en) | 2000-11-07 | 2001-11-06 | Bottom gate-type thin-film transistor and method for manufacturing the same |
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US10/008,389 Expired - Lifetime US6815272B2 (en) | 2000-11-07 | 2001-11-06 | Bottom gate-type thin-film transistor and method for manufacturing the same |
US10/945,233 Expired - Fee Related US7163850B2 (en) | 2000-11-07 | 2004-09-20 | Bottom gate-type thin-film transistor and method for manufacturing the same |
US10/946,037 Abandoned US20050042809A1 (en) | 2000-11-07 | 2004-09-21 | Bottom gate-type thin-film transistor and method for manufacturing the same |
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US10/008,389 Expired - Lifetime US6815272B2 (en) | 2000-11-07 | 2001-11-06 | Bottom gate-type thin-film transistor and method for manufacturing the same |
US10/945,233 Expired - Fee Related US7163850B2 (en) | 2000-11-07 | 2004-09-20 | Bottom gate-type thin-film transistor and method for manufacturing the same |
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US (3) | US6815272B2 (en) |
JP (1) | JP2002141514A (en) |
KR (1) | KR100500068B1 (en) |
TW (1) | TW594103B (en) |
Cited By (1)
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US9437743B2 (en) | 2010-10-07 | 2016-09-06 | Semiconductor Energy Laboratory Co., Ltd. | Thin film element, semiconductor device, and method for manufacturing the same |
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JP2002141514A (en) * | 2000-11-07 | 2002-05-17 | Sanyo Electric Co Ltd | Bottom-gate thin-film transistor and its manufacturing method |
TWI569441B (en) | 2005-01-28 | 2017-02-01 | 半導體能源研究所股份有限公司 | Semiconductor device, electronic device, and method of manufacturing semiconductor device |
TWI562380B (en) * | 2005-01-28 | 2016-12-11 | Semiconductor Energy Lab Co Ltd | Semiconductor device, electronic device, and method of manufacturing semiconductor device |
TW200941592A (en) * | 2008-03-26 | 2009-10-01 | Au Optronics Corp | Thin-film-transistor structure, pixel structure and manufacturing method thereof |
US7750414B2 (en) * | 2008-05-29 | 2010-07-06 | International Business Machines Corporation | Structure and method for reducing threshold voltage variation |
US9634029B2 (en) | 2011-03-17 | 2017-04-25 | E Ink Holdings Inc. | Thin film transistor substrate and display device having same |
TWI451573B (en) * | 2011-03-17 | 2014-09-01 | E Ink Holdings Inc | Thin film transistor structure and display device using the same |
US9893060B2 (en) * | 2015-12-17 | 2018-02-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
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Also Published As
Publication number | Publication date |
---|---|
US20050035348A1 (en) | 2005-02-17 |
KR100500068B1 (en) | 2005-07-18 |
JP2002141514A (en) | 2002-05-17 |
US6815272B2 (en) | 2004-11-09 |
US20020090774A1 (en) | 2002-07-11 |
KR20020035762A (en) | 2002-05-15 |
TW594103B (en) | 2004-06-21 |
US7163850B2 (en) | 2007-01-16 |
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