US20050067715A1 - Electronic parts built-in substrate and method of manufacturing the same - Google Patents
Electronic parts built-in substrate and method of manufacturing the same Download PDFInfo
- Publication number
- US20050067715A1 US20050067715A1 US10/918,348 US91834804A US2005067715A1 US 20050067715 A1 US20050067715 A1 US 20050067715A1 US 91834804 A US91834804 A US 91834804A US 2005067715 A1 US2005067715 A1 US 2005067715A1
- Authority
- US
- United States
- Prior art keywords
- electronic parts
- semiconductor chip
- substrate
- insulating film
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
Definitions
- the present invention relates to an electronic parts built-in substrate and, more particularly, an electronic parts built-in substrate having a structure in which electronic parts are packaged in a multi-layered fashion in a state that these electronic parts are buried in insulating films and a method of manufacturing the same.
- Patent Literature 1 Patent Application Publication (KOKAI) Hei 11-274734
- the multi-layered wiring structure is formed by flip-chip connecting a bare chip on the wiring substrate, then forming an insulating film on the bare chip, then forming wiring patterns on the insulating film, and then repeating these steps plural times.
- the present invention is relevant to an electronic parts built-in substrate that comprises a wiring substrate including a wiring pattern having connecting pads, a first electronic parts a bump of which is flip-chip connected to the connecting pad, a second electronic parts a bump of which is flip-chip connected to the connecting pad arranged on an outside of a periphery of the first electronic parts and which is packaged at a predetermined interval from an upper surface of the first electronic parts, and a filling insulating body filled in a clearance between the first electronic parts and the wiring substrate and clearances between the second electronic parts and the first electronic parts and the wiring substrate, wherein the first electronic parts is buried in the filling insulating body.
- the bumps of the first electronic parts are flip-chip connected to the connecting pads of the wiring substrate that includes the wiring patterns having the connecting pads.
- the bumps of the second electronic parts having a larger area than an area of the first electronic parts are flip-chip connected to the connecting pads arranged on the outside of the periphery of the first electronic parts.
- a height of the bumps of the second electronic parts is set higher than a thickness that contains the bumps of the first electronic parts, and the second electronic parts is packaged on the wiring substrate at a predetermined interval from the upper surface of the first electronic parts, and the first electronic parts is installed in a space between the lower surface of the second electronic parts and the wiring substrate.
- the filling insulating body (the underfill resin) is filled in the clearance between the first electronic parts and the wiring substrate and clearances between the second electronic parts and the first electronic parts and the wiring substrate, and thus the first electronic parts is buried in the filling insulating body.
- the method of forming a flat insulating film on the electronic parts by eliminating easily the level difference caused by the electronic parts is explained.
- the special steps such as the step of patterning the insulating film having the opening portion in the packaging area, the step of forming the flat interlayer insulating film by filling the insulating film in the clearances between the electronic parts packaged in the packaging area and the insulating film, etc. are required.
- the insulating film used to bury the electronic parts has such disadvantages that the crack resistance is low, the sufficient flatness cannot be obtained, etc.
- the first and second semiconductor chips are flip-chip connected in sequence to the wiring substrates manufactured by the normal manufacturing method such that the first semiconductor chip is installed in the space under the second semiconductor chip, and then the filling insulating body (underfill resin) is filled at a time in the clearances under the first and second semiconductor chips. Therefore, the first semiconductor chip is easily buried in the filling insulating body (underfill resin) having the high crack resistance and then packaged.
- FIGS. 1A to 1 E are sectional views showing a method of manufacturing an electronic parts built-in substrate according to the related art 1;
- FIGS. 2A to 2 E are sectional views showing a method of manufacturing an electronic parts built-in substrate according to the related art 2;
- FIGS. 3A to 3 H are sectional views showing a method of manufacturing an electronic parts built-in substrate according to an embodiment of the present invention.
- an insulating base substrate 100 to manufacture a built-up wiring substrate is prepared.
- Through holes 100 x are provided in the base substrate 100 , then through-hole plating layers 102 x connected to first wiring patterns 102 are formed on inner surfaces of the through holes 100 x , and then the openings are buried with a resin body 101 .
- first interlayer insulating film 104 made of resin to coat the first wiring patterns 102 is formed. Then, predetermined portions of the first interlayer insulating film 104 on the first wiring patterns 102 are worked by the laser or the RIE. Thus, first via holes 104 x each having a depth that reaches the first wiring pattern 102 are formed. Then, a second wiring pattern 106 connected to the first wiring patterns 102 via the first via holes 104 x is formed on the first interlayer insulating film 104 .
- a semiconductor chip 110 which has connection terminals 110 a and whose thickness is thinned up to about 150 ⁇ m or less is prepared. Then, a back surface of the semiconductor chip 110 is secured onto the wiring pattern 106 via an adhesive layer 111 such that the connection terminals 110 a of the semiconductor chip 110 are directed upward. At this time, since the first insulating film 108 a is formed in areas except the packaging area A to have a film thickness almost equal to a thickness of the semiconductor chip 110 , an upper surface of the semiconductor chip 110 and an upper surface of the first insulating film 108 a have an almost same height respectively and therefore the level difference caused by the semiconductor chip 110 is overcome.
- a second insulating film 108 b is formed by pasting a resin film on the semiconductor chip 110 and the first insulating film 108 a .
- the second insulating film 108 b is filled in clearances between side surfaces of the semiconductor chip 110 and side surfaces of the opening portion 108 x in the first insulating film 108 a to form a coplanar upper surface.
- a second interlayer insulating film 108 consisting of the first insulating film 108 a and the second insulating film 108 b is obtained.
- the structure in which the semiconductor chip 110 is face-up buried in the flat second interlayer insulating film 108 and packaged is obtained.
- second via holes 108 y are formed in predetermined portions in the second interlayer insulating film 108 on the connection terminals 110 a of the semiconductor chip 110 and the second wiring pattern 106 .
- third wiring patterns 112 connected to the connection terminals 110 a of the semiconductor chip 110 and the second wiring pattern 106 via the second via holes 108 y respectively are formed on the second interlayer insulating film 108 .
- a solder resist film 114 having an opening portion 114 x to expose predetermined portions of the third wiring patterns 112 is formed on the second interlayer insulating film 108 .
- Ni/Au layers 112 a are formed on the third wiring patterns 112 in the opening portion 114 x by the electroless plating.
- bumps 116 a of an upper semiconductor chip 116 with the bumps 116 a are flip-chip connected to the Ni/Au plating layers 112 a on the third wiring patterns 112 .
- an underfill resin 118 is filled in clearances under the upper semiconductor chip 116 .
- the level difference caused due to the semiconductor chip 110 when the semiconductor chip 110 is buried in the second interlayer insulating film 108 can be easily eliminated, nevertheless a crack is prone to occur in portions of the second insulating film (resin film) 108 b buried in the clearances on the outside of the periphery of the semiconductor chip 110 (in particular, the portions corresponding to the corner portions of the semiconductor chip) when the temperature cycle test is applied in the range of 125 to ⁇ 55° C. Therefore, the measure must be taken such that a special resin film having a high crack resistance should be used as the second insulating film 108 b , and so forth, and it is possible that an increase in a production cost is brought about.
- the base substrate 100 having the first wiring patterns 102 is prepared, like the related art 1.
- the second wiring patterns 106 connected to the first wiring patterns 102 via the first via holes 104 x formed in the first interlayer insulating film 104 are formed on the first interlayer insulating film 104 .
- the first insulating film 108 a having the opening portion 108 x in the packaging area A in which the semiconductor chip is mounted is formed.
- connecting pads 106 x of the second wiring patterns 106 to which the semiconductor chip is flip-chip connected later, are exposed from the packaging area A.
- Ni/Au layers 106 a are formed on the connecting pads 106 x of the second wiring patterns 106 , which are exposed from the packaging area A, by the electroless plating.
- the semiconductor chip 110 which has the bumps 110 a and whose thickness is thinned up to about 150 ⁇ m or less is prepared. Then, the bumps 110 a of the semiconductor chip 110 are flip-chip connected to the Ni/Au layers 106 a on the connecting pads 106 x of the second wiring patterns 106 . Then, an underfill resin 108 c is filled in the clearances under the semiconductor chip 110 and the clearances between the side surfaces of the semiconductor chip 110 and the side surfaces of the opening portion 108 x in the first insulating film 108 a . Then, as shown in FIG. 2C , the second insulating film 108 b is formed on the upper surface of the semiconductor chip 110 . Thus, the second interlayer insulating film 108 consisting of the first insulating film 108 a , the second insulating film 108 b , and the underfill resin 108 c is obtained.
- the second via holes 108 y are formed in the predetermined portions in the second interlayer insulating film 108 on the second wiring patterns 106 .
- the third wiring patterns 112 connected to the second wiring patterns 106 via the second via holes 108 y are formed on the second interlayer insulating film 108 .
- the solder resist film 114 having the opening portion 114 x to expose the predetermined portions of the third wiring patterns 112 is formed on the second interlayer insulating film 108 .
- the Ni/Au layers 112 a are formed on the third wiring patterns 112 , which are exposed from the opening portion 114 x , by the electroless plating.
- the bumps 116 a of an upper semiconductor chip 116 having the bumps 116 a are flip-chip connected to the Ni/Au layers 112 a on the third wiring patterns 112 .
- the underfill resin 118 is filled in the clearances under the upper semiconductor chip 116 .
- the level difference caused due to the semiconductor chip 110 when such semiconductor chip 110 is buried in the first interlayer insulating film 108 can be easily eliminated.
- An electronic parts built-in substrate according to an embodiment of the present invention to be explained in the following can overcome disadvantages of the above related arts 1 and 2.
- FIGS. 3A to 3 H are sectional views showing a method of manufacturing an electronic parts built-in substrate according to an embodiment of the present invention in order.
- a base substrate 10 is prepared to manufacture a build-up wiring substrate.
- This base substrate 10 is made of insulating material such as glass epoxy resin, or the like.
- Through holes 10 a are provided in the base substrate 10 , then a through-hole plating layer 10 b connected to a first wiring pattern 12 on the base substrate 10 respectively is formed on inner surfaces of the through holes 10 a , and then the openings are buried with a resin body 10 c.
- a first interlayer insulating film 14 is formed on the first wiring patterns 12 .
- a resin such as epoxy resin, polyimide resin, polyphenylene ether resin, or the like may be employed.
- a resin film is formed by laminating a resin film on the first wiring patterns 12 and then thermally treating the film at 80 to 140° C. to cure.
- the resin film may be formed by the spin coating method or the printing.
- first interlayer insulating film 14 on the first wiring patterns 12 are worked by the laser or the RIE.
- first via holes 14 x each having a depth that reaches the first wiring pattern 12 are formed.
- second wiring patterns 16 connected to the first wiring patterns 12 via the first via holes 14 x are formed on the first interlayer insulating film 14 by the semi-additive process.
- a seed Cu layer (not shown) is formed on inner surfaces of the first via holes 14 x and the first interlayer insulating film 14 by the electroless plating or the sputter method, and then a resist film (not shown) having opening portions that correspond to the second wiring patterns 16 is formed. Then, Cu film patterns (not shown) are formed in the opening portions in the resist film by the electrolytic plating using the seed Cu layer as a plating power-supply layer. Then, the resist film is removed and then the seed Cu film is etched while using the Cu film patterns as a mask. In this case, the subtractive process or the full additive process may be used in place of the semi-additive process.
- a second interlayer insulating film 18 made of the same material as the first interlayer insulating film 14 is formed on the second wiring patterns 16 , and then second via holes 18 x are formed in predetermined portions of the second interlayer insulating film 18 on the second wiring patterns 16 .
- third wiring patterns 20 connected to the second wiring patterns 16 via the second via holes 18 x are formed on the second interlayer insulating film 18 by the same method as the method of forming the second wiring patterns 16 .
- the third wiring patterns 20 are formed in a state that a first connecting pad C 1 to which the bump of the first semiconductor chip is connected later and a second connecting pad C 2 to which the bump of the second semiconductor chip is connected are provided thereto.
- solder resist film 22 (protection insulating film) having an opening portion 22 x to expose collectively the packaging area A, in which a plurality of first, second connecting pads C 1 , C 2 of the third wiring patterns 20 are arranged, is formed. That is, the solder resist film 22 is formed to surround the packaging area A.
- an Ni (nickel)/Au (gold) layer 21 is formed on the third wiring patterns 20 containing the first, second connecting pads C 1 , C 2 , which are exposed from the packaging area A, by the electroless plating while using the solder resist film 22 as a mask.
- a first semiconductor chip 24 (first electronic parts) having bumps 24 a is prepared.
- This semiconductor chip 24 is obtained by grinding a semiconductor wafer (not shown) having elements such as transistors, etc. and connecting terminals on the element forming surface side to reduce a thickness and then dicing the semiconductor wafer into individual pieces.
- the semiconductor chip 24 (except the bumps 24 a ) is reduced in thickness up to 150 ⁇ m or less, preferably 10 to 100 ⁇ m.
- the bumps 24 a of the first semiconductor chip 24 are formed on the connecting terminals of the semiconductor chip 24 , before or after the semiconductor wafer is subjected to the dicing.
- the bumps 24 a of the first semiconductor chip 24 are flip-chip connected to the Ni/Au layers 21 on the first connecting pads C 1 of the third wiring patterns 20 ( FIG. 3E ).
- the Au bump, the solder bump, or the like may be used as the bumps 24 a of the first semiconductor chip 24 .
- Au bump When the Au bump is used, Au and Au are bonded by the ultrasonic wave. Also, when the solder bump is used, the solder and Au are bonded by the reflow heating.
- a second semiconductor chip 26 (second electronic parts) having bumps 26 a and having an area that is larger than an area of the first semiconductor chip 24 is prepared.
- the bumps 26 a of the second semiconductor chip 26 are flip-chip connected to the Ni/Au layers 21 on the second connecting pads C 2 of the third wiring patterns 20 ( FIG. 3E ) arranged on the outside of the periphery of the first semiconductor chip 24 . Accordingly, the second semiconductor chip 26 is packaged at a predetermined interval from the upper surface of the first semiconductor chip 24 , and the first semiconductor chip 24 is installed into a space between the lower surface of the second semiconductor chip 26 and the wiring substrate.
- a height of the bumps 26 a of the second semiconductor chip 26 is set higher than a thickness containing the bumps 24 a of the first semiconductor chip 24 .
- a height of the bumps 26 a of the second semiconductor chip 26 is set to about 100 ⁇ m when a thickness of the first semiconductor chip 24 is about 50 ⁇ m and a height of the bumps 24 a is about 20 ⁇ m.
- the semiconductor chip is taken as an example of the electronic parts. But various electronic parts such as the capacitor parts, or the like may be employed.
- a filling insulating body 28 is formed by filling the underfill resin in the clearance under the first semiconductor chip 24 , the clearances on both surface sides of the first semiconductor chip 24 , the clearance between the upper surface of the first semiconductor chip 24 and the lower surface of the second semiconductor chip 26 , and the clearances between the side surfaces of the second semiconductor chip 26 and the opening portion 22 x of the solder resist film 22 and then thermally treating the resin to cure.
- the first semiconductor chip 24 is buried in the filling insulating body 28 but also the clearances under the second semiconductor chip 26 and on the side surface side thereof are filled with the filling insulating body 28 .
- the filling insulating body 28 on the side surface side of the second semiconductor chip 26 is formed in a state that such body is dammed up by the side surface of the opening portion 22 x of the solder resist film 22 .
- the resin which contains filler (silica), and has a coefficient of thermal expansion (CTE) of 20 to 30 ppm/° C. and has a Young's modulus of 10 to 15 GPa is used.
- the first semiconductor chip 24 is mounted on the wiring substrate in a state that such first semiconductor chip 24 is buried in the filling insulating body 28
- the second semiconductor chip 26 is mounted on the wiring substrate in a state that such second semiconductor chip 26 is stacked three-dimensionally over the first semiconductor chip 24 .
- the solder resist film 22 having the opening portion 22 x to expose collectively the packaging area A in which a plurality of first, second connecting pads C 1 , C 2 are arranged is formed.
- Such structure is also suitable from such a respect that a desired bonding area can be assured upon bonding the bumps 24 a , 26 a of the semiconductor chips 24 , 26 to the connecting pads C 1 , C 2 and thus the reliability of the electrical bonding can be improved, even though a pitch between the connecting pads C 1 , C 2 is narrowed (e.g., about 150 ⁇ m or less).
- the opening portions in the solder resist film are liable to displace from the major portions of the connecting pads C 1 , C 2 in formation due to displacements in the forming step when a pitch between the connecting pads C 1 , C 2 is narrowed. Therefore, the bonding area between the bumps of the semiconductor chip and the connecting pads C 1 , C 2 is reduced and the bonding failure, and the like are readily caused with the reduction in a bonding strength of the bumps.
- the first to third wiring patterns 12 , 16 , 20 are formed on the base substrate 10 in a multi-layered fashion, and then these wiring patterns 12 , 16 , 20 are connected mutually via the first and second via holes 14 x , 18 x provided in the first and second interlayer insulating films 14 , 18 .
- the third wiring patterns 20 have a plurality of connecting pads C 1 , C 2 , and the solder resist film 22 having the opening portion 22 x to expose collectively the packaging area A in which the first, second connecting pads C 1 , C 2 are arranged is formed on the second interlayer insulating film 18 .
- the bumps 24 a of the first semiconductor chip 24 are flip-chip connected to the Ni/Au layers 21 on the first connecting pads C 1 of the third wiring patterns 20 .
- the bumps 26 a of the second semiconductor chip 26 which have a larger area than an area of the first semiconductor chip 24 , are flip-chip connected to the Ni/Au layers 21 on the second connecting pads C 2 arranged on the outside of the periphery of the first semiconductor chip 24 . Then, a height of the bumps 26 a of the second semiconductor chip 26 is set higher than a thickness containing the bumps 24 a of the first semiconductor chip 24 , whereby the first semiconductor chip 24 is installed into an area between the lower surface of the second semiconductor chip 26 and the wiring substrate.
- the filling insulating body 28 is filled in the clearances under the first semiconductor chip 24 and the second semiconductor chip 26 and on the side surface sides thereof, and the first semiconductor chip 24 is mounted to be buried in the filling insulating body 28 .
- the first semiconductor chip 24 is buried in the filling insulating body 28 made of the underfill resin for which the material having a high crack resistance can be easily chosen. For this reason, no crack is generated in the filling insulating body 28 on the peripheral portion of the first semiconductor chip 24 during the temperature cycle test, and thus the reliability of the electronic parts built-in substrate 1 can be improved.
- the special steps such as the step of patterning the insulating film having the opening portion in the packaging area, the step of forming the flat interlayer insulating film by filling the insulating film in the clearances between the electronic parts packaged in the packaging area and the insulating film, etc. are required.
- the first and second semiconductor chips 24 , 26 are flip-chip connected in sequence to the wiring substrates manufactured by the normal manufacturing method such that the first semiconductor chip 24 is installed in the space under the second semiconductor chip 26 , and then the filling insulating body 28 is filled at a time in the clearances under the first and second semiconductor chips 24 , 26 . Therefore, the electronic parts built-in substrate 1 of the present embodiment can be manufactured by very simple manufacturing steps and at a low cost rather than the related arts 1 and 2.
- the film thickness of the insulating film of the wiring substrate should be formed to coincide with the thickness of the semiconductor chip. Therefore, since the film thickness of the insulating film can be adjusted appropriately to meet the characteristics of the wiring substrate, an overall thickness of the electronic parts built-in substrate can be adjusted thinly rather than the related arts 1 and 2.
- the substrate in which three wiring patterns are stacked on the base substrate is exemplified as the wiring substrate.
- various wiring substrates in which the wiring patterns are provided in the n-layered (n is an integer of 1 or more) fashion may be employed.
- a mode in which the n-layered (n is an integer of 1 or more) wiring pattern is also formed on the back surface side of the base substrate 10 may be employed.
Abstract
An electronic parts built-in substrate of the present invention includes a wiring substrate having connecting pads, a first electronic parts a bump of which is flip-chip connected to the connecting pad, a second electronic parts having a larger area than an area of the first electronic parts a bump of which is flip-chip connected to the connecting pad arranged on an outside of a periphery of the first electronic parts and which is packaged at a predetermined interval over the first electronic parts, and a filling insulating body filled in a clearance between the first electronic parts and the wiring substrate and clearances between the second electronic parts and the first electronic parts and the wiring substrate, wherein the first electronic parts is buried in the filling insulating body.
Description
- 1. Field of the Invention
- The present invention relates to an electronic parts built-in substrate and, more particularly, an electronic parts built-in substrate having a structure in which electronic parts are packaged in a multi-layered fashion in a state that these electronic parts are buried in insulating films and a method of manufacturing the same.
- 2. Description of the Prior Art
- The development of the LSI technology serving as a key technology to implement the multimedia devices is proceeding steadily to a higher speed and a larger capacity in data transmission. With this development, a higher density in the packaging technology serving as the interface between LSI and the electronic device is advanced.
- In reply to the request for the higher density, the electronic parts built-in substrate having the structure in which electronic parts are packaged on the wiring substrate in a multi-layered fashion in a state that semiconductor chips are buried in the insulating film was developed. As an example, in Patent Literature 1 (Patent Application Publication (KOKAI) Hei 11-274734), it is set forth that the multi-layered wiring structure is formed by flip-chip connecting a bare chip on the wiring substrate, then forming an insulating film on the bare chip, then forming wiring patterns on the insulating film, and then repeating these steps plural times.
- Meanwhile, in the production of the above electronic parts built-in substrate, upon forming the insulating film on the semiconductor chip, such insulating film is formed in the situation that a level difference is caused due to a thickness of the semiconductor chip. If the level difference is caused in the insulating film on the semiconductor chip, defocus is liable to occur in the photolithography applied to form the wiring patterns on the insulating film. Thus, it becomes difficult to form the wiring patterns on the insulating film with good precision.
- Further, since a level difference is also caused in the wiring patterns formed on the insulating film, there is a possibility of lowering the reliability of the electric bonding applied to flip-chip bond the upper semiconductor chip to the wiring patterns.
- Therefore, the technology capable of forming easily the flat insulating film on the semiconductor chip is desired.
- It is an object of the present invention to provide an electronic parts built-in substrate in which electronic parts are buried in insulating films and packaged at low cost with good reliability to cause no disadvantage, and a method of manufacturing the same.
- The present invention is relevant to an electronic parts built-in substrate that comprises a wiring substrate including a wiring pattern having connecting pads, a first electronic parts a bump of which is flip-chip connected to the connecting pad, a second electronic parts a bump of which is flip-chip connected to the connecting pad arranged on an outside of a periphery of the first electronic parts and which is packaged at a predetermined interval from an upper surface of the first electronic parts, and a filling insulating body filled in a clearance between the first electronic parts and the wiring substrate and clearances between the second electronic parts and the first electronic parts and the wiring substrate, wherein the first electronic parts is buried in the filling insulating body.
- In the electronic parts built-in substrate of the present invention, first the bumps of the first electronic parts (the thinned semiconductor chip, or the like) are flip-chip connected to the connecting pads of the wiring substrate that includes the wiring patterns having the connecting pads. Then, the bumps of the second electronic parts (the semiconductor chip, or the like) having a larger area than an area of the first electronic parts are flip-chip connected to the connecting pads arranged on the outside of the periphery of the first electronic parts. That is, a height of the bumps of the second electronic parts is set higher than a thickness that contains the bumps of the first electronic parts, and the second electronic parts is packaged on the wiring substrate at a predetermined interval from the upper surface of the first electronic parts, and the first electronic parts is installed in a space between the lower surface of the second electronic parts and the wiring substrate.
- Then, the filling insulating body (the underfill resin) is filled in the clearance between the first electronic parts and the wiring substrate and clearances between the second electronic parts and the first electronic parts and the wiring substrate, and thus the first electronic parts is buried in the filling insulating body.
- In the
related arts related arts related arts - In contrast, in the present invention, the first and second semiconductor chips are flip-chip connected in sequence to the wiring substrates manufactured by the normal manufacturing method such that the first semiconductor chip is installed in the space under the second semiconductor chip, and then the filling insulating body (underfill resin) is filled at a time in the clearances under the first and second semiconductor chips. Therefore, the first semiconductor chip is easily buried in the filling insulating body (underfill resin) having the high crack resistance and then packaged.
- As a result, the manufacturing steps become very simple rather than the
related arts - Also, unlike the
related arts -
FIGS. 1A to 1E are sectional views showing a method of manufacturing an electronic parts built-in substrate according to therelated art 1; -
FIGS. 2A to 2E are sectional views showing a method of manufacturing an electronic parts built-in substrate according to therelated art 2; and -
FIGS. 3A to 3H are sectional views showing a method of manufacturing an electronic parts built-in substrate according to an embodiment of the present invention. - An embodiment of the present invention will be explained with reference to the drawings hereinafter.
- The related arts having relevance to the present invention and their disadvantages will be explained prior to explanation of the embodiment of the present invention.
- (Related Art 1)
- In the method of manufacturing the electronic parts built-in substrate according to the
related art 1, as shown inFIG. 1A , first aninsulating base substrate 100 to manufacture a built-up wiring substrate is prepared. Throughholes 100 x are provided in thebase substrate 100, then through-hole plating layers 102 x connected tofirst wiring patterns 102 are formed on inner surfaces of the throughholes 100 x, and then the openings are buried with aresin body 101. - Then, a first
interlayer insulating film 104 made of resin to coat thefirst wiring patterns 102 is formed. Then, predetermined portions of the firstinterlayer insulating film 104 on thefirst wiring patterns 102 are worked by the laser or the RIE. Thus, first viaholes 104 x each having a depth that reaches thefirst wiring pattern 102 are formed. Then, asecond wiring pattern 106 connected to thefirst wiring patterns 102 via thefirst via holes 104 x is formed on the first interlayerinsulating film 104. - Then, as shown in
FIG. 1B , a firstinsulating film 108 a having anopening portion 108 x in a packaging area A, in which the semiconductor chip is flip-chip mounted, of thesecond wiring pattern 106 and the first interlayerinsulating film 104 is formed. - Then, a
semiconductor chip 110 which hasconnection terminals 110 a and whose thickness is thinned up to about 150 μm or less is prepared. Then, a back surface of thesemiconductor chip 110 is secured onto thewiring pattern 106 via anadhesive layer 111 such that theconnection terminals 110 a of thesemiconductor chip 110 are directed upward. At this time, since the firstinsulating film 108 a is formed in areas except the packaging area A to have a film thickness almost equal to a thickness of thesemiconductor chip 110, an upper surface of thesemiconductor chip 110 and an upper surface of the firstinsulating film 108 a have an almost same height respectively and therefore the level difference caused by thesemiconductor chip 110 is overcome. - Then, as shown in
FIG. 1C , a secondinsulating film 108 b is formed by pasting a resin film on thesemiconductor chip 110 and the firstinsulating film 108 a. At this time, the secondinsulating film 108 b is filled in clearances between side surfaces of thesemiconductor chip 110 and side surfaces of theopening portion 108 x in the firstinsulating film 108 a to form a coplanar upper surface. - In this manner, a second
interlayer insulating film 108 consisting of the firstinsulating film 108 a and the secondinsulating film 108 b is obtained. Thus, the structure in which thesemiconductor chip 110 is face-up buried in the flat secondinterlayer insulating film 108 and packaged is obtained. - Then, as shown in
FIG. 1D ,second via holes 108 y are formed in predetermined portions in the second interlayerinsulating film 108 on theconnection terminals 110 a of thesemiconductor chip 110 and thesecond wiring pattern 106. Then,third wiring patterns 112 connected to theconnection terminals 110 a of thesemiconductor chip 110 and thesecond wiring pattern 106 via thesecond via holes 108 y respectively are formed on the second interlayerinsulating film 108. - Then, a solder resist
film 114 having anopening portion 114 x to expose predetermined portions of thethird wiring patterns 112 is formed on the second interlayerinsulating film 108. Then, Ni/Au layers 112 a are formed on thethird wiring patterns 112 in theopening portion 114 x by the electroless plating. - Then, as shown in
FIG. 1E , bumps 116 a of anupper semiconductor chip 116 with thebumps 116 a are flip-chip connected to the Ni/Au plating layers 112 a on thethird wiring patterns 112. Then, anunderfill resin 118 is filled in clearances under theupper semiconductor chip 116. With the above, the electronic parts built-in substrate of therelated art 1 can be obtained. - In the electronic parts built-in substrate of the
related art 1, the level difference caused due to thesemiconductor chip 110 when thesemiconductor chip 110 is buried in the secondinterlayer insulating film 108 can be easily eliminated, nevertheless a crack is prone to occur in portions of the second insulating film (resin film) 108 b buried in the clearances on the outside of the periphery of the semiconductor chip 110 (in particular, the portions corresponding to the corner portions of the semiconductor chip) when the temperature cycle test is applied in the range of 125 to −55° C. Therefore, the measure must be taken such that a special resin film having a high crack resistance should be used as the secondinsulating film 108 b, and so forth, and it is possible that an increase in a production cost is brought about. - (Related Art 2)
- In the method of manufacturing the electronic parts built-in substrate according to the
related art 2, as shown inFIG. 2A , first thebase substrate 100 having thefirst wiring patterns 102 is prepared, like therelated art 1. Then, thesecond wiring patterns 106 connected to thefirst wiring patterns 102 via the first viaholes 104 x formed in the firstinterlayer insulating film 104 are formed on the firstinterlayer insulating film 104. Then, the first insulatingfilm 108 a having the openingportion 108 x in the packaging area A in which the semiconductor chip is mounted is formed. At this time, connectingpads 106 x of thesecond wiring patterns 106, to which the semiconductor chip is flip-chip connected later, are exposed from the packaging area A. Then, Ni/Au layers 106 a are formed on the connectingpads 106 x of thesecond wiring patterns 106, which are exposed from the packaging area A, by the electroless plating. - Then, as shown in
FIG. 2B , thesemiconductor chip 110 which has thebumps 110 a and whose thickness is thinned up to about 150 μm or less is prepared. Then, thebumps 110 a of thesemiconductor chip 110 are flip-chip connected to the Ni/Au layers 106 a on the connectingpads 106 x of thesecond wiring patterns 106. Then, anunderfill resin 108 c is filled in the clearances under thesemiconductor chip 110 and the clearances between the side surfaces of thesemiconductor chip 110 and the side surfaces of theopening portion 108 x in the first insulatingfilm 108 a. Then, as shown inFIG. 2C , the secondinsulating film 108 b is formed on the upper surface of thesemiconductor chip 110. Thus, the secondinterlayer insulating film 108 consisting of the first insulatingfilm 108 a, the secondinsulating film 108 b, and theunderfill resin 108 c is obtained. - Then, as shown in
FIG. 2D , the second viaholes 108 y are formed in the predetermined portions in the secondinterlayer insulating film 108 on thesecond wiring patterns 106. Then, thethird wiring patterns 112 connected to thesecond wiring patterns 106 via the second viaholes 108 y are formed on the secondinterlayer insulating film 108. - Then, the solder resist
film 114 having the openingportion 114 x to expose the predetermined portions of thethird wiring patterns 112 is formed on the secondinterlayer insulating film 108. Then, the Ni/Au layers 112 a are formed on thethird wiring patterns 112, which are exposed from theopening portion 114 x, by the electroless plating. - Then, as shown in
FIG. 2E , thebumps 116 a of anupper semiconductor chip 116 having thebumps 116 a are flip-chip connected to the Ni/Au layers 112 a on thethird wiring patterns 112. Then, theunderfill resin 118 is filled in the clearances under theupper semiconductor chip 116. With the above, the electronic parts built-in substrate of therelated art 2 can be obtained. - In the electronic parts built-in substrate of the
related art 2, like therelated art 1, the level difference caused due to thesemiconductor chip 110 whensuch semiconductor chip 110 is buried in the firstinterlayer insulating film 108 can be easily eliminated. However, in the step of filling theunderfill resin 108 c inFIG. 2B , it is difficult to control a supply amount of theunderfill resin 108 c in such a way that the upper surface of theunderfill resin 108 c and the upper surface of thesemiconductor chip 110 constitute a coplanar surface. Therefore, in many cases theunderfill resin 108 c is formed to rise around the peripheral portion of thesemiconductor chip 110. As a result, a height of thethird wiring patterns 112 formed over this resin is varied and thus the reliability of the electrical bonding of theupper semiconductor chip 116 is lowered. - In this manner, according to the
related art 2, since the measure must be taken such that the planarizing step should be particularly added, etc., it is possible that an increase in a production cost is brought about. - An electronic parts built-in substrate according to an embodiment of the present invention to be explained in the following can overcome disadvantages of the above
related arts - (Embodiment)
-
FIGS. 3A to 3H are sectional views showing a method of manufacturing an electronic parts built-in substrate according to an embodiment of the present invention in order. As shown inFIG. 3A , first abase substrate 10 is prepared to manufacture a build-up wiring substrate. Thisbase substrate 10 is made of insulating material such as glass epoxy resin, or the like. Throughholes 10 a are provided in thebase substrate 10, then a through-hole plating layer 10 b connected to afirst wiring pattern 12 on thebase substrate 10 respectively is formed on inner surfaces of the throughholes 10 a, and then the openings are buried with aresin body 10 c. - Then, as shown in
FIG. 3B , a firstinterlayer insulating film 14 is formed on thefirst wiring patterns 12. As the firstinterlayer insulating film 14, a resin such as epoxy resin, polyimide resin, polyphenylene ether resin, or the like may be employed. As an example of the forming method, a resin film is formed by laminating a resin film on thefirst wiring patterns 12 and then thermally treating the film at 80 to 140° C. to cure. Alternately, the resin film may be formed by the spin coating method or the printing. - Then, predetermined portions of the first
interlayer insulating film 14 on thefirst wiring patterns 12 are worked by the laser or the RIE. Thus, first viaholes 14 x each having a depth that reaches thefirst wiring pattern 12 are formed. Then,second wiring patterns 16 connected to thefirst wiring patterns 12 via the first viaholes 14 x are formed on the firstinterlayer insulating film 14 by the semi-additive process. - To explain in detail, a seed Cu layer (not shown) is formed on inner surfaces of the first via
holes 14 x and the firstinterlayer insulating film 14 by the electroless plating or the sputter method, and then a resist film (not shown) having opening portions that correspond to thesecond wiring patterns 16 is formed. Then, Cu film patterns (not shown) are formed in the opening portions in the resist film by the electrolytic plating using the seed Cu layer as a plating power-supply layer. Then, the resist film is removed and then the seed Cu film is etched while using the Cu film patterns as a mask. In this case, the subtractive process or the full additive process may be used in place of the semi-additive process. - Then, as shown in
FIG. 3C , a secondinterlayer insulating film 18 made of the same material as the firstinterlayer insulating film 14 is formed on thesecond wiring patterns 16, and then second viaholes 18 x are formed in predetermined portions of the secondinterlayer insulating film 18 on thesecond wiring patterns 16. Then,third wiring patterns 20 connected to thesecond wiring patterns 16 via the second viaholes 18 x are formed on the secondinterlayer insulating film 18 by the same method as the method of forming thesecond wiring patterns 16. - At this time, the
third wiring patterns 20 are formed in a state that a first connecting pad C1 to which the bump of the first semiconductor chip is connected later and a second connecting pad C2 to which the bump of the second semiconductor chip is connected are provided thereto. - Then, as shown in
FIG. 3D , a solder resist film 22 (protection insulating film) having an openingportion 22 x to expose collectively the packaging area A, in which a plurality of first, second connecting pads C1, C2 of thethird wiring patterns 20 are arranged, is formed. That is, the solder resistfilm 22 is formed to surround the packaging area A. - Then, as shown in
FIG. 3E , an Ni (nickel)/Au (gold)layer 21 is formed on thethird wiring patterns 20 containing the first, second connecting pads C1, C2, which are exposed from the packaging area A, by the electroless plating while using the solder resistfilm 22 as a mask. - Then, as shown in
FIG. 3F , a first semiconductor chip 24 (first electronic parts) havingbumps 24 a is prepared. Thissemiconductor chip 24 is obtained by grinding a semiconductor wafer (not shown) having elements such as transistors, etc. and connecting terminals on the element forming surface side to reduce a thickness and then dicing the semiconductor wafer into individual pieces. The semiconductor chip 24 (except thebumps 24 a) is reduced in thickness up to 150 μm or less, preferably 10 to 100 μm. Thebumps 24 a of thefirst semiconductor chip 24 are formed on the connecting terminals of thesemiconductor chip 24, before or after the semiconductor wafer is subjected to the dicing. - Then, the
bumps 24 a of thefirst semiconductor chip 24 are flip-chip connected to the Ni/Au layers 21 on the first connecting pads C1 of the third wiring patterns 20 (FIG. 3E ). As thebumps 24 a of thefirst semiconductor chip 24, the Au bump, the solder bump, or the like may be used. When the Au bump is used, Au and Au are bonded by the ultrasonic wave. Also, when the solder bump is used, the solder and Au are bonded by the reflow heating. - Then, as shown in
FIG. 3G , a second semiconductor chip 26 (second electronic parts) havingbumps 26 a and having an area that is larger than an area of thefirst semiconductor chip 24 is prepared. Thebumps 26 a of thesecond semiconductor chip 26 are flip-chip connected to the Ni/Au layers 21 on the second connecting pads C2 of the third wiring patterns 20 (FIG. 3E ) arranged on the outside of the periphery of thefirst semiconductor chip 24. Accordingly, thesecond semiconductor chip 26 is packaged at a predetermined interval from the upper surface of thefirst semiconductor chip 24, and thefirst semiconductor chip 24 is installed into a space between the lower surface of thesecond semiconductor chip 26 and the wiring substrate. - As a consequence, a height of the
bumps 26 a of thesecond semiconductor chip 26 is set higher than a thickness containing thebumps 24 a of thefirst semiconductor chip 24. As an example of this, a height of thebumps 26 a of thesecond semiconductor chip 26 is set to about 100 μm when a thickness of thefirst semiconductor chip 24 is about 50 μm and a height of thebumps 24 a is about 20 μm. - In this case, the semiconductor chip is taken as an example of the electronic parts. But various electronic parts such as the capacitor parts, or the like may be employed.
- Then, as shown in
FIG. 3H , a filling insulatingbody 28 is formed by filling the underfill resin in the clearance under thefirst semiconductor chip 24, the clearances on both surface sides of thefirst semiconductor chip 24, the clearance between the upper surface of thefirst semiconductor chip 24 and the lower surface of thesecond semiconductor chip 26, and the clearances between the side surfaces of thesecond semiconductor chip 26 and the openingportion 22 x of the solder resistfilm 22 and then thermally treating the resin to cure. Thus, not only thefirst semiconductor chip 24 is buried in the filling insulatingbody 28 but also the clearances under thesecond semiconductor chip 26 and on the side surface side thereof are filled with the filling insulatingbody 28. The filling insulatingbody 28 on the side surface side of thesecond semiconductor chip 26 is formed in a state that such body is dammed up by the side surface of the openingportion 22 x of the solder resistfilm 22. - As the filling insulating
body 28, in order to improve the reliability such as the crack resistance, etc., it is preferable that the resin which contains filler (silica), and has a coefficient of thermal expansion (CTE) of 20 to 30 ppm/° C. and has a Young's modulus of 10 to 15 GPa is used. - In this fashion, the
first semiconductor chip 24 is mounted on the wiring substrate in a state that suchfirst semiconductor chip 24 is buried in the filling insulatingbody 28, and thesecond semiconductor chip 26 is mounted on the wiring substrate in a state that suchsecond semiconductor chip 26 is stacked three-dimensionally over thefirst semiconductor chip 24. - With the above, an electronic parts built-in
substrate 1 of the present embodiment is completed. - In this case, as described above, in the present embodiment, in order to bury the
first semiconductor chip 24 in the filling insulatingbody 28, the solder resistfilm 22 having the openingportion 22 x to expose collectively the packaging area A in which a plurality of first, second connecting pads C1, C2 are arranged is formed. Such structure is also suitable from such a respect that a desired bonding area can be assured upon bonding thebumps - In other words, if the method of forming the continuous solder resist film having the opening portions that expose the major portions of the connecting pads C1, C2 of the
third wiring patterns 20 respectively is employed, the opening portions in the solder resist film are liable to displace from the major portions of the connecting pads C1, C2 in formation due to displacements in the forming step when a pitch between the connecting pads C1, C2 is narrowed. Therefore, the bonding area between the bumps of the semiconductor chip and the connecting pads C1, C2 is reduced and the bonding failure, and the like are readily caused with the reduction in a bonding strength of the bumps. - In the electronic parts built-in
substrate 1 of the present embodiment, the first tothird wiring patterns base substrate 10 in a multi-layered fashion, and then thesewiring patterns holes interlayer insulating films third wiring patterns 20 have a plurality of connecting pads C1, C2, and the solder resistfilm 22 having the openingportion 22 x to expose collectively the packaging area A in which the first, second connecting pads C1, C2 are arranged is formed on the secondinterlayer insulating film 18. Then, thebumps 24 a of thefirst semiconductor chip 24 are flip-chip connected to the Ni/Au layers 21 on the first connecting pads C1 of thethird wiring patterns 20. - Also, the
bumps 26 a of thesecond semiconductor chip 26, which have a larger area than an area of thefirst semiconductor chip 24, are flip-chip connected to the Ni/Au layers 21 on the second connecting pads C2 arranged on the outside of the periphery of thefirst semiconductor chip 24. Then, a height of thebumps 26 a of thesecond semiconductor chip 26 is set higher than a thickness containing thebumps 24 a of thefirst semiconductor chip 24, whereby thefirst semiconductor chip 24 is installed into an area between the lower surface of thesecond semiconductor chip 26 and the wiring substrate. - In addition, the filling insulating
body 28 is filled in the clearances under thefirst semiconductor chip 24 and thesecond semiconductor chip 26 and on the side surface sides thereof, and thefirst semiconductor chip 24 is mounted to be buried in the filling insulatingbody 28. - In this manner, in the present embodiment, the
first semiconductor chip 24 is buried in the filling insulatingbody 28 made of the underfill resin for which the material having a high crack resistance can be easily chosen. For this reason, no crack is generated in the filling insulatingbody 28 on the peripheral portion of thefirst semiconductor chip 24 during the temperature cycle test, and thus the reliability of the electronic parts built-insubstrate 1 can be improved. - Also, in the
related arts first semiconductor chip 24, the special steps such as the step of patterning the insulating film having the opening portion in the packaging area, the step of forming the flat interlayer insulating film by filling the insulating film in the clearances between the electronic parts packaged in the packaging area and the insulating film, etc. are required. - In contrast, in the present embodiment, the first and second semiconductor chips 24, 26 are flip-chip connected in sequence to the wiring substrates manufactured by the normal manufacturing method such that the
first semiconductor chip 24 is installed in the space under thesecond semiconductor chip 26, and then the filling insulatingbody 28 is filled at a time in the clearances under the first and second semiconductor chips 24, 26. Therefore, the electronic parts built-insubstrate 1 of the present embodiment can be manufactured by very simple manufacturing steps and at a low cost rather than therelated arts - Also, unlike the
related art 2, since there is no necessity to consider the flatness in forming the filling insulatingbody 28, there is no necessity to control finely a supply amount of the underfill resin. - Further, unlike the
related arts related arts - In this case, in the present embodiment, the substrate in which three wiring patterns are stacked on the base substrate is exemplified as the wiring substrate. But various wiring substrates in which the wiring patterns are provided in the n-layered (n is an integer of 1 or more) fashion may be employed. Also, a mode in which the n-layered (n is an integer of 1 or more) wiring pattern is also formed on the back surface side of the
base substrate 10 may be employed.
Claims (12)
1. An electronic parts built-in substrate comprising:
a wiring substrate including a wiring pattern having connecting pads;
a first electronic parts a bump of which is flip-chip connected to the connecting pad;
a second electronic parts a bump of which is flip-chip connected to the connecting pad arranged on an outside of a periphery of the first electronic parts and which is packaged at a predetermined interval from an upper surface of the first electronic parts; and
a filling insulating body filled in a clearance between the first electronic parts and the wiring substrate, and clearances between the second electronic parts and the first electronic parts, and the wiring substrate;
wherein the first electronic parts is buried in the filling insulating body.
2. An electronic parts built-in substrate according to claim 1 , wherein a height of the bump of the second electronic parts is set higher than a thickness that contains the bump of the first electronic parts.
3. An electronic parts built-in substrate according to claim 1 , wherein a thickness of the first electronic parts except the bump is 150 μm or less.
4. An electronic parts built-in substrate according to claim 1 , wherein a protection insulating film in which an opening portion to open collectively a packaging area in which the first and second electronic parts are packaged is provided is formed on the wiring substrate, and the filling insulating body is formed to extend from a side surface of the second electronic parts to a side surface of the opening portion of the protection insulating film.
5. An electronic parts built-in substrate according to claim 1 , wherein the filling insulating body is formed of a resin containing a filler and having a coefficient of thermal expansion of 20 to 30 ppm/° C.
6. An electronic parts built-in substrate according to claim 1 , wherein the electronic parts is a semiconductor chip.
7. A method of manufacturing an electronic parts built-in substrate comprising the steps of:
preparing a wiring substrate including a wiring pattern having connecting pads;
flip-chip connecting a bump of a first electronic parts to the connecting pad;
flip-chip connecting a bump of a second electronic parts to the connecting pad arranged on an outside of a periphery of the first electronic parts to package the second electronic parts at a predetermined interval from an upper surface of the first electronic parts; and
filling a filling insulating body in a clearance between the first electronic parts and the wiring substrate, and clearances between the second electronic parts and the first electronic parts, and the wiring substrate, to bury the first electronic parts in the filling insulating body.
8. A method of manufacturing an electronic parts built-in substrate according to claim 7 , further comprising the step of:
forming a protection insulating film having an opening portion that exposes collectively a plurality of connecting pads on the wiring substrate, prior to the step of flip-chip connecting the bump of the first electronic parts to the connecting pad; and
wherein the filling insulating body is formed to extend from a side surface of the second electronic parts to a side surface of the opening portion of the protection insulating film in the step of filling the filling insulating body.
9. A method of manufacturing an electronic parts built-in substrate according to claim 7 , wherein a height of the bump of the second electronic parts is set higher than a thickness that contains the bump of the first electronic parts.
10. A method of manufacturing an electronic parts built-in substrate according to claim 7 , wherein a thickness of the first electronic parts except the bump is 150 μm or less.
11. A method of manufacturing an electronic parts built-in substrate according to claim 7 , wherein the filling insulating body is formed of a resin containing a filler and having a coefficient of thermal expansion of 20 to 30 ppm/° C.
12. A method of manufacturing an electronic parts built-in substrate according to claim 7 , wherein the electronic parts is a semiconductor chip.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/049,958 US7198986B2 (en) | 2003-09-29 | 2005-02-04 | Electronic parts built-in substrate and method of manufacturing the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003-337323 | 2003-09-29 | ||
JP2003337323A JP4198566B2 (en) | 2003-09-29 | 2003-09-29 | Manufacturing method of electronic component built-in substrate |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/049,958 Division US7198986B2 (en) | 2003-09-29 | 2005-02-04 | Electronic parts built-in substrate and method of manufacturing the same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050067715A1 true US20050067715A1 (en) | 2005-03-31 |
Family
ID=34191565
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/918,348 Abandoned US20050067715A1 (en) | 2003-09-29 | 2004-08-16 | Electronic parts built-in substrate and method of manufacturing the same |
US11/049,958 Active 2024-11-23 US7198986B2 (en) | 2003-09-29 | 2005-02-04 | Electronic parts built-in substrate and method of manufacturing the same |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/049,958 Active 2024-11-23 US7198986B2 (en) | 2003-09-29 | 2005-02-04 | Electronic parts built-in substrate and method of manufacturing the same |
Country Status (5)
Country | Link |
---|---|
US (2) | US20050067715A1 (en) |
EP (1) | EP1519415A3 (en) |
JP (1) | JP4198566B2 (en) |
KR (1) | KR20050031364A (en) |
TW (1) | TW200515585A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080246163A1 (en) * | 2004-09-28 | 2008-10-09 | Kazumasa Tanida | Semiconductor Device |
US20100320622A1 (en) * | 2009-06-23 | 2010-12-23 | Shinko Electric Industries Co., Ltd. | Electronic component built-in wiring substrate and method of manufacturing the same |
US20110227215A1 (en) * | 2010-03-19 | 2011-09-22 | Boseong Kim | Electronic device, package including the same and method of fabricating the package |
US20120104623A1 (en) * | 2010-10-28 | 2012-05-03 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Stepped Interposer for Stacking and Electrically Connecting Semiconductor Die |
US20150223330A1 (en) * | 2014-02-05 | 2015-08-06 | Shinko Electric Industries Co., Ltd. | Wiring substrate, semiconductor device, method of manufacturing wiring substrate, and method of manufacturing semiconductor device |
US11842972B2 (en) | 2004-09-28 | 2023-12-12 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102004047753B4 (en) * | 2004-09-30 | 2009-01-02 | Advanced Micro Devices, Inc., Sunnyvale | Improved chip contacting arrangement for chip carriers for flip-chip applications |
JP2007123524A (en) * | 2005-10-27 | 2007-05-17 | Shinko Electric Ind Co Ltd | Substrate with built-in electronic part |
US20080157316A1 (en) * | 2007-01-03 | 2008-07-03 | Advanced Chip Engineering Technology Inc. | Multi-chips package and method of forming the same |
KR100867150B1 (en) * | 2007-09-28 | 2008-11-06 | 삼성전기주식회사 | Printed circuit board with embedded chip capacitor and method for embedding chip capacitor |
JP5395360B2 (en) * | 2008-02-25 | 2014-01-22 | 新光電気工業株式会社 | Manufacturing method of electronic component built-in substrate |
FI122217B (en) | 2008-07-22 | 2011-10-14 | Imbera Electronics Oy | Multi-chip package and manufacturing method |
US8441804B2 (en) | 2008-07-25 | 2013-05-14 | Infineon Technologies Ag | Semiconductor device and method of manufacturing a semiconductor device |
US7989950B2 (en) * | 2008-08-14 | 2011-08-02 | Stats Chippac Ltd. | Integrated circuit packaging system having a cavity |
US8823160B2 (en) * | 2008-08-22 | 2014-09-02 | Stats Chippac Ltd. | Integrated circuit package system having cavity |
US8390083B2 (en) | 2009-09-04 | 2013-03-05 | Analog Devices, Inc. | System with recessed sensing or processing elements |
JP5667381B2 (en) | 2010-06-01 | 2015-02-12 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | Semiconductor device and manufacturing method thereof |
WO2012051340A1 (en) | 2010-10-12 | 2012-04-19 | Analog Devices, Inc. | Microphone package with embedded asic |
KR101301424B1 (en) * | 2011-11-28 | 2013-08-28 | 삼성전기주식회사 | Printed circuit board and method of manufacturing the same |
KR101420514B1 (en) | 2012-10-23 | 2014-07-17 | 삼성전기주식회사 | Substrate structure having electronic components and method of manufacturing substrate structure having electronic components |
US9847462B2 (en) | 2013-10-29 | 2017-12-19 | Point Engineering Co., Ltd. | Array substrate for mounting chip and method for manufacturing the same |
CN103745967A (en) * | 2013-12-05 | 2014-04-23 | 南通富士通微电子股份有限公司 | Lead frame and packaging structure |
US9653322B2 (en) * | 2014-06-23 | 2017-05-16 | Infineon Technologies Austria Ag | Method for fabricating a semiconductor package |
SG11201704445XA (en) | 2014-12-19 | 2017-07-28 | Cardlab Aps | A method and an assembly for generating a magnetic field and a method of manufacturing an assembly |
EP3035230A1 (en) | 2014-12-19 | 2016-06-22 | Cardlab ApS | A method and an assembly for generating a magnetic field |
EP3082071A1 (en) | 2015-04-17 | 2016-10-19 | Cardlab ApS | Device for and method of outputting a magnetic field |
US9666558B2 (en) | 2015-06-29 | 2017-05-30 | Point Engineering Co., Ltd. | Substrate for mounting a chip and chip package using the substrate |
KR102494332B1 (en) * | 2015-07-15 | 2023-02-02 | 삼성전기주식회사 | Electronic Component Package |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5646828A (en) * | 1995-02-24 | 1997-07-08 | Lucent Technologies Inc. | Thin packaging of multi-chip modules with enhanced thermal/power management |
US6335571B1 (en) * | 1997-07-21 | 2002-01-01 | Miguel Albert Capote | Semiconductor flip-chip package and method for the fabrication thereof |
US20020033378A1 (en) * | 2000-07-31 | 2002-03-21 | Ngk Spark Plug Co., Ltd. | Printed wiring substrate and method for fabricating the same |
US6369448B1 (en) * | 2000-01-21 | 2002-04-09 | Lsi Logic Corporation | Vertically integrated flip chip semiconductor package |
US20040036152A1 (en) * | 2002-07-18 | 2004-02-26 | Harper Timothy V. | Integrated circuit package employing flip-chip technology and method of assembly |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1084076A (en) * | 1996-09-05 | 1998-03-31 | Hitachi Ltd | Semiconductor device and method for manufacturing the same |
JP3367886B2 (en) * | 1998-01-20 | 2003-01-20 | 株式会社村田製作所 | Electronic circuit device |
JPH11274734A (en) | 1998-03-20 | 1999-10-08 | Sony Corp | Electronic circuit device and its manufacture |
SG75873A1 (en) * | 1998-09-01 | 2000-10-24 | Texas Instr Singapore Pte Ltd | Stacked flip-chip integrated circuit assemblage |
CN1199536C (en) * | 1999-10-26 | 2005-04-27 | 伊比登株式会社 | Multilayer printed wiring board and method of producing multilayer printed wiring board |
-
2003
- 2003-09-29 JP JP2003337323A patent/JP4198566B2/en not_active Expired - Fee Related
-
2004
- 2004-08-16 US US10/918,348 patent/US20050067715A1/en not_active Abandoned
- 2004-08-17 EP EP04254934A patent/EP1519415A3/en not_active Ceased
- 2004-08-17 KR KR1020040064544A patent/KR20050031364A/en not_active Application Discontinuation
- 2004-08-27 TW TW093125809A patent/TW200515585A/en unknown
-
2005
- 2005-02-04 US US11/049,958 patent/US7198986B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5646828A (en) * | 1995-02-24 | 1997-07-08 | Lucent Technologies Inc. | Thin packaging of multi-chip modules with enhanced thermal/power management |
US6335571B1 (en) * | 1997-07-21 | 2002-01-01 | Miguel Albert Capote | Semiconductor flip-chip package and method for the fabrication thereof |
US6369448B1 (en) * | 2000-01-21 | 2002-04-09 | Lsi Logic Corporation | Vertically integrated flip chip semiconductor package |
US20020033378A1 (en) * | 2000-07-31 | 2002-03-21 | Ngk Spark Plug Co., Ltd. | Printed wiring substrate and method for fabricating the same |
US20040036152A1 (en) * | 2002-07-18 | 2004-02-26 | Harper Timothy V. | Integrated circuit package employing flip-chip technology and method of assembly |
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9831204B2 (en) | 2004-09-28 | 2017-11-28 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
US10522494B2 (en) | 2004-09-28 | 2019-12-31 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
US9117774B2 (en) | 2004-09-28 | 2015-08-25 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
US11842972B2 (en) | 2004-09-28 | 2023-12-12 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
US11355462B2 (en) | 2004-09-28 | 2022-06-07 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
US8405227B2 (en) * | 2004-09-28 | 2013-03-26 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
US8754535B2 (en) | 2004-09-28 | 2014-06-17 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
US10818628B2 (en) | 2004-09-28 | 2020-10-27 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
US20080246163A1 (en) * | 2004-09-28 | 2008-10-09 | Kazumasa Tanida | Semiconductor Device |
US9721865B2 (en) | 2004-09-28 | 2017-08-01 | Rohm Co., Ltd. | Semiconductor device with a semiconductor chip connected in a flip chip manner |
US8274153B2 (en) * | 2009-06-23 | 2012-09-25 | Shinko Electric Industries Co., Ltd. | Electronic component built-in wiring substrate |
US20100320622A1 (en) * | 2009-06-23 | 2010-12-23 | Shinko Electric Industries Co., Ltd. | Electronic component built-in wiring substrate and method of manufacturing the same |
US20110227215A1 (en) * | 2010-03-19 | 2011-09-22 | Boseong Kim | Electronic device, package including the same and method of fabricating the package |
US9337116B2 (en) * | 2010-10-28 | 2016-05-10 | Stats Chippac, Ltd. | Semiconductor device and method of forming stepped interposer for stacking and electrically connecting semiconductor die |
US20120104623A1 (en) * | 2010-10-28 | 2012-05-03 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Stepped Interposer for Stacking and Electrically Connecting Semiconductor Die |
US20150223330A1 (en) * | 2014-02-05 | 2015-08-06 | Shinko Electric Industries Co., Ltd. | Wiring substrate, semiconductor device, method of manufacturing wiring substrate, and method of manufacturing semiconductor device |
US9622347B2 (en) * | 2014-02-05 | 2017-04-11 | Shinko Electric Industries Co., Ltd. | Wiring substrate, semiconductor device, method of manufacturing wiring substrate, and method of manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
EP1519415A3 (en) | 2008-04-09 |
TW200515585A (en) | 2005-05-01 |
US20050130349A1 (en) | 2005-06-16 |
US7198986B2 (en) | 2007-04-03 |
KR20050031364A (en) | 2005-04-06 |
JP2005108962A (en) | 2005-04-21 |
EP1519415A2 (en) | 2005-03-30 |
JP4198566B2 (en) | 2008-12-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7198986B2 (en) | Electronic parts built-in substrate and method of manufacturing the same | |
US10212818B2 (en) | Methods and apparatus for a substrate core layer | |
US7573135B2 (en) | Electronic parts packaging structure in which a semiconductor chip is mounted on a wiring substrate and buried in an insulation film | |
US7057290B2 (en) | Electronic parts packaging structure and method of manufacturing the same | |
US5744758A (en) | Multilayer circuit board and process of production thereof | |
KR101003437B1 (en) | Electronic parts packaging structure and method of manufacturing the same | |
JP4927146B2 (en) | Manufacturing method of electronic component mounting structure | |
JP4133782B2 (en) | Electronic component mounting structure and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SHINKO ELECTRIC INDUSTRIES CO., LTD., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SUNOHARA, MASAHIRO;REEL/FRAME:015705/0500 Effective date: 20040728 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |