US20050068432A1 - Image sensor and method for driving an image sensor for reducing fixed pattern noise - Google Patents
Image sensor and method for driving an image sensor for reducing fixed pattern noise Download PDFInfo
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- US20050068432A1 US20050068432A1 US10/967,219 US96721904A US2005068432A1 US 20050068432 A1 US20050068432 A1 US 20050068432A1 US 96721904 A US96721904 A US 96721904A US 2005068432 A1 US2005068432 A1 US 2005068432A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
- H04N25/671—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction
- H04N25/672—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction between adjacent sensors or output registers for reading a single image
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/701—Line sensors
- H04N25/7013—Line sensors using abutted sensors forming a long line
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
Definitions
- FIG. 1A is a partial block diagram showing the arrangement of a conventional contact image sensor having an amplifier element, which is disclosed in Journal of Television Society Vol. 47, No. 9 (1993), pp. 1180.
- this contact image sensor a plurality of amplifier type semiconductor photosensor chips having amplifier elements in units of pixels are mounted.
- FIG. 1A shows the arrangement of a single sensor chip.
- FIG. 1B shows a state wherein a plurality of sensor chips are connected. In order to enable the output of a specific chip, the analog switch 37 of that chip is energized.
- one sensor chip comprises a plurality of sensor elements (phototransistors 9 ), an output line 3 ( 4 ) which commonly receive the outputs from these transistors 9 , differential amplifier 33 , clamping circuit 204 , and buffer amplifier 36 , the above-mentioned analog switch 37 , and the like.
- FPN fixed pattern noise
- the bipolar transistor 9 constructs a sensor portion of an photo-electric conversion element.
- Each transistor 9 is connected to a MOS transistor 27 ( 28 ), MOS transistor 31 ( 32 ), capacitances C TS 1 and C TN 2 , and MOS transistor 25 ( 26 ), and the MOS transistors 25 and 26 of the respective bits are connected to the common output lines 3 and 4 .
- Reference symbols C HS and C HN denote capacitances for the output lines 3 and 4 .
- the output lines 3 and 4 are connected to the differential amplifier 33 via voltage-follower amplifiers 13 and 14 .
- a light signal i.e., a charge
- h is a Planck constant, and ⁇ is the frequency of the light
- ⁇ is the frequency of the light
- the transistor 9 is set in a floating state (by turning off ⁇ ERS ) and ⁇ TS is turned on to transfer the charge accumulated on the PN junction to the light signal holding capacitance C TS 1 .
- a reset pulse ⁇ ERS is turned on to reset the sensor (transistor 9 ).
- the charge transferred to the capacitance C TS 1 contains noise components.
- ⁇ TN is turned on to transfer a noise (N) signal of the sensor to the noise signal holding capacitance C TN 2 .
- a reset pulse ⁇ ERS is turned on to enable a MOS transistor 29
- the reset pulse ⁇ ERS is turned on to enable a MOS transistor 30 . Since the MOS transistors 29 and 30 are ON, the sensor transistor 9 is reset and then starts the next accumulation.
- Some components of the charges accumulated on the C TS 1 and C TN 2 are respectively shifted to the output line capacitances C HS and C HN during the next accumulation. This operation is called “capacitive division” for the sake of simplicity since the original charges accumulated on C TS 1 and C TN 2 are divided as a result of movement of the charges between the two capacitances.
- the “capacitive division” is activated by the MOS transistors 25 and 26 when a control timing signal ⁇ N is ON. The “capacitive division” will be explained below.
- MOS transistors 5 and 6 are turned on by a signal ⁇ HC .
- MOS transistors 25 and 26 are turned on by the timing signal ⁇ N output from a shift register (not shown).
- the MOS transistors 25 and 26 are ON, data in the light signal holding capacitance C TS 1 and noise signal holding capacitance C TN 2 (some components of charges) are respectively transferred to the capacitances C HS 7 and C HN 8 connected to the common output lines 3 and 4 .
- the potential that appears on the output line 3 ( 4 ) is determined by the ratio between the capacitances C HS 7 and C TS 1 (the ratio between C HN 8 and C TN 2 ).
- the potential on the output line 3 ( 4 ) is amplified by the differential amplifier 33 via an amplifier 13 ( 14 ).
- one sensor chip has sensor elements 9 for a plurality of bits.
- the capacitances C HS 7 and C HN 8 are reset by turning on the MOS transistors 5 and 6 , and a drive signal ⁇ N for that bit is then supplied to read out data accumulated on the capacitances C TS and C TN to the common capacitances C HS 7 and C HN 8 .
- the charges accumulated on the sensors (transistors 9 ) of the respective bits are read out to the capacitances C HS 7 and C HN 8 .
- Voltages induced on the capacitances C HS 7 and C HN 8 are input to the differential amplifier 33 via the voltage-follower amplifiers 13 and 14 .
- Fixed pattern noise FPN in the sensor IC mainly arises from variations of h FE or the like of the bipolar transistors 9 of the respective pixels (bits). Such variations are reflected in the charges accumulated on the holding capacitances C TS and C TN .
- FPN removal using the S-N method removes noise resulting from h FE variations of the bipolar transistors 9 in units of pixels by detecting any level differences between the signal lines by the differential amplifier 33 upon reading out the charges accumulated on the holding capacitances C TS and C TN onto the common signal lines 3 and 4 .
- the S-N method using the differential amplifier 33 is effective for removing FPN produced in the sensor chip.
- the differential amplifiers 33 and buffer amplifiers 36 are arranged in units of chips.
- the DC components of the output voltages vary due to variations of offset potentials.
- Such variations of the DC offset voltages among chips will be referred to as “FPN resulting from inter-chip differences (inter-chip FPN)” in contrast to “FPN produced in the chip (intra-chip FPN)” in this specification.
- the clamping circuit 204 copes with inter-chip FPN resulting from the differential amplifier 33 . That is, the clamping circuit 204 is constructed by a capacitance 34 for cutting DC. components from the output from the amplifier 33 , and a MOS transistor 35 for fixing to earth level the potential between this capacitance 34 and the input portion of the amplifier 36 , that shifts to the minus side. With this arrangement, the clamping circuit 204 can prevent inter-chip FPN attributed to the differential amplifier 33 .
- each sensor chip includes a large-scale analog circuit such as a sensor, holding capacitances, and the like, and 10 to 20 chips are mounted. For this reason, the chip area for the analog circuit portion increases, and it is hard to reduce cost.
- each sensor chip includes both a digital circuit such as MOS transistors for light signal read and reset, and the aforementioned analog circuit, and the sensor output is readily influenced by noise produced by the digital circuit.
- a digital circuit such as MOS transistors for light signal read and reset
- the aforementioned analog circuit and the sensor output is readily influenced by noise produced by the digital circuit.
- FIG. 1A is the equivalent circuit diagram of a conventional image sensor
- FIG. 1B is a diagram for explaining connections among individual sensor chips in the conventional image sensor shown in FIG. 1A ;
- FIG. 2 is a timing chart for explaining the operation of the conventional image sensor shown in FIG. 1A ;
- FIG. 3 is a schematic view showing an image sensor assembly according to the first embodiment of the present invention.
- FIG. 4A is the equivalent circuit diagram of an image sensor of the first embodiment
- FIG. 4B is a diagram for explaining connections of principal part of the image sensor of the first embodiment
- FIG. 5 is a timing chart showing one operation example of the image sensor of the first embodiment
- FIG. 6 is a timing chart showing another operation example of the image sensor of the first embodiment
- FIG. 7 is the equivalent circuit diagram of an image sensor according to the second embodiment of the present invention.
- FIG. 8 is a timing chart showing one operation example of the image sensor of the second embodiment
- FIG. 9 is the equivalent circuit diagram of an image sensor according to the third embodiment of the present invention.
- FIG. 10 is a timing chart showing one operation example of the image sensor of the third embodiment.
- FIG. 3 shows the arrangement of an assembly 300 of a contact image sensor according to the first embodiment.
- the assembly 300 has a plurality of sensor chips 100 , 100 ′, 100 ′′, . . . , 100 n , a pair of common output lines 101 and 102 from these sensor chips, and one amplifier chip 200 .
- each of the sensor chips 100 . . . has two output terminals, which are respectively connected to the common output lines 101 and 102 .
- the two input terminals of the amplifier chip 200 are respectively connected to the common output lines 101 and 102 .
- the amplifier chip 200 has a single output terminal V OUT .
- the output from this terminal V OUT is that of the assembly 300 .
- the sensor chips 100 , 100 ′, and 100 ′′, and the amplifier chip 200 are mounted on a single mounting substrate 300 , but the amplifier chip 200 may be mounted on another mounting substrate.
- the size of the assembly 300 can be reduced, and external noise that may be produced in the outputs of the sensor chips 100 , . . . can be reduced, thus stabilizing the output.
- the amplifier chip 200 which is encapsulated in a ceramic package may be mounted on the mounting substrate 300 by soldering, or its bear chip may be mounted on the mounting substrate 300 by dye-bonding.
- the bear chip is mounted by dye-bonding, common chucks can be used for the sensor and amplifier chips if the short side length of each sensor chip is set to be substantially equal to that of the amplifier chip, thus reducing the number of steps in amounting process.
- FIG. 4A shows the equivalent circuit of each sensor chip ( 100 , 100 ′, 100 ′′, . . . ) and that of the amplifier chip 200 according to the first embodiment.
- the sensor chip according to the first embodiment has a plurality of photo-electric converters 10 , 10 ′, 10 ′′, . . . , noise signal holders 2 , 2 ′, 2 ′′, . . . for reading out noise signals (to be abbreviated as “N signals” hereinafter) from these photo-electric converters and holding the N signals, S signal holders 1 , 1 ′, 1 ′′, . . .
- S signals for reading out light signals (to be referred to as “S signals” hereinafter) from the photo-electric converters and holding the S signals, an N signal output line 4 for commonly outputting N signals, an S signal output line 3 for commonly outputting S signals, reset circuits 5 and 6 for resetting the N and S signal output lines 4 and 3 , and a read-out circuit for reading out signals held by the N signal holders 2 , 2 ′, 2 ′′, . . . and those held by the S signal holders 1 , 1 ′, 1 ′′, . . . by capacitance or capacitive division between capacitances C HN 8 and C HS 7 of the N and S signal output lines 4 and 3 .
- the capacitance division will be explained later.
- the photo-electric converter 10 , 10 ′, 10 ′′, . . . preferably use bipolar elements such as, e.g., BASIS, or amplifiers each consisting of a photo-diode and MOS transistor.
- the signal holder preferably comprises a capacitor, as shown in FIG. 4A
- the reset circuit preferably comprises a transistor circuit.
- Each of the photo-electric converters 10 , 10 ′, 10 ′′, . . . is connected to a pair of MOS transistors 27 and 28 .
- An array of MOS transistors 27 commonly receive a control signal ⁇ TS .
- An array of MOS transistors 28 commonly receive a control signal ⁇ TN .
- S signals are stored in the S signal holders (capacitances) C TS 1 , 1 ′, 1 ′′, . . . ; when a transfer pulse ⁇ TN is turned on, N signals are stored in the N signal holders.
- the S and N signals detected by the photo-electric converters 10 , 10 ′, 10 ′′, . . . are respectively stored in the holders C TS 1 , 1 ′, 1 ′′, . . . , and the holders C TN 2 , 2 ′, 2 ′′, . . . .
- the common output lines 3 and 4 In order to supply the outputs from the photo-electric converters 10 , 10 ′, 10 ′′, . . . onto the common output lines 3 and 4 , the common output lines 3 and 4 must be reset before that.
- the MOS transistors 5 and 6 are turned on to reset the S and N signal output lines 3 and 4 . Upon being reset in this way, the lines 3 and 4 are ready to transfer data to the capacitances C HS 7 and C HN 8 .
- the MOS transistors 25 and 26 are then enabled using a shift pulse ⁇ 1 of a shift register SR to output data (charges) in the capacitances C TS and C TN in turn onto the common output lines 3 and 4 by capacitance division.
- Some components of the charges accumulated on C TS and C TN are respectively transferred to the capacitances C HS 7 and C HN 8 .
- the charge accumulated on C TS is divided into C TS 1 and C HS 7
- the charge accumulated on C TN is divided into C TN 2 and C HN 8 .
- the potential between these two capacitances will be referred to as the capacitively divided output in this specification.
- each of the amplifiers 11 and 12 uses a source-follower circuit including two transistors, but may use, e.g., a normal voltage-follower circuit.
- Data detected by the sensor element 10 is output onto the S and N signal lines 101 and 102 in response to a shift pulse ⁇ 1 , as described above.
- data detected by the sensor element 10 ′ is similarly output onto the S and N signal lines 101 and 102 in response to a shift pulse ⁇ 2 .
- data detected by the sensor elements 10 ′′ is output onto the S and N signal lines 101 and 102 in response to a shift pulse ⁇ 3 .
- the sensor module ( 100 , 100 ′, 100 ′′, . . . ) as a semiconductor photosensor is connected to the S and N signal lines 101 and 102 and one amplifier chip 200 mounted on a single mounting substrate via terminals 99 mounted on the same mounting substrate by wire bonding. That is, S and N signals from the sensor modules ( 100 , 100 ′, 100 ′′, . . . ) are input to the amplifier chip 200 .
- the amplifier chip 200 shared by the plurality of sensor modules ( 100 , 100 ′, 100 ′′, . . . ) has a buffer amplifier 201 for receiving an N signal, a buffer amplifier 202 for receiving an S signal, a differential amplifier 203 for calculating the difference between the outputs from the amplifiers 201 and 202 , a voltage clamping circuit 204 connected to the output side of the differential amplifier 203 , and an output buffer amplifier 205 , as shown in FIG. 4A .
- the voltage clamping circuit 204 comprises a clamping capacitance 206 , and a MOS switch 207 , and has a function of clamping the input signal toward a clamping reset voltage V CD .
- the clamping circuit 204 for removing inter-chip FPN is mounted outside the plurality of sensor chips 100 , . . . but inside the amplifier chip 200 as a circuit common to these sensor chips. For this reason, clamping circuits ( 204 in FIG. 1A ) in units of sensor chips, which are required in the conventional image sensor ( FIG. 1A ), can be omitted.
- inter-chip FPN due to inter-chip variations of the source-follower amplifier 11 (or 12 ) remains unsolved.
- the drive control method for the image sensor of the first embodiment especially, the drive control method for removing inter-chip FPN will be explained below with reference to FIG. 5 .
- FIG. 5 shows signals ⁇ TN and ⁇ TS for determining the charge transfer timings of the converter 10 , shift pulses ⁇ 1 , ⁇ 2 , and ⁇ 3 from the shift register SR, a reset pulse ⁇ CHR for resetting the common signal lines 3 and 4 , and a reset pulse ⁇ CD for resetting the clamping circuit 204 in the amplifier chip 200 .
- FIG. 4B shows principal elements of the image sensor ( FIG. 4A ) of the first embodiment.
- the reset circuit which receives ⁇ CHR and the clamping circuit 204 which receives ⁇ CD are present between the capacitances C HS 7 , 7 ′, 7 ′′, . . . (capacitances C HN 8 , 8 ′, 8 ′′, . . . ) on the common output lines 3 , 3 ′, 3 ′′ (and output lines 4 , 4 ′, 4 ′′), and the output V OUT of the amplifier chip 200 .
- the MOS transistors 5 and 6 must be reset by ⁇ CHR at each shift timing ( ⁇ 1 , ⁇ 2 , ⁇ 3 , .
- DC offset variations resulting from the source-follower amplifiers 11 and 12 can be removed by driving the clamping circuit 204 in FIG. 4B . More specifically, referring to FIG. 4A , a clamping pulse ⁇ CD which changes LOW ⁇ “H” ⁇ LOW is input to the gate of the MOS transistor 207 . During the LOW period of ⁇ CD , the differential amplifier 203 outputs an output signal which reflects DC offset variations caused by the source-follower amplifiers 11 and 12 .
- This voltage is input to the DC cutoff capacitor (clamping capacitance) 206 .
- ⁇ CD changes from LOW to HIGH
- the source side of the MOS transistor 207 is clamped to a potential V CD .
- the potential difference across the two terminals of the DC cutoff capacitor 206 reflect DC offset variations caused by the source-follower amplifiers 11 and 12 .
- ⁇ CD changes from HIGH to LOW
- the MOS transistor 207 is turned off, the charge accumulated on the capacitor 206 is held at a charge value for canceling inter-chip FPN.
- V to output the clamping pulse ⁇ CD before each shift pulse ⁇ N (one of ⁇ 1 , ⁇ 2 , ⁇ 3 , . . . );
- the reset pulse ⁇ CHR goes HIGH and then LOW before the clamping pulse ⁇ CD goes HIGH.
- the MOS transistor 207 in the clamping circuit 204 is controlled by the control signal ⁇ CD .
- ⁇ CD is enabled after ⁇ CHR is enabled.
- the capacitances C HS 7 and C HN 8 are reset to desired voltages by ⁇ CHR immediately before the signals on the signal lines 3 and 4 are read out after ⁇ CHR .
- the state after the capacitances C HS 7 and C HS 8 have been reset is clamped by ⁇ CD , and is used as a reference state.
- the outputs after capacitance division contain Vth variations of the source-follower amplifiers 11 and 12 in units of chips.
- Vth variations are corrected by the above-mentioned operations, inter-chip FPN that has conventionally posed a problem can be removed without any dark correction.
- control timings of the clamping circuit 204 of the first embodiment are not limited to those shown in FIG. 5 .
- FIG. 6 shows another timing example that can be applied to the image sensor ( FIG. 4A ) of the first embodiment.
- the reset pulse ⁇ CHR is held at HIGH, and then goes LOW after the clamping pulse ⁇ CD goes LOW and before the shift pulse ⁇ N is turned on.
- the timing example shown in FIG. 6 since the reset state of the capacitances C HS 7 and C HN 8 by the reset pulse ⁇ CHR is clamped by the clamping pulse ⁇ CD , the same effect as in the timing example shown in FIG. 5 can be obtained.
- each sensor chip since the need for a differential amplifier in each sensor chip can be obviated as compared to the image sensor shown in FIG. 1A , the output portion of each sensor chip can be simplified, and the chip area of the analog portion in each sensor chip can be minimized. In addition, since the analog portion for all the sensor chips can be integrated using the common signal lines 101 and 102 , the chip area of each module can be minimized, thus attaining a cost reduction.
- the power supply for the sensor chips 100 , 100 ′, 100 ′′, . . . and that for the amplifier chip 200 are independently set, a broad dynamic range of the output can be maintained even when the sensor power supply voltage is decreased.
- a contact image sensor using a plurality of line sensor chips has been exemplified.
- the present invention is not limited to such specific sensor, but may be effective for a two-dimensional area sensor including a large number of sensor chips.
- FPN variations become more conspicuous than a 1-line contact sensor and, hence, it is very effective to apply the present invention.
- the amplification function when an amplification function is added to the amplifier chip 200 , the amplification function may be added to, e.g., the differential amplifier 203 or a gain amplifier may be inserted on the output side of the differential amplifier 203 .
- the sensor chip 100 and amplifier chip 200 use a common power supply.
- the sensor chip and amplifier chip may use different power supply voltages, or independent GND terminals may be used on the mounting substrate to reduce noise in analog output.
- FIG. 7 is a circuit diagram of an image sensor according to the second embodiment of the present invention.
- photo-electric converters in each of the sensor chips 100 , 100 ′, 100 ′′, . . . of the first embodiment are respectively constructed by photo-diodes 20 , 20 ′, 20 ′′, . . . , reset switches 21 , 21 ′, 21 ′′, . . . , NMOS source-follower transistors 22 , 22 ′, 22 ′′, . . . , transfer switches 23 , 23 ′, 23 ′′, . . . .
- each sensor chip has N signal holders 2 , 2 ′, 2 ′′, . . . , S signal holders 1 , 1 ′, 1 ′′, . . . , an N signal output line 4 , an S signal output line 3 , and reset switches 5 and 6 , as in the first embodiment ( FIG. 4A ).
- the characteristic feature of the second embodiment lies in that the level of a final output V OUT of a sensor assembly 300 can be adjusted by adding a gain amplifier 208 to an amplifier chip 200 ′.
- the gain amplifier 208 is added, the output V OUT of the assembly 300 suffers an individual difference due to individual offset variations in the gain amplifier 208 .
- Such individual difference will be referred to as an “inter-assembly FPN” hereinafter for the sake of simplicity.
- a clamping circuit 209 is added to remove this “inter-assembly FPN”.
- the capacitively divided outputs that appear on the N and S signal output lines 4 and 3 are impedance-converted by source-follower amplifiers 11 and 12 each including two transistors, and are then output onto S and N signal lines 101 and 102 via analog switches 14 and 15 .
- S and N signals on the S and N signal lines 101 and 102 are input to the amplifier chip 200 ′ mounted on the same chip as the sensor chips.
- a clamping control signal to the voltage clamping circuit 204 is ⁇ CD as in the first embodiment, and a clamping signal for controlling the voltage clamping circuit 209 is ⁇ CL .
- FIG. 8 is a timing chart of control signals in the second embodiment.
- the clamping signal ⁇ CD to the clamping circuit 204 must be generated at the charge transfer timing ( ⁇ 1 , ⁇ 2 , and ⁇ 3 in FIG. 8 ) of each bit as in the first embodiment, since it aims at removing FPN for each bit.
- the clamping signal ⁇ CL for the clamping circuit 209 need only be generated once for a start signal SP (equivalent to a signal SP in FIG. 2 ) which is generated once for the assembly 300 at the beginning of image reading, as shown in FIG. 8 .
- the voltage clamping circuit 209 reduces offset variations (“inter-assembly FPN”) for each module including the sensor chips 100 , 100 ′, 100 ′′, . . . , and the amplifier chip 200 ′, and a nearly uniform reference level of the module (i.e., the assembly) can be maintained. Since variations of the module (i.e., the assembly) can be reduced, variations in units of products can be reduced, and the manufacture of high-quality products can be achieved.
- inter-assembly FPN offset variations
- the power supplies and GND terminals for the sensor chips 100 , 100 ′, 100 ′′, . . . , and amplifier chip 200 ′ are isolated from each other on the mounting substrate, and the power supply voltages for the sensor chip and amplifier chip are respectively 3.3 V and 5.0 V.
- FIG. 8 shows the drive timing relationship among read-out signals ⁇ 1 , ⁇ 2 , and ⁇ 3 from a shift register SR, a reset pulse ⁇ CHR of the common signal lines 3 and 4 , and reset pulses ⁇ CD and ⁇ CL in the amplifier chip 200 ′.
- the second embodiment can remove all of “intra-chip FPN”, “inter-chip FPN”, and “inter-assembly FPN”.
- the inter-chip difference is around 10 mV in the conventional module, but is 3 mV or less in the second embodiment.
- ⁇ CD for controlling the clamping timing of the clamping circuit 204 is generated at the first bit in the second embodiment, but may be generated in synchronism with the generation timings of other bits.
- FIG. 9 is a circuit diagram showing the third embodiment of the present invention.
- N and S signals are read out time-serially (i.e., by time division), and the output state of N signals is clamped and is used as a reference signal.
- each of the sensor chips 100 , 100 ′, 100 ′′, . . . is substantially the same as that in the second embodiment, i.e., comprises photo-diodes 20 , 20 ′, 20 ′′, . . . , reset switches 21 , 21 ′, 21 ′′, . . . , NMOS source-follower transistors 22 , 22 ′, 22 ′′, . . . , transfer switches 23 , 23 ′, 23 ′′, . . . , N signal holders 2 , 2 ′, 2 ′′, . . . , and S signal holders 1 , 1 ′, 1 ′′, . . .
- N and S signals are time-serially (time-divisionally) read out onto a single common output line 55 . That is, the single common output line 55 is sequentially reset by a reset MOS transistor 56 . Since time-division driving is done, the number of source-follower amplifiers 11 including two transistors for amplifying N and S signals can be reduced to one as compared to the second embodiment.
- An amplifier chip 200 ′ of the third embodiment comprises an input buffer amplifier 201 , voltage clamping circuit 204 , gain amplifier 208 , voltage clamping circuit 209 , and output buffer amplifier 205 as in the second embodiment. That is, the reason why the voltage clamping circuit 209 is added in the third embodiment is to remove “inter-assembly FPN” as in the second embodiment.
- FIG. 10 shows the operation of the third embodiment, i.e., the drive timing relationship among read-out signals ⁇ 1S , ⁇ 1N , ⁇ 2S , ⁇ 2N , ⁇ 3S , and ⁇ 3N from a shift register SR, a reset pulse ⁇ CHR of the common signal line 55 , and reset pulses ⁇ CD and ⁇ CL in the amplifier chip 200 ′.
- the common output line is reset by ⁇ CHR , and an N signal for the first bit is read out by capacitance division onto the common output line 55 in response to ⁇ 1N .
- the read-out state of the N signal is clamped in response to ⁇ CD , and is used as a reference signal for the first bit.
- the common output line 55 is reset by ⁇ CHR , and an S signal for the first bit is read out by capacitance division onto the common output line 55 in response to ⁇ 1S .
- the difference between the S signal for the first bit and a voltage clamped to the N signal is input to the gain amplifier 208 via the signal input buffer amplifier 201 , and variations in units of pixels can be removed by this clamping function.
- variations of the sensor chips 100 , 100 ′, 100 ′′, . . . can be removed.
- signals for the second and third bits are read out, and after all the bit pixel signals of the sensor chip are read out, a switch 14 of that sensor chip output is turned off and a signal for the first bit of the next sensor chip is read out.
- inter-chip FPN is 2.9 mV or less; the FPN removal effect can be improved.
- ⁇ CD for controlling the clamping timing of the clamping circuit 204 is generated at the first bit in the third embodiment, but may be generated in synchronism with the generation timings of other bits.
- a method of driving a high-performance contact image sensor which can remove inter-chip FPN without requiring any dark correction can be provided. More specifically, since the output is clamped using as a reference signal the level obtained upon resetting the common output lines after signals are output from each sensor module to the amplifier chip, a reference potential can be obtained in the final state of photo-electric conversion, thus reliably removing FPN. Of course, since the dynamic range can be maximized, the need for dark level correction means can be obviated. Also, since the state immediately after the common output lines are reset is used as a reference potential for the clamping circuit, the clamping circuit can clamp at a reliable level in correspondence with a stable reset level, thus removing FPN for each chip.
- FPN can be removed as a whole.
- a method of driving a high-performance contact image sensor which can remove inter-chip FPN without requiring any dark correction can be provided. More specifically, since the level obtained upon resetting the common output lines after signals are output from each sensor module to the amplifier chip is clamped as a reference signal, a reference potential can be obtained in the final state of photo-electric conversion, thus reliably removing FPN. Of course, since the dynamic range can be maximized, the need for dark level correction can be obviated. Also, since the state immediately after the common output lines are reset is used as a reference potential for the clamping circuit, the clamping circuit can clamp at a reliable level in correspondence with a stable reset level, thus removing FPN for each chip.
- the image sensor assembly 300 according to each of the first to third embodiments can be constructed by discrete circuit parts.
- the present invention is more effective when the module chips 100 and amplifier chips 200 are integrated into a single module.
- the image sensor of each of the first to third embodiments strongly has an aspect of a semiconductor device.
- inter-chip FPN is produced as in the image sensor of the present invention.
- the FPN removal method of the present invention can be applied to such semiconductor device.
Abstract
There is provided a method of driving an image sensor which can remove FPN resulting from inter-chip variations without requiring any dark correction. A semiconductor photosensor chip has a plurality of sensor modules mounted on a mounting substrate, and a semiconductor device in which at least an N signal input buffer circuit for receiving N signals, an S signal input buffer circuit for receiving S signals, a differential circuit for calculating any difference between the outputs from the N and S signal input buffer circuits, and a voltage clamping circuit for clamping the output from the differential circuit are formed on a single semiconductor substrate, and the voltage clamping circuit clamps the reset state of S and N signal common output line.
Description
- The present invention relates to a method of driving an image sensor (for example, a linear contact image sensor) for reading images in a facsimile, image scanner, digital copying machine, X-ray imaging apparatus, or the like and, more particularly, to removal of fixed pattern noise (FPN) arising from inter-chip differences or deviations in a contact image sensor in which a plurality of semiconductor photosensor chips are mounted on a mounting substrate.
- In recent years, in the field of linear photo-electric conversion devices, an equal-magnification (magnification=1) contact image sensor in which a plurality of semiconductor photosensors are mounted has been extensively developed in addition to CCDs using reducing optics.
-
FIG. 1A is a partial block diagram showing the arrangement of a conventional contact image sensor having an amplifier element, which is disclosed in Journal of Television Society Vol. 47, No. 9 (1993), pp. 1180. In this contact image sensor, a plurality of amplifier type semiconductor photosensor chips having amplifier elements in units of pixels are mounted. Especially,FIG. 1A shows the arrangement of a single sensor chip. - The output from one sensor module is externally output via an
analog switch 37.FIG. 1B shows a state wherein a plurality of sensor chips are connected. In order to enable the output of a specific chip, theanalog switch 37 of that chip is energized. - As shown in
FIG. 1A , one sensor chip comprises a plurality of sensor elements (phototransistors 9), an output line 3 (4) which commonly receive the outputs from thesetransistors 9,differential amplifier 33,clamping circuit 204, andbuffer amplifier 36, the above-mentionedanalog switch 37, and the like. - In the image sensor, since fixed pattern noise (FPN) resulting from variations of the amplifier elements used for a plurality of pixels is produced, FPN produced in the chip is removed by calculating the difference between a light signal (S signal) and noise signal (N signal) in a dark state (to be referred to as an “S-N method” hereinafter for the sake of simplicity) in the prior art shown in
FIG. 1A . - FPN removal using the S-N method in the image sensor shown in
FIG. 1A will be described below with reference toFIGS. 1A and 2 (timing chart). - In
FIG. 1A , thebipolar transistor 9 constructs a sensor portion of an photo-electric conversion element. Eachtransistor 9 is connected to a MOS transistor 27 (28), MOS transistor 31 (32),capacitances C TS 1 andC TN 2, and MOS transistor 25 (26), and theMOS transistors common output lines output lines output lines differential amplifier 33 via voltage-follower amplifiers 13 and 14. - Upon irradiation of light onto the
sensor 9 of the photo-electric conversion element, a light signal (i.e., a charge) corresponding to its light amount hν (h is a Planck constant, and ν is the frequency of the light) is accumulated on the PN junction of the emitter-follower transistor 9. Upon completion of accumulation, thetransistor 9 is set in a floating state (by turning off φERS) and φTS is turned on to transfer the charge accumulated on the PN junction to the light signal holdingcapacitance C TS 1. Subsequently, a reset pulse φERS is turned on to reset the sensor (transistor 9). At this time, the charge transferred to thecapacitance C TS 1 contains noise components. After that, φTN is turned on to transfer a noise (N) signal of the sensor to the noise signal holdingcapacitance C TN 2. Again, a reset pulse φERS is turned on to enable aMOS transistor 29, and the reset pulse φERS is turned on to enable aMOS transistor 30. Since theMOS transistors sensor transistor 9 is reset and then starts the next accumulation. - Some components of the charges accumulated on the
C TS 1 andC TN 2 are respectively shifted to the output line capacitances CHS and CHN during the next accumulation. This operation is called “capacitive division” for the sake of simplicity since the original charges accumulated onC TS 1 andC TN 2 are divided as a result of movement of the charges between the two capacitances. The “capacitive division” is activated by theMOS transistors - In order to reset holding
capacitances C HS 7 and CHN 8,MOS transistors MOS transistors MOS transistors capacitance C TS 1 and noise signal holding capacitance CTN 2 (some components of charges) are respectively transferred to thecapacitances C HS 7 and CHN 8 connected to thecommon output lines capacitances C HS 7 and CTS 1 (the ratio between CHN 8 and CTN 2). The potential on the output line 3 (4) is amplified by thedifferential amplifier 33 via an amplifier 13 (14). - Although not shown in
FIG. 1A , as described above, one sensor chip hassensor elements 9 for a plurality of bits. In order to read out the sensor output of the next bit, thecapacitances C HS 7 and CHN 8 are reset by turning on theMOS transistors common capacitances C HS 7 and CHN 8. - By repeating such shift operation, the charges accumulated on the sensors (transistors 9) of the respective bits are read out to the
capacitances C HS 7 and CHN 8. Voltages induced on thecapacitances C HS 7 and CHN 8 are input to thedifferential amplifier 33 via the voltage-follower amplifiers 13 and 14. - Fixed pattern noise FPN in the sensor IC mainly arises from variations of hFE or the like of the
bipolar transistors 9 of the respective pixels (bits). Such variations are reflected in the charges accumulated on the holding capacitances CTS and CTN. FPN removal using the S-N method removes noise resulting from hFE variations of thebipolar transistors 9 in units of pixels by detecting any level differences between the signal lines by thedifferential amplifier 33 upon reading out the charges accumulated on the holding capacitances CTS and CTN onto thecommon signal lines - The S-N method using the
differential amplifier 33 is effective for removing FPN produced in the sensor chip. - However, in case of the equal-magnification contact image sensor in which a plurality of photosensors are mounted, since a plurality of linear line sensor chips are cascade-connected, as shown in
FIG. 1B , as it is of contact type, thedifferential amplifiers 33 andbuffer amplifiers 36 are arranged in units of chips. Among the differential amplifiers 33 (or buffer amplifiers 36) of the different chips, the DC components of the output voltages vary due to variations of offset potentials. Such variations of the DC offset voltages among chips will be referred to as “FPN resulting from inter-chip differences (inter-chip FPN)” in contrast to “FPN produced in the chip (intra-chip FPN)” in this specification. - The above-mentioned S-N method is not effective for inter-chip FPN.
- In the image sensor shown in
FIG. 1A , theclamping circuit 204 copes with inter-chip FPN resulting from thedifferential amplifier 33. That is, theclamping circuit 204 is constructed by acapacitance 34 for cutting DC. components from the output from theamplifier 33, and aMOS transistor 35 for fixing to earth level the potential between thiscapacitance 34 and the input portion of theamplifier 36, that shifts to the minus side. With this arrangement, theclamping circuit 204 can prevent inter-chip FPN attributed to thedifferential amplifier 33. - However, the present inventors found that it is difficult to remove inter-chip FPN arising from the offsets of the
output buffer amplifier 36 even by the prior art technique shown inFIG. 1A . - Especially, when the initial stage of the
output buffer amplifier 36 adopts a MOS top arrangement (in which the MOS transistor is located on the input side), since threshold value unbalance of that MOS influences the offsets, offset variations of, e.g., around 10 mV are produced among theoutput buffer amplifiers 36 of different chips. Even after a plurality of sensor chips are mounted, as shown inFIG. 1B , FPN of around 10 mV is produced. - Hence, when a high-gradation image is to be obtained using the conventional image sensor, dark correction is required in units of chips to assure its dynamic range, and the cost required for system design and manufacture increases.
- In the prior art, each sensor chip includes a large-scale analog circuit such as a sensor, holding capacitances, and the like, and 10 to 20 chips are mounted. For this reason, the chip area for the analog circuit portion increases, and it is hard to reduce cost.
- Furthermore, each sensor chip includes both a digital circuit such as MOS transistors for light signal read and reset, and the aforementioned analog circuit, and the sensor output is readily influenced by noise produced by the digital circuit.
- It is an object of the present invention to provide a high-performance image sensor which can remove FPN arising from inter-chip variations and does not require any dark correction.
- It is another object of the present invention to provide an inexpensive image sensor which can obviate the need for any dark correction means, and can avoid an increase in cost resulting from an increase in chip area, which is inevitable in the prior art.
- It is still another object of the present invention to provide a drive method that can remove inter-chip FPN in an image sensor.
- It is still another object of the present invention to provide an image sensor and its drive method, which can simultaneously remove intra-chip FPN and inter-chip FPN.
- It is still another object of the present invention to provide an image sensor in which a plurality of sensor chips are mounted on a single mounting substrate, and a circuit for removing inter-chip FPN is mounted on a semiconductor substrate different from that of the plurality of sensor chips.
- It is still another object of the present invention to provide an image sensor in which a power supply for a plurality of sensor chips is isolated from that for a circuit on the semiconductor substrate.
- It is still another object of the present invention to provide an image sensor in which ground for a plurality of sensor chips is isolated from that for a circuit on the semiconductor substrate.
- It is still another object of the present:invention to provide an image sensor in which differential amplifiers are removed from individual sensor chips.
- It is still another object of the present invention to provide an image sensor which can adjust gain and can remove individual differences of image sensor assemblies, and its drive method.
-
FIG. 1A is the equivalent circuit diagram of a conventional image sensor; -
FIG. 1B is a diagram for explaining connections among individual sensor chips in the conventional image sensor shown inFIG. 1A ; -
FIG. 2 is a timing chart for explaining the operation of the conventional image sensor shown inFIG. 1A ; -
FIG. 3 is a schematic view showing an image sensor assembly according to the first embodiment of the present invention; -
FIG. 4A is the equivalent circuit diagram of an image sensor of the first embodiment; -
FIG. 4B is a diagram for explaining connections of principal part of the image sensor of the first embodiment; -
FIG. 5 is a timing chart showing one operation example of the image sensor of the first embodiment; -
FIG. 6 is a timing chart showing another operation example of the image sensor of the first embodiment; -
FIG. 7 is the equivalent circuit diagram of an image sensor according to the second embodiment of the present invention; -
FIG. 8 is a timing chart showing one operation example of the image sensor of the second embodiment; -
FIG. 9 is the equivalent circuit diagram of an image sensor according to the third embodiment of the present invention; and -
FIG. 10 is a timing chart showing one operation example of the image sensor of the third embodiment. - The arrangement, operation, and drive method of an image sensor according to the preferred embodiments of the present invention will be explained hereinafter with reference to the accompanying drawings.
-
FIG. 3 shows the arrangement of anassembly 300 of a contact image sensor according to the first embodiment. InFIG. 3 , theassembly 300 has a plurality ofsensor chips common output lines amplifier chip 200. In principle, each of thesensor chips 100, . . . has two output terminals, which are respectively connected to thecommon output lines amplifier chip 200 are respectively connected to thecommon output lines amplifier chip 200 has a single output terminal VOUT. The output from this terminal VOUT is that of theassembly 300. - Note that parts such as capacitances, resistors, and the like (not shown) are also mounted on the
assembly 300 shown inFIG. 3 . - In
FIG. 3 , thesensor chips amplifier chip 200 are mounted on asingle mounting substrate 300, but theamplifier chip 200 may be mounted on another mounting substrate. However, since thesensor chips 100, . . . are mounted on a single mounting substrate together with theamplifier chip 200, the size of theassembly 300 can be reduced, and external noise that may be produced in the outputs of thesensor chips 100, . . . can be reduced, thus stabilizing the output. Note that theamplifier chip 200 which is encapsulated in a ceramic package may be mounted on the mountingsubstrate 300 by soldering, or its bear chip may be mounted on the mountingsubstrate 300 by dye-bonding. When the bear chip is mounted by dye-bonding, common chucks can be used for the sensor and amplifier chips if the short side length of each sensor chip is set to be substantially equal to that of the amplifier chip, thus reducing the number of steps in amounting process. -
FIG. 4A shows the equivalent circuit of each sensor chip (100, 100′, 100″, . . . ) and that of theamplifier chip 200 according to the first embodiment. - In
FIG. 4A , the sensor chip according to the first embodiment has a plurality of photo-electric converters noise signal holders S signal holders signal output line 4 for commonly outputting N signals, an Ssignal output line 3 for commonly outputting S signals, resetcircuits signal output lines N signal holders S signal holders C HS 7 of the N and Ssignal output lines - Note that the photo-
electric converter - The signal holder preferably comprises a capacitor, as shown in
FIG. 4A , and the reset circuit preferably comprises a transistor circuit. - Each of the photo-
electric converters MOS transistors MOS transistors 27 commonly receive a control signal φTS. An array ofMOS transistors 28 commonly receive a control signal φTN. When a transfer pulse φTS is turned on, S signals are stored in the S signal holders (capacitances)C C electric converters holders C holders C - In order to supply the outputs from the photo-
electric converters common output lines common output lines MOS transistors signal output lines lines capacitances C HS 7 and CHN 8. TheMOS transistors common output lines capacitances C HS 7 and CHN 8. As a result, the charge accumulated on CTS is divided intoC TS 1 andC HS 7, and the charge accumulated on CTN is divided intoC TN 2 and CHN 8. When the charge is divided into two capacitances, the potential between these two capacitances will be referred to as the capacitively divided output in this specification. - The capacitively divided outputs are impedance-converted by
amplifiers N signal lines FIG. 4A , each of theamplifiers - Data detected by the
sensor element 10 is output onto the S andN signal lines sensor element 10′ is similarly output onto the S andN signal lines sensor elements 10″ is output onto the S andN signal lines - The sensor module (100, 100′, 100″, . . . ) as a semiconductor photosensor is connected to the S and
N signal lines amplifier chip 200 mounted on a single mounting substrate viaterminals 99 mounted on the same mounting substrate by wire bonding. That is, S and N signals from the sensor modules (100, 100′, 100″, . . . ) are input to theamplifier chip 200. - The
amplifier chip 200 shared by the plurality of sensor modules (100, 100′, 100″, . . . ) has abuffer amplifier 201 for receiving an N signal, abuffer amplifier 202 for receiving an S signal, adifferential amplifier 203 for calculating the difference between the outputs from theamplifiers voltage clamping circuit 204 connected to the output side of thedifferential amplifier 203, and anoutput buffer amplifier 205, as shown inFIG. 4A . - Note that the
voltage clamping circuit 204 comprises a clampingcapacitance 206, and aMOS switch 207, and has a function of clamping the input signal toward a clamping reset voltage VCD. - The characteristic features of the first embodiment shown in
FIG. 4A are as follows: - I: The clamping
circuit 204 for removing inter-chip FPN is mounted outside the plurality ofsensor chips 100, . . . but inside theamplifier chip 200 as a circuit common to these sensor chips. For this reason, clamping circuits (204 inFIG. 1A ) in units of sensor chips, which are required in the conventional image sensor (FIG. 1A ), can be omitted. - II: In order to effectively remove inter-chip FPN, the generation timing of a signal φCHR for controlling the reset timing of the
output lines clamping circuit 204 are appropriately set. Two examples of the generation timings of φCHR and φCD will be explained later. - III: Since the
differential amplifier 203 for differentially amplifying the outputs from the pair ofcommon output lines amplifier chip 200, the number of differential amplifiers which are required in units of chips in the prior art (FIG. 1A ) can be reduced to one, and the number of circuit elements can be greatly decreased. - IV: As a combined effect of the features I to III, the timings set in II can remove not only “inter-chip FPN” but also “intra-chip FPN” at the same time.
- According to the arrangement shown in
FIG. 4A , since thebuffer amplifier 36 can be omitted from each sensor chip, generation of inter-chip FPN can be reduced as compared toFIG. 1A . However, since the source-follower amplifiers buffer amplifier 36, “inter-chip FPN” due to inter-chip variations of the source-follower amplifier 11 (or 12) remains unsolved. - The drive control method for the image sensor of the first embodiment, especially, the drive control method for removing inter-chip FPN will be explained below with reference to
FIG. 5 . -
FIG. 5 shows signals φTN and φTS for determining the charge transfer timings of theconverter 10, shift pulses φ1, φ2, and φ3 from the shift register SR, a reset pulse φCHR for resetting thecommon signal lines clamping circuit 204 in theamplifier chip 200. -
FIG. 4B shows principal elements of the image sensor (FIG. 4A ) of the first embodiment. Referring toFIG. 4B , the reset circuit which receives φCHR and theclamping circuit 204 which receives φCD are present between thecapacitances C common output lines output lines amplifier chip 200. TheMOS transistors sensor converter 10 in a single chip. DC offset variations resulting from the source-follower amplifiers clamping circuit 204 inFIG. 4B . More specifically, referring toFIG. 4A , a clamping pulse φCD which changes LOW→“H”→LOW is input to the gate of theMOS transistor 207. During the LOW period of φCD, thedifferential amplifier 203 outputs an output signal which reflects DC offset variations caused by the source-follower amplifiers MOS transistor 207 is clamped to a potential VCD. Then, the potential difference across the two terminals of theDC cutoff capacitor 206 reflect DC offset variations caused by the source-follower amplifiers MOS transistor 207 is turned off, the charge accumulated on thecapacitor 206 is held at a charge value for canceling inter-chip FPN. When a shift pulse φN is applied from the shift register SR to theMOS transistors follower amplifier 205. That is, it is important for the timings inFIG. 5 : - V: to output the clamping pulse φCD before each shift pulse φN (one of φ1, φ2, φ3, . . . ); and
- VI: to reset the
MOS transistors - In the control timing example shown in
FIG. 5 , the reset pulse φCHR goes HIGH and then LOW before the clamping pulse φCD goes HIGH. - The operation of the circuit shown in
FIG. 4A will be described in more detail below with the aid ofFIG. 5 . - After signals φTN and φTS are input, S signals have already been read out to the
capacitances C capacitances C signal lines - In
FIG. 4A , theMOS transistor 207 in theclamping circuit 204 is controlled by the control signal φCD. According to the timings shown inFIG. 5 , φCD is enabled after φCHR is enabled. Hence, during the period from when φCHR is enabled until φCD is enabled, thecapacitances C HS 7 and CHN 8 are reset to desired voltages by φCHR immediately before the signals on thesignal lines capacitances C HS 7 and CHS 8 have been reset is clamped by φCD, and is used as a reference state. Hence, the outputs after capacitance division contain Vth variations of the source-follower amplifiers - The control timings of the
clamping circuit 204 of the first embodiment are not limited to those shown inFIG. 5 . -
FIG. 6 shows another timing example that can be applied to the image sensor (FIG. 4A ) of the first embodiment. In the example shown inFIG. 6 , the reset pulse φCHR is held at HIGH, and then goes LOW after the clamping pulse φCD goes LOW and before the shift pulse φN is turned on. According to the timing example shown inFIG. 6 , since the reset state of thecapacitances C HS 7 and CHN 8 by the reset pulse φCHR is clamped by the clamping pulse φCD, the same effect as in the timing example shown inFIG. 5 can be obtained. - According to the first embodiment, since the need for a differential amplifier in each sensor chip can be obviated as compared to the image sensor shown in
FIG. 1A , the output portion of each sensor chip can be simplified, and the chip area of the analog portion in each sensor chip can be minimized. In addition, since the analog portion for all the sensor chips can be integrated using thecommon signal lines - In the
image sensor assembly 300 of the first embodiment, when the power supply for thesensor chips amplifier chip 200 are independently set, a broad dynamic range of the output can be maintained even when the sensor power supply voltage is decreased. - In the first embodiment, a contact image sensor using a plurality of line sensor chips has been exemplified. However, the present invention is not limited to such specific sensor, but may be effective for a two-dimensional area sensor including a large number of sensor chips. Especially, when area chips in small regions have different photo-electric conversion sensitivities, FPN variations become more conspicuous than a 1-line contact sensor and, hence, it is very effective to apply the present invention.
- As another modification, when an amplification function is added to the
amplifier chip 200, the amplification function may be added to, e.g., thedifferential amplifier 203 or a gain amplifier may be inserted on the output side of thedifferential amplifier 203. - In the arrangement shown in
FIG. 4A , thesensor chip 100 andamplifier chip 200 use a common power supply. Alternatively, when the power supplies for thesensor chip 100 andamplifier chip 200 are isolated on the mounting substrate, the sensor chip and amplifier chip may use different power supply voltages, or independent GND terminals may be used on the mounting substrate to reduce noise in analog output. -
FIG. 7 is a circuit diagram of an image sensor according to the second embodiment of the present invention. In the second embodiment, photo-electric converters in each of thesensor chips diodes follower transistors - As other building elements of the second embodiment, each sensor chip has
N signal holders S signal holders signal output line 4, an Ssignal output line 3, and resetswitches FIG. 4A ). - The characteristic feature of the second embodiment lies in that the level of a final output VOUT of a
sensor assembly 300 can be adjusted by adding again amplifier 208 to anamplifier chip 200′. However, when thegain amplifier 208 is added, the output VOUT of theassembly 300 suffers an individual difference due to individual offset variations in thegain amplifier 208. Such individual difference will be referred to as an “inter-assembly FPN” hereinafter for the sake of simplicity. - In the image sensor of the second embodiment, a
clamping circuit 209 is added to remove this “inter-assembly FPN”. - The arrangement of the image sensor of the second embodiment will be described in more detail below.
- The capacitively divided outputs that appear on the N and S
signal output lines follower amplifiers N signal lines N signal lines amplifier chip 200′ mounted on the same chip as the sensor chips. - The
amplifier chip 200′ of the second embodiment comprises an N signalinput buffer amplifier 201, S signalinput buffer amplifier 202,differential amplifier 203,voltage clamping circuit 204, gain amplifier 208 (gain=A),voltage clamping circuit 209, andoutput buffer amplifier 205. A clamping control signal to thevoltage clamping circuit 204 is φCD as in the first embodiment, and a clamping signal for controlling thevoltage clamping circuit 209 is φCL. -
FIG. 8 is a timing chart of control signals in the second embodiment. - The clamping signal φCD to the
clamping circuit 204 must be generated at the charge transfer timing (φ1, φ2, and φ3 inFIG. 8 ) of each bit as in the first embodiment, since it aims at removing FPN for each bit. On the other hand, as theclamping circuit 209 removes offset FPN produced in each assembly, the clamping signal φCL for theclamping circuit 209 need only be generated once for a start signal SP (equivalent to a signal SP inFIG. 2 ) which is generated once for theassembly 300 at the beginning of image reading, as shown inFIG. 8 . - In the second embodiment, the
voltage clamping circuit 209 reduces offset variations (“inter-assembly FPN”) for each module including thesensor chips amplifier chip 200′, and a nearly uniform reference level of the module (i.e., the assembly) can be maintained. Since variations of the module (i.e., the assembly) can be reduced, variations in units of products can be reduced, and the manufacture of high-quality products can be achieved. - In the second embodiment, the power supplies and GND terminals for the
sensor chips amplifier chip 200′ are isolated from each other on the mounting substrate, and the power supply voltages for the sensor chip and amplifier chip are respectively 3.3 V and 5.0 V. - The operation of the second embodiment will be described below with reference to the timing chart in
FIG. 8 . -
FIG. 8 shows the drive timing relationship among read-out signals φ1, φ2, and φ3 from a shift register SR, a reset pulse φCHR of thecommon signal lines amplifier chip 200′. - After signals are read out to the S signal holding capacitances (holders)
C C capacitances C HS 7 and CHN 8 are reset to desired voltages by turning on the MOS transistors (switches) 5 and 6 in response to the reset pulse φCHR. AfterC HS 7 and CHN 8 are reset, the clampingcircuits follower amplifiers - In this way, the second embodiment can remove all of “intra-chip FPN”, “inter-chip FPN”, and “inter-assembly FPN”.
- More specifically, the inter-chip difference is around 10 mV in the conventional module, but is 3 mV or less in the second embodiment.
- Note that φCD for controlling the clamping timing of the
clamping circuit 204 is generated at the first bit in the second embodiment, but may be generated in synchronism with the generation timings of other bits. -
FIG. 9 is a circuit diagram showing the third embodiment of the present invention. In this embodiment, N and S signals are read out time-serially (i.e., by time division), and the output state of N signals is clamped and is used as a reference signal. - In the third embodiment, the arrangement of each of the
sensor chips diodes follower transistors N signal holders S signal holders common output line 55. That is, the singlecommon output line 55 is sequentially reset by areset MOS transistor 56. Since time-division driving is done, the number of source-follower amplifiers 11 including two transistors for amplifying N and S signals can be reduced to one as compared to the second embodiment. - An
amplifier chip 200′ of the third embodiment comprises aninput buffer amplifier 201,voltage clamping circuit 204,gain amplifier 208,voltage clamping circuit 209, andoutput buffer amplifier 205 as in the second embodiment. That is, the reason why thevoltage clamping circuit 209 is added in the third embodiment is to remove “inter-assembly FPN” as in the second embodiment. -
FIG. 10 shows the operation of the third embodiment, i.e., the drive timing relationship among read-out signals φ1S, φ1N, φ2S, φ2N, φ3S, and φ3N from a shift register SR, a reset pulse φCHR of thecommon signal line 55, and reset pulses φCD and φCL in theamplifier chip 200′. - After signals are read out to the S signal holding capacitances (holders)
C C common output line 55 in response to φ1N. The read-out state of the N signal is clamped in response to φCD, and is used as a reference signal for the first bit. Subsequently, thecommon output line 55 is reset by φCHR, and an S signal for the first bit is read out by capacitance division onto thecommon output line 55 in response to φ1S. The difference between the S signal for the first bit and a voltage clamped to the N signal is input to thegain amplifier 208 via the signalinput buffer amplifier 201, and variations in units of pixels can be removed by this clamping function. In addition, variations of thesensor chips switch 14 of that sensor chip output is turned off and a signal for the first bit of the next sensor chip is read out. - In the arrangement of the third embodiment, inter-chip FPN is 2.9 mV or less; the FPN removal effect can be improved.
- Note that φCD for controlling the clamping timing of the
clamping circuit 204 is generated at the first bit in the third embodiment, but may be generated in synchronism with the generation timings of other bits. - According to the present invention, a method of driving a high-performance contact image sensor which can remove inter-chip FPN without requiring any dark correction can be provided. More specifically, since the output is clamped using as a reference signal the level obtained upon resetting the common output lines after signals are output from each sensor module to the amplifier chip, a reference potential can be obtained in the final state of photo-electric conversion, thus reliably removing FPN. Of course, since the dynamic range can be maximized, the need for dark level correction means can be obviated. Also, since the state immediately after the common output lines are reset is used as a reference potential for the clamping circuit, the clamping circuit can clamp at a reliable level in correspondence with a stable reset level, thus removing FPN for each chip.
- Furthermore, since variations in units of output lines in the capacitively divided outputs from each photo-electric conversion chip can be corrected in units of chips, FPN can be removed as a whole.
- According to the present invention, a method of driving a high-performance contact image sensor which can remove inter-chip FPN without requiring any dark correction can be provided. More specifically, since the level obtained upon resetting the common output lines after signals are output from each sensor module to the amplifier chip is clamped as a reference signal, a reference potential can be obtained in the final state of photo-electric conversion, thus reliably removing FPN. Of course, since the dynamic range can be maximized, the need for dark level correction can be obviated. Also, since the state immediately after the common output lines are reset is used as a reference potential for the clamping circuit, the clamping circuit can clamp at a reliable level in correspondence with a stable reset level, thus removing FPN for each chip.
- As described above, the
image sensor assembly 300 according to each of the first to third embodiments can be constructed by discrete circuit parts. However, the present invention is more effective when the module chips 100 andamplifier chips 200 are integrated into a single module. In other words, the image sensor of each of the first to third embodiments strongly has an aspect of a semiconductor device. In general, when the outputs from a plurality of semiconductor chips which form a module and have an identical function are combined, inter-chip FPN is produced as in the image sensor of the present invention. Hence, the FPN removal method of the present invention can be applied to such semiconductor device. - As many apparently widely different embodiments of the present invention can be made without departing from the spirit and scope thereof, it is to be understood that the invention is not limited to the specific embodiments thereof except as defined in the appended claims.
Claims (9)
1-32. (canceled)
33. An image sensor comprising:
a plurality of photo sensor chips mounted on a single mounting substrate, each photo sensor chip having a plurality of photo-electric conversion circuits, a common output line through which signals from said plurality of photo-electric conversion circuits are outputted, and a photo sensor chip output device which outputs signals from said common output line to outside of said photo sensor chip, wherein each said photo-electric conversion circuit has a photo-electric conversion part and an amplifier for amplifying an output signal from the photo-electric conversion part; and
a correction circuit output chip mounted on said single mounting substrate, said correction circuit output chip having a noise compensation circuit which receives a noise signal outputted from the amplifier and including an offset component of the amplifier, the noise signal being obtained by resetting an input portion of the amplifier and a photo-electric conversion signal generated in said photo-electric conversion part, wherein said noise compensation circuit corrects a noise component of the photo-electric conversion signal by using the noise signal outputted from the amplifier,
wherein said correction circuit output chip is arranged commonly to said plurality of photo sensor chips, and
wherein an output terminal for outputting a signal to outside of said correction circuit output chip and an output terminal for outputting a signal to outside of said single mounting substrate are connected to each other.
34. The image sensor according to claim 33 , wherein said noise compensation circuit has a differential circuit which calculates a difference between a first signal and a second signal and a clamp circuit connected to an output of said differential circuit.
35. The image sensor according to claim 34 , wherein said differential circuit calculates a difference between the noise signal and the photo-electric conversion signal read out from said photo sensor chip output device and said clamp circuit clamps a reset state of said common output line in said photo sensor chip.
36. The image sensor according to claim 33 , wherein said noise compensation circuit has a clamp circuit which clamps a reset state of said common output line in said photo sensor chip.
37. The semiconductor device according to claim 33 , wherein a power supply voltage of said correction circuit output chip is higher than a power supply voltage of said photo sensor chips.
38. The semiconductor device according to claim 33 , wherein GND wiring for said correction circuit output chip and GND wiring for said photo sensor chips are isolated from each other on said single mounting substrate.
39. The semiconductor device according to claim 37 , wherein GND wiring for said correction circuit output chip and GND wiring for said photo sensor chips are isolated from each other on said single mounting substrate.
40. A method of driving an image sensor, said image sensor including:
(a) a plurality of photo sensor chips mounted on a single mounting substrate, each photo sensor chip having a plurality of photo-electric conversion circuits, a common output line through which signals from said plurality of photo-electric conversion circuits are outputted, and a photo sensor chip output device which outputs signals from said common output line to outside of said photo sensor chip, wherein each said photo-electric conversion circuit has a photo-electric conversion part and an amplifier for amplifying an output signal from the photo-electric conversion part; and
(b) a correction circuit output chip mounted on said single mounting substrate, said correction circuit output chip having a noise compensation circuit which receives a noise signal outputted from the amplifier and including an offset component of the amplifier, the noise signal being obtained by resetting an input portion of the amplifier and a photo-electric conversion signal generated in said photo-electric conversion part, wherein said noise compensation circuit corrects a noise component of the photo-electric conversion signal by using the noise signal outputted from the amplifier,
wherein said correction circuit output chip is arranged commonly to said plurality of photo sensor chips, and
wherein an output terminal for outputting a signal to outside of said correction circuit output chip and an output terminal for outputting a signal to outside of said single mounting substrate are connected to each other,
said method comprising the step of:
driving said compensation circuit to compensate for a noise component included in a photo-electric conversion signal read out from said photo sensor chip output device by using a noise signal read out from said photo sensor chip output device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/967,219 US20050068432A1 (en) | 1997-10-06 | 2004-10-19 | Image sensor and method for driving an image sensor for reducing fixed pattern noise |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9272574A JPH11112728A (en) | 1997-10-06 | 1997-10-06 | Semiconductor device and contact image sensor |
JP9-272574 | 1997-10-06 | ||
JP9-272575 | 1997-10-06 | ||
JP9272575A JPH11112015A (en) | 1997-10-06 | 1997-10-06 | Driving method for contact-type image sensor |
US09/161,405 US6950132B1 (en) | 1997-10-06 | 1998-09-28 | Image sensor and method for driving an image sensor for reducing fixed pattern noise |
US10/967,219 US20050068432A1 (en) | 1997-10-06 | 2004-10-19 | Image sensor and method for driving an image sensor for reducing fixed pattern noise |
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US09/161,405 Division US6950132B1 (en) | 1997-10-06 | 1998-09-28 | Image sensor and method for driving an image sensor for reducing fixed pattern noise |
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US20050068432A1 true US20050068432A1 (en) | 2005-03-31 |
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US09/161,405 Expired - Fee Related US6950132B1 (en) | 1997-10-06 | 1998-09-28 | Image sensor and method for driving an image sensor for reducing fixed pattern noise |
US10/967,219 Abandoned US20050068432A1 (en) | 1997-10-06 | 2004-10-19 | Image sensor and method for driving an image sensor for reducing fixed pattern noise |
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US09/161,405 Expired - Fee Related US6950132B1 (en) | 1997-10-06 | 1998-09-28 | Image sensor and method for driving an image sensor for reducing fixed pattern noise |
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US (2) | US6950132B1 (en) |
EP (1) | EP0909086B1 (en) |
KR (1) | KR100307472B1 (en) |
CN (1) | CN1246904C (en) |
DE (1) | DE69810232T2 (en) |
SG (1) | SG70128A1 (en) |
TW (1) | TW412872B (en) |
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US20060291008A1 (en) * | 2005-06-22 | 2006-12-28 | Xerox Corporation | System for adjusting a reference voltage in a photosensor chip |
US20070126904A1 (en) * | 2000-04-12 | 2007-06-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of driving the same |
CN114945062A (en) * | 2022-05-18 | 2022-08-26 | 金华高等研究院(金华理工学院筹建工作领导小组办公室) | Burr eliminating circuit of image sensor |
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JP5665484B2 (en) | 2010-10-29 | 2015-02-04 | キヤノン株式会社 | Imaging apparatus, radiation imaging system, and image sensor control method |
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Citations (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4584607A (en) * | 1983-04-14 | 1986-04-22 | Ricoh Company, Ltd. | Photoelectric element control system |
US4672453A (en) * | 1984-07-10 | 1987-06-09 | Nec Corporation | Contact type image sensor and driving method therefor |
US4780765A (en) * | 1986-03-19 | 1988-10-25 | Sony Corporation | Solid state image pick-up device |
US4835404A (en) * | 1986-09-19 | 1989-05-30 | Canon Kabushiki Kaisha | Photoelectric converting apparatus with a switching circuit and a resetting circuit for reading and resetting a plurality of lines sensors |
US4942474A (en) * | 1987-12-11 | 1990-07-17 | Hitachi, Ltd. | Solid-state imaging device having photo-electric conversion elements and other circuit elements arranged to provide improved photo-sensitivity |
US4965570A (en) * | 1986-02-04 | 1990-10-23 | Canon Kabushiki Kaisha | Photoelectric conversion apparatus |
US5021888A (en) * | 1987-12-18 | 1991-06-04 | Kabushiki Kaisha Toshiba | Miniaturized solid state imaging device |
US5109440A (en) * | 1988-05-26 | 1992-04-28 | Seiko Instruments Inc. | Image sensing apparatus |
US5229848A (en) * | 1990-08-28 | 1993-07-20 | Ikegami Tsushinki Co., Ltd. | Circuit for processing image signals read out of pick-up apparatus having solid state image sensing devices adopting spatial pixel shift |
US5262870A (en) * | 1989-02-10 | 1993-11-16 | Canon Kabushiki Kaisha | Image sensor in which reading and resetting are simultaneously performed |
US5311320A (en) * | 1986-09-30 | 1994-05-10 | Canon Kabushiki Kaisha | Solid state image pickup apparatus |
US5321528A (en) * | 1990-11-30 | 1994-06-14 | Canon Kabushiki Kaisha | Image pick-up device correcting offset errors from a plurality of output amplifiers |
US5329312A (en) * | 1992-08-17 | 1994-07-12 | Eastman Kodak Company | DC level control circuitry for CCD images |
US5591960A (en) * | 1990-02-28 | 1997-01-07 | Canon Kabushiki Kaisha | Photoelectric converter with signal processing |
US5592222A (en) * | 1989-02-10 | 1997-01-07 | Canon Kabushiki Kaisha | Sensor chip and photo-electric conversion apparatus using the same |
US5640207A (en) * | 1993-05-19 | 1997-06-17 | Rahmouni; Gilbert | Camera for high-speed imaging |
US5771070A (en) * | 1985-11-15 | 1998-06-23 | Canon Kabushiki Kaisha | Solid state image pickup apparatus removing noise from the photoelectric converted signal |
US5907359A (en) * | 1995-08-30 | 1999-05-25 | Sanyo Electric Co., Ltd. | Highly-integrated image sensing apparatus producing digitized output |
US5933188A (en) * | 1994-10-19 | 1999-08-03 | Canon Kabushiki Kaisha | Photoelectric conversion apparatus and method with reset |
US5998779A (en) * | 1996-12-24 | 1999-12-07 | Canon Kabushiki Kaisha | Photoelectric conversion apparatus |
US6002287A (en) * | 1997-05-08 | 1999-12-14 | Canon Kabushiki Kaisha | Signal outputting apparatus |
US6118115A (en) * | 1997-07-18 | 2000-09-12 | Canon Kabushiki Kaisha | Photoelectric conversion apparatus |
US6130712A (en) * | 1996-06-11 | 2000-10-10 | Canon Kabushiki Kaisha | Eliminating the influence of random noise produced by an optical black pixel on a reference output |
US6184516B1 (en) * | 1997-05-30 | 2001-02-06 | Canon Kabushiki Kaisha | Photoelectric conversion device and image sensor |
US6215521B1 (en) * | 1996-09-27 | 2001-04-10 | Nec Corporation | Solid state image sensor having an unnecessary electric charge exhausting section formed adjacent to a horizontal electric charge transfer section, and a method for manufacturing the same |
US6288742B1 (en) * | 1995-09-21 | 2001-09-11 | Lucent Technologies Inc. | Video camera including multiple image sensors |
US6421085B1 (en) * | 1998-04-14 | 2002-07-16 | Eastman Kodak Company | High speed CMOS imager column CDS circuit |
US6473538B2 (en) * | 1998-02-19 | 2002-10-29 | Canon Kabushiki Kaisha | Image sensor |
US6534757B2 (en) * | 1998-01-30 | 2003-03-18 | Canon Kabushiki Kaisha | Image sensor noise reduction |
US20040027471A1 (en) * | 2002-05-30 | 2004-02-12 | Ken Koseki | Captured-image-signal processing method and apparatus and imaging apparatus |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61214657A (en) | 1985-03-20 | 1986-09-24 | Matsushita Electric Ind Co Ltd | Image sensor |
US4914519A (en) | 1986-09-19 | 1990-04-03 | Canon Kabushiki Kaisha | Apparatus for eliminating noise in a solid-state image pickup device |
JPH0720219B2 (en) | 1985-11-15 | 1995-03-06 | キヤノン株式会社 | Driving method for photoelectric conversion device |
JPH03280663A (en) | 1990-03-29 | 1991-12-11 | Canon Inc | Photoelectric converter |
-
1998
- 1998-09-21 SG SG1998003778A patent/SG70128A1/en unknown
- 1998-09-23 TW TW087115845A patent/TW412872B/en not_active IP Right Cessation
- 1998-09-28 US US09/161,405 patent/US6950132B1/en not_active Expired - Fee Related
- 1998-09-30 CN CNB981208649A patent/CN1246904C/en not_active Expired - Fee Related
- 1998-09-30 EP EP98307958A patent/EP0909086B1/en not_active Expired - Lifetime
- 1998-09-30 DE DE69810232T patent/DE69810232T2/en not_active Expired - Lifetime
- 1998-10-07 KR KR1019980041846A patent/KR100307472B1/en not_active IP Right Cessation
-
2004
- 2004-10-19 US US10/967,219 patent/US20050068432A1/en not_active Abandoned
Patent Citations (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4584607A (en) * | 1983-04-14 | 1986-04-22 | Ricoh Company, Ltd. | Photoelectric element control system |
US4672453A (en) * | 1984-07-10 | 1987-06-09 | Nec Corporation | Contact type image sensor and driving method therefor |
US5771070A (en) * | 1985-11-15 | 1998-06-23 | Canon Kabushiki Kaisha | Solid state image pickup apparatus removing noise from the photoelectric converted signal |
US4965570A (en) * | 1986-02-04 | 1990-10-23 | Canon Kabushiki Kaisha | Photoelectric conversion apparatus |
US4780765A (en) * | 1986-03-19 | 1988-10-25 | Sony Corporation | Solid state image pick-up device |
US4835404A (en) * | 1986-09-19 | 1989-05-30 | Canon Kabushiki Kaisha | Photoelectric converting apparatus with a switching circuit and a resetting circuit for reading and resetting a plurality of lines sensors |
US5311320A (en) * | 1986-09-30 | 1994-05-10 | Canon Kabushiki Kaisha | Solid state image pickup apparatus |
US4942474A (en) * | 1987-12-11 | 1990-07-17 | Hitachi, Ltd. | Solid-state imaging device having photo-electric conversion elements and other circuit elements arranged to provide improved photo-sensitivity |
US5021888A (en) * | 1987-12-18 | 1991-06-04 | Kabushiki Kaisha Toshiba | Miniaturized solid state imaging device |
US5109440A (en) * | 1988-05-26 | 1992-04-28 | Seiko Instruments Inc. | Image sensing apparatus |
US5592222A (en) * | 1989-02-10 | 1997-01-07 | Canon Kabushiki Kaisha | Sensor chip and photo-electric conversion apparatus using the same |
US5262870A (en) * | 1989-02-10 | 1993-11-16 | Canon Kabushiki Kaisha | Image sensor in which reading and resetting are simultaneously performed |
US5591960A (en) * | 1990-02-28 | 1997-01-07 | Canon Kabushiki Kaisha | Photoelectric converter with signal processing |
US5229848A (en) * | 1990-08-28 | 1993-07-20 | Ikegami Tsushinki Co., Ltd. | Circuit for processing image signals read out of pick-up apparatus having solid state image sensing devices adopting spatial pixel shift |
US5321528A (en) * | 1990-11-30 | 1994-06-14 | Canon Kabushiki Kaisha | Image pick-up device correcting offset errors from a plurality of output amplifiers |
US5329312A (en) * | 1992-08-17 | 1994-07-12 | Eastman Kodak Company | DC level control circuitry for CCD images |
US5640207A (en) * | 1993-05-19 | 1997-06-17 | Rahmouni; Gilbert | Camera for high-speed imaging |
US5933188A (en) * | 1994-10-19 | 1999-08-03 | Canon Kabushiki Kaisha | Photoelectric conversion apparatus and method with reset |
US5907359A (en) * | 1995-08-30 | 1999-05-25 | Sanyo Electric Co., Ltd. | Highly-integrated image sensing apparatus producing digitized output |
US6288742B1 (en) * | 1995-09-21 | 2001-09-11 | Lucent Technologies Inc. | Video camera including multiple image sensors |
US6130712A (en) * | 1996-06-11 | 2000-10-10 | Canon Kabushiki Kaisha | Eliminating the influence of random noise produced by an optical black pixel on a reference output |
US6215521B1 (en) * | 1996-09-27 | 2001-04-10 | Nec Corporation | Solid state image sensor having an unnecessary electric charge exhausting section formed adjacent to a horizontal electric charge transfer section, and a method for manufacturing the same |
US5998779A (en) * | 1996-12-24 | 1999-12-07 | Canon Kabushiki Kaisha | Photoelectric conversion apparatus |
US6002287A (en) * | 1997-05-08 | 1999-12-14 | Canon Kabushiki Kaisha | Signal outputting apparatus |
US6184516B1 (en) * | 1997-05-30 | 2001-02-06 | Canon Kabushiki Kaisha | Photoelectric conversion device and image sensor |
US6118115A (en) * | 1997-07-18 | 2000-09-12 | Canon Kabushiki Kaisha | Photoelectric conversion apparatus |
US6534757B2 (en) * | 1998-01-30 | 2003-03-18 | Canon Kabushiki Kaisha | Image sensor noise reduction |
US6473538B2 (en) * | 1998-02-19 | 2002-10-29 | Canon Kabushiki Kaisha | Image sensor |
US6421085B1 (en) * | 1998-04-14 | 2002-07-16 | Eastman Kodak Company | High speed CMOS imager column CDS circuit |
US20040027471A1 (en) * | 2002-05-30 | 2004-02-12 | Ken Koseki | Captured-image-signal processing method and apparatus and imaging apparatus |
Cited By (13)
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---|---|---|---|---|
US9019408B2 (en) | 2000-04-12 | 2015-04-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of driving the same |
US20070126904A1 (en) * | 2000-04-12 | 2007-06-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of driving the same |
US7808535B2 (en) | 2000-04-12 | 2010-10-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of driving the same |
US20110018041A1 (en) * | 2000-04-12 | 2011-01-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor Device and Method of Driving the Same |
US8203636B2 (en) | 2000-04-12 | 2012-06-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of driving the same |
US8355065B2 (en) | 2000-04-12 | 2013-01-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of driving the same |
US8743250B2 (en) | 2000-04-12 | 2014-06-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of driving the same |
US9274236B2 (en) | 2000-04-12 | 2016-03-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of driving the same |
US9568615B2 (en) | 2000-04-12 | 2017-02-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of driving the same |
US7477299B2 (en) * | 2005-02-03 | 2009-01-13 | Fujitsu Limited | Imaging device |
US20060170794A1 (en) * | 2005-02-03 | 2006-08-03 | Fujitsu Limited | Imaging device |
US20060291008A1 (en) * | 2005-06-22 | 2006-12-28 | Xerox Corporation | System for adjusting a reference voltage in a photosensor chip |
CN114945062A (en) * | 2022-05-18 | 2022-08-26 | 金华高等研究院(金华理工学院筹建工作领导小组办公室) | Burr eliminating circuit of image sensor |
Also Published As
Publication number | Publication date |
---|---|
EP0909086B1 (en) | 2002-12-18 |
CN1213862A (en) | 1999-04-14 |
DE69810232T2 (en) | 2003-07-24 |
TW412872B (en) | 2000-11-21 |
KR19990036903A (en) | 1999-05-25 |
CN1246904C (en) | 2006-03-22 |
US6950132B1 (en) | 2005-09-27 |
EP0909086A2 (en) | 1999-04-14 |
EP0909086A3 (en) | 1999-08-18 |
SG70128A1 (en) | 2000-01-25 |
KR100307472B1 (en) | 2001-10-19 |
DE69810232D1 (en) | 2003-01-30 |
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