US20050097251A1 - System and method for arbitration of a plurality of processing modules - Google Patents
System and method for arbitration of a plurality of processing modules Download PDFInfo
- Publication number
- US20050097251A1 US20050097251A1 US10/996,494 US99649404A US2005097251A1 US 20050097251 A1 US20050097251 A1 US 20050097251A1 US 99649404 A US99649404 A US 99649404A US 2005097251 A1 US2005097251 A1 US 2005097251A1
- Authority
- US
- United States
- Prior art keywords
- bus
- data
- arbitration
- address
- processing module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/7075—Synchronisation aspects with code phase acquisition
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
- G06F13/374—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a self-select method with individual priority code comparator
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
- G06F13/376—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a contention resolving method, e.g. collision detection, collision avoidance
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/7075—Synchronisation aspects with code phase acquisition
- H04B1/70751—Synchronisation aspects with code phase acquisition using partial detection
- H04B1/70753—Partial phase search
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/7075—Synchronisation aspects with code phase acquisition
- H04B1/70755—Setting of lock conditions, e.g. threshold
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/7075—Synchronisation aspects with code phase acquisition
- H04B1/70758—Multimode search, i.e. using multiple search strategies
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/7075—Synchronisation aspects with code phase acquisition
- H04B1/708—Parallel implementation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
- H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
- H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
- H04B2201/70702—Intercell-related aspects
Definitions
- This invention relates generally to a system for transferring data between a data processing module and a plurality of data processing modules. More particularly, the invention relates to a high-speed data communication system which transfers information between different digital processing modules on a shared parallel bus.
- a communication bus is often employed.
- a communication bus is a set of shared electrical conductors for the exchange of digital words. In this manner, communication between devices is simplified, thereby obviating separate interconnections.
- a communication bus typically contains a set of data lines, address lines for determining which device should transmit or receive, and control and strobe lines that specify the type of command is executing.
- the address and strobe lines communicate one-way from a central processing unit. Typically, all data lines are bidirectional.
- Data lines are asserted by the CPU during the write instruction, and by the peripheral device during read. Both the CPU and peripheral device use three-state drivers for the data lines.
- Three-state or open-collector drivers are used so that devices connected to the bus can disable their bus drivers, since only one device is asserting data onto the bus at a given time.
- Each bus system has a defined protocol for determining which device asserts data.
- a bus system is designed so that, at most, one device has its drivers enabled at one time with all other devices disabled (third state).
- a device knows to assert data onto the bus by recognizing its own address on the control lines. The device looks at the control lines and asserts data when it sees its particular address on the address lines and a read pulse. However, there must be some external logic ensuring that the three-state devices sharing the same lines do not talk at the same time or bus contention will result.
- Bus control logic or a Abus master@ executes code for the protocol used to arbitrate control of the bus.
- the bus master may be part of a CPU or function independently. More importantly, control of the bus may be granted to another device. More complex bus systems permit other devices located on the bus to master the bus.
- Data processing systems have processors which execute programmed instructions stored in a plurality of memory locations. As shown in FIG. 1 , the processed data is transferred in and out of the system by using I/O devices onto a bus, interconnecting with other digital devices.
- a bus protocol, or handshaking rules delineate a predetermined series of steps to permit data exchange between the devices.
- Communication buses are either synchronous or asynchronous.
- a synchronous bus data is asserted onto or retrieved from the bus synchronously with strobing signals generated by the CPU or elsewhere in the system. However, the device sending the data does not know if the data was received.
- asynchronous bus although handshaking between communicating devices assures the sending device that the data was received, the hardware and signaling complexity is increased.
- DMA direct memory access
- SDLC/HDLC synchronous/high-level data link control
- CSMA/CD carrier-sense multiple-access/collision-detection
- the system features a simplified hardware architecture featuring fast FIFO (first-in/first-out) queing, TTL CMOS (complimentary metal-oxide silicon) compatible level clocking signals, single bus master arbitration, synchronous clocking, DMA, and unique module addressing for multiprocessor systems.
- the present invention includes a parallel data bus with sharing bus masters residing on each processing module controlling the communication and data transfer protocols.
- the high-speed intermodule communication bus (HSB) provides between various microprocessor modules.
- the data bus is synchronous and completely bidirectional. Each processing module that communicates on the bus will have the described bus control architecture.
- the HSB comprises, in one embodiment, eight shared parallel data lines for the exchange of digital data, and two independent lines for arbitration and clock signals. The need for explicit bus request or grant signals is eliminated.
- the HSB can also be configured as a semi-redundant system, duplicating data lines while maintaining a single component level.
- the bus is driven by three-state gates with resistor pullups serving as terminators to minimize signal reflections.
- each processing module specifies the data, the recipient, and the moment when the data is valid. Only one message source, known as the bus master, is allowed to drive the bus at any given time. Since the data flow is bidirectional, the bus arbitration scheme establishes a protocol of rules to prevent collisions on the data lines when a given processing module microprocessor is executing instructions. The arbitration method depends on the detection of collisions present only on the arbitration bus and uses state machines on each data processing module to determine bus status. Additionally, the arbitration method is not daisy chained, allowing greater system flexibility.
- the state machines located on each processing module are the controlling interface between the microprocessor used within a given processing module and the HSB. The circuitry required for the interface is comprised of a transmit FIFO, receive FIFO, miscellaneous directional/bidirectional signal buffers and the software code for the state machines executed in an EPLD (erasable programmable logic device).
- EPLD erasable programmable logic device
- FIG. 1 is a block diagram of a typical, prior art data communication bus.
- FIG. 2 is a table of prior art data bus architectures.
- FIG. 3 is a simplified block diagram of the preferred embodiment.
- FIGS. 4A-4E taken together, is an electrical schematic of the preferred embodiment.
- FIG. 5 is a block diagram of the message transmit DMA.
- FIG. 6 is a block diagram of the message receive DMA.
- FIG. 7 is a block diagram of the digital processor system.
- FIG. 8 is a general flow diagram of the transmit instruction.
- FIG. 9 is a state diagram of the inquiry phase.
- FIG. 10 is a state diagram of the arbitrate phase.
- FIG. 11 is a state diagram of the transmit phase.
- FIG. 12 is a general flow diagram of the receive instruction.
- FIG. 13 is a state diagram of the delay phase.
- FIG. 14 is a state diagram of the receive phase.
- the high-speed intermodule bus (HSB) 20 of the present invention is shown in simplified form in FIG. 3 .
- the preferred embodiment comprises a bus controller 22 , a transmit FIFO 24 , a receive FIFO 26 , an eight bit parallel data bus 28 and a serial arbitration bus 50 .
- the ends of the bus 28 are terminated with a plurality of resistive dividers to minimize signal reflections.
- An internal 8 bit address and data bus 30 couples the transmit 24 and receive 26 FIFOs and bus controller 22 to a CPU 32 and DMA controller 33 located on a given processor module 34 .
- the internal address and data bus 30 also permits communication between the CPU 32 and bus controller 22 and various memory elements such as PROM 36 , SRAM 38 , and DRAM 40 required to support the applications of the data processing module 34 .
- the HSB 20 is a packetized message transfer bus system.
- Various processor modules 34 can communicate data, control and status messages via the present invention.
- the HSB 20 provides high speed service for a plurality of processor modules 34 with minimum delay.
- the message transfer time between modules is kept short along with the overhead of accessing the data bus 28 and queuing each message. These requirements are achieved by using a moderately high clock rate and a parallel data bus 28 architecture.
- Transmit 24 and receive 26 FIFOs are used to simplify and speed up the interface between a processor module 34 CPU 32 and the data bus 28 .
- a common clock signal (HSB_CLK) 42 shown in FIG. 4A , comprising a TTL compatible CMOS level signal with a frequency nominally 12.5 MHz and a duty cycle of approximately 50% synchronizes all HSB 20 components and executions.
- the clock 42 pulse may originate in any part of the complete digital system and its origination is beyond the scope of this disclosure.
- the parallel data bus 28 (HSB_DAT) lines 0 - 7 , FIG. 4E , provides 8 bidirectional TTL compatible CMOS level signals. Only one message source, the bus controller or master 22 , is allowed to drive the bus 28 at any one time.
- a bus arbitration scheme determines which out of a plurality of processing module may become bus master and when.
- the relationship of the data 28 and control signal transitions to the clock 42 edges are important to recovering the data reliably at a receiving module.
- Data is clocked out from a transmitting module 24 onto the data bus 28 with the negative or trailing edge of the clock signal 42 .
- the data is then clocked on the positive or leading edge of the clock signal 42 at an addressed receiving module. This feature provides a sufficient setup and hold time of approximately 40 ns without violating the minimum setup time for octal register 60 .
- the bus controller 22 Before data can be transmitted on the data bus 28 , the bus controller 22 must obtain permission from the arbitration bus 50 , FIG. 4D , to prevent a possible data collision.
- the message source must win an arbitration from a potential multiplicity of processor module 34 access requests. The winner is granted temporary bus mastership for sending a single message. After the transfer of data is complete, bus mastership is relinquished, thereby permitting bus 28 access by other processor modules 34 .
- serial arbitration method of the present invention eliminates complex signaling and signal lines, along with the requisite centralized priority encoder and usual granting mechanism.
- the arbitration method is not daisy chained so that any processor module location on the bus 28 may be empty or occupied without requiring a change to address wiring.
- the open-collector arbitration bus 50 permits multiple processing modules 34 to compete for control of the data bus 28 . Since no processing module 34 in the digital system knows a priori if another processing module has accessed the arbitration bus 50 , modules within the HSB system may drive high and low level logic signals on the HSB simultaneously, causing arbitration collisions. The collisions occur without harm to the driving circuit elements. However, the collisions provide a method of determining bus activity.
- the arbitration bus 50 includes pullup resistors connected to a regulated voltage source to provide a logic 1 level.
- the arbitration bus driver 52 FIG. 4D , connects the arbitration bus 50 to ground to drive a logic 0 level. This results in a logic 1 only when no other processing module 34 drives a logic 0.
- the arbitration bus 50 will be low if any processing module 34 arbitration bus 50 driver 52 asserts a logic 0.
- An active low receiver inverts a logic 0 level, producing an equivalent OR gate.
- Using positive-true logic conventions yields a Awired-AND,@ using negative logic yields a Awired-OR.@ This is used to indicate if at least one device is driving the arbitration bus 50 and does not require additional logic.
- a processing module 34 asserts a logic 1 on the arbitration bus 50 and monitors a logic 0, via buffer 53 on monitor line 55 (BUS_ACT_N), the processing module 34 bus controller 22 determines that a collision has occurred and that it has lost the arbitration for access.
- the arbitration method depends on the detection of collisions and uses state machines 46 and 48 , FIG. 4A , within the bus controller 22 on each processing module 34 to determine arbitration bus 50 status as arbitration proceeds. All transitions on the arbitration bus 50 are synchronized to the bus clock 42 .
- Each processor module 34 has a unique programmed binary address to present to the arbitration bus 50 .
- the device address in the current embodiment is six bits, thereby yielding 63 unique processing module 34 identifications.
- Each processing module 34 bus controller 22 located on the HSB 20 monitors, (via a buffer 53 ), and interrogates, (via a buffer 52 ), the arbitration bus (HSBI_ARB1_N) 50 .
- the arbitration bus (HSBI_ARB1_N) 50 Six or more high level signals clocked indicate that the bus is not busy. If a processing module 34 desires to send a message, it begins arbitration by serially shifting out its own unique six bit address onto the arbitration bus 50 starting with the most significant bit. Collisions will occur on the arbitration bus 50 bit by bit as each bit of the six bit address is shifted out and examined. The first detected collision drops the processing module 34 wishing to gain access out of the arbitration. If the transmit state machine 46 of the sending module 34 detects a collision it will cease driving the arbitration bus 50 , otherwise it proceeds to shift out the entire six bit address. Control of the data bus 28 is achieved if the entire address shifts out successfully with no errors.
- a priority scheme results since logic O's pull the arbitration bus 50 low. Therefore, a processor module 34 serially shifting a string of logic O's that constitute its address will not recognize a collision until a logic 1 is shifted. Addresses having leading zeroes effectively have priority when arbitrating for the bus 50 . As long as bus 28 traffic is not heavy, this effect will not be significant.
- a processor module 34 assumes bus mastership it is free to send data on the data bus 28 .
- the bus controller 22 enables its octal bus transceiver (driver) 60 and transmits at the clock 42 rate.
- the maximum allowed message length is 512 bytes. Typically, messages will be 256 bytes or shorter.
- the arbitration bus 50 is held low by the transmitting processor module 34 during this period as an indication of a busy arbitration bus 50 .
- the bus controller 22 disables its octal bus transceiver (drivers) 60 via line 54 (HSB_A_EN_N) and releases the arbitration bus 50 to high. Another arbitration anywhere in the system may then take place.
- An alternative embodiment allows bus 28 arbitration to take place simultaneous with data transfer improving on data throughput throughout the digital system.
- the delay is considered insignificant obviating the added complexity.
- the bus controller 22 is required to control the interface between the processing module 34 microprocessor 32 and the HSB 20 and between the HSB and the bus (data bus 28 and arbitration bus 50 ) signals.
- the bus controller 22 is an Altera 7000 series EPLD (erasable programmable logic device).
- the 8 bit internal data bus 30 interfaces the bus controller 22 with the processor module 34 CPU 32 .
- the processor module 34 CPU 32 will read and write directly to the bus controller 22 internal registers via the internal data bus 30 .
- the bus controller 22 monitors the arbitration bus 50 for bus status. This is necessary to gain control for outgoing messages and to listen and recognize its address to receive incoming messages.
- the bus controller 22 also contains a number of internal registers that can be read or written to.
- the CPU 32 communicates with and instructs the bus controller 22 over the 8 bit internal data bus 30 .
- Loading the transmit FIFO 24 is handled by the bus controller 28 , DMA and address decoding circuits contained within the bus controller 22 . Gaining access to the bus 28 and unloading the FIFO 24 is handled by the transmit state machine.
- the bus controller 22 On power up the bus controller 22 receives a hardware reset 56 .
- the application software running on the processor module 34 CPU 32 has the option of resetting the bus controller 22 via a write strobe if the application requires a module reset.
- the bus controller 22 monitors, at input BUS_ACT, the arbitration bus 50 on line 55 to determine bus activity and to sync with the data bus 28 .
- the bus controller 22 After a period of inactivity, the bus controller 22 knows that the bus 28 is between messages and not busy. A processor module 34 can then request control of the bus via arbitration. If no messages are to be sent, the bus controller 22 continues to monitor the arbitration bus 50 .
- the processor module CPU 32 writes messages into the transmit FIFO 24 at approximately 20 MBps.
- the DMA controller a Motorola 68360 33 running at 25 MHz will be able to DMA the transmit FIFO 24 at approximately 12.5 MBps. Since only one message is allowed in the transmit FIFO 24 at any one time, the CPU 32 must buffer additional transmit messages in its own RAM 40 . Since the maximum allowable message length is 512 bytes with anticipated messages averaging 256 bytes, a FIFO length of 1 KB is guaranteed not to overflow.
- the transmit FIFO 24 flags empty and the next message can be loaded.
- a typical 256 byte message sent by a processing module 34 CPU 32 at 12.5 MBps will take less than 21 ⁇ sec from RAM 40 to transmit FIFO 24 .
- Bus arbitration should occupy not more than 1 ⁇ sec if the bus is not busy.
- Total elapsed time from the loading of one transmit message to the next is approximately 43 to 64 ⁇ sec. Since not many messages can queue during this period, circular RAM buffers are not required.
- the DMA controller 33 disables the processor module 34 CPU 32 and assumes control of the internal data bus 30 .
- the DMA transfer is brought about by the processor module 34 or by a request from another processor module 134 .
- the other processor 134 successfully arbitrates control of the data bus 28 and signals the processor module CPU 32 .
- the CPU 32 gives permission and releases control of bus 30 .
- the processor module CPU 32 signals the DMA controller 33 to initiate a data transfer.
- the DMA controller 33 generates the necessary addresses and tracks the number of bytes moved and in what direction. A byte and address counter are a part of the DMA controller 33 . Both are loaded from the processor module CPU 32 to setup the desired DMA transfer.
- a DMA request is made and data is moved from RAM memory 40 to the transmit FIFO 24 .
- Each processing module 34 located on the bus 28 contains the destination addresses of all devices on the bus 28 . If a match is found, the input to that receiving processing module 34 FIFO 26 is enabled. Since multiple messages may be received by this FIFO 26 , it must have more storage than a transmit FIFO 24 .
- the receive FIFO 26 has at a minimum 4 KB ⁇ 9 of storage. This amount of storage will allow at least 16 messages to queue within the receive FIFO 26 based on the message length of 256 bytes. A message burst from multiple sources could conceivably cause multiple messages to temporarily congest the receive FIFO 26 .
- the receiving module CPU 32 must have a suitable message throughput from the receive FIFO 26 or else a data overflow will result in lost information.
- DMA is used to automatically transfer messages from the receive FIFO 26 to RAM 40 .
- the transfer time from the receive FIFO 26 to RAM 40 is typically 21 ⁇ sec.
- the DMA controller 33 When a message is received by the bus controller 22 , a request for DMA service is made. Referring to FIG. 6 , the DMA controller 33 generates a message received hardware interrupt (DMA DONE) and signals processor module CPU 32 that it has control of the internal bus 30 . An interrupt routine updates the message queue pointer and transfers the contents of receive FIFO 26 to RAM memory 40 . The DMA controller 33 is then readied for the next message to be received and points to the next available message buffer. This continues until all of the contents of the receive FIFO 26 are transferred. An end of message signal is sent by the receive FIFO 26 to the DMA controller 33 via the bus controller 22 . The processor module 34 CPU 32 then regains control of the internal communication bus 30 .
- DMA DONE message received hardware interrupt
- An interrupt routine updates the message queue pointer and transfers the contents of receive FIFO 26 to RAM memory 40 .
- the DMA controller 33 is then readied for the next message to be received and points to the next available message buffer. This continues until all of
- the total elapsed time that it takes for a source to destination message transfer is approximately 64 to 85 ⁇ sec. As shown in FIG. 7 , the time is computed from when a processor module 34 starts to send a message, load its transmit FIFO 24 , arbitrate and acquire the data bus 28 , transfer the data to the destination receive FIFO 126 , bus the message to the CPU 132 , and then finally transfer the message into RAM 140 of the recipient module 134 .
- the actual throughput is almost 200 times that of a 8 KBps time slot on a PCM highway.
- Controlling the HSB 20 requires two state machines; one transmitting information 70 , the other receiving information 72 .
- Any arbitrary state machine has a set of states and a set of transition rules for moving between those states at each clock edge.
- the transition rules depend both on the present state and on the particular combination of inputs present at the next clock edge.
- the Altera EPLD 22 used in the preferred embodiment contains enough register bits to represent all possible states and enough inputs and logic gates to implement the transition rules.
- a general transmit program flow diagram 70 for the transmit state machine is shown in FIG. 8 .
- Within the general flow diagram 70 are three state machine diagrams for the inquire 74 , arbitrate 76 , and transmit 78 phases of the transmit state machine.
- the processor module CPU 32 initiates the inquire phase 74 . As shown in FIG. 9 , eight states are shown along with the transition rules necessary for the bus controller 22 to sense bus activity. After initiation, a transmit request is forwarded to the bus controller 22 to see if there is bus activity. The bus controller 22 monitors the arbitration bus 50 for a minimum of 7 clock cycles. Six internal bus controller addresses are examined for collisions. If no collisions are detected, a request to arbitrate is made on the inactive bus.
- the arbitrate request sets a flip-flop 80 and begins sending out a unique identifier followed by six address bits on the arbitration line (HSBI ARB1 N) 50 .
- a collision is detected if any of the bits transmitted are not the same as monitored. If the six bits are successfully shifted onto the bus 28 , then that particular bus controller 22 has bus mastership and seizes the bus. A transmit FIFO 24 read enable is then set. If any one of the bits suffers a collision, the arbitration bus 50 is busy and the processor module 34 stops arbitrating.
- the transmit FIFO 24 read enable sets a flip-flop 82 and initiates a transmit enable.
- the contents of transmit FIFO 24 are output through the bus controller 22 , through octal bus transceiver 60 , onto the data bus 28 .
- the data is transmitted until an end of message flag is encountered.
- a clear transmit request signal is output, returning the bus controller 22 back to monitoring the bus 28 .
- the state machine for controlling the receive FIFO 26 is similarly reduced into two state machines. As shown in FIG. 12 , a general flow diagram is shown for controlling the receive FIFO 26 .
- the bus controller 22 monitors the arbitration bus 50 for a period lasting seven clock cycles. Bus activity is determined by the reception of a leading start bit from another processor module 34 bus controller 22 . If after seven clock cycles the bus has not been seized, a receive alert signal is input to receive flip-flop 89 .
- the bus controller 22 examines the first bit of data transmitted and compares it with its own address. If the first data bit is the unique identifier for that bus controller 22 , data is accumulated until an end of message flag is encountered. If the first data bit is not the unique identifier of the listening bus controller 22 , the bus controller 22 returns to the listening state.
- the software to transmit messages There are two embodiments for the software to transmit messages.
- the first embodiment will allow waiting an average of 50 ⁇ sec to send a message since there are no system interrupts performed. This simplifies queuing and unqueuing messages.
- the second embodiment assumes that messages are being sent fast, the operating system is fast and preemptive, system interrupts are handled quickly, and idling of the processor 32 is not allowed while messaging.
- data bus 28 arbitration must take place.
- the bus controller 22 may release the transmit FIFO 24 thereby placing the contents on the data bus 28 .
- An empty flag signals a complete transfer to the bus controller 22 and processor module 34 CPU 32 .
Abstract
Method and apparatus for an arbitrated high speed control data bus system providing high speed communications between microprocessor modules in a complex digital processing environment. The system features a simplified hardware architecture featuring fast FIFO queuing, TTL CMOS compatible level clocking signals, single bus master arbitration, synchronous clocking, DMA, and unique module addressing for multiprocessor systems. The system includes a parallel data bus with sharing bus masters residing on each processing module decreeing the communication and data transfer protocol. Bur arbitration is performed over a dedicated, independent, serial arbitration line. Each requesting module competes for access to the parallel data bus by placing the address of the requesting module on the arbitration line and monitoring the arbitration line for collisions, eliminating the need for both bus request and bus grant signals.
Description
- This application is a continuation of U.S. patent application Ser. No. 10/166,216 filed on Jun. 10, 2002; which is a continuation of U.S. patent application Ser. No. 09/079,600, filed on May 15, 1998, which issued on Jun. 11, 2002 as U.S. Pat. No. 6,405,272; which is a continuation of U.S. patent application Ser. No. 08/671,221, filed on Jun. 27, 1996, which issued on May 19, 1998 as U.S. Pat. No. 5,754,803, all of which are incorporated herein by reference.
- 1. Field of the Invention
- This invention relates generally to a system for transferring data between a data processing module and a plurality of data processing modules. More particularly, the invention relates to a high-speed data communication system which transfers information between different digital processing modules on a shared parallel bus.
- 2. Description of the Related Art
- For communication within a digital device, such as between a CPU (central processing unit), memory, peripherals, I/O (input/output) devices, or other data processors, a communication bus is often employed. As shown in
FIG. 1 , a communication bus is a set of shared electrical conductors for the exchange of digital words. In this manner, communication between devices is simplified, thereby obviating separate interconnections. - A communication bus typically contains a set of data lines, address lines for determining which device should transmit or receive, and control and strobe lines that specify the type of command is executing. The address and strobe lines communicate one-way from a central processing unit. Typically, all data lines are bidirectional.
- Data lines are asserted by the CPU during the write instruction, and by the peripheral device during read. Both the CPU and peripheral device use three-state drivers for the data lines.
- In a computer system where several data processing devices exchange data on a shared data bus, the two normal states of high and low voltage (representing the binary 1's and 0's) are implemented by an active voltage pullup. However, when several processing modules are exchanging data on a data bus, a third output state, open circuit, must be added so that another device located on the bus can drive the same line.
- Three-state or open-collector drivers are used so that devices connected to the bus can disable their bus drivers, since only one device is asserting data onto the bus at a given time. Each bus system has a defined protocol for determining which device asserts data. A bus system is designed so that, at most, one device has its drivers enabled at one time with all other devices disabled (third state). A device knows to assert data onto the bus by recognizing its own address on the control lines. The device looks at the control lines and asserts data when it sees its particular address on the address lines and a read pulse. However, there must be some external logic ensuring that the three-state devices sharing the same lines do not talk at the same time or bus contention will result.
- Bus control logic or a Abus master@ executes code for the protocol used to arbitrate control of the bus. The bus master may be part of a CPU or function independently. More importantly, control of the bus may be granted to another device. More complex bus systems permit other devices located on the bus to master the bus.
- Data processing systems have processors which execute programmed instructions stored in a plurality of memory locations. As shown in
FIG. 1 , the processed data is transferred in and out of the system by using I/O devices onto a bus, interconnecting with other digital devices. A bus protocol, or handshaking rules delineate a predetermined series of steps to permit data exchange between the devices. - To move data on a shared bus, the data, recipient and moment of transmission must be specified. Therefore, data, address and a strobe line must be specified. There are as many data lines as there are bits in a word to enable a whole word to be transferred simultaneously. Data transfer is synchronized by pulses on additional strobe bus lines. The number of address lines determines the number of addressable devices.
- Communication buses are either synchronous or asynchronous. In a synchronous bus, data is asserted onto or retrieved from the bus synchronously with strobing signals generated by the CPU or elsewhere in the system. However, the device sending the data does not know if the data was received. In an asynchronous bus, although handshaking between communicating devices assures the sending device that the data was received, the hardware and signaling complexity is increased.
- In most high-speed, computationally intensive multichannel data processing applications, digital data must be moved very rapidly to or from another processing device. The transfer of data is performed between memory and a peripheral device via the bus without program intervention. This is also known as direct memory access (DMA). In DMA transfers, the device requests access to the bus via special bus request lines and the bus master arbitrates how the data is moved, (either in bytes, blocks or packets), prior to releasing the bus to the CPU.
- A number of different types of bus communication systems and protocols are currently in use today to perform data transfer. As shown in the table of
FIG. 2 , various methods have been devised to manipulate data between processing devices. Data communication buses having powerful SDLC/HDLC (synchronous/high-level data link control) protocols exist, along with standardized parallel transmission such as small computer system interface (SCSI) and carrier-sense multiple-access/collision-detection (CSMA/CD)(Ethernet) networks. However, in specialized, high-speed applications, a simplified data communication bus is desired. - Accordingly, there exists a need for a simplified data processing system architecture to optimize data and message transfer between various processor modules residing on a data bus.
- Method and apparatus for an arbitrated high speed control data bus system is provided which allows high speed communication between microprocessor modules in a more complex digital processing environment. The system features a simplified hardware architecture featuring fast FIFO (first-in/first-out) queing, TTL CMOS (complimentary metal-oxide silicon) compatible level clocking signals, single bus master arbitration, synchronous clocking, DMA, and unique module addressing for multiprocessor systems. The present invention includes a parallel data bus with sharing bus masters residing on each processing module controlling the communication and data transfer protocols. The high-speed intermodule communication bus (HSB) provides between various microprocessor modules. The data bus is synchronous and completely bidirectional. Each processing module that communicates on the bus will have the described bus control architecture. The HSB comprises, in one embodiment, eight shared parallel data lines for the exchange of digital data, and two independent lines for arbitration and clock signals. The need for explicit bus request or grant signals is eliminated. The HSB can also be configured as a semi-redundant system, duplicating data lines while maintaining a single component level. The bus is driven by three-state gates with resistor pullups serving as terminators to minimize signal reflections.
- To move data on the HSB, each processing module specifies the data, the recipient, and the moment when the data is valid. Only one message source, known as the bus master, is allowed to drive the bus at any given time. Since the data flow is bidirectional, the bus arbitration scheme establishes a protocol of rules to prevent collisions on the data lines when a given processing module microprocessor is executing instructions. The arbitration method depends on the detection of collisions present only on the arbitration bus and uses state machines on each data processing module to determine bus status. Additionally, the arbitration method is not daisy chained, allowing greater system flexibility. The state machines located on each processing module are the controlling interface between the microprocessor used within a given processing module and the HSB. The circuitry required for the interface is comprised of a transmit FIFO, receive FIFO, miscellaneous directional/bidirectional signal buffers and the software code for the state machines executed in an EPLD (erasable programmable logic device).
- Objects and advantages of the system and method will become apparent to those skilled in the art after reading the detailed description of the preferred embodiment.
-
FIG. 1 is a block diagram of a typical, prior art data communication bus. -
FIG. 2 is a table of prior art data bus architectures. -
FIG. 3 is a simplified block diagram of the preferred embodiment. -
FIGS. 4A-4E , taken together, is an electrical schematic of the preferred embodiment. -
FIG. 5 is a block diagram of the message transmit DMA. -
FIG. 6 is a block diagram of the message receive DMA. -
FIG. 7 is a block diagram of the digital processor system. -
FIG. 8 is a general flow diagram of the transmit instruction. -
FIG. 9 is a state diagram of the inquiry phase. -
FIG. 10 is a state diagram of the arbitrate phase. -
FIG. 11 is a state diagram of the transmit phase. -
FIG. 12 is a general flow diagram of the receive instruction. -
FIG. 13 is a state diagram of the delay phase. -
FIG. 14 is a state diagram of the receive phase. - The preferred embodiment will be described with reference to the drawing figures where like numerals represent like elements throughout.
- The high-speed intermodule bus (HSB) 20 of the present invention is shown in simplified form in
FIG. 3 . The preferred embodiment comprises abus controller 22, a transmitFIFO 24, a receiveFIFO 26, an eight bitparallel data bus 28 and aserial arbitration bus 50. The ends of thebus 28 are terminated with a plurality of resistive dividers to minimize signal reflections. An internal 8 bit address anddata bus 30 couples the transmit 24 and receive 26 FIFOs andbus controller 22 to aCPU 32 andDMA controller 33 located on a givenprocessor module 34. The internal address anddata bus 30 also permits communication between theCPU 32 andbus controller 22 and various memory elements such asPROM 36,SRAM 38, andDRAM 40 required to support the applications of thedata processing module 34. - The
HSB 20 is a packetized message transfer bus system.Various processor modules 34 can communicate data, control and status messages via the present invention. - The
HSB 20 provides high speed service for a plurality ofprocessor modules 34 with minimum delay. The message transfer time between modules is kept short along with the overhead of accessing thedata bus 28 and queuing each message. These requirements are achieved by using a moderately high clock rate and aparallel data bus 28 architecture. Transmit 24 and receive 26 FIFOs are used to simplify and speed up the interface between aprocessor module 34CPU 32 and thedata bus 28. - Referring to
FIGS. 4A-4E , a common clock signal (HSB_CLK) 42, shown inFIG. 4A , comprising a TTL compatible CMOS level signal with a frequency nominally 12.5 MHz and a duty cycle of approximately 50% synchronizes allHSB 20 components and executions. Theclock 42 pulse may originate in any part of the complete digital system and its origination is beyond the scope of this disclosure. - The parallel data bus 28 (HSB_DAT) lines 0-7,
FIG. 4E , provides 8 bidirectional TTL compatible CMOS level signals. Only one message source, the bus controller ormaster 22, is allowed to drive thebus 28 at any one time. A bus arbitration scheme determines which out of a plurality of processing module may become bus master and when. - The relationship of the
data 28 and control signal transitions to theclock 42 edges are important to recovering the data reliably at a receiving module. Data is clocked out from a transmittingmodule 24 onto thedata bus 28 with the negative or trailing edge of theclock signal 42. The data is then clocked on the positive or leading edge of theclock signal 42 at an addressed receiving module. This feature provides a sufficient setup and hold time of approximately 40 ns without violating the minimum setup time foroctal register 60. - Before data can be transmitted on the
data bus 28, thebus controller 22 must obtain permission from thearbitration bus 50,FIG. 4D , to prevent a possible data collision. The message source must win an arbitration from a potential multiplicity ofprocessor module 34 access requests. The winner is granted temporary bus mastership for sending a single message. After the transfer of data is complete, bus mastership is relinquished, thereby permittingbus 28 access byother processor modules 34. - No explicit bus request and grant signals are required with the serial arbitration method of the present invention. The preferred method eliminates complex signaling and signal lines, along with the requisite centralized priority encoder and usual granting mechanism. The arbitration method is not daisy chained so that any processor module location on the
bus 28 may be empty or occupied without requiring a change to address wiring. - In the present invention, the open-
collector arbitration bus 50 permitsmultiple processing modules 34 to compete for control of thedata bus 28. Since noprocessing module 34 in the digital system knows a priori if another processing module has accessed thearbitration bus 50, modules within the HSB system may drive high and low level logic signals on the HSB simultaneously, causing arbitration collisions. The collisions occur without harm to the driving circuit elements. However, the collisions provide a method of determining bus activity. - The
arbitration bus 50 includes pullup resistors connected to a regulated voltage source to provide alogic 1 level. Thearbitration bus driver 52,FIG. 4D , connects thearbitration bus 50 to ground to drive alogic 0 level. This results in alogic 1 only when noother processing module 34 drives alogic 0. Thearbitration bus 50 will be low if anyprocessing module 34arbitration bus 50driver 52 asserts alogic 0. - As known to those familiar with the art, the connection is called Awired-OR@ since it behaves like a large NOR gate with the line going low if any device drives high (DeMorgan=s theorem). An active low receiver inverts a
logic 0 level, producing an equivalent OR gate. Using positive-true logic conventions yields a Awired-AND,@ using negative logic yields a Awired-OR.@ This is used to indicate if at least one device is driving thearbitration bus 50 and does not require additional logic. Therefore, if aprocessing module 34 asserts alogic 1 on thearbitration bus 50 and monitors alogic 0, viabuffer 53 on monitor line 55 (BUS_ACT_N), theprocessing module 34bus controller 22 determines that a collision has occurred and that it has lost the arbitration for access. - The arbitration method depends on the detection of collisions and uses
state machines FIG. 4A , within thebus controller 22 on eachprocessing module 34 to determinearbitration bus 50 status as arbitration proceeds. All transitions on thearbitration bus 50 are synchronized to thebus clock 42. Eachprocessor module 34 has a unique programmed binary address to present to thearbitration bus 50. The device address in the current embodiment is six bits, thereby yielding 63unique processing module 34 identifications. - Each
processing module 34bus controller 22 located on theHSB 20 monitors, (via a buffer 53), and interrogates, (via a buffer 52), the arbitration bus (HSBI_ARB1_N) 50. Six or more high level signals clocked indicate that the bus is not busy. If aprocessing module 34 desires to send a message, it begins arbitration by serially shifting out its own unique six bit address onto thearbitration bus 50 starting with the most significant bit. Collisions will occur on thearbitration bus 50 bit by bit as each bit of the six bit address is shifted out and examined. The first detected collision drops theprocessing module 34 wishing to gain access out of the arbitration. If the transmitstate machine 46 of the sendingmodule 34 detects a collision it will cease driving thearbitration bus 50, otherwise it proceeds to shift out the entire six bit address. Control of thedata bus 28 is achieved if the entire address shifts out successfully with no errors. - A priority scheme results since logic O's pull the
arbitration bus 50 low. Therefore, aprocessor module 34 serially shifting a string of logic O's that constitute its address will not recognize a collision until alogic 1 is shifted. Addresses having leading zeroes effectively have priority when arbitrating for thebus 50. As long asbus 28 traffic is not heavy, this effect will not be significant. - In an alternative embodiment, measures can be taken to add equity between
processor modules 34 if required. This can be done by altering module arbitration ID=s or the waiting period between messages. - Once a
processor module 34 assumes bus mastership it is free to send data on thedata bus 28. Thebus controller 22 enables its octal bus transceiver (driver) 60 and transmits at theclock 42 rate. The maximum allowed message length is 512 bytes. Typically, messages will be 256 bytes or shorter. After a successful arbitration, thearbitration bus 50 is held low by the transmittingprocessor module 34 during this period as an indication of abusy arbitration bus 50. - Once the data transfer is complete, the
bus controller 22 disables its octal bus transceiver (drivers) 60 via line 54 (HSB_A_EN_N) and releases thearbitration bus 50 to high. Another arbitration anywhere in the system may then take place. - An alternative embodiment allows
bus 28 arbitration to take place simultaneous with data transfer improving on data throughput throughout the digital system. In the preferred embodiment, the delay is considered insignificant obviating the added complexity. - The
bus controller 22 is required to control the interface between theprocessing module 34microprocessor 32 and theHSB 20 and between the HSB and the bus (data bus 28 and arbitration bus 50) signals. In the preferred embodiment thebus controller 22 is an Altera 7000 series EPLD (erasable programmable logic device). The 8 bitinternal data bus 30 interfaces thebus controller 22 with theprocessor module 34CPU 32. Theprocessor module 34CPU 32 will read and write directly to thebus controller 22 internal registers via theinternal data bus 30. Thebus controller 22 monitors thearbitration bus 50 for bus status. This is necessary to gain control for outgoing messages and to listen and recognize its address to receive incoming messages. Thebus controller 22 monitors and controls the data FIFO=s 24 and 26,DMA controller 33, and bus buffer enable 54. - The components used in the preferred embodiment are shown in Table 1.
TABLE 1 MANU- ELE- QTY FACTURER PART NUMBER DESCRIPTION MENT 1 IDT, or IDT7202LA-50J 1Kx9 Receive FIFO 24 Samsung KM75C02AJ50 1 IDT, or IDT7204LA-50J 4Kx9 Transmit 26 Samsung KM75C04AJ50 FIFO 1 TI, or SN74ABT125 Quad tristate 58 TI SN74BCT125 driver 3 TI, or SN74ABT245 TTL Octal Buffers 60 TI SN74BCT245 1 Altera 7128E erasable 22 programmable logic device - Address decoding and DMA gating are required and are performed by the
bus controller 22. Thebus controller 22 also contains a number of internal registers that can be read or written to. TheCPU 32 communicates with and instructs thebus controller 22 over the 8 bitinternal data bus 30. - Loading the transmit
FIFO 24 is handled by thebus controller 28, DMA and address decoding circuits contained within thebus controller 22. Gaining access to thebus 28 and unloading theFIFO 24 is handled by the transmit state machine. - On power up the
bus controller 22 receives ahardware reset 56. The application software running on theprocessor module 34CPU 32 has the option of resetting thebus controller 22 via a write strobe if the application requires a module reset. After a reset, thebus controller 22 monitors, at input BUS_ACT, thearbitration bus 50 online 55 to determine bus activity and to sync with thedata bus 28. - After a period of inactivity, the
bus controller 22 knows that thebus 28 is between messages and not busy. Aprocessor module 34 can then request control of the bus via arbitration. If no messages are to be sent, thebus controller 22 continues to monitor thearbitration bus 50. - The
processor module CPU 32 writes messages into the transmitFIFO 24 at approximately 20 MBps. The DMA controller, aMotorola 68360 33 running at 25 MHz will be able to DMA the transmitFIFO 24 at approximately 12.5 MBps. Since only one message is allowed in the transmitFIFO 24 at any one time, theCPU 32 must buffer additional transmit messages in itsown RAM 40. Since the maximum allowable message length is 512 bytes with anticipated messages averaging 256 bytes, a FIFO length of 1 KB is guaranteed not to overflow. Once a message has been successfully sent, the transmitFIFO 24 flags empty and the next message can be loaded. - A typical 256 byte message sent by a
processing module 34CPU 32 at 12.5 MBps will take less than 21 μsec fromRAM 40 to transmitFIFO 24. Bus arbitration should occupy not more than 1 μsec if the bus is not busy. Total elapsed time from the loading of one transmit message to the next is approximately 43 to 64 μsec. Since not many messages can queue during this period, circular RAM buffers are not required. - As shown in
FIGS. 5 and 7 , during DMA transfers, theDMA controller 33 disables theprocessor module 34CPU 32 and assumes control of theinternal data bus 30. The DMA transfer is brought about by theprocessor module 34 or by a request from anotherprocessor module 134. Theother processor 134 successfully arbitrates control of thedata bus 28 and signals theprocessor module CPU 32. TheCPU 32 gives permission and releases control ofbus 30. Theprocessor module CPU 32 signals theDMA controller 33 to initiate a data transfer. TheDMA controller 33 generates the necessary addresses and tracks the number of bytes moved and in what direction. A byte and address counter are a part of theDMA controller 33. Both are loaded from theprocessor module CPU 32 to setup the desired DMA transfer. On command from theCPU 32, a DMA request is made and data is moved fromRAM memory 40 to the transmitFIFO 24. - Data transferred on the
bus 28 is monitored by eachprocessing module 34 located on thebus 28. Eachbus controller 22 in the entire processor system contains the destination addresses of all devices on thebus 28. If a match is found, the input to that receivingprocessing module 34FIFO 26 is enabled. Since multiple messages may be received by thisFIFO 26, it must have more storage than a transmitFIFO 24. The receiveFIFO 26 has at aminimum 4 KB×9 of storage. This amount of storage will allow at least 16 messages to queue within the receiveFIFO 26 based on the message length of 256 bytes. A message burst from multiple sources could conceivably cause multiple messages to temporarily congest the receiveFIFO 26. The receivingmodule CPU 32 must have a suitable message throughput from the receiveFIFO 26 or else a data overflow will result in lost information. DMA is used to automatically transfer messages from the receiveFIFO 26 toRAM 40. The transfer time from the receiveFIFO 26 to RAM 40 is typically 21 μsec. - When a message is received by the
bus controller 22, a request for DMA service is made. Referring toFIG. 6 , theDMA controller 33 generates a message received hardware interrupt (DMA DONE) and signalsprocessor module CPU 32 that it has control of theinternal bus 30. An interrupt routine updates the message queue pointer and transfers the contents of receiveFIFO 26 toRAM memory 40. TheDMA controller 33 is then readied for the next message to be received and points to the next available message buffer. This continues until all of the contents of the receiveFIFO 26 are transferred. An end of message signal is sent by the receiveFIFO 26 to theDMA controller 33 via thebus controller 22. Theprocessor module 34CPU 32 then regains control of theinternal communication bus 30. - The total elapsed time that it takes for a source to destination message transfer is approximately 64 to 85 μsec. As shown in
FIG. 7 , the time is computed from when aprocessor module 34 starts to send a message, load its transmitFIFO 24, arbitrate and acquire thedata bus 28, transfer the data to the destination receiveFIFO 126, bus the message to theCPU 132, and then finally transfer the message intoRAM 140 of therecipient module 134. The actual throughput is almost 200 times that of a 8 KBps time slot on a PCM highway. - Controlling the
HSB 20 requires two state machines; one transmittinginformation 70, the other receiving information 72. Both state machines are implemented in thebus controller 22 as programmable logic in the form of Altera=s MAX+PLUS II, Version 6.0 state machine syntax. - Any arbitrary state machine has a set of states and a set of transition rules for moving between those states at each clock edge. The transition rules depend both on the present state and on the particular combination of inputs present at the next clock edge. The
Altera EPLD 22 used in the preferred embodiment contains enough register bits to represent all possible states and enough inputs and logic gates to implement the transition rules. - A general transmit program flow diagram 70 for the transmit state machine is shown in
FIG. 8 . Within the general flow diagram 70 are three state machine diagrams for the inquire 74, arbitrate 76, and transmit 78 phases of the transmit state machine. - The
processor module CPU 32 initiates the inquirephase 74. As shown inFIG. 9 , eight states are shown along with the transition rules necessary for thebus controller 22 to sense bus activity. After initiation, a transmit request is forwarded to thebus controller 22 to see if there is bus activity. Thebus controller 22 monitors thearbitration bus 50 for a minimum of 7 clock cycles. Six internal bus controller addresses are examined for collisions. If no collisions are detected, a request to arbitrate is made on the inactive bus. - As shown in
FIG. 10 , the arbitrate request sets a flip-flop 80 and begins sending out a unique identifier followed by six address bits on the arbitration line (HSBI ARB1 N) 50. A collision is detected if any of the bits transmitted are not the same as monitored. If the six bits are successfully shifted onto thebus 28, then thatparticular bus controller 22 has bus mastership and seizes the bus. A transmitFIFO 24 read enable is then set. If any one of the bits suffers a collision, thearbitration bus 50 is busy and theprocessor module 34 stops arbitrating. - Referencing
FIG. 11 , the transmitFIFO 24 read enable sets a flip-flop 82 and initiates a transmit enable. The contents of transmitFIFO 24 are output through thebus controller 22, throughoctal bus transceiver 60, onto thedata bus 28. The data is transmitted until an end of message flag is encountered. Once the transmitFIFO 24 is emptied, a clear transmit request signal is output, returning thebus controller 22 back to monitoring thebus 28. - The state machine for controlling the receive
FIFO 26 is similarly reduced into two state machines. As shown inFIG. 12 , a general flow diagram is shown for controlling the receiveFIFO 26. - Referencing
FIG. 13 , thebus controller 22 monitors thearbitration bus 50 for a period lasting seven clock cycles. Bus activity is determined by the reception of a leading start bit from anotherprocessor module 34bus controller 22. If after seven clock cycles the bus has not been seized, a receive alert signal is input to receive flip-flop 89. - As shown in
FIG. 14 , thebus controller 22 examines the first bit of data transmitted and compares it with its own address. If the first data bit is the unique identifier for thatbus controller 22, data is accumulated until an end of message flag is encountered. If the first data bit is not the unique identifier of the listeningbus controller 22, thebus controller 22 returns to the listening state. - There are two embodiments for the software to transmit messages. The first embodiment will allow waiting an average of 50 μsec to send a message since there are no system interrupts performed. This simplifies queuing and unqueuing messages. The second embodiment assumes that messages are being sent fast, the operating system is fast and preemptive, system interrupts are handled quickly, and idling of the
processor 32 is not allowed while messaging. - Upon completion of the transmit DMA,
data bus 28 arbitration must take place. After thedata bus 28 has been successfully arbitrated, thebus controller 22 may release the transmitFIFO 24 thereby placing the contents on thedata bus 28. An empty flag signals a complete transfer to thebus controller 22 andprocessor module 34CPU 32. - While specific embodiments of the present invention have been shown and described, many modifications and variations could be made by one skilled in the art without departing from the spirit and scope of the invention. The above description serves to illustrate and not limit the particular form in any way.
Claims (10)
1. A method for controlling access to a data bus which is shared by a plurality of data processing modules, the method comprising:
providing an arbitration bus independent from the data bus;
placing a unique address of the data processing module bit by bit on the arbitration bus, while monitoring the arbitration bus simultaneously, wherein the data processing module stops placing its address when a bit different from its own address bit is detected on the arbitration bus;
asserting the data bus when the data processing module succeeds to place and detect all the bits of its own address on the arbitration bus; and
withholding the arbitration bus until data transfer is completed.
2. The method of claim 1 further comprising a step of monitoring the arbitration bus for a predetermined duration before placing the address on the arbitration bus, whereby the data processing module places its own address only if the arbitration bus is not busy.
3. The method of claim 2 wherein the data processing module monitors the arbitration bus for a period equal to the length of the address of the data processing module.
4. The method of claim 1 wherein the address of the plurality of data processing modules are prioritized.
5. The method of claim 1 wherein the address of the data processing module is a binary code.
6. An apparatus for transferring data through a data bus, the apparatus comprising:
a data bus;
an arbitration bus; and
a plurality of data processing modules, each data processing module comprising a bus controller for placing a unique address of the data processing module in series on the arbitration bus while detecting occurrence of collision on the arbitration bus simultaneously, whereby the data processing module withholds the data bus if the data processing module succeeds to place all the bits of its own address on the arbitration bus without collision.
7. The apparatus of claim 6 wherein the bus controller of the data processing module monitors the arbitration bus for a predetermined duration before placing the address on the arbitration bus, whereby the data processing module places its own address only if the arbitration bus is not busy.
8. The apparatus of claim 7 wherein the data processing module monitors the arbitration bus for a period equal to the length of the address of the data processing module.
9. The apparatus of claim 6 wherein the address of the plurality of data processing modules are prioritized.
10. The apparatus of claim 6 wherein the address of the data processing module is a binary code.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/996,494 US20050097251A1 (en) | 1996-06-27 | 2004-11-23 | System and method for arbitration of a plurality of processing modules |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/671,221 US5754803A (en) | 1996-06-27 | 1996-06-27 | Parallel packetized intermodule arbitrated high speed control and data bus |
US09/079,600 US6405272B1 (en) | 1996-06-27 | 1998-05-15 | System and method for arbitration of a plurality of processing modules |
US10/166,216 US6823412B2 (en) | 1996-06-27 | 2002-06-10 | System and method for arbitration of a plurality of processing modules |
US10/996,494 US20050097251A1 (en) | 1996-06-27 | 2004-11-23 | System and method for arbitration of a plurality of processing modules |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/166,216 Continuation US6823412B2 (en) | 1996-06-27 | 2002-06-10 | System and method for arbitration of a plurality of processing modules |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050097251A1 true US20050097251A1 (en) | 2005-05-05 |
Family
ID=24693614
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/671,221 Expired - Lifetime US5754803A (en) | 1995-06-30 | 1996-06-27 | Parallel packetized intermodule arbitrated high speed control and data bus |
US09/079,600 Expired - Lifetime US6405272B1 (en) | 1995-06-30 | 1998-05-15 | System and method for arbitration of a plurality of processing modules |
US10/166,216 Expired - Lifetime US6823412B2 (en) | 1996-06-27 | 2002-06-10 | System and method for arbitration of a plurality of processing modules |
US10/996,494 Abandoned US20050097251A1 (en) | 1996-06-27 | 2004-11-23 | System and method for arbitration of a plurality of processing modules |
Family Applications Before (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/671,221 Expired - Lifetime US5754803A (en) | 1995-06-30 | 1996-06-27 | Parallel packetized intermodule arbitrated high speed control and data bus |
US09/079,600 Expired - Lifetime US6405272B1 (en) | 1995-06-30 | 1998-05-15 | System and method for arbitration of a plurality of processing modules |
US10/166,216 Expired - Lifetime US6823412B2 (en) | 1996-06-27 | 2002-06-10 | System and method for arbitration of a plurality of processing modules |
Country Status (14)
Country | Link |
---|---|
US (4) | US5754803A (en) |
EP (2) | EP1174798A3 (en) |
JP (2) | JP3604398B2 (en) |
KR (1) | KR100321490B1 (en) |
CN (2) | CN1107913C (en) |
AT (1) | ATE216100T1 (en) |
AU (1) | AU3649597A (en) |
CA (1) | CA2259257C (en) |
DE (2) | DE69711877T2 (en) |
DK (1) | DK0907921T3 (en) |
ES (1) | ES2137909T3 (en) |
HK (2) | HK1017108A1 (en) |
PT (1) | PT907921E (en) |
WO (1) | WO1997050039A1 (en) |
Families Citing this family (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7929498B2 (en) | 1995-06-30 | 2011-04-19 | Interdigital Technology Corporation | Adaptive forward power control and adaptive reverse power control for spread-spectrum communications |
US7020111B2 (en) | 1996-06-27 | 2006-03-28 | Interdigital Technology Corporation | System for using rapid acquisition spreading codes for spread-spectrum communications |
ZA965340B (en) | 1995-06-30 | 1997-01-27 | Interdigital Tech Corp | Code division multiple access (cdma) communication system |
US6885652B1 (en) | 1995-06-30 | 2005-04-26 | Interdigital Technology Corporation | Code division multiple access (CDMA) communication system |
US6178476B1 (en) * | 1997-01-06 | 2001-01-23 | Texas Instruments Incorporated | Data communication interface including an integrated data processor and serial memory device |
JPH11168524A (en) * | 1997-12-05 | 1999-06-22 | Canon Inc | Communication controller, data processing method for the communication controller and storage medium storing program readable by computer |
US6615291B1 (en) * | 1999-03-08 | 2003-09-02 | Minolta Co., Ltd. | DMA controller with dynamically variable access priority |
US6311284B1 (en) * | 1999-03-15 | 2001-10-30 | Advanced Micro Devices, Inc. | Using an independent clock to coordinate access to registers by a peripheral device and a host system |
US6831925B1 (en) * | 1999-04-06 | 2004-12-14 | National Semiconductor Corporation | Single wire interface with collision detection |
US6467006B1 (en) * | 1999-07-09 | 2002-10-15 | Pmc-Sierra, Inc. | Topology-independent priority arbitration for stackable frame switches |
US6701397B1 (en) * | 2000-03-21 | 2004-03-02 | International Business Machines Corporation | Pre-arbitration request limiter for an integrated multi-master bus system |
US7072988B1 (en) * | 2000-03-31 | 2006-07-04 | Adaptec, Inc. | Key-based collision detection algorithm for multi-initiator domain validation |
US6804527B2 (en) | 2001-01-19 | 2004-10-12 | Raze Technologies, Inc. | System for coordination of TDD transmission bursts within and between cells in a wireless access system and method of operation |
US20020112109A1 (en) * | 2001-02-14 | 2002-08-15 | Jorgenson Anthony William | Method and apparatus for providing full duplex/half duplex radially distributed serial control bus architecture |
KR20020069448A (en) * | 2001-02-26 | 2002-09-04 | 삼성전자 주식회사 | Apparatus for Fast Packet Bus |
US6898658B2 (en) * | 2001-12-27 | 2005-05-24 | Koninklijke Philips Electronics N.V. | Method to prevent net update oscillation |
CN100461724C (en) * | 2002-09-27 | 2009-02-11 | 中兴通讯股份有限公司 | POS transmitting-receiving control device |
US7096307B2 (en) * | 2002-12-18 | 2006-08-22 | Freescale Semiconductor, Inc. | Shared write buffer in a peripheral interface and method of operating |
CN1310300C (en) * | 2003-07-09 | 2007-04-11 | 华为技术有限公司 | Method for testing chips of wideband data communicatioin and chip |
US7676621B2 (en) * | 2003-09-12 | 2010-03-09 | Hewlett-Packard Development Company, L.P. | Communications bus transceiver |
KR100775876B1 (en) * | 2005-03-11 | 2007-11-13 | (주)테르텐 | An transaction method of digital data |
US7350002B2 (en) * | 2004-12-09 | 2008-03-25 | Agere Systems, Inc. | Round-robin bus protocol |
JP2006313479A (en) * | 2005-05-09 | 2006-11-16 | Toshiba Corp | Semiconductor integrated circuit device and data transfer method |
CN1984148B (en) * | 2006-05-15 | 2010-11-03 | 华为技术有限公司 | Device and method for controlling high-level data link |
US8468283B2 (en) * | 2006-06-01 | 2013-06-18 | Telefonaktiebolaget Lm Ericsson (Publ) | Arbiter diagnostic apparatus and method |
US8639867B2 (en) * | 2006-11-03 | 2014-01-28 | Sew-Eurodrive Gmbh & Co. Kg | Method and device for bus arbitration, converter and production facility |
CN100471156C (en) * | 2007-03-07 | 2009-03-18 | 今创集团有限公司 | Data bus bridge and its working method |
CN100464317C (en) * | 2007-06-27 | 2009-02-25 | 北京中星微电子有限公司 | Bus access collision detection method and system |
US8634470B2 (en) | 2007-07-24 | 2014-01-21 | Samsung Electronics Co., Ltd. | Multimedia decoding method and multimedia decoding apparatus based on multi-core processor |
US7886096B2 (en) * | 2008-08-08 | 2011-02-08 | Texas Instruments Incorporated | Throughput measurement of a total number of data bits communicated during a communication period |
JP5382003B2 (en) * | 2009-02-02 | 2014-01-08 | 富士通株式会社 | Arbitration device |
US8095700B2 (en) | 2009-05-15 | 2012-01-10 | Lsi Corporation | Controller and method for statistical allocation of multichannel direct memory access bandwidth |
JP4766160B2 (en) * | 2009-07-29 | 2011-09-07 | 株式会社デンソー | Communication system and communication node |
JP2011039905A (en) * | 2009-08-17 | 2011-02-24 | Panasonic Corp | Information processing device |
US8812287B2 (en) * | 2011-02-08 | 2014-08-19 | International Business Machines Corporation | Autonomous, scalable, digital system for emulation of wired-or hardware connection |
CN103714026B (en) * | 2014-01-14 | 2016-09-28 | 中国人民解放军国防科学技术大学 | A kind of memory access method supporting former address data exchange and device |
CN109947019A (en) * | 2019-03-27 | 2019-06-28 | 中国铁道科学研究院集团有限公司 | The processing unit and concurrent working control method of train network input-output system |
CN111314193A (en) * | 2020-04-15 | 2020-06-19 | 联合华芯电子有限公司 | Data transmission bus system, device and method |
CN111343068A (en) * | 2020-04-15 | 2020-06-26 | 联合华芯电子有限公司 | Double-speed arbitration bus system for giant carrier and carrier |
CN111478840A (en) * | 2020-04-15 | 2020-07-31 | 联合华芯电子有限公司 | Double-rate arbitration relay device for bus system |
CN111478841A (en) * | 2020-04-15 | 2020-07-31 | 联合华芯电子有限公司 | Data transmission system and method adopting special coding mode |
CN111343069A (en) * | 2020-04-15 | 2020-06-26 | 联合华芯电子有限公司 | Distributed control communication bus based on robot sensing system and robot |
CN112491680A (en) * | 2020-12-10 | 2021-03-12 | 上海镭隆科技发展有限公司 | Novel middle-layer FPGA (field programmable Gate array) bus arbitration mechanism and implementation method thereof |
CN112711550B (en) * | 2021-01-07 | 2023-12-29 | 无锡沐创集成电路设计有限公司 | DMA automatic configuration module and system-on-chip SOC |
CN113992474B (en) * | 2021-12-29 | 2022-04-01 | 北京万维盈创科技发展有限公司 | Code division multiple access coding method based on bus |
Citations (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3622985A (en) * | 1969-11-25 | 1971-11-23 | Ibm | Optimum error-correcting code device for parallel-serial transmissions in shortened cyclic codes |
US4156277A (en) * | 1977-09-26 | 1979-05-22 | Burroughs Corporation | Access request mechanism for a serial data input/output system |
US4292623A (en) * | 1979-06-29 | 1981-09-29 | International Business Machines Corporation | Port logic for a communication bus system |
US4373183A (en) * | 1980-08-20 | 1983-02-08 | Ibm Corporation | Bus interface units sharing a common bus using distributed control for allocation of the bus |
US4434421A (en) * | 1981-11-18 | 1984-02-28 | General Electric Company | Method for digital data transmission with bit-echoed arbitration |
US4458314A (en) * | 1982-01-07 | 1984-07-03 | Bell Telephone Laboratories, Incorporated | Circuitry for allocating access to a demand shared bus |
US4467418A (en) * | 1980-09-12 | 1984-08-21 | Quinquis Jean Paul | Data transmission system resolving access conflicts between transmitters-receivers to a common bus |
US4480307A (en) * | 1982-01-04 | 1984-10-30 | Intel Corporation | Interface for use between a memory and components of a module switching apparatus |
US4570220A (en) * | 1983-11-25 | 1986-02-11 | Intel Corporation | High speed parallel bus and data transfer method |
US4608700A (en) * | 1982-07-29 | 1986-08-26 | Massachusetts Institute Of Technology | Serial multi-drop data link |
US4626843A (en) * | 1983-09-27 | 1986-12-02 | Trw Inc. | Multi-master communication bus system with parallel bus request arbitration |
US4634534A (en) * | 1984-09-21 | 1987-01-06 | Bs Smogless S.P.A. | Modular plastic packing for the biological treatment of waste waters by percolation |
US4646232A (en) * | 1984-01-03 | 1987-02-24 | Texas Instruments Incorporated | Microprocessor with integrated CPU, RAM, timer, bus arbiter data for communication system |
US4656627A (en) * | 1984-11-21 | 1987-04-07 | At&T Company | Multiphase packet switching system |
US4667192A (en) * | 1983-05-24 | 1987-05-19 | The Johns Hopkins University | Method and apparatus for bus arbitration using a pseudo-random sequence |
US4675865A (en) * | 1985-10-04 | 1987-06-23 | Northern Telecom Limited | Bus interface |
US4719458A (en) * | 1986-02-24 | 1988-01-12 | Chrysler Motors Corporation | Method of data arbitration and collision detection in a data bus |
US4744079A (en) * | 1986-10-01 | 1988-05-10 | Gte Communication Systems Corporation | Data packet multiplexer/demultiplexer |
US4768145A (en) * | 1984-11-28 | 1988-08-30 | Hewlett-Packard Company | Bus system |
US4818985A (en) * | 1986-11-22 | 1989-04-04 | Nec Corporation | Bus arbitration network capable of quickly carrying out arbitration among bus masters |
US4914574A (en) * | 1984-08-16 | 1990-04-03 | Mitsubishi Denki Kabushiki Kaisha | Data transmission apparatus having cascaded data processing modules for daisy chain data transfer |
US4974148A (en) * | 1987-07-06 | 1990-11-27 | Motorola Computer X, Inc. | Bus arbiter with equitable priority scheme |
US5101482A (en) * | 1989-10-16 | 1992-03-31 | Massachusetts Institute Of Technology | Bus-based priority arbitration system with optimum codewords |
US5159551A (en) * | 1989-08-09 | 1992-10-27 | Picker International, Inc. | Prism architecture for ct scanner image reconstruction |
US5241628A (en) * | 1990-01-04 | 1993-08-31 | Intel Corporation | Method wherein source arbitrates for bus using arbitration number of destination |
US5253347A (en) * | 1988-11-18 | 1993-10-12 | Bull Hn Information Systems Italia S.P.A. | Centralized arbitration system using the status of target resources to selectively mask requests from master units |
US5263163A (en) * | 1990-01-19 | 1993-11-16 | Codex Corporation | Arbitration among multiple users of a shared resource |
US5276684A (en) * | 1991-07-22 | 1994-01-04 | International Business Machines Corporation | High performance I/O processor |
US5287463A (en) * | 1988-05-11 | 1994-02-15 | Digital Equipment Corporation | Method and apparatus for transferring information over a common parallel bus using a fixed sequence of bus phase transitions |
US5355453A (en) * | 1989-09-08 | 1994-10-11 | Auspex Systems, Inc. | Parallel I/O network file server architecture |
US5396599A (en) * | 1990-01-16 | 1995-03-07 | Nec Electronics, Inc. | Computer system with a bus controller |
US5398243A (en) * | 1991-06-05 | 1995-03-14 | Telemecanique | Arbitration method and bus for serial data transmission |
US5509126A (en) * | 1993-03-16 | 1996-04-16 | Apple Computer, Inc. | Method and apparatus for a dynamic, multi-speed bus architecture having a scalable interface |
US5557754A (en) * | 1992-06-22 | 1996-09-17 | International Business Machines Corporation | Computer system and system expansion unit |
US5561669A (en) * | 1994-10-26 | 1996-10-01 | Cisco Systems, Inc. | Computer network switching system with expandable number of ports |
US5572687A (en) * | 1994-04-22 | 1996-11-05 | The University Of British Columbia | Method and apparatus for priority arbitration among devices in a computer system |
US5689657A (en) * | 1991-03-30 | 1997-11-18 | Deutsche Itt Industries Gmbh | Apparatus and methods for bus arbitration in a multimaster system |
US5740174A (en) * | 1995-11-02 | 1998-04-14 | Cypress Semiconductor Corp. | Method and apparatus for performing collision detection and arbitration within an expansion bus having multiple transmission repeater units |
US5754800A (en) * | 1991-07-08 | 1998-05-19 | Seiko Epson Corporation | Multi processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruption |
US5884051A (en) * | 1997-06-13 | 1999-03-16 | International Business Machines Corporation | System, methods and computer program products for flexibly controlling bus access based on fixed and dynamic priorities |
US5968154A (en) * | 1995-07-25 | 1999-10-19 | Cho; Jin Young | Distributed priority arbitrating method and system in multi-point serial networks with different transmission rates |
US6157963A (en) * | 1998-03-24 | 2000-12-05 | Lsi Logic Corp. | System controller with plurality of memory queues for prioritized scheduling of I/O requests from priority assigned clients |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL7906578A (en) | 1979-09-03 | 1981-03-05 | Philips Nv | TUNING SHIFT. |
JPS5837725A (en) | 1981-08-31 | 1983-03-05 | Toshiba Corp | Control system for occupancy of bus line |
JPS58139190A (en) | 1982-02-12 | 1983-08-18 | 松下電器産業株式会社 | Keyboard type electronic musical instrument |
JP3151966B2 (en) | 1992-10-26 | 2001-04-03 | 日本電気株式会社 | Bus controller |
JPH0773138A (en) | 1993-09-02 | 1995-03-17 | Pfu Ltd | Arbitration method for bus use right and arbitration device |
-
1996
- 1996-06-27 US US08/671,221 patent/US5754803A/en not_active Expired - Lifetime
-
1997
- 1997-06-27 DE DE69711877T patent/DE69711877T2/en not_active Expired - Lifetime
- 1997-06-27 AU AU36495/97A patent/AU3649597A/en not_active Abandoned
- 1997-06-27 WO PCT/US1997/011607 patent/WO1997050039A1/en active IP Right Grant
- 1997-06-27 EP EP01122637A patent/EP1174798A3/en not_active Withdrawn
- 1997-06-27 DE DE0907921T patent/DE907921T1/en active Pending
- 1997-06-27 CN CN97195970A patent/CN1107913C/en not_active Expired - Lifetime
- 1997-06-27 CA CA002259257A patent/CA2259257C/en not_active Expired - Lifetime
- 1997-06-27 JP JP50361498A patent/JP3604398B2/en not_active Expired - Fee Related
- 1997-06-27 AT AT97933270T patent/ATE216100T1/en not_active IP Right Cessation
- 1997-06-27 ES ES97933270T patent/ES2137909T3/en not_active Expired - Lifetime
- 1997-06-27 EP EP97933270A patent/EP0907921B1/en not_active Expired - Lifetime
- 1997-06-27 DK DK97933270T patent/DK0907921T3/en active
- 1997-06-27 PT PT97933270T patent/PT907921E/en unknown
- 1997-06-27 KR KR1019980710704A patent/KR100321490B1/en not_active IP Right Cessation
-
1998
- 1998-05-15 US US09/079,600 patent/US6405272B1/en not_active Expired - Lifetime
-
1999
- 1999-05-05 HK HK99102016A patent/HK1017108A1/en not_active IP Right Cessation
-
2002
- 2002-06-10 US US10/166,216 patent/US6823412B2/en not_active Expired - Lifetime
- 2002-07-22 HK HK02105403.8A patent/HK1044388A1/en unknown
-
2003
- 2003-03-11 CN CNB031205542A patent/CN1228723C/en not_active Expired - Lifetime
-
2004
- 2004-05-31 JP JP2004161115A patent/JP2004318901A/en active Pending
- 2004-11-23 US US10/996,494 patent/US20050097251A1/en not_active Abandoned
Patent Citations (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3622985A (en) * | 1969-11-25 | 1971-11-23 | Ibm | Optimum error-correcting code device for parallel-serial transmissions in shortened cyclic codes |
US4156277A (en) * | 1977-09-26 | 1979-05-22 | Burroughs Corporation | Access request mechanism for a serial data input/output system |
US4292623A (en) * | 1979-06-29 | 1981-09-29 | International Business Machines Corporation | Port logic for a communication bus system |
US4373183A (en) * | 1980-08-20 | 1983-02-08 | Ibm Corporation | Bus interface units sharing a common bus using distributed control for allocation of the bus |
US4467418A (en) * | 1980-09-12 | 1984-08-21 | Quinquis Jean Paul | Data transmission system resolving access conflicts between transmitters-receivers to a common bus |
US4434421A (en) * | 1981-11-18 | 1984-02-28 | General Electric Company | Method for digital data transmission with bit-echoed arbitration |
US4480307A (en) * | 1982-01-04 | 1984-10-30 | Intel Corporation | Interface for use between a memory and components of a module switching apparatus |
US4458314A (en) * | 1982-01-07 | 1984-07-03 | Bell Telephone Laboratories, Incorporated | Circuitry for allocating access to a demand shared bus |
US4608700A (en) * | 1982-07-29 | 1986-08-26 | Massachusetts Institute Of Technology | Serial multi-drop data link |
US4667192A (en) * | 1983-05-24 | 1987-05-19 | The Johns Hopkins University | Method and apparatus for bus arbitration using a pseudo-random sequence |
US4626843A (en) * | 1983-09-27 | 1986-12-02 | Trw Inc. | Multi-master communication bus system with parallel bus request arbitration |
US4570220A (en) * | 1983-11-25 | 1986-02-11 | Intel Corporation | High speed parallel bus and data transfer method |
US4646232A (en) * | 1984-01-03 | 1987-02-24 | Texas Instruments Incorporated | Microprocessor with integrated CPU, RAM, timer, bus arbiter data for communication system |
US4914574A (en) * | 1984-08-16 | 1990-04-03 | Mitsubishi Denki Kabushiki Kaisha | Data transmission apparatus having cascaded data processing modules for daisy chain data transfer |
US4634534A (en) * | 1984-09-21 | 1987-01-06 | Bs Smogless S.P.A. | Modular plastic packing for the biological treatment of waste waters by percolation |
US4656627A (en) * | 1984-11-21 | 1987-04-07 | At&T Company | Multiphase packet switching system |
US4768145A (en) * | 1984-11-28 | 1988-08-30 | Hewlett-Packard Company | Bus system |
US4675865A (en) * | 1985-10-04 | 1987-06-23 | Northern Telecom Limited | Bus interface |
US4719458A (en) * | 1986-02-24 | 1988-01-12 | Chrysler Motors Corporation | Method of data arbitration and collision detection in a data bus |
US4744079A (en) * | 1986-10-01 | 1988-05-10 | Gte Communication Systems Corporation | Data packet multiplexer/demultiplexer |
US4818985A (en) * | 1986-11-22 | 1989-04-04 | Nec Corporation | Bus arbitration network capable of quickly carrying out arbitration among bus masters |
US4974148A (en) * | 1987-07-06 | 1990-11-27 | Motorola Computer X, Inc. | Bus arbiter with equitable priority scheme |
US5287463A (en) * | 1988-05-11 | 1994-02-15 | Digital Equipment Corporation | Method and apparatus for transferring information over a common parallel bus using a fixed sequence of bus phase transitions |
US5253347A (en) * | 1988-11-18 | 1993-10-12 | Bull Hn Information Systems Italia S.P.A. | Centralized arbitration system using the status of target resources to selectively mask requests from master units |
US5159551A (en) * | 1989-08-09 | 1992-10-27 | Picker International, Inc. | Prism architecture for ct scanner image reconstruction |
US5355453A (en) * | 1989-09-08 | 1994-10-11 | Auspex Systems, Inc. | Parallel I/O network file server architecture |
US5101482A (en) * | 1989-10-16 | 1992-03-31 | Massachusetts Institute Of Technology | Bus-based priority arbitration system with optimum codewords |
US5241628A (en) * | 1990-01-04 | 1993-08-31 | Intel Corporation | Method wherein source arbitrates for bus using arbitration number of destination |
US5396599A (en) * | 1990-01-16 | 1995-03-07 | Nec Electronics, Inc. | Computer system with a bus controller |
US5263163A (en) * | 1990-01-19 | 1993-11-16 | Codex Corporation | Arbitration among multiple users of a shared resource |
US5689657A (en) * | 1991-03-30 | 1997-11-18 | Deutsche Itt Industries Gmbh | Apparatus and methods for bus arbitration in a multimaster system |
US5398243A (en) * | 1991-06-05 | 1995-03-14 | Telemecanique | Arbitration method and bus for serial data transmission |
US5754800A (en) * | 1991-07-08 | 1998-05-19 | Seiko Epson Corporation | Multi processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruption |
US5276684A (en) * | 1991-07-22 | 1994-01-04 | International Business Machines Corporation | High performance I/O processor |
US5557754A (en) * | 1992-06-22 | 1996-09-17 | International Business Machines Corporation | Computer system and system expansion unit |
US5509126A (en) * | 1993-03-16 | 1996-04-16 | Apple Computer, Inc. | Method and apparatus for a dynamic, multi-speed bus architecture having a scalable interface |
US5572687A (en) * | 1994-04-22 | 1996-11-05 | The University Of British Columbia | Method and apparatus for priority arbitration among devices in a computer system |
US5561669A (en) * | 1994-10-26 | 1996-10-01 | Cisco Systems, Inc. | Computer network switching system with expandable number of ports |
US5968154A (en) * | 1995-07-25 | 1999-10-19 | Cho; Jin Young | Distributed priority arbitrating method and system in multi-point serial networks with different transmission rates |
US5740174A (en) * | 1995-11-02 | 1998-04-14 | Cypress Semiconductor Corp. | Method and apparatus for performing collision detection and arbitration within an expansion bus having multiple transmission repeater units |
US5884051A (en) * | 1997-06-13 | 1999-03-16 | International Business Machines Corporation | System, methods and computer program products for flexibly controlling bus access based on fixed and dynamic priorities |
US6157963A (en) * | 1998-03-24 | 2000-12-05 | Lsi Logic Corp. | System controller with plurality of memory queues for prioritized scheduling of I/O requests from priority assigned clients |
Also Published As
Publication number | Publication date |
---|---|
PT907921E (en) | 2002-09-30 |
AU3649597A (en) | 1998-01-14 |
ATE216100T1 (en) | 2002-04-15 |
CA2259257C (en) | 2001-05-08 |
CA2259257A1 (en) | 1997-12-31 |
JP3604398B2 (en) | 2004-12-22 |
DE69711877D1 (en) | 2002-05-16 |
CN1107913C (en) | 2003-05-07 |
KR100321490B1 (en) | 2002-06-20 |
CN1442795A (en) | 2003-09-17 |
EP0907921B1 (en) | 2002-04-10 |
JP2004318901A (en) | 2004-11-11 |
DE907921T1 (en) | 1999-10-21 |
US20020184422A1 (en) | 2002-12-05 |
HK1044388A1 (en) | 2002-10-18 |
US6405272B1 (en) | 2002-06-11 |
JPH11513158A (en) | 1999-11-09 |
US5754803A (en) | 1998-05-19 |
CN1228723C (en) | 2005-11-23 |
KR20000022283A (en) | 2000-04-25 |
WO1997050039A1 (en) | 1997-12-31 |
ES2137909T1 (en) | 2000-01-01 |
EP1174798A3 (en) | 2003-12-17 |
DE69711877T2 (en) | 2002-11-28 |
US6823412B2 (en) | 2004-11-23 |
ES2137909T3 (en) | 2002-11-16 |
EP0907921A1 (en) | 1999-04-14 |
HK1017108A1 (en) | 1999-11-12 |
EP1174798A2 (en) | 2002-01-23 |
CN1223730A (en) | 1999-07-21 |
DK0907921T3 (en) | 2002-08-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6823412B2 (en) | System and method for arbitration of a plurality of processing modules | |
US4570220A (en) | High speed parallel bus and data transfer method | |
US5530874A (en) | Network adapter with an indication signal mask and an interrupt signal mask | |
US4807109A (en) | High speed synchronous/asynchronous local bus and data transfer method | |
EP0660955B1 (en) | A device with host indication combination | |
US5878217A (en) | Network controller for switching into DMA mode based on anticipated memory overflow and out of DMA mode when the host processor is available | |
US5479395A (en) | Serial bus system | |
US5781745A (en) | High speed communication bus | |
US6970921B1 (en) | Network interface supporting virtual paths for quality of service | |
EP0576240A1 (en) | Computer system and system expansion unit | |
EP0805400B1 (en) | IEEE488 interface and message handling method | |
EP0576241A1 (en) | Computer system and system expansion unit | |
JP2933039B2 (en) | Communication controller | |
JPS61177560A (en) | Fast parallel bus construction and data transfer | |
JPH077954B2 (en) | Control device | |
JPS61175841A (en) | Fast multi-bus construction and data transfer |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |