|Número de publicación||US20050124175 A1|
|Tipo de publicación||Solicitud|
|Número de solicitud||US 11/035,649|
|Fecha de publicación||9 Jun 2005|
|Fecha de presentación||13 Ene 2005|
|Fecha de prioridad||10 Oct 2003|
|También publicado como||US6989573, US20050077519|
|Número de publicación||035649, 11035649, US 2005/0124175 A1, US 2005/124175 A1, US 20050124175 A1, US 20050124175A1, US 2005124175 A1, US 2005124175A1, US-A1-20050124175, US-A1-2005124175, US2005/0124175A1, US2005/124175A1, US20050124175 A1, US20050124175A1, US2005124175 A1, US2005124175A1|
|Inventores||Kie Ahn, Leonard Forbes|
|Cesionario original||Kie Ahn, Leonard Forbes|
|Exportar cita||BiBTeX, EndNote, RefMan|
|Citas de patentes (12), Citada por (23), Clasificaciones (26)|
|Enlaces externos: USPTO, Cesión de USPTO, Espacenet|
The invention relates to the field of semiconductor dielectric layers, and particularly to dielectric layers used in the formation of transistor gates and capacitors in dynamic random access memory devices.
Dynamic Random Access Memory Devices (DRAMs) have become the standard type of storage device in modern computer systems. Modern DRAMs are high density, highly integrated structures having a variety of configurations, most typically stacked and trench configurations. As ever increasing density is sought, more sophisticated manufacturing processes and materials are required to achieve sub micron sized electrical component layers with reliable conformity to operational specifications.
As density increases, the minimum feature sizes of DRAM components approach 100 nm and smaller. For example, the gate dielectric material thickness of MOS devices may be required to be 20 nm (200 Å) or less in certain designs. In this thickness range the most commonly used gate dielectrics, SiO2, is not suitable because of leakage current caused by direct tunneling. As a result, gate dielectric materials with high dielectric constants (k) and large band gap with a favorable band alignment, low interface density, and good thermal stability are needed for future gate dielectric applications.
There are many known high-k unilaminate dielectric materials with high dielectric constants, such as Ta2O5, TiO2 and SrTiO3, but unfortunately these materials are not thermally stable when formed directly in contact with silicon. In addition, the interface of such materials need to be coated with a diffusion barrier, which not only adds process complexity, but also defeats the purpose of using the high-k dielectric. This added interfacial layer becomes a series capacitor to the gate capacitance, and degrades the high capacitance. Moreover, materials having too high or too low a dielectric constant may not be an adequate choice for alternate gate applications. Ultra high-k materials such as SrTiO3 may cause fringing-field induced barrier lowering effect. On the other hand, materials with relatively low dielectric constant such as Al2O3 and Y2O3 do not provide sufficient advantage over the SiO2 or Si3N4.
Lanthanide oxides have also been investigated as possible dielectric materials for use in gate dielectric oxides. Jeon et al reported an investigation of the electrical characteristics of amorphous lanthanide oxides prepared by electron beam evaporation and sputtering (Jeon et al., Technical Digest of Int'l Electron Devices Meetings, 471-474, 2001). Excellent electrical characteristics were found for the amorphous lanthanide oxides including a high oxide capacitance, low leakage current, and high thermal stability. Typical dielectric constants ranged between 11.4 and 15.0 in thin samples. Accordingly, lanthanide oxides alone may be a suitable alternative for certain applications using single layers of dielectric material. Also, a single layer of ZrO2 may be used in certain applications. Recently, a zirconium oxide layer formed by atomic layer deposition (ALD) from an iodide precursor was shown to have exhibit a relative permititivity at 10 kHz of about 23-24 for films deposited at 275-325° C. (Kukli et al, Thin Solid Films 410, 53-56 (2003)).
An alternative configuration for gate electrode dielectric layers is a composite laminate dielectric layer made of two or more layers of different materials. Thin (about 10 nm) nanolaminate dielectric materials made of layers of tantalum oxide and hafnium oxide (Ta2O5-HfO2), tantalum oxide and zirconium oxide (Ta2O5—ZrO2) or zirconium oxide hafnium oxide (ZrO2—HfO2) deposited on a silicon substrate by ALD were characterized for possible gate dielectric applications by Zhang et al, J. App. Physics, 87 (4) 1921-1924 (2000). The dielectric constants of these films were in the range of 12-14 and the leakage currents were in the range of 2.6×10−8 to 4.2×10−7 A/cm−2 at MV/cm electric field.
The ALD method of forming layers is also known as “alternately pulsed chemical vapor deposition.” ALD was developed as a modification of conventional CVD techniques. While there are a variety of variations on ALD, the most commonly used method is reaction sequence ALD (RS-ALD). In RS-ALD, gaseous precursors are introduced one at a time to the substrate surface in separate pulses. Between pulses, the reactor is purged with an inert gas or is evacuated. In the first reaction step, the precursor is saturatively chemi-adsorbed at the substrate surface, and during the subsequent purging step, free precursor is removed from the reactor. In the second step, another precursor is introduced on the substrate and the desired film growth reaction takes place on the substrate surface. When the chemistry is favorable, the precursors adsorb and react with each other aggressively forming the film. Subsequent to film growth, the by-products and excess precursors are finally purged from the reactor. One advantage of RS-ALD is that one cycle of first precursor depositing, purging, second precursor depositing, reaction, and final purging can be performed in less than one second in a properly designed flow type reactor.
One striking feature of RS-ALD is the saturation of all the reaction and purging steps, which makes the growth self-limiting. This allows for large area uniformity and conformality to planar substrates and deep trenches, even in the extreme cases of porous silicon or high surface area silica and alumina powders. The control of film thickness is straight forward and can be made by simply calculating the growth cycles. ALD was originally developed to manufacture luminescent and dielectric films needed for electroluminescent displays where much effort was put to the growth of doped zinc sulfide an alkaline earth metal sulfide films. Later ALD was studied for the growth of different epitaxial composite II-V, and II-VI films, nonepitaxial crystalline or amorphous oxide and nitride firms in composite multiplaner structures. Unfortunately however, although considerable effort was put into use of ALD for growth of silicon and germanium films, difficult precursor chemistry precluded success in this area.
There is therefore a need in the art to provide other types of composite laminate dielectric layers, particularly using the favorable features of RS-ALD deposition methods.
The present invention provides semiconductor devices that include a substrate material and a composite laminate dielectric layer formed on the substrate material. The composite laminate dielectric layer includes a layer of ZrO2 and a layer of a lanthanide oxide formed on the ZrO2 layer. Alternatively, the composite laminate dielectric layer includes the layer of ZrO2 formed on the layer of lanthanide oxide. In general embodiments, the lanthanide oxide layer may be made of any one of Pr2O3, Nd2O3, Sm2O3, Gd2O3, Dy2O3 and PrTixOy, where x and y are variable, typically in a ratio of 1.0 x to 0.9-1.0 y.
In certain embodiments, the composite laminate dielectric layer is a gate dielectric layer of a MOS transistor. In other embodiments, the composite laminate dielectric layer is a dielectric insulating layer of a semiconductor capacitor. Other embodiments include MOS gate dielectric layers, semiconductor capacitors and DRAMs having one or more of the composite laminate dielectric layers made of the ZrO2 layer and the lanthanide oxide layer. In certain embodiments for a transistor gate electrode dielectric, the ZrO2 layer has a thickness of between about 1 to about 6 nm and the lanthanide oxide layer has a thickness of about 2 to 12 nm. In various embodiments, the ZrO2 layer is formed on a substrate by RS-ALD from a ZrI4 precursor and an oxygen precursor, typically H2O/H2O2, and the lanthanide oxide layer is formed by electron beam evaporation of a lanthanide oxide.
In another aspect, the invention includes methods of forming a composite laminate dielectric layer for a semiconductor device, that includes the steps of depositing a layer of ZrO2 on a silicon substrate and depositing a layer of lanthanide oxide on the ZrO2 layer or vice versa. In one embodiment, the ZrO2 oxide layer is formed by RS-ALD from a ZrI4 precursor. In another embodiment, the lanthanide oxide layer is formed by electron beam evaporation of a lanthanide oxide. In still another embodiment, the ZrO2 layer is formed RS-ALD of ZrI4 H2O/H2O2 precursors, and the lanthanide oxide layer is formed by electron beam evaporation of a lanthanide oxide.
Another aspect of the invention is a system for forming the foregoing composite laminate dielectric layers on a substrate. The system includes a first reaction vessel configured for depositing a layer of ZrO2 on a silicon substrate and a second reaction vessel configured for depositing a layer of lanthanide oxide on the ZrO2 layer. In certain embodiments, the first reaction vessel is configured for depositing the ZrO2 layer by RS-ALD and the second reaction vessel is configured for depositing the lanthanide oxide layer by electron beam evaporation. The system also includes means for transporting the substrate between the first and the second reaction vessels.
In setting forth the invention in detail, citation is made to various references that may aid one of ordinary skill in the art in the understanding or practice of various embodiments of the invention. Each such reference is incorporated herein by reference in its entirety, including the references that may be cited in the incorporated references to the extent they may required to practice the invention to its fullest scope. The drawings provided herein are not to scale nor do they necessarily depict actual geometries of the devices of the invention. Rather, the drawings are schematics that illustrate various features of the invention in a manner readily understood by one of ordinary skill in the art, who can make actual devices based on these drawings and the description that follows.
Typically, the composite laminate dielectric layer 12 is positioned between a first conductive layer 18 and a second conductive layer 20 of the semiconductor device 10. The first conductive layer 18 or the second conductive layer 20 may each be a semiconductor or a metal in certain embodiments, or one may be a semiconductor and the other may be a metal in other embodiments.
The relative thickness of the ZrO2 layer 14 and the lanthanide oxide layer 16 can be varied. In one embodiment, where the composite laminate dielectric layer 12 may be used for a MOS component, for example, as a gate dielectric, the lanthanide oxide layer 16 may be equal in thickness to the ZrO2 layer 14, or alternatively, the lanthanide oxide layer 16 may be up to 5 times the thickness of the ZrO2 layer 14. In embodiments where the composite laminate dielectric layer 12 is used for other devices, the relative thickness of the ZrO2 layer 14 and the lanthanide oxide 16 can be varied according to need. The lanthanide oxide layer 16 has a dielectric constant of about 11.4-15 while the ZrO2 material used for the ZrO2 layer 14 has a dielectric constant of about 23-25. The composite laminate dielectric layer 12, therefore, will have a dielectric constant between about 12 and 24 depending on the relative thickness of the layers used.
One of ordinary skill in the art can readily select the relative thickness of layers to use according to need. The “equivalent oxide thickness” (EOT) measurement, sometimes simply called “oxide equivalent,” is a convenient measure of the relative capacitance of any dielectric layer of a given thickness relative to the thickness that might be required in any given application. The EOT of a dielectric layer is calculated by dividing the thickness of the layer by its silicon oxide dielectric ratio. The silicon dioxide dielectric ratio is the dielectric constant of the subject material divided by the dielectric constant of silicon dioxide. The dielectric constant of silicon dioxide is about 4. Accordingly, the silicon oxide dielectric ratio for ZrO2 is about 6 (viz, 5.75-6.25) and for lanthanide oxide is about 3 (viz, 2.85-3.75). Therefore, for example, a 3 nm ZrO2 layer 14 has an EOT about 0.5 nm (i.e., 3 divided by 6) while a 3 nm lanthanide oxide layer 16 has an EOT of about 1 nm. The EOT of a composite laminate dielectric layer 12 made of a 3 nm of ZrO2 layer 14 and a 3 nm lanthanide oxide layer 16 would be the sum of the oxide equivalents for each layer, or about 1.5 nm.
One factor to consider in selecting the relative thickness of layers to use is roughness of the ZrO2 layer 14. The ZrO2 layer 14 has a smooth, cubic ZrO2 crystalline structure (c-ZrO2) within the first 5 nm when deposited by RS-ALD as describe hereafter. This smooth structure transitions to a more rough, tetragonal crystalline structure (t-ZrO2) as the layer is made thicker. Accordingly, in high density embodiments, such as in MOS gate dielectric layers where a relatively smooth ZrO2 layer is desirable, the ZrO2 layer 14 should be less than about 5 nm in thickness. In capacitor applications where the smoothness of the ZrO2 layer is less critical, the ZrO2 layer 14 can be made thicker than the lanthanide oxide layer 16 to achieve a higher dielectric constant.
As mentioned above, one embodiment of the invention is a MOS transistor made with the composite laminate dielectric layer 12 for the gate dielectric.
The capacitor 60 is used to store charge representing one bit of data. Access to the capacitor is made via a wordline 52 and digitline 78. The wordline 52 is the gate electrode 52 of the transistor 40 that is used to form a conductive channel between source/drain regions 42 and 44 when sufficient voltage is applied to the wordline 16. In certain embodiments of the DRAMS of the invention, the gate electrode 52 is located above the gate dielectric layer 12 a made of composite laminate gate dielectric material 12, having the ZrO2 layer 14 a and the lanthanide oxide layer 16 a.
As depicted in
Although the ZrO2 layer 14 and lanthanide oxide layer 16 in the embodiments shown in the foregoing Figures are depicted with the ZrO2 layer 14 positioned below the lanthanide oxide layer 16, the relative position of the layers can be reversed in various applications. The order of placement of the layers depends on the particular fabrication process for the semiconductor device and relative position of the layers with respect to other components of the device. In certain embodiments, the ZrO2 layer 14 can be formed first by depositing the ZrO2 onto and approriate surfaces by one of the RS-ALD deposition methods described herein after. Alternatively, in other embodiments, the lanthanide oxide layer 16 can be deposited first, using for example, the e-beam deposition method described herein after. In most embodiments, the ZrO2 layer 14 will be deposited first because the thickness of this layer can easily be controlled by the number of cycles used in the RS-ALD and typically forms a smooth surface on polysilicon, crystalline silicon, or other substrates.
Another aspect of the invention includes methods of forming a semiconductor structure that include forming the composite laminate dielectric layer 12 by forming the ZrO2 layer 14 and then forming the layer of lanthanide oxide 16 on the surface of the ZrO2 layer 14, or vice versa.
There are a variety of methods of depositing the ZrO2 layer used in various embodiments of the invention. One embodiment uses DC magnetron-reactive-sputtering from a Zr target in an Ar+O2 ambient atmosphere with an O2 flow rate of 2 sccm and total pressure of 40 mTorr, as described by for example, by Wen-Jie Qi, et al, Technical Digest of IEDM, 145, 1999. The sputtering may be done at different temperatures and at different power levels. After sputtering, the samples are furnace annealed in either an O2 or an N2 ambient atmospheres. The ZrO2 films deposited using this technique are amorphous and form a thin interfacial silicate layer of about 9 Å thickness. This interfacial layer can be minimized through optimization of process parameters such as power and temperature. There is no significant inter-diffusion between ZrO2 and Si. After high temperature annealing, the layer grows and converts to a more stoichiometric ZrO2 layer.
Another method for depositing the ZrO2 layer 14 in certain embodiments is atomic layer chemical vapor deposition (AL-CVD) as described for example by M. Copel, et al, Appl. Phys. Lett., 76, 436, 2000. Films of ZrO2 are grown using alternating surface saturation reactions of ZrCl4 and H2O at about 300° C. After film growth, the substrates may be transferred in air to a characterization system where they are treated to in situ annealing under ultra high vacuum or to oxidizing in a stainless-steel turbo-pumped side chamber. In certain practices, prior to deposition, a 15 Å thick SiO2 layer may be grown by thermal oxidation in a separate furnace. In these practices, samples can be treated to dilute 5% HF for 2 min prior to AL-CVD growth of the ZrO2 layer 14 to remove the SiO2. It should be noted, however, that attempts to grow ZrO2 directly on HF stripped silicon, without prior silicon oxide oxidation may result in uneven and discontinuous ZrO2 films.
Another technique for depositing the ZrO2 layer 14 in certain embodiments, is a pulsed-laser-ablation deposition method as described for example, by Yamaguchi et al. Solid State Devices and Materials, 228-229, 2000. Ultra-thin ZrO2 layers having a large dielectric constant and a smooth interface can be formed using this technique.
Another technique for depositing the ZrO2 layer 14 used in other embodiments, is in-situ rapid thermal processing as described, for example, by H. Lee et al, IEDM 2000, 27-30, 2000. Lee et al. reported the MOS characteristics of ultra thin, high quality CVD ZrO2 and Zr silicate (Zr27Si10O63) gate dielectrics deposited on silicon substrates by this method. These high-k gate dielectrics showed an excellent EOT of 8.9 Å (ZrO2) and 9.6 Å (Zr27Si10O63) with extremely low leakage current of 20 mA/cm2 and 23 mA/cm2 at Vg=−1 V, respectively.
Yet another method for depositing the ZrO2 layer 14 in other embodiments, is Jet-Vapor-Deposition (JVD), as described, for example, by Z. J. Luo et al., 2001 Symposium on VLSI Technology Digest of Technical Papers, 135-13 Luo et al. demonstrated that films with EOT of 1 nm possess high thermal stability, low leakage, high reliability and other good electrical properties. The composition of JVD films varies with thickness. Thinner films are found to be Zr silicate-like whereas thicker films are likely graded with a transition to stoichiometric ZrO2. In addition, these films were found to survive annealing temperatures as high as 1000° C.
Still another method for forming a ZrO2 layer 14 in other embodiments, is to use a modification of the low temperature oxidation method for forming a silicon oxide layer described, for example, by Saito et al. which uses oxygen generated in a high-density krypton plasma (Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials”, 152-153, 1999. In the modified method, instead of oxidizing silicon with atomic oxygen generated in the high-frequency krypton plasma at about 400° C., a thin film of Zr is first deposited on the silicon substrate by simple thermal evaporation, preferably using electron-beam evaporation of an ultra high purity Zr metal slug at a low temperature of about 150-200° C. This forms a thin film of Zr on the silicon while maintaining an atomically smooth surface. After forming the layer of Zr metal, it is oxidized to ZrO2 using the high frequency krypton plasma at about 300-500° C.
Still another and more preferred method for forming the ZrO2 layer 14 in other embodiments, is to use reaction sequence atomic layer deposition (RS-ALD) of a ZrI4 precursor followed by deposition of oxygen reactants in multiple cycles to sequentially grow the ZrO2 layer as described, for example, by Kukli et al., J. of the Electochemical Soc., 148 (12) F227-F232, 2001. In this method, the silicon substrate is first etched by treatment with about 5% HF to remove any native SiO2 formed on the surface. The etched substrate is then placed in an RS-ALD reaction vessel along with an open reservoir containing the ZrI4 precursor. The pressure in the reaction ALD reaction vessel is lowered to a value of about 250 Pa or lower for one or more pulse periods of about 0.5 to 5 seconds. A pressure of about 250 Pa is a suitable pressure for evaporating the ZrI4 and a pulse of about 0.5-2 seconds is sufficient to deposit a layer of about 0.5 to 5 angstroms per cycle. The temperature in the reaction vessel is typically maintained between about 230 and 325° C. Oxygen is then supplied by a vapor of an H2O—H2O2 precursor generated form an external reservoir at room temperature. The oxygen precursor material is passed into the ALD reaction vessel after each ZrI4 evaporative precursor pulse for a period of about 2 seconds or less.
Between each ZrI4 evaporation pulse and oxygen pulse and between each oxygen pulse and the next evaporative pulse, the reaction vessel is purged with a suitable carrier gas, such as nitrogen or a noble gas, to separate the precursors flows in the gas phase and remove excess reactants and by-products from the system. A suitable purge time for efficiency is about 2 seconds or less. Approximately 6 to 50, and typically about 10-20 evaporative cycles of 2 seconds in duration at a temperature of about 230 to 600° C. is suitable for forming a ZrO2 oxide layer of about to 2 to about 5 nm in thickness. In various embodiments, temperatures of about 230° C. to 350° C., 272-325° C. or 272-275° C. are used because less residual iodine remains in the final layers and these temperatures lead to better quality oxides having a cubic ZrO2 lattice structure at the silicon/ZrO2 interface only giving way to a tetragonal lattice structure with increasing layer thickness. Temperatures greater than about 350° C. tend to form films with more t-ZrO2 structure and reduced capacitance. The permittivity of a ZrO2 layer of 2 to 5 nm in thickness made the foregoing method is about 2-8 at 100 kHz and has an EOT of about 0.3 to about 2.4 nm.
Once the ZrO2 layer 14 is deposited, the lanthanide oxide layer 16 is deposited thereon by any suitable technique. A preferred technique for depositing the lanthanide oxide layer is e-beam evaporation.
The temperature of the substrate 96 and chamber environment is controlled by a heater 106 assembly that may include an optional reflector 97 in proximity to the substrate 96. The temperature in the chamber is raised to about 2000° C. to ensure efficient e-beam evaporation and deposition of the lanthanide oxide 102. An oxygen distribution ring 108 is located below the shutter 100. The oxygen distribution ring is a manifold that distributes oxygen around the surface of the substrate 96 at final pressure of about 10−7 Torr. The electron beam evaporation chamber 90 is configured with a vacuum pump 110 for evacuating the chamber to a pressure of about 10−6 Torr or less. Oxygen pressure in the chamber is regulated by oxygen control regulator 112. A small amount of oxygen is needed in the chamber to ensure that the deposited layer of lanthanide oxide is completely oxidized because the process of e-beam evaporation tends to degrade the oxidation stoichiometry of the lanthanide oxide material 102. Optional detectors or monitors may be included on the interior or exterior of the chamber 90, such as an interiorly situated detector 114 for detecting the thickness of the layer and the exteriorly situated monitor 116 for displaying the thickness of the layer. The lanthanide oxide layer 16 is formed to a suitable thickness of 2-10 nm on the surface of the substrate or ZrO2 layer 14 by controlling the duration of electron beam evaporation.
From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the following claims.
|Patente citada||Fecha de presentación||Fecha de publicación||Solicitante||Título|
|US5763922 *||28 Feb 1997||9 Jun 1998||Intel Corporation||CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers|
|US6420279 *||28 Jun 2001||16 Jul 2002||Sharp Laboratories Of America, Inc.||Methods of using atomic layer deposition to deposit a high dielectric constant material on a substrate|
|US6492283 *||22 Feb 2001||10 Dic 2002||Asm Microchemistry Oy||Method of forming ultrathin oxide layer|
|US6660660 *||31 Ago 2001||9 Dic 2003||Asm International, Nv.||Methods for making a dielectric stack in an integrated circuit|
|US6902763 *||16 Oct 2000||7 Jun 2005||Asm International N.V.||Method for depositing nanolaminate thin films on sensitive surfaces|
|US6967154 *||26 Ago 2002||22 Nov 2005||Micron Technology, Inc.||Enhanced atomic layer deposition|
|US7026219 *||11 Feb 2002||11 Abr 2006||Asm America, Inc.||Integration of high k gate dielectric|
|US20010032995 *||17 Ene 2001||25 Oct 2001||Jon-Paul Maria||Lanthanum oxide-based gate dielectrics for integrated circuit field effect transistors and methods of fabricating same|
|US20040106249 *||19 Jun 2003||3 Jun 2004||Hannu Huotari||Method to fabricate dual metal CMOS devices|
|US20040219746 *||29 Abr 2003||4 Nov 2004||Micron Technology, Inc.||Systems and methods for forming metal oxide layers|
|US20050077519 *||10 Oct 2003||14 Abr 2005||Kie Ahn||Lanthanide oxide/zirconium oxide atomic layer deposited nanolaminate gate dielectrics|
|US20050160981 *||28 Ago 2002||28 Jul 2005||Micron Technology, Inc.||Systems and methods for forming zirconium and/or hafnium-containing layers|
|Patente citante||Fecha de presentación||Fecha de publicación||Solicitante||Título|
|US7393736||29 Ago 2005||1 Jul 2008||Micron Technology, Inc.||Atomic layer deposition of Zrx Hfy Sn1-x-y O2 films as high k gate dielectrics|
|US7544596||30 Ago 2005||9 Jun 2009||Micron Technology, Inc.||Atomic layer deposition of GdScO3 films as gate dielectrics|
|US7662729||28 Abr 2005||16 Feb 2010||Micron Technology, Inc.||Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer|
|US7670646||5 Ene 2007||2 Mar 2010||Micron Technology, Inc.||Methods for atomic-layer deposition|
|US7687409||29 Mar 2005||30 Mar 2010||Micron Technology, Inc.||Atomic layer deposited titanium silicon oxide films|
|US7700989||1 Dic 2006||20 Abr 2010||Micron Technology, Inc.||Hafnium titanium oxide films|
|US7709402||16 Feb 2006||4 May 2010||Micron Technology, Inc.||Conductive layers for hafnium silicon oxynitride films|
|US7719065||29 Ago 2005||18 May 2010||Micron Technology, Inc.||Ruthenium layer for a dielectric layer containing a lanthanide oxide|
|US7772132 *||29 Jun 2006||10 Ago 2010||Hynix Semiconductor, Inc.||Method for forming tetragonal zirconium oxide layer and method for fabricating capacitor having the same|
|US7867919||8 Dic 2006||11 Ene 2011||Micron Technology, Inc.||Method of fabricating an apparatus having a lanthanum-metal oxide dielectric layer|
|US7869242||28 Abr 2009||11 Ene 2011||Micron Technology, Inc.||Transmission lines for CMOS integrated circuits|
|US7875912||23 May 2008||25 Ene 2011||Micron Technology, Inc.||Zrx Hfy Sn1-x-y O2 films as high k gate dielectrics|
|US7915174||22 Jul 2008||29 Mar 2011||Micron Technology, Inc.||Dielectric stack containing lanthanum and hafnium|
|US7923381||11 Jul 2008||12 Abr 2011||Micron Technology, Inc.||Methods of forming electronic devices containing Zr-Sn-Ti-O films|
|US7956168||25 May 2007||7 Jun 2011||Praxair Technology, Inc.||Organometallic compounds having sterically hindered amides|
|US8003985||17 Feb 2009||23 Ago 2011||Micron Technology, Inc.||Apparatus having a dielectric containing scandium and gadolinium|
|US8313994||8 Mar 2010||20 Nov 2012||Tokyo Electron Limited||Method for forming a high-K gate stack with reduced effective oxide thickness|
|US8581352||31 Ago 2009||12 Nov 2013||Micron Technology, Inc.||Electronic devices including barium strontium titanium oxide films|
|US8603907||19 Ago 2011||10 Dic 2013||Micron Technology, Inc.||Apparatus having a dielectric containing scandium and gadolinium|
|US8785312||28 Nov 2011||22 Jul 2014||Micron Technology, Inc.||Conductive layers for hafnium silicon oxynitride|
|US8933449||6 Dic 2013||13 Ene 2015||Micron Technology, Inc.||Apparatus having a dielectric containing scandium and gadolinium|
|US20050148127 *||15 Nov 2004||7 Jul 2005||Samsung Electronics Co., Ltd.||Semiconductor device including gate dielectric layer formed of high dielectric alloy and method of fabricating the same|
|WO2010111453A1 *||25 Mar 2010||30 Sep 2010||Tokyo Electron Limited||Method for forming a high-k gate stack with reduced effective oxide thickness|
|Clasificación de EE.UU.||438/785, 257/E21.647, 257/E21.654|
|Clasificación internacional||C23C16/40, H01L21/469, H01L21/31, C23C14/08, H01L21/28, H01L29/51, H01L21/314, H01L21/00, H01L21/8242|
|Clasificación cooperativa||H01L21/3142, C23C14/08, H01L27/10873, H01L21/28194, H01L29/513, H01L29/517, C23C16/405, H01L27/1085|
|Clasificación europea||H01L29/51M, C23C14/08, C23C16/40H, H01L21/314A2, H01L21/28E2C2D, H01L29/51B2|