US20050126920A1 - Method and apparatus for electrochemical processing - Google Patents

Method and apparatus for electrochemical processing Download PDF

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US20050126920A1
US20050126920A1 US10/953,888 US95388804A US2005126920A1 US 20050126920 A1 US20050126920 A1 US 20050126920A1 US 95388804 A US95388804 A US 95388804A US 2005126920 A1 US2005126920 A1 US 2005126920A1
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semi
electrolyte
conductive layer
article
conducting
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Oleg Sulima
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Heritage Power LLC
GE Energy USA LLC
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GE Energy USA LLC
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02241—III-V semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02258—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by anodic treatment, e.g. anodic oxidation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28264—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/3167—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself of anodic oxidation
    • H01L21/31679—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself of anodic oxidation of AIII BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
    • H01L31/1844—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising ternary or quaternary compounds, e.g. Ga Al As, In Ga As P
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868—Passivation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/544—Solar cells from Group III-V materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention is directed to a method of electrochemically processing a conducting element which is positioned on a semi-insulating element.
  • the present invention is directed to a method of electrochemically processing a conducting epitaxial layer (or layers) which have been grown on a semi-insulating substrate.
  • epitaxial layers on semi-insulating substrates has been used to provide series connection of semiconductor devices (e.g., in high-voltage, low-current solar cells and thermophotovoltaic cells). Electrochemical processing of such devices can significantly simplify their fabrication.
  • two methods of electrochemical processing which have been employed are: (i) holding the sample 10 (see FIG. 1 ), which includes a conducting epitaxial layer 11 and a semi-insulating substrate 12 , with a metal holder 13 contacting an electrolyte 14 and applying current through a circuit including an electrode 15 submerged in the electrolyte 14 , the electrolyte 14 , the conducting layer 11 and wires 16 and 17 , and (ii) a similar arrangement except for holding the sample with a metal holder which is not in contact with the electrolyte (see FIG. 2 ). Both of these methods have substantial drawbacks.
  • Method (i) leads to the uncertainty of the current density for the processed area because an unknown portion of current flows through the low-resistance metal holder.
  • the processed area is considerably limited to avoid contacting the holder with the electrolyte.
  • a factor which limits the area which can be processed is the electrolyte creeping along the processed surface toward the holder, a phenomenon which is especially strong for rough surfaces and long processes.
  • the present invention provides a more precise and more reproducible method of performing electrochemical processing on a conducting element positioned on a semi-insulating element.
  • a method of electrochemical processing comprising:
  • the article is a wafer, including a semi-insulating substrate having substantially flat front and back surfaces and a conducting epitaxial layer grown on the substrate and also having substantially flat front and back surfaces, whereby the gripper can be placed on the back surface of the wafer (i.e., the portion of the conductive layer adjacent to the back of the substrate) and only the front side of the wafer (i.e., the portion of the conductive layer adjacent to the front surface of the conducting epitaxial layer) contacts the electrolyte, such that the processed area or current density can be specified with high accuracy.
  • a particularly preferred method for forming a conductive layer on the outside of the article comprising a semi-insulating element and a conducting element is to perform a diffusion of a dopant suitable for the top epitaxial layer from a vapor phase. Using a vapor phase dopant, the dopant can penetrate the article from all sides, including the semi-insulating element.
  • the present invention is also directed to devices utilizing the anodic oxide layer thus grown, including electrical and optoelectrical devices such as transistors, capacitors, waveguides, light emitters, light detectors and lasers, e.g., as disclosed in U.S. Pat. Nos. 5,696,023, 5,567,980, 5,550,081 and 5,262,360 (the entireties of which are hereby incorporated herein by reference), as well as methods of making such devices including methods according to the present invention.
  • the present invention is directed to forming a III-V MOS device on a semi-insulating substrate using an anodic oxide, e.g., in forming a high-speed, high-power device (such as cell phones and radars).
  • the present invention relates to the masking and passivation of semiconductors utilizing the anodic oxide that forms from the practice of the present invention.
  • FIG. 1 is a schematic view depicting a first known method of electrochemically processing a sample having a conducting epitaxial layer on a semi-insulating substrate.
  • FIG. 2 is a schematic view depicting a second known method of electrochemically processing a sample having a conducting epitaxial layer on a semi-insulating substrate.
  • FIG. 3 is a schematic view depicting a method of electrochemically processing an article comprising a conducting element on a semi-insulating element.
  • the present invention is direct to a method of electrochemically processing an article comprising a conducting element positioned on a semi-insulating element.
  • the present invention can be used to perform any kind of electrochemical processing, a wide variety of which are well known to those of skill in the art.
  • the present invention can be used to perform electroplating.
  • the present invention can be used to perform anodic oxidation.
  • the present invention can be used to make galvanic contacts.
  • the present invention can be used to perform any other kind of electrochemical processing.
  • the present invention is applicable to electrochemically processing any article comprising any conducting element positioned on any semi-insulating element.
  • the present invention is therefore not limited to any particular kind of conducting element made of any particular material, or any particular kind of semi-insulating element made of any particular material.
  • skilled artisans would readily be able to apply the methods of the present invention to any such article.
  • Standard solar cells generate relatively high current but relatively low voltage (usually less than 1 volt), e.g., voltage which is not high enough to charge standard batteries (which typically require at least several volts).
  • a solar array consisting of several cells can be connected in series.
  • insulating semiconductor substrates can be used. Because trenches are provided between respective cells, the presence of a conductive layer in accordance with the present invention, which conductive layer electrically connects the opposite surfaces of each cell, does not present an electrical problem.
  • a first side of the conducting element is in contact with a second surface of the semi-insulating element.
  • the second surface and a first surface of the semi-insulating element are substantially flat, with the first surface being substantially parallel to the second surface.
  • the first side and a second side of the conducting element are substantially flat, with the first side being substantially parallel to the second side.
  • the method according to the present invention comprises forming a conductive layer on an outside of the article comprising a semi-insulating element and a conducting element.
  • the conductive layer comprises at least a first region and a second region, the first region covering at least a portion of the semi-insulating element, the second region covering at least a portion of the conducting element.
  • the conductive layer completely surrounds the article (i.e., is formed on all of the outer surfaces of the conductive layer). It is not necessary, however, for the conductive layer to completely surround the article, so long as the conductive layer has a least a first region covering at least a portion of the semi-insulating element and a second region covering at least a portion of the conducting element, and the first region and the second region are electrically connected to each other (e.g., the first region and the second region both being connected to a third region of the conductive layer).
  • Any suitable method for forming a conductive layer on the outside of the article can be employed.
  • a wide variety of techniques for forming a conductive layer on the outside of an article comprising a semi-insulating element and a conducting element are known to those of skill in the art, and any such technique can be employed.
  • a preferred method for forming the conductive layer on the outside of the article is to perform a diffusion of a dopant suitable for the top epitaxial layer from a vapor phase. Using a vapor phase dopant, the dopant can penetrate the article from all sides, including the semi-insulating element, such that the conductive layer completely surrounds the article.
  • a preferred dopant in such a method is zinc.
  • the present invention is not limited, however, to any particular method of forming the conductive layer, or any particular type of conductive layer.
  • a portion of the first region is gripped with at least one conductive gripper.
  • conductive grippers are known to those of skill in the art, and any such gripper can be employed in carrying out the present invention.
  • an example of a suitable gripper is metal vacuum tweezers.
  • At least a portion of the second region of the conductive layer (i.e., the portion which covers at least a portion of the conductive element) is submerged in an electrolyte while keeping the conductive gripper out of the electrolyte.
  • the article is submerged to a depth where the entire conducting element is beneath the level of the electrolyte and the entire semi-insulating element is above the level of the electrolyte.
  • Any suitable electrolyte can be employed, depending on the nature of the electrochemical processing being performed. Those of skill in the art can readily select an appropriate electrolyte based on the nature of the electrochemical processing being performed and the chemical nature of the other elements involved.
  • Electrode can be employed, and persons of skill in the art are readily able to select an appropriate electrode, based on the nature of the electrochemical processing being carried out and the materials of the other elements.
  • any suitable circuitry can be employed in order to provide the necessary current for performing the electrochemical processing being performed, and persons of skill can readily select appropriate circuitry.
  • the present invention is not limited to any particular electrolyte, circuitry or electrodes.
  • an article 30 (including a conducting epitaxial element 31 and a semi-insulating element 32 ), and a conductive layer 33 surrounding the article 30 on all sides.
  • the article 30 is held with a pair of metal vacuum tweezers 34 and is submerged in an electrolyte 35 , to a depth where the conducting epitaxial element 31 is beneath the level of the electrolyte 35 and the semi-insulating element 32 is above the level of the electrolyte 35 .
  • Current is applied through a circuit including an electrode 36 which is submerged in the electrolyte 35 , the electrolyte 35 , the conducting epitaxial element 31 , the conductive layer 33 and wires 37 and 38 .
  • a process for making a photovoltaic cell for use in a device comprising scintillating fibers and a solar cell array, in which the scintillating fibers are used to absorb short wavelength light and re-emit the light at a longer wavelength, and the solar cell array is used to absorb the re-emitted light and convert it into energy.
  • a gallium-arsenide semi-insulating layer (or any other semi-insulating layer, e.g., indium phosphide) is provided, and then an n-doped gallium arsenide layer is epitaxially formed on the semi-insulating layer (using any material which acts as an n-dopant, e.g., tin dopant), then a p-doped gallium arsenide layer is epitaxially formed on the n-doped layer (using any material which acts as a p-dopant, e.g., germanium dopant), and then an un-doped aluminum gallium arsenide layer is formed on the p-doped layer.
  • an n-doped gallium arsenide layer is epitaxially formed on the semi-insulating layer (using any material which acts as an n-dopant, e.g., tin dopant)
  • the n-doped layer, the p-doped layer and the un-doped layer are formed by liquid phase epitaxy, preferably in a single melt run.
  • the un-doped aluminum gallium arsenide layer has a composition at or near Al 0.8 Ga 0.2 As.
  • a low-temperature vapor phase zinc diffusion is carried out, e.g., in a pseudo-closed graphite cassette. This diffusion leads to the formation of a thin zinc-doped diffused layer on the outer surfaces of the entire wafer, including the semi-insulating substrate.
  • the zinc-doped aluminum gallium arsenide layer is anodically oxidized to form an anti-reflection coating.
  • This anodic oxidation is carried out in accordance with the present invention, with the gallium arsenide semi-insulating layer functioning as the semi-insulating element, the aluminum gallium arsenide layer functioning as the conducting element, and the zinc-doped diffused layer surrounding the entire wafer functioning as the conductive layer.
  • the aluminum gallium arsenide layer functions as a passivating layer.
  • Group III-V materials for the fabrication of semiconductor devices. While the utilization of silicon (Si) is still prevalent, Group III-v compounds—such as GaAs—have been the subject of much research due to significant advantages these compounds offer. For example, Group III-V compounds generally exhibit larger band gaps, larger electron mobilities and have the ability to produce light, which properties result in unique electrical and optical characteristics.
  • the oxide must be able to fulfill, without the disruption and strain caused by over-expansion of the oxide thickness, a variety of functions in a practical and consistent manner. Examples of these functions include: serving as a mask during device fabrication, providing surface passivation, isolating one device from another (dielectric isolation, as opposed to junction isolation), acting as a component in the anatomy of various device structures and providing electrical isolation of multilevel metallization systems. Accordingly, the presence of a high-quality, stable oxide layer having adequate physical properties and proper thickness, as provided by the present invention, is important to the successful development of Group III-V semiconductor technology.
  • Silicon-based materials unlike Group III-V semiconductors, readily form a high quality oxide (SiO 2 ) by such methods as reacting the silicon crystal with water vapor, e.g., in the form of steam. Indeed, the very existence of silicon-based integrated circuit technology is largely due and owing to this ability of silicon to form a high quality silicon oxide. Moreover, this oxide is a native oxide, as opposed to a deposited oxide layer. Native oxides, e.g., the anodic oxides formed according to the present invention, are more desirable than deposited oxides in that they are monolithic with the crystal and thus avoid potential mismatching of dielectric characteristics and problems associated with oxide-substrate interface bonding, such as lifting and cracking. Further, deposition processes are on the whole more complicated and costly than are methods of growing a native oxide thus making the latter more attractive for commercial use.

Abstract

A method of electrochemically processing an article having a semi-insulating element and a conducting element comprises forming a conductive layer on the article, the conductive layer comprising at least a first region covering at least a portion of the semi-insulating element and a second region covering at least a portion of the conducting element; gripping with at least one conductive gripper a portion of the first region; submerging at least a portion of the second region in an electrolyte while keeping the conductive gripper out of said electrolyte; and conducting current through a circuit comprising the conducting element, the conductive layer, the conductive gripper, and an electrode submerged in the electrolyte. The conductive layer is preferably formed by diffusing a dopant from a vapor phase.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a Continuation of International Application No. PCT/US03/09596 filed Mar. 28, 2003, the entirety of which is incorporated herein by reference. This application claims the benefit of U.S. Provisional Application 60/368,717, filed Mar. 29, 2002, and U.S. Provisional Application 60/368,543 filed Mar. 29, 2002, the entireties of which are incorporated herein by reference.
    • FIELD OF THE INVENTION
  • The present invention is directed to a method of electrochemically processing a conducting element which is positioned on a semi-insulating element. In preferred aspects, the present invention is directed to a method of electrochemically processing a conducting epitaxial layer (or layers) which have been grown on a semi-insulating substrate.
    • BACKGROUND OF THE INVENTION
  • There are a variety of devices known to those of skill in the art which require one or more structure including a conducting element positioned on a semi-insulating element, e.g., a conducting layer formed epitaxially on a semi-insulating substrate. In addition, there are a variety of situations known to those of skill in the art where it is necessary or desirable to electrochemically process such a conducting element positioned on a semi-insulating element.
  • For instance, growth of epitaxial layers on semi-insulating substrates has been used to provide series connection of semiconductor devices (e.g., in high-voltage, low-current solar cells and thermophotovoltaic cells). Electrochemical processing of such devices can significantly simplify their fabrication.
  • For samples having a conducting epitaxial layer on a semi-insulating substrate, two methods of electrochemical processing which have been employed are: (i) holding the sample 10 (see FIG. 1), which includes a conducting epitaxial layer 11 and a semi-insulating substrate 12, with a metal holder 13 contacting an electrolyte 14 and applying current through a circuit including an electrode 15 submerged in the electrolyte 14, the electrolyte 14, the conducting layer 11 and wires 16 and 17, and (ii) a similar arrangement except for holding the sample with a metal holder which is not in contact with the electrolyte (see FIG. 2). Both of these methods have substantial drawbacks. Method (i) leads to the uncertainty of the current density for the processed area because an unknown portion of current flows through the low-resistance metal holder. For method (ii), the processed area is considerably limited to avoid contacting the holder with the electrolyte. In method (ii), a factor which limits the area which can be processed is the electrolyte creeping along the processed surface toward the holder, a phenomenon which is especially strong for rough surfaces and long processes.
    • BRIEF SUMMARY OF THE INVENTION
  • The present invention provides a more precise and more reproducible method of performing electrochemical processing on a conducting element positioned on a semi-insulating element.
  • In accordance with the present invention, there is provided a method of electrochemical processing, comprising:
      • forming a conductive layer on the outside of an article comprising a semi-insulating element and a conducting element;
      • gripping the article with a conductive gripper at a region of the conductive layer which is adjacent to the semi-insulating element;
      • submerging the portion of the conductive layer which is in contact with the conducting element in an electrolyte while keeping the conductive gripper out of the electrolyte; and
      • conducting current through a circuit comprising the conducting element, the conductive layer, the conductive gripper, and an electrode submerged in the electrolyte.
  • Preferably, the article is a wafer, including a semi-insulating substrate having substantially flat front and back surfaces and a conducting epitaxial layer grown on the substrate and also having substantially flat front and back surfaces, whereby the gripper can be placed on the back surface of the wafer (i.e., the portion of the conductive layer adjacent to the back of the substrate) and only the front side of the wafer (i.e., the portion of the conductive layer adjacent to the front surface of the conducting epitaxial layer) contacts the electrolyte, such that the processed area or current density can be specified with high accuracy.
  • A particularly preferred method for forming a conductive layer on the outside of the article comprising a semi-insulating element and a conducting element is to perform a diffusion of a dopant suitable for the top epitaxial layer from a vapor phase. Using a vapor phase dopant, the dopant can penetrate the article from all sides, including the semi-insulating element.
  • The present invention is also directed to devices utilizing the anodic oxide layer thus grown, including electrical and optoelectrical devices such as transistors, capacitors, waveguides, light emitters, light detectors and lasers, e.g., as disclosed in U.S. Pat. Nos. 5,696,023, 5,567,980, 5,550,081 and 5,262,360 (the entireties of which are hereby incorporated herein by reference), as well as methods of making such devices including methods according to the present invention. For example, the present invention is directed to forming a III-V MOS device on a semi-insulating substrate using an anodic oxide, e.g., in forming a high-speed, high-power device (such as cell phones and radars).
  • In addition, the present invention relates to the masking and passivation of semiconductors utilizing the anodic oxide that forms from the practice of the present invention.
  • The invention may be more fully understood with reference to the accompanying drawings and the following detailed description of the invention.
    • BRIEF DESCRIPTION OF THE DRAWING FIGURES
  • FIG. 1 is a schematic view depicting a first known method of electrochemically processing a sample having a conducting epitaxial layer on a semi-insulating substrate.
  • FIG. 2 is a schematic view depicting a second known method of electrochemically processing a sample having a conducting epitaxial layer on a semi-insulating substrate.
  • FIG. 3 is a schematic view depicting a method of electrochemically processing an article comprising a conducting element on a semi-insulating element.
    • DETAILED DESCRIPTION OF THE INVENTION
  • As noted above, the present invention is direct to a method of electrochemically processing an article comprising a conducting element positioned on a semi-insulating element.
  • The present invention can be used to perform any kind of electrochemical processing, a wide variety of which are well known to those of skill in the art. For example, the present invention can be used to perform electroplating. Also, the present invention can be used to perform anodic oxidation. The present invention can be used to make galvanic contacts. Similarly, the present invention can be used to perform any other kind of electrochemical processing.
  • The present invention is applicable to electrochemically processing any article comprising any conducting element positioned on any semi-insulating element. The present invention is therefore not limited to any particular kind of conducting element made of any particular material, or any particular kind of semi-insulating element made of any particular material. Those of skill in the art will appreciate that skilled artisans would readily be able to apply the methods of the present invention to any such article.
  • Standard solar cells generate relatively high current but relatively low voltage (usually less than 1 volt), e.g., voltage which is not high enough to charge standard batteries (which typically require at least several volts). To increase voltage, a solar array consisting of several cells can be connected in series. For such series connection, insulating semiconductor substrates can be used. Because trenches are provided between respective cells, the presence of a conductive layer in accordance with the present invention, which conductive layer electrically connects the opposite surfaces of each cell, does not present an electrical problem.
  • A first side of the conducting element is in contact with a second surface of the semi-insulating element. Preferably, the second surface and a first surface of the semi-insulating element are substantially flat, with the first surface being substantially parallel to the second surface. Preferably, the first side and a second side of the conducting element are substantially flat, with the first side being substantially parallel to the second side.
  • As noted above, the method according to the present invention comprises forming a conductive layer on an outside of the article comprising a semi-insulating element and a conducting element.
  • The conductive layer comprises at least a first region and a second region, the first region covering at least a portion of the semi-insulating element, the second region covering at least a portion of the conducting element.
  • Preferably, the conductive layer completely surrounds the article (i.e., is formed on all of the outer surfaces of the conductive layer). It is not necessary, however, for the conductive layer to completely surround the article, so long as the conductive layer has a least a first region covering at least a portion of the semi-insulating element and a second region covering at least a portion of the conducting element, and the first region and the second region are electrically connected to each other (e.g., the first region and the second region both being connected to a third region of the conductive layer).
  • Any suitable method for forming a conductive layer on the outside of the article can be employed. A wide variety of techniques for forming a conductive layer on the outside of an article comprising a semi-insulating element and a conducting element are known to those of skill in the art, and any such technique can be employed.
  • As noted above, a preferred method for forming the conductive layer on the outside of the article is to perform a diffusion of a dopant suitable for the top epitaxial layer from a vapor phase. Using a vapor phase dopant, the dopant can penetrate the article from all sides, including the semi-insulating element, such that the conductive layer completely surrounds the article. A preferred dopant in such a method is zinc. The present invention is not limited, however, to any particular method of forming the conductive layer, or any particular type of conductive layer.
  • Next, a portion of the first region is gripped with at least one conductive gripper. A variety of conductive grippers are known to those of skill in the art, and any such gripper can be employed in carrying out the present invention. For example, an example of a suitable gripper is metal vacuum tweezers.
  • At least a portion of the second region of the conductive layer (i.e., the portion which covers at least a portion of the conductive element) is submerged in an electrolyte while keeping the conductive gripper out of the electrolyte.
  • Preferably, the article is submerged to a depth where the entire conducting element is beneath the level of the electrolyte and the entire semi-insulating element is above the level of the electrolyte.
  • Any suitable electrolyte can be employed, depending on the nature of the electrochemical processing being performed. Those of skill in the art can readily select an appropriate electrolyte based on the nature of the electrochemical processing being performed and the chemical nature of the other elements involved.
  • Current is then conducted through a circuit comprising the conductive layer, the conductive gripper, and an electrode submerged in the electrolyte. Any suitable electrode can be employed, and persons of skill in the art are readily able to select an appropriate electrode, based on the nature of the electrochemical processing being carried out and the materials of the other elements. Likewise, any suitable circuitry can be employed in order to provide the necessary current for performing the electrochemical processing being performed, and persons of skill can readily select appropriate circuitry. The present invention is not limited to any particular electrolyte, circuitry or electrodes.
  • Referring to FIG. 3, there is shown an article 30 (including a conducting epitaxial element 31 and a semi-insulating element 32), and a conductive layer 33 surrounding the article 30 on all sides. The article 30 is held with a pair of metal vacuum tweezers 34 and is submerged in an electrolyte 35, to a depth where the conducting epitaxial element 31 is beneath the level of the electrolyte 35 and the semi-insulating element 32 is above the level of the electrolyte 35. Current is applied through a circuit including an electrode 36 which is submerged in the electrolyte 35, the electrolyte 35, the conducting epitaxial element 31, the conductive layer 33 and wires 37 and 38.
  • For example, in a specific embodiment of the present invention, there is provided a process for making a photovoltaic cell for use in a device comprising scintillating fibers and a solar cell array, in which the scintillating fibers are used to absorb short wavelength light and re-emit the light at a longer wavelength, and the solar cell array is used to absorb the re-emitted light and convert it into energy.
  • According to this process, a gallium-arsenide semi-insulating layer (or any other semi-insulating layer, e.g., indium phosphide) is provided, and then an n-doped gallium arsenide layer is epitaxially formed on the semi-insulating layer (using any material which acts as an n-dopant, e.g., tin dopant), then a p-doped gallium arsenide layer is epitaxially formed on the n-doped layer (using any material which acts as a p-dopant, e.g., germanium dopant), and then an un-doped aluminum gallium arsenide layer is formed on the p-doped layer. Preferably, the n-doped layer, the p-doped layer and the un-doped layer are formed by liquid phase epitaxy, preferably in a single melt run. Preferably, the un-doped aluminum gallium arsenide layer has a composition at or near Al0.8Ga0.2As. Next, a low-temperature vapor phase zinc diffusion is carried out, e.g., in a pseudo-closed graphite cassette. This diffusion leads to the formation of a thin zinc-doped diffused layer on the outer surfaces of the entire wafer, including the semi-insulating substrate.
  • Then the zinc-doped aluminum gallium arsenide layer is anodically oxidized to form an anti-reflection coating. This anodic oxidation is carried out in accordance with the present invention, with the gallium arsenide semi-insulating layer functioning as the semi-insulating element, the aluminum gallium arsenide layer functioning as the conducting element, and the zinc-doped diffused layer surrounding the entire wafer functioning as the conductive layer. In the resulting product, the aluminum gallium arsenide layer functions as a passivating layer.
  • In another aspect of the present invention, an important trend in semiconductor technology is the use of Group III-V materials for the fabrication of semiconductor devices. While the utilization of silicon (Si) is still prevalent, Group III-v compounds—such as GaAs—have been the subject of much research due to significant advantages these compounds offer. For example, Group III-V compounds generally exhibit larger band gaps, larger electron mobilities and have the ability to produce light, which properties result in unique electrical and optical characteristics.
  • Notwithstanding these qualities, there has been difficulty in producing, on the Group III-v semiconductor, an oxide layer of desired thickness that exhibits the necessary surface state and electrical properties required for practical application. In this regard, the oxide must be able to fulfill, without the disruption and strain caused by over-expansion of the oxide thickness, a variety of functions in a practical and consistent manner. Examples of these functions include: serving as a mask during device fabrication, providing surface passivation, isolating one device from another (dielectric isolation, as opposed to junction isolation), acting as a component in the anatomy of various device structures and providing electrical isolation of multilevel metallization systems. Accordingly, the presence of a high-quality, stable oxide layer having adequate physical properties and proper thickness, as provided by the present invention, is important to the successful development of Group III-V semiconductor technology.
  • Silicon-based materials, unlike Group III-V semiconductors, readily form a high quality oxide (SiO2) by such methods as reacting the silicon crystal with water vapor, e.g., in the form of steam. Indeed, the very existence of silicon-based integrated circuit technology is largely due and owing to this ability of silicon to form a high quality silicon oxide. Moreover, this oxide is a native oxide, as opposed to a deposited oxide layer. Native oxides, e.g., the anodic oxides formed according to the present invention, are more desirable than deposited oxides in that they are monolithic with the crystal and thus avoid potential mismatching of dielectric characteristics and problems associated with oxide-substrate interface bonding, such as lifting and cracking. Further, deposition processes are on the whole more complicated and costly than are methods of growing a native oxide thus making the latter more attractive for commercial use.

Claims (5)

1. A method of electrochemically processing an article comprising a conducting element positioned on a semi-insulating element, the method comprising:
forming a conductive layer on an article, said article comprising a semi-insulating element and a conducting element, said conductive layer comprising at least a first region and a second region, said first region covering at least a portion of said semi-insulating element, said second region covering at least a portion of said conducting element;
gripping with at least one conductive gripper a portion of said first region;
submerging at least a portion of said second region in an electrolyte while keeping said conductive gripper out of said electrolyte; and
conducting current through a circuit comprising said conducting element, said conductive layer, said conductive gripper, and an electrode submerged in said electrolyte.
2. A method as recited in claim 1, wherein said semi-insulating element has a substantially flat first surface and a substantially flat second surface, said first surface of said semi-insulating element being substantially parallel to said second surface of said semi-insulating element, and said conducting element is substantially flat and has a substantially flat first side and a substantially flat second side, said first side of said conducting element being substantially parallel to said second side of said conducting element, said first side of said conducting element being in contact with said second surface of said semi-insulating element.
3. A method as recited in claim 1, wherein said conductive layer completely surrounds said article.
4. A method as recited in claim 1, wherein said conductive layer is formed by diffusing a dopant from a vapor phase.
5. A method as recited in claim 1, wherein said article is submerged in said electrolyte to a depth where substantially an entirety of said conducting element is beneath a top surface of said electrolyte and substantially an entirety of said semi-insulating element is above said top surface of said electrolyte.
US10/953,888 2002-03-29 2004-09-29 Method and apparatus for electrochemical processing Abandoned US20050126920A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110241185A1 (en) * 2010-04-05 2011-10-06 International Business Machines Corporation Signal shielding through-substrate vias for 3d integration

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5262360A (en) * 1990-12-31 1993-11-16 The Board Of Trustees Of The University Of Illinois AlGaAs native oxide
US5550081A (en) * 1994-04-08 1996-08-27 Board Of Trustees Of The University Of Illinois Method of fabricating a semiconductor device by oxidizing aluminum-bearing 1H-V semiconductor in water vapor environment
US5739067A (en) * 1995-12-07 1998-04-14 Advanced Micro Devices, Inc. Method for forming active devices on and in exposed surfaces of both sides of a silicon wafer
US6071400A (en) * 1996-03-29 2000-06-06 Atotech Deutschland Gmbh Method and device for the electrochemical treatment with treatment liquid of an item to be treated
US6168691B1 (en) * 1996-08-09 2001-01-02 Atotech Deutschland Gmbh Device for electrochemical treatment of elongate articles
US6508826B2 (en) * 2001-04-30 2003-01-21 Embol-X, Inc. Cannula with flow diversion mechanism and methods of use

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19837973C1 (en) * 1998-08-21 2000-01-20 Atotech Deutschland Gmbh Apparatus for electrochemical treatment of parts of bar-shaped workpieces in immersion bath installations

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5262360A (en) * 1990-12-31 1993-11-16 The Board Of Trustees Of The University Of Illinois AlGaAs native oxide
US5696023A (en) * 1990-12-31 1997-12-09 The Board Of Trustees Of The University Of Illinois Method for making aluminum gallium arsenide semiconductor device with native oxide layer
US5550081A (en) * 1994-04-08 1996-08-27 Board Of Trustees Of The University Of Illinois Method of fabricating a semiconductor device by oxidizing aluminum-bearing 1H-V semiconductor in water vapor environment
US5739067A (en) * 1995-12-07 1998-04-14 Advanced Micro Devices, Inc. Method for forming active devices on and in exposed surfaces of both sides of a silicon wafer
US6071400A (en) * 1996-03-29 2000-06-06 Atotech Deutschland Gmbh Method and device for the electrochemical treatment with treatment liquid of an item to be treated
US6168691B1 (en) * 1996-08-09 2001-01-02 Atotech Deutschland Gmbh Device for electrochemical treatment of elongate articles
US6508826B2 (en) * 2001-04-30 2003-01-21 Embol-X, Inc. Cannula with flow diversion mechanism and methods of use

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110241185A1 (en) * 2010-04-05 2011-10-06 International Business Machines Corporation Signal shielding through-substrate vias for 3d integration

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