US20050145979A1 - Semiconductor devices and methods to form trenches in semiconductor devices - Google Patents
Semiconductor devices and methods to form trenches in semiconductor devices Download PDFInfo
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- US20050145979A1 US20050145979A1 US10/969,552 US96955204A US2005145979A1 US 20050145979 A1 US20050145979 A1 US 20050145979A1 US 96955204 A US96955204 A US 96955204A US 2005145979 A1 US2005145979 A1 US 2005145979A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 238000000034 method Methods 0.000 title claims abstract description 55
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 49
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000009413 insulation Methods 0.000 claims abstract description 9
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 239000010408 film Substances 0.000 description 96
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 239000011800 void material Substances 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000013459 approach Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000012774 insulation material Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Definitions
- the present disclosure relates to semiconductors and, more particularly, to semiconductor devices and methods to form trenches in semiconductor devices.
- Shallow trench isolation (STI) structures have been widely used to isolate areas within semiconductor devices. These STI structures are advantageous to miniaturization of semiconductor devices because a size of a field region is limited to a desired size of a trench by forming trenches in a semiconductor substrate and filling the trenches with insulation material.
- FIGS. 1 a to 1 d are sectional views showing the conventional STI manufacture method.
- a pad oxide film 2 is deposited at a thickness of about 200 ⁇ on an entire surface of a silicon substrate 1 .
- a silicon nitride film 3 is deposited at a thickness of about 2000 ⁇ on the pad oxide film 2 and a photosensitive film is applied and exposed on the silicon nitride film 3 .
- a pattern of photosensitive film 4 is then formed by removing only the photosensitive film on a region that is to include a trench.
- a trench 100 is formed in the silicon substrate I by dry etching the exposed silicon nitride film 3 , the pad oxide film 2 , and the silicon substrate 1 up to a predetermined depth using the pattern of photosensitive film 4 as a mask.
- the pattern of photosensitive film 4 is removed and then a cleaning process is performed.
- an edge at which a side and a bottom of the formed trench intersect forms a nearly right angle. It is almost impossible to decrease this angle so that the edge is gently slanted.
- a liner oxide film 5 is formed at an inner wall of the trench 100 using a thermal oxidation process.
- the liner oxide film 5 is formed at about 60% of its total thickness inside the silicon substrate 1 and at about 40% of the total thickness outside the silicon substrate 1 by a typical thermal oxidation process.
- the liner oxide file 5 is centered at a surface (shown as a dotted line in FIG. 1 c ) of the silicon substrate 1 of the trench.
- a field oxide 6 is thickly deposited on an entire surface of the silicon nitride film 3 including the liner oxide film 5 such that the trench 100 is sufficiently buried or filled.
- the field oxide 6 is consecutively deposited at the same speed on the silicon nitride film 3 or in the interior of the trench 100 on the liner oxide film 5 with a surface state as shown as a dotted line in FIG. 1 d .
- the field oxide 6 may create a shape that is difficult to fill. Accordingly, a void 200 in the field oxide 6 may be created in the interior of the trench 100 . If this void 200 is excessively large, the void 200 will be exposed when a chemical mechanical polishing is performed to planarize the filed oxide 6 . The exposing of the void 200 results in difficulties during the planarization process.
- Korean Patent No. 36355 discloses a technique by which a composite film structure of an anti-diffusion insulation film and a thermal oxide film is provided between a nitride film liner and a trench in order to minimize a transistor characteristic deterioration due to the nitride film liner.
- this approach has a disadvantage in that a manufacturing process for forming the composite film structure is complicated.
- Korean Patent Application No. 2003-1409 discloses techniques by which a first liner oxide film formed in an inner wall of a trench is etched away by a wet etching method, a second liner oxide film is thermally grown such that a top surface of the second liner oxide film has a smoothly curved edge, and then a filed oxide is formed on the top surface of the second liner oxide film such that the trench is completely filled without any void.
- this technique requires a process of wet etching the liner oxide film and two deposition processes, this second prior approach also has a disadvantage of a complicated manufacturing process.
- FIGS. 1 a to 1 d are sectional views showing the results of a method of forming a trench in a conventional semiconductor device.
- FIGS. 2 a to 2 f are sectional views showing results of a disclosed example method of forming a trench in a semiconductor device.
- a pad oxide film 12 is thinly deposited on an entire surface of a silicon substrate 12 , and a silicon nitride film 13 is deposited on the pad oxide film 12 .
- a photosensitive film 14 is then applied and exposed on the silicon nitride film 13 , and then a pattern of photosensitive film 14 is formed by removing only the photosensitive film on a region to be formed with a trench.
- the pad oxide film 12 is optionally deposited to prevent a stress of the silicon nitride film 13 from being transferred to the semiconductor substrate 11 .
- the pad oxide film 12 is deposited thinly at a thickness of between about 100-300 ⁇ , for example, 200 ⁇ .
- the silicon nitride film 13 is made of material having a high selectivity over the pad oxide film, it functions as a buffer layer in a subsequent chemical mechanical polishing process for the field oxide.
- the silicon nitride film 13 is deposited at a thickness of 1000-3000 ⁇ , for example, 2000 ⁇ .
- a trench 100 is formed in the semiconductor substrate 11 by dry etching the exposed silicon nitride film 13 , the pad oxide film 12 , and the semiconductor substrate 11 to a predetermined depth using the pattern of photosensitive film 14 as a mask. Subsequently, the pattern of photosensitive film 14 is removed and a cleaning process is performed.
- the dry etching may be performed in two steps. In more detail, after the silicon nitride 13 is first etched away, the semiconductor substrate 11 is etched away up to a predetermined depth with etching process conditions different from those of the silicon nitride film 13 . When etching of the silicon nitride film 13 and etching of the semiconductor substrate 11 are consecutively performed with different process conditions, as described above, etching process time can be shortened.
- the trench 100 formed by the etching process has an angled edge at which a side and a bottom of the trench intersect. It is almost impossible to form this edge into a gently slanted shape.
- a liner oxide film 15 is formed at an inner wall of the trench 100 using a thermal oxidation process.
- the liner oxide film 15 is formed at about 60% of its total thickness inside the silicon substrate 11 and at about 40% of the total thickness outside the silicon substrate 11 by a typical thermal diffusion process, centering at a surface (shown as a dotted line in FIG. 2 c ) of the semiconductor substrate 11 of the trench.
- the liner oxide film 15 may be deposited at a thickness of 100-500 ⁇ , for example, 300 ⁇ .
- a negative ( ⁇ ) voltage of ⁇ 2000V to ⁇ 1000V is applied to a back surface of the semiconductor substrate 11 .
- An electrostatic chuck (ESC) 20 can be used for this voltage application, however it is not limited thereto.
- the negative voltage may be directly applied using any electrode.
- electrons can be injected into the back surface of the semiconductor substrate 11 using an electron gun 20 .
- a voltage of ⁇ 2000V to ⁇ 1000V is applied to the back surface of the semiconductor substrate 11 .
- ⁇ means a dielectric constant.
- Dielectric constants of the liner oxide film 15 and the silicon nitride film 13 are 4.3 and 7.2, respectively.
- a thickness of the liner oxide film 15 is about 300 ⁇ and a thickness of the silicon nitride film 13 is about 2000 ⁇ . Accordingly, charges stored in the relatively thin liner oxide film 15 are even more than those stored in the relatively thick silicon nitride film 13 .
- a field oxide 16 is thickly deposited on an entire surface of the liner oxide film 15 and the silicon nitride film 13 such that the trench is sufficiently filled.
- the field oxide 16 is formed by an atmospheric pressure chemical vapor deposition (APCVD) method or a sub-atmospheric chemical vapor deposition (SACVD) method.
- APCVD atmospheric pressure chemical vapor deposition
- SACVD sub-atmospheric chemical vapor deposition
- the field oxide 16 is still lively deposited on the liner oxide film 15 .
- a speed of deposition of the field oxide 16 in the trench 100 is higher than that on the silicon nitride film 13 .
- the trench 100 can be completely filled with the field oxide 16 without any void.
- the trench isolation process may be completed by chemical mechanical polishing and planarizing the field oxide 16 until the silicon nitride film 13 is exposed.
- the deterioration of the reliability of device due to a leakage current or circuit short by voids can be prevented and the device yield can be improved.
- example semiconductor device manufacturing methods fill a trench formed as a field region to isolate one active region from another in a semiconductor device with insulation material without any void.
- an example trench formation method is characterized in that electrons are scanned to a back surface of a semiconductor substrate by an electron gun and a trench is filled with an insulation film under a state where positive charges are more stored in a relatively thin liner oxide film and are less stored in a relatively thick silicon nitride film.
- One example method includes forming a silicon nitride film on an entire surface of a semiconductor substrate, forming the trench by etching the silicon nitride film and the semiconductor substrate up to a predetermined depth, forming a liner oxide film with a thickness thinner than that of the silicon nitride film on an inner wall of the trench, applying a negative voltage to a back surface of the semiconductor substrate, and forming an insulation film to fill the trench on the liner oxide film.
- the silicon nitride film is formed at a thickness of 1000-3000 ⁇
- the liner oxide film is formed at a thickness of 100-500 ⁇ by a thermal oxidation process.
- the application of the negative voltage includes applying a voltage of ⁇ 2000V to ⁇ 1000V to the back surface of the semiconductor substrate. The voltage application may be accomplished by applying the negative voltage to the back surface of the semiconductor substrate using an electrostatic chuck (ESC) or by injecting electrons into the back surface of the semiconductor substrate using an electron gun.
- ESC electrostatic chuck
- forming the insulation film may include forming a filling oxide film to fill the trench on an entire surface of the silicon nitride film and then chemical mechanical polishing the oxide film until the silicon nitride film is exposed.
- the filling oxide film is formed at a thickness of 6000-12000 ⁇ using an atmospheric pressure chemical vapor deposition (APCVD) method or a subatmospheric chemical vapor deposition (SACVD) method.
- APCVD atmospheric pressure chemical vapor deposition
- SACVD subatmospheric chemical vapor deposition
- a pad oxide film may be formed at a thickness of 100-300 ⁇ on the entire surface of the semiconductor substrate.
Abstract
Description
- The present disclosure relates to semiconductors and, more particularly, to semiconductor devices and methods to form trenches in semiconductor devices.
- Shallow trench isolation (STI) structures have been widely used to isolate areas within semiconductor devices. These STI structures are advantageous to miniaturization of semiconductor devices because a size of a field region is limited to a desired size of a trench by forming trenches in a semiconductor substrate and filling the trenches with insulation material.
- Hereinafter, a conventional method of manufacturing the STI structure will be in brief described.
FIGS. 1 a to 1 d are sectional views showing the conventional STI manufacture method. - First, as shown in
FIG. 1 a, apad oxide film 2 is deposited at a thickness of about 200 Å on an entire surface of asilicon substrate 1. Subsequently, asilicon nitride film 3 is deposited at a thickness of about 2000 Å on thepad oxide film 2 and a photosensitive film is applied and exposed on thesilicon nitride film 3. A pattern ofphotosensitive film 4 is then formed by removing only the photosensitive film on a region that is to include a trench. - Next, as shown in
FIG. 1 b, atrench 100 is formed in the silicon substrate I by dry etching the exposedsilicon nitride film 3, thepad oxide film 2, and thesilicon substrate 1 up to a predetermined depth using the pattern ofphotosensitive film 4 as a mask. The pattern ofphotosensitive film 4 is removed and then a cleaning process is performed. - As shown, an edge at which a side and a bottom of the formed trench intersect forms a nearly right angle. It is almost impossible to decrease this angle so that the edge is gently slanted.
- Next, as shown in
FIG. 1 c, aliner oxide film 5 is formed at an inner wall of thetrench 100 using a thermal oxidation process. According to one example, theliner oxide film 5 is formed at about 60% of its total thickness inside thesilicon substrate 1 and at about 40% of the total thickness outside thesilicon substrate 1 by a typical thermal oxidation process. Theliner oxide file 5 is centered at a surface (shown as a dotted line inFIG. 1 c) of thesilicon substrate 1 of the trench. - During the thermal oxidation process for the formation of the
liner oxide film 5, as an angle of an edge at which a side and a bottom of thetrench 100 intersect becomes smaller, it becomes difficult for oxygen molecules to penetrate into the silicon substrate. For example, a nearly vertical trench edge creates a state in which oxygen molecules do not easily penetrate into the silicon substrate. - At this time, because most of deposition processes are performed using only heat in a high temperature without any electric power, the entire surface of the
silicone substrate 1 assumes electrical neutrality. Under this state, as shown inFIG. 1 d, a field oxide 6 is thickly deposited on an entire surface of thesilicon nitride film 3 including theliner oxide film 5 such that thetrench 100 is sufficiently buried or filled. - The field oxide 6 is consecutively deposited at the same speed on the
silicon nitride film 3 or in the interior of thetrench 100 on theliner oxide film 5 with a surface state as shown as a dotted line inFIG. 1 d. During the deposition process, the field oxide 6 may create a shape that is difficult to fill. Accordingly, avoid 200 in the field oxide 6 may be created in the interior of thetrench 100. If thisvoid 200 is excessively large, thevoid 200 will be exposed when a chemical mechanical polishing is performed to planarize the filed oxide 6. The exposing of thevoid 200 results in difficulties during the planarization process. - In addition, in a state where the void is exposed after the planarization, when a polysilicon to be deposited for formation of an electrode in a subsequent process enters the void, a leakage current may result, thereby causing erroneous operation of a device and a circuit-short between adjacent devices. These effects are fatal to the operation of the device.
- The above problems become more serious as a width of the trench becomes narrower.
- One prior approach to filling the trench without any void is disclosed in Korean Patent No. 36355, which discloses a technique by which a composite film structure of an anti-diffusion insulation film and a thermal oxide film is provided between a nitride film liner and a trench in order to minimize a transistor characteristic deterioration due to the nitride film liner. However, this approach has a disadvantage in that a manufacturing process for forming the composite film structure is complicated.
- Another approach is disclosed in Korean Patent Application No. 2003-1409, which discloses techniques by which a first liner oxide film formed in an inner wall of a trench is etched away by a wet etching method, a second liner oxide film is thermally grown such that a top surface of the second liner oxide film has a smoothly curved edge, and then a filed oxide is formed on the top surface of the second liner oxide film such that the trench is completely filled without any void. However, because this technique requires a process of wet etching the liner oxide film and two deposition processes, this second prior approach also has a disadvantage of a complicated manufacturing process.
- Still other prior approaches are disclosed in U.S. Pat. Nos. 6,521,413 and 6,214,698, which disclose techniques by which an undoped thin film is used for preventing voids, or a gap fill is achieved by two processes. However, since these techniques require a modification of process conditions, it also has a disadvantage of a complicated manufacturing process.
-
FIGS. 1 a to 1 d are sectional views showing the results of a method of forming a trench in a conventional semiconductor device. -
FIGS. 2 a to 2 f are sectional views showing results of a disclosed example method of forming a trench in a semiconductor device. - First, as shown in
FIG. 2 a, apad oxide film 12 is thinly deposited on an entire surface of asilicon substrate 12, and asilicon nitride film 13 is deposited on thepad oxide film 12. Aphotosensitive film 14 is then applied and exposed on thesilicon nitride film 13, and then a pattern ofphotosensitive film 14 is formed by removing only the photosensitive film on a region to be formed with a trench. - At this time, the
pad oxide film 12 is optionally deposited to prevent a stress of thesilicon nitride film 13 from being transferred to thesemiconductor substrate 11. In one example, thepad oxide film 12 is deposited thinly at a thickness of between about 100-300 Å, for example, 200 Å. - Because the
silicon nitride film 13 is made of material having a high selectivity over the pad oxide film, it functions as a buffer layer in a subsequent chemical mechanical polishing process for the field oxide. In one example, thesilicon nitride film 13 is deposited at a thickness of 1000-3000 Å, for example, 2000 Å. - Next, as shown in
FIG. 2 b, atrench 100 is formed in thesemiconductor substrate 11 by dry etching the exposedsilicon nitride film 13, thepad oxide film 12, and thesemiconductor substrate 11 to a predetermined depth using the pattern ofphotosensitive film 14 as a mask. Subsequently, the pattern ofphotosensitive film 14 is removed and a cleaning process is performed. - At this time, because an etching rate of the
silicon nitride film 13 is different from an etching rate of thesemiconductor substrate 11, process conditions for a dry etching of thesilicon nitride film 13 are different from those for a dry etching of thesemiconductor substrate 11. Accordingly, the dry etching may be performed in two steps. In more detail, after thesilicon nitride 13 is first etched away, thesemiconductor substrate 11 is etched away up to a predetermined depth with etching process conditions different from those of thesilicon nitride film 13. When etching of thesilicon nitride film 13 and etching of thesemiconductor substrate 11 are consecutively performed with different process conditions, as described above, etching process time can be shortened. - The
trench 100 formed by the etching process has an angled edge at which a side and a bottom of the trench intersect. It is almost impossible to form this edge into a gently slanted shape. - Next, as shown in
FIG. 2 c, aliner oxide film 15 is formed at an inner wall of thetrench 100 using a thermal oxidation process. In one example, theliner oxide film 15 is formed at about 60% of its total thickness inside thesilicon substrate 11 and at about 40% of the total thickness outside thesilicon substrate 11 by a typical thermal diffusion process, centering at a surface (shown as a dotted line inFIG. 2 c) of thesemiconductor substrate 11 of the trench. Theliner oxide film 15 may be deposited at a thickness of 100-500 Å, for example, 300 Å. - Next, as shown in
FIG. 2 d, a negative (−) voltage of −2000V to −1000V is applied to a back surface of thesemiconductor substrate 11. An electrostatic chuck (ESC) 20 can be used for this voltage application, however it is not limited thereto. For example, the negative voltage may be directly applied using any electrode. As another method of applying the negative voltage, as shown inFIG. 2 e, electrons can be injected into the back surface of thesemiconductor substrate 11 using anelectron gun 20. According to one example, for the electron injection, a voltage of −2000V to −1000V is applied to the back surface of thesemiconductor substrate 11. - When the negative voltage is applied to the back surface of the semiconductor substrate, as described above, positive (+) charges are stored in the front surface of the
semiconductor substrate 11. At this time, the positive charges stored in theliner oxide film 15 are more than those stored in thesilicon nitride film 13, which is thicker than theliner oxide film 15. - This can be seen from the following
mathematical expression 1 showing that an electrostatic capacity C is proportional to an area A of a dielectric and is inversely proportional to a thickness d of the dielectric.
C=(A/d)×ε (1) - Where, ε means a dielectric constant. Dielectric constants of the
liner oxide film 15 and thesilicon nitride film 13 are 4.3 and 7.2, respectively. A thickness of theliner oxide film 15 is about 300 Å and a thickness of thesilicon nitride film 13 is about 2000 Å. Accordingly, charges stored in the relatively thinliner oxide film 15 are even more than those stored in the relatively thicksilicon nitride film 13. - Next, as shown in
FIG. 2 f, afield oxide 16 is thickly deposited on an entire surface of theliner oxide film 15 and thesilicon nitride film 13 such that the trench is sufficiently filled. Thefield oxide 16 is formed by an atmospheric pressure chemical vapor deposition (APCVD) method or a sub-atmospheric chemical vapor deposition (SACVD) method. In this course, reactive gas particles for deposition assume negative (−) charges through decomposition and generation steps, and are electrically and chemically combined to the substrate assuming positive (+) charges, resulting in the deposition of thefield oxide 16. - Because positive (+) charges stored in the
liner oxide film 15 are even more than those stored in thesilicon nitride film 13, thefield oxide 16 is still lively deposited on theliner oxide film 15. In other words, a speed of deposition of thefield oxide 16 in thetrench 100 is higher than that on thesilicon nitride film 13. As a result, thetrench 100 can be completely filled with thefield oxide 16 without any void. - Finally, the trench isolation process may be completed by chemical mechanical polishing and planarizing the
field oxide 16 until thesilicon nitride film 13 is exposed. - As described above, by injecting electrons into the back surface of the semiconductor substrate using an electron gun, positive charges are stored in the liner oxide film and the silicon nitride film located on the front surface of the semiconductor substrate such that positive charges are more stored in the liner oxide film and are less stored in the silicon nitride film thicker than the liner oxide film. Under this state, because the field oxide for filling the trench is deposited on the entire surface the liner oxide film and the silicon nitride film, the speed of deposition of the field oxide in the trench is higher than that on the silicon nitride film. Accordingly, the trench can be completely filled with the filled oxide without any void.
- Accordingly, the deterioration of the reliability of device due to a leakage current or circuit short by voids can be prevented and the device yield can be improved.
- As disclosed herein, example semiconductor device manufacturing methods fill a trench formed as a field region to isolate one active region from another in a semiconductor device with insulation material without any void. In particular, an example trench formation method is characterized in that electrons are scanned to a back surface of a semiconductor substrate by an electron gun and a trench is filled with an insulation film under a state where positive charges are more stored in a relatively thin liner oxide film and are less stored in a relatively thick silicon nitride film.
- One example method includes forming a silicon nitride film on an entire surface of a semiconductor substrate, forming the trench by etching the silicon nitride film and the semiconductor substrate up to a predetermined depth, forming a liner oxide film with a thickness thinner than that of the silicon nitride film on an inner wall of the trench, applying a negative voltage to a back surface of the semiconductor substrate, and forming an insulation film to fill the trench on the liner oxide film.
- In one example, the silicon nitride film is formed at a thickness of 1000-3000 Å, and the liner oxide film is formed at a thickness of 100-500 Å by a thermal oxidation process. By way of further example, the application of the negative voltage includes applying a voltage of −2000V to −1000V to the back surface of the semiconductor substrate. The voltage application may be accomplished by applying the negative voltage to the back surface of the semiconductor substrate using an electrostatic chuck (ESC) or by injecting electrons into the back surface of the semiconductor substrate using an electron gun.
- In one example, forming the insulation film may include forming a filling oxide film to fill the trench on an entire surface of the silicon nitride film and then chemical mechanical polishing the oxide film until the silicon nitride film is exposed. According to one example, the filling oxide film is formed at a thickness of 6000-12000 Å using an atmospheric pressure chemical vapor deposition (APCVD) method or a subatmospheric chemical vapor deposition (SACVD) method.
- By way of example, prior to the step of forming the silicon nitride film, a pad oxide film may be formed at a thickness of 100-300 Å on the entire surface of the semiconductor substrate.
- Although certain example methods and semiconductor devices are disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers every apparatus, method and article of manufacture fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.
Claims (13)
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KR10-2003-0036001A KR100478500B1 (en) | 2003-06-04 | 2003-06-04 | Semiconductor device and formation method of trench in the semiconductor device |
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KR10-2003-0036002A KR100478501B1 (en) | 2003-06-04 | 2003-06-04 | Semiconductor device and formation method of trench in the semiconductor device |
KR10-2003-0036002 | 2003-06-04 | ||
US10/746,089 US7354834B2 (en) | 2003-06-04 | 2003-12-26 | Semiconductor devices and methods to form trenches in semiconductor devices |
US10/969,552 US20050145979A1 (en) | 2003-06-04 | 2004-10-20 | Semiconductor devices and methods to form trenches in semiconductor devices |
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CN102437082A (en) * | 2011-08-15 | 2012-05-02 | 上海华力微电子有限公司 | Method for improving filling performance in ultra-high depth-to-width ratio shallow trench isolation (STI) process |
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US7645677B2 (en) * | 2004-03-16 | 2010-01-12 | Ishikawajima-Harima Heavy Industries Co., Ltd. | Method for manufacturing semiconductor device |
KR100606954B1 (en) * | 2004-07-08 | 2006-08-01 | 동부일렉트로닉스 주식회사 | Method for fabricating a photodiode in a CMOS image sensor |
US7666735B1 (en) * | 2005-02-10 | 2010-02-23 | Advanced Micro Devices, Inc. | Method for forming semiconductor devices with active silicon height variation |
US7709345B2 (en) | 2006-03-07 | 2010-05-04 | Micron Technology, Inc. | Trench isolation implantation |
CN104701235B (en) * | 2013-12-04 | 2019-01-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of forming method of shallow trench |
KR102246280B1 (en) * | 2014-03-26 | 2021-04-29 | 에스케이하이닉스 주식회사 | Semiconductor device and method for fabricating the same |
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DE60134842D1 (en) | 2000-04-11 | 2008-08-28 | Thomson Licensing | DEVICE FOR SAFE SAVING OF SECRET INFORMATION |
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- 2003-12-26 US US10/746,089 patent/US7354834B2/en not_active Expired - Fee Related
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CN102437082A (en) * | 2011-08-15 | 2012-05-02 | 上海华力微电子有限公司 | Method for improving filling performance in ultra-high depth-to-width ratio shallow trench isolation (STI) process |
Also Published As
Publication number | Publication date |
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US20040248373A1 (en) | 2004-12-09 |
US7354834B2 (en) | 2008-04-08 |
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