US20050151566A1 - Dual-stage comparator unit - Google Patents
Dual-stage comparator unit Download PDFInfo
- Publication number
- US20050151566A1 US20050151566A1 US10/995,950 US99595004A US2005151566A1 US 20050151566 A1 US20050151566 A1 US 20050151566A1 US 99595004 A US99595004 A US 99595004A US 2005151566 A1 US2005151566 A1 US 2005151566A1
- Authority
- US
- United States
- Prior art keywords
- pair
- amplifier
- stage
- amplifier stage
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356182—Bistable circuits using complementary field-effect transistors with additional means for controlling the main nodes
- H03K3/356191—Bistable circuits using complementary field-effect transistors with additional means for controlling the main nodes with synchronous operation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
- H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
Definitions
- This invention relates to integrated circuits and, more particularly, to integrated circuit comparators.
- a comparator is a circuit that compares the instantaneous magnitude of a first input signal to the magnitude of a second input signal. If the magnitude of the first input signal is less than the magnitude of the second input signal, then the comparator generates an output signal having a first logic level. If the magnitude of the first input signal is greater than the magnitude of the second input signal, then the comparator generates an output signal having a second logic level.
- An ideal comparator has infinite gain and infinite bandwidth.
- a comparator having infinite gain and infinite bandwidth can convert a small analog signal to a large logic signal very quickly.
- most comparators are not ideal.
- the gain of most high-bandwidth comparators is usually low, less than about ten, and the bandwidth of most high-gain comparators is also low, less than about one megahertz.
- the gain-bandwidth product is not critical to the success of the application.
- a comparator having a gain of about ten and a bandwidth of about one megahertz is suitable for use in connection with a smoke detector.
- comparators that can operate in high-speed signaling applications that are common in modern digital systems, such as microprocessors, digital signal processors, communications circuits, and storage systems. These high-speed signaling applications require the comparator gain to be as high as possible, usually much greater than ten, and the comparator bandwidth also to be as high as possible, usually much greater than one megahertz.
- FIG. 1A is a block diagram of some embodiments of a comparator unit, according to the teachings of the present invention.
- FIG. 1B is a schematic diagram of one embodiment of the differential amplifier shown in FIG. 1A , according to the teachings of the present invention
- FIG. 1C is a schematic diagram of an alternative embodiment of the differential amplifier shown in FIG. 1A , according to the teachings of the present invention.
- FIG. 1D is a schematic diagram of another alternative embodiment of the differential amplifier shown in FIG. 1A , according to the teachings of the present invention.
- FIG. 1E is a schematic diagram of one embodiment of the switch shown in FIG. 1A , according to the teachings of the present invention.
- FIG. 1F is a schematic diagram of an alternative embodiment of the switch shown in FIG. 1A , according to the teachings of the present invention.
- FIG. 1G is a schematic diagram of one embodiment of the non-linear load shown in FIG. 1A , according to the teachings of the present invention.
- FIG. 1H is a schematic diagram of an alternative embodiment of the non-linear load shown in FIG. 1A , according to the teachings of the present invention.
- FIG. 2 is a timing diagram illustrating signals processed and generated by the comparator unit shown in FIG. 1A , according to the teachings of the present invention
- FIG. 3 is a flow diagram of one embodiment of a method of processing a differential signal, according to the teachings of the present invention.
- FIG. 4 is a block diagram of some embodiments of a sample-and-hold unit coupled to a comparator unit, according to the teachings of the present invention.
- FIG. 5 is a block diagram of some embodiments of a signal transmission unit, according to the teachings of the present invention.
- FIG. 1A is a block diagram of some embodiments of a comparator unit 100 according to the teachings of the present invention.
- the comparator unit 100 includes a first amplifier stage 102 and a second amplifier stage 104 .
- the first amplifier stage 102 includes a differential amplifier 106 , a switch 114 , and a non-linear load 116 .
- the differential amplifier 106 includes a pair of input nodes 108 and 109 and a pair of output nodes 111 and 112 .
- the switch 114 and the non-linear load 116 are connected across the pair of output nodes 111 and 112 .
- the differential amplifier 106 is not limited to a particular type of differential amplifier, however the differential amplifier 106 preferably comprises a high-gain linear differential amplifier.
- the differential amplifier 106 (shown in FIG. 1A ) comprises a differential pair 118 , including isolated gate field effect transistors 120 and 122 , configured as shown in FIG. 1B .
- the differential amplifier 106 (shown in FIG. 1A ) comprises a pair of differential pairs 124 , including differential pairs 126 and 128 comprising n-channel isolated gate field-effect transistors 130 - 131 and 132 - 133 , respectively, configured as shown in FIG. 1C .
- the differential amplifier 106 (shown in FIG. 1A ) comprises a differential pair 135 , including bipolar junction transistors 137 and 139 , configured as shown in FIG. 1D .
- the differential amplifier 106 receives a +INPUT SIGNAL and a ⁇ INPUT SIGNAL at the pair of input nodes 108 and 109 , respectively, and generates an amplified signal at the pair of output nodes 111 and 112 by amplifying the difference between the +INPUT SIGNAL and the ⁇ INPUT SIGNAL.
- the switch 114 is not limited to a particular type of switch.
- the switch 114 is an electronically controllable switch.
- FIG. 1E one exemplary embodiment of an electronically controllable switch suitable for use in connection with the present invention is isolated gate field-effect transistor 142 .
- the switch 114 is an optically controllable switch.
- an optically controllable switch suitable for use in connection with the present invention is photo-transistor 144 .
- Using an optically controllable switch, such as the photo-transistor 144 , for the switch 114 in the comparator unit 100 reduces the electrical noise in the comparator unit 100 by eliminating an electrical signal transmission line and the noise associated with an electrical signal transmission line from the comparator unit 100 .
- the switch 114 when closed, provides a conductive path between nodes 111 and 112 to equalize the potential at the nodes 111 and 112 .
- the isolated gate field-effect transistor switch 142 shown in FIG. 1E , is opened and closed by applying an electronic clock signal (not shown) to the gate 145 of the isolated gate field-effect transistor switch 142 .
- the photo-transistor 144 shown in FIG. 1F , is opened and closed by applying an optical clock signal (not shown) to the base (not shown) of the photo-transistor 144 .
- the non-linear load 116 is not limited to a particular type of non-linear load.
- the non-linear load 116 comprises a pair of cross-coupled n-channel, isolated gate field-effect transistors 160 and 162 , configured as shown in FIG. 1G .
- the non-linear load 116 comprises a pair of cross-coupled bipolar junction transistors 164 and 166 , configured as shown in FIG. 1H .
- the non-linear load 116 allows the signals at the output nodes 111 and 112 to reach the supply voltages (not shown) and supports a higher slew rate or bandwidth for signals at output nodes 111 and 112 than a linear load.
- the second amplifier stage 104 is coupled to the pair of output nodes 111 and 112 of the first amplifier stage 102 .
- the second amplifier stage 104 includes a pair of second stage input nodes 170 and 172 , a pair of second-stage output nodes 174 and 176 , a pair of cross-coupled n-channel isolated gate field-effect transistors 178 and 180 , a pair of cross-coupled p-channel isolated gate field-effect transistors 182 and 184 , a switch 186 , and input pair of n-channel isolated gate field-effect input transistors 188 and 190 .
- the input pair of n-channel isolated gate field-effect input transistors 188 and 190 are coupled to the input nodes 170 and 172 .
- the n-channel isolated gate field effect input transistor 188 is connected in parallel with the n-channel isolated gate field-effect transistor 178
- the n-channel isolated gate field-effect input transistor 190 is connected in parallel with the n-channel isolated gate field-effect transistor 180 .
- the pair of cross-coupled p-channel isolated gate field-effect transistors 182 and 184 and the switch 186 are connected between the second stage output nodes 174 and 176 .
- the second amplifier stage 104 is a non-linear amplifier.
- FIG. 2 is a timing diagram 200 illustrating signals processed and generated by the comparator unit 100 shown in FIG. 1A , according to the teachings of the present invention.
- the comparator unit 100 receives three input signals—a differential input signal 202 including the +INPUT SIGNAL and the ⁇ INPUT SIGNAL at the pair of input nodes 111 and 112 of the differential amplifier 106 , the CLOCK SIGNAL 204 at the switch 114 , and a DELAYED CLOCK SIGNAL 206 at the switch 186 .
- the comparator unit 100 generates an amplified differential signal 208 at the pair of output nodes 111 and 112 and a differential output signal 210 including the +OUTPUT SIGNAL and the ⁇ OUTPUT SIGNAL at the pair of second amplifier stage output nodes 174 and 176 .
- the CLOCK SIGNAL 204 and the DELAYED CLOCK SIGNAL 206 are shown as being one-hundred and eighty degrees out of phase. However, in a preferred embodiment, the DELAYED CLOCK SIGNAL 206 lags the CLOCK SIGNAL 204 by about one gate delay (for example one inverter delay). In an alternative embodiment, the DELAYED CLOCK SIGNAL 206 has a phase delay with respect to the CLOCK SIGNAL 204 of about ten degrees.
- the timing diagram 200 shows the signals described above during the four time periods T 1 , T 2 , T 3 and T 4 .
- the switch 114 is closed by the CLOCK SIGNAL 204 to equalize the pair of output nodes 111 and 112 to a common potential as can be seen in amplified differential signal 208 .
- the switch 114 is opened by the CLOCK SIGNAL 204
- the switch 186 is closed by the DELAYED CLOCK SIGNAL 206 .
- the pair of output nodes 111 and 112 assume potential values that represent an amplified difference between the +INPUT SIGNAL and the ⁇ INPUT SIGNAL, as can be seen in amplified differential signal 208 , and the pair of second stage output nodes 174 and 176 are equalized to a common potential, as can be seen at the differential output signal 210 .
- the switch 114 is closed by the CLOCK SIGNAL 204
- the switch 186 is opened by the DELAYED CLOCK SIGNAL 206 .
- the pair of output nodes 111 and 112 are equalized to a common potential, as can be seen in amplified differential signal 208 , and the pair of second stage output nodes 174 and 176 assume potential values that represent an amplified difference between the signals at the pair of second stage input nodes 170 and 172 , as can be seen at the differential output signal 210 .
- the time periods T 1 and T 3 are sometimes referred to as equalization phases, and the time periods T 2 and T 4 are sometimes referred to as evaluation phases.
- the time periods T 2 and T 4 are sometimes referred to as equalization phases, and the time periods T 1 and T 3 are sometimes referred to as evaluation phases.
- an equalization phase a pair of nodes are equalized to a potential, and in an evaluation phase an amplifier amplifies an input signal.
- FIG. 3 is a flow diagram of one embodiment of a method 300 of processing a differential signal, according to the teachings of the present invention.
- the method 300 includes the operations shown in blocks 302 , 304 , 306 , and 308 .
- an equalization phase in a first amplifier stage begins. For example, referring to FIG. 1A , to begin an equalization phase in the first amplifier stage 102 a phase of the clock signal is provided to the switch 114 to close the switch 114 to equalize the potential at the nodes 111 and 112 .
- an equalization phase in a second amplifier stage begins about one gate delay after the beginning of the equalization phase in the first amplifier stage.
- a phase of the delayed clock signal is provided to the switch 186 to close the switch 186 about one gate delay (or about 10% of the period of the clock signal) after applying a phase of the clock signal to the switch 114 to close the switch 1 14 .
- the differential signal in the first amplifier output stage is evaluated to form a first stage output differential signal after completing the equalization phase in the first amplifier stage.
- the differential input signal is amplified in the first amplifier stage 102 after the end of an equalization phase of the clock signal.
- the first stage output differential signal is evaluated in the second amplifier stage after completing the equalization phase in the second amplifier stage.
- the first stage amplifier 102 output differential signal is amplified by a non-linear amplifier in the second amplifier stage 104 after the end of an equalization phase of the delayed clock signal.
- the first amplifier stage 102 in an alternative embodiment, includes the differential amplifier 106 , switches 164 and 166 , and the non-linear load 116 .
- the differential amplifier 106 includes the pair of input nodes 108 and 109 and the pair of output nodes 111 and 112 .
- the non-linear load 116 is connected across the pair of output nodes 111 and 112 .
- the switch 164 is connected between the output node 111 and a common node 168
- the switch 166 is connected between the output node 112 and a common node 168 .
- the switches 164 and 166 are connected between the output nodes 111 and 112 and the common node 168 and, when closed, equalize the voltage at the nodes 111 and 112 by providing a conductive path between the nodes 111 and 112 and the common node 168 .
- the switches 164 and 166 are not limited to a particular type of switch.
- the switches 164 and 166 are electrically controllable switches.
- One exemplary embodiment of an electrically controllable switch suitable for use in connection with the present invention is the isolated gate field-effect transistor 142 shown in FIG. 1E .
- the switches 164 and 166 are optically controllable switches.
- an optically controllable switch suitable for use in connection with the present invention is the photo-transistor 144 shown in FIG. 1F .
- the switch 164 is an electrically controllable switch and the switch 166 is an optically controllable switch. Selecting an optically controllable switch for the switch 166 reduces electrical noise in the comparator unit 100 .
- the comparator 100 in the above-described embodiment, functions as shown in FIG. 2 , except that the signal 204 (shown in FIG. 2 ) opens and closes switches 164 and 166 (instead of switch 114 ) to equalize the output nodes 111 and 112 to the potential at the common node 168 .
- FIG. 4 is a block diagram of some embodiments of a sample-and-hold unit 400 coupled to a comparator unit 100 , according to the teachings of the present invention.
- the sample-and-hold unit 400 includes input nodes 402 and 404 coupled to switches 406 and 408 .
- the switches 406 and 408 are coupled to the capacitors 410 and 412 , and the capacitors 410 and 412 are coupled to input nodes 108 and 109 of the comparator unit 100 .
- the sample-and-hold unit 400 receives a differential signal at the input nodes 402 and 404 .
- the sample-and-hold unit 400 samples the differential signal when the switches are closed and holds the differential signal at the capacitors 410 and 412 when the switches are open.
- a CLOCK SIGNAL is coupled to the switches 406 and 408 to open and close the switches.
- the comparator unit 100 processes the sampled signal during the hold time. Sampling the differential signal prior to processing by the comparator unit 100 reduces the probability of the comparator unit 100 processing spurious noise signals.
- FIG. 5 is a block diagram of some embodiments of a signal transmission unit 500 , according to the teachings of the present invention.
- the signal transmission unit 500 in one embodiment, includes a differential signal source 502 , a comparator unit 100 , and a transmission line 506 .
- the transmission line 506 couples the differential signal source 502 to the comparator unit 100 .
- the signal transmission unit 500 includes the differential signal source 502 formed on a first integrated circuit die 508 , the comparator unit 100 formed on a second integrated circuit die 510 , and the first integrated circuit die 508 and the second integrated circuit die 510 and the transmission line 506 formed on a substrate 512 .
- the first integrated circuit die 508 comprises a processor unit
- the second integrated circuit die 510 comprises a processor unit.
- the first integrated circuit die 503 comprises a communication unit
- the second integrated circuit die 510 comprises a processor unit.
- the first integrated circuit die 508 comprises a data storage unit
- the second integrated circuit die 510 comprises a processor unit.
- the substrate 512 is not limited to being fabricated from a particular material.
- the substrate 512 comprises a semiconductor.
- the substrate 512 comprises a ceramic.
- the substrate 512 comprises a dielectric.
- the differential signal source 502 transmits a differential signal (such as the differential signal 202 shown in FIG. 2 ) on the transmission line 506 .
- the differential signal is received and processed, as described above, by the comparator unit 100 shown in FIG. 1A .
Abstract
A comparator unit comprising a first amplifier stage and a second amplifier stage. The first amplifier stage includes a differential amplifier having a pair of input nodes for receiving a differential signal and a pair of output nodes, a switch connected across the pair of output nodes, and a non-linear load connected across the pair of output nodes. The second amplifier stage is coupled to the pair of output nodes of the first amplifier stage. In one embodiment the second amplifier stage is a non-linear amplifier. In an alternative embodiment, the differential amplifier is a differential pair. In another alternative embodiment, the differential amplifier is a pair of differential pairs.
Description
- This application is a Divisional of U.S. application Ser. No. 09/893,184 filed Jun. 27, 2001 which is incorporated herein by reference.
- This invention relates to integrated circuits and, more particularly, to integrated circuit comparators.
- A comparator is a circuit that compares the instantaneous magnitude of a first input signal to the magnitude of a second input signal. If the magnitude of the first input signal is less than the magnitude of the second input signal, then the comparator generates an output signal having a first logic level. If the magnitude of the first input signal is greater than the magnitude of the second input signal, then the comparator generates an output signal having a second logic level.
- An ideal comparator has infinite gain and infinite bandwidth. A comparator having infinite gain and infinite bandwidth can convert a small analog signal to a large logic signal very quickly. Unfortunately, most comparators are not ideal. The gain of most high-bandwidth comparators is usually low, less than about ten, and the bandwidth of most high-gain comparators is also low, less than about one megahertz. For some comparator applications, such as detecting a light level change in a smoke detector, the gain-bandwidth product is not critical to the success of the application. A comparator having a gain of about ten and a bandwidth of about one megahertz is suitable for use in connection with a smoke detector. However, there is a great demand for comparators that can operate in high-speed signaling applications that are common in modern digital systems, such as microprocessors, digital signal processors, communications circuits, and storage systems. These high-speed signaling applications require the comparator gain to be as high as possible, usually much greater than ten, and the comparator bandwidth also to be as high as possible, usually much greater than one megahertz.
- For these an other reasons there is a need for a comparator having a high gain-bandwidth product.
-
FIG. 1A is a block diagram of some embodiments of a comparator unit, according to the teachings of the present invention; -
FIG. 1B is a schematic diagram of one embodiment of the differential amplifier shown inFIG. 1A , according to the teachings of the present invention; -
FIG. 1C is a schematic diagram of an alternative embodiment of the differential amplifier shown inFIG. 1A , according to the teachings of the present invention; -
FIG. 1D is a schematic diagram of another alternative embodiment of the differential amplifier shown inFIG. 1A , according to the teachings of the present invention; -
FIG. 1E is a schematic diagram of one embodiment of the switch shown inFIG. 1A , according to the teachings of the present invention; -
FIG. 1F is a schematic diagram of an alternative embodiment of the switch shown inFIG. 1A , according to the teachings of the present invention; -
FIG. 1G is a schematic diagram of one embodiment of the non-linear load shown inFIG. 1A , according to the teachings of the present invention; -
FIG. 1H is a schematic diagram of an alternative embodiment of the non-linear load shown inFIG. 1A , according to the teachings of the present invention; -
FIG. 2 is a timing diagram illustrating signals processed and generated by the comparator unit shown inFIG. 1A , according to the teachings of the present invention; -
FIG. 3 is a flow diagram of one embodiment of a method of processing a differential signal, according to the teachings of the present invention; -
FIG. 4 is a block diagram of some embodiments of a sample-and-hold unit coupled to a comparator unit, according to the teachings of the present invention; and -
FIG. 5 is a block diagram of some embodiments of a signal transmission unit, according to the teachings of the present invention. - In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which are shown, by way of illustration, specific embodiments of the invention which may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
-
FIG. 1A is a block diagram of some embodiments of acomparator unit 100 according to the teachings of the present invention. Thecomparator unit 100 includes afirst amplifier stage 102 and asecond amplifier stage 104. - The
first amplifier stage 102, in one embodiment, includes adifferential amplifier 106, aswitch 114, and anon-linear load 116. Thedifferential amplifier 106 includes a pair ofinput nodes output nodes switch 114 and thenon-linear load 116 are connected across the pair ofoutput nodes - The
differential amplifier 106 is not limited to a particular type of differential amplifier, however thedifferential amplifier 106 preferably comprises a high-gain linear differential amplifier. - Referring to
FIG. 1B , in one embodiment, the differential amplifier 106 (shown inFIG. 1A ) comprises adifferential pair 118, including isolated gatefield effect transistors FIG. 1B . - Referring to
FIG. 1C , in an alternative embodiment, the differential amplifier 106 (shown inFIG. 1A ) comprises a pair ofdifferential pairs 124, includingdifferential pairs FIG. 1C . - Referring to
FIG. 1D , in another alternative embodiment, the differential amplifier 106 (shown inFIG. 1A ) comprises adifferential pair 135, includingbipolar junction transistors FIG. 1D . - Selecting a differential pair or a pair of differential pairs for the
differential amplifier 106 allows thefirst amplifier stage 102 to have a high bandwidth. - Referring again to
FIG. 1A , in operation, thedifferential amplifier 106 receives a +INPUT SIGNAL and a −INPUT SIGNAL at the pair ofinput nodes output nodes - The
switch 114 is not limited to a particular type of switch. In one embodiment, theswitch 114 is an electronically controllable switch. Referring toFIG. 1E , one exemplary embodiment of an electronically controllable switch suitable for use in connection with the present invention is isolated gate field-effect transistor 142. - In an alternative embodiment, the
switch 114 is an optically controllable switch. Referring toFIG. 1F , one exemplary embodiment of an optically controllable switch suitable for use in connection with the present invention is photo-transistor 144. Using an optically controllable switch, such as the photo-transistor 144, for theswitch 114 in thecomparator unit 100 reduces the electrical noise in thecomparator unit 100 by eliminating an electrical signal transmission line and the noise associated with an electrical signal transmission line from thecomparator unit 100. - In operation, the
switch 114, when closed, provides a conductive path betweennodes nodes effect transistor switch 142, shown inFIG. 1E , is opened and closed by applying an electronic clock signal (not shown) to thegate 145 of the isolated gate field-effect transistor switch 142. The photo-transistor 144, shown inFIG. 1F , is opened and closed by applying an optical clock signal (not shown) to the base (not shown) of the photo-transistor 144. - The
non-linear load 116 is not limited to a particular type of non-linear load. Referring toFIG. 1G , in one embodiment, thenon-linear load 116 comprises a pair of cross-coupled n-channel, isolated gate field-effect transistors FIG. 1G . - Referring to
FIG. 1H , in an alternative embodiment, thenon-linear load 116 comprises a pair of cross-coupledbipolar junction transistors FIG. 1H . - In operation, the
non-linear load 116 allows the signals at theoutput nodes output nodes - The
second amplifier stage 104 is coupled to the pair ofoutput nodes first amplifier stage 102. Thesecond amplifier stage 104, in one embodiment, includes a pair of secondstage input nodes stage output nodes effect transistors effect transistors switch 186, and input pair of n-channel isolated gate field-effect input transistors effect input transistors input nodes effect input transistor 188 is connected in parallel with the n-channel isolated gate field-effect transistor 178, and the n-channel isolated gate field-effect input transistor 190 is connected in parallel with the n-channel isolated gate field-effect transistor 180. The pair of cross-coupled p-channel isolated gate field-effect transistors switch 186 are connected between the secondstage output nodes second amplifier stage 104 is a non-linear amplifier. - Combining a
non-linear load 116 in thefirst amplifier stage 102 with a non-linear amplifier in thesecond stage amplifier 104 allows thecomparator unit 100 to have a high gain. -
FIG. 2 is a timing diagram 200 illustrating signals processed and generated by thecomparator unit 100 shown inFIG. 1A , according to the teachings of the present invention. Thecomparator unit 100 receives three input signals—adifferential input signal 202 including the +INPUT SIGNAL and the −INPUT SIGNAL at the pair ofinput nodes differential amplifier 106, theCLOCK SIGNAL 204 at theswitch 114, and aDELAYED CLOCK SIGNAL 206 at theswitch 186. Thecomparator unit 100 generates an amplifieddifferential signal 208 at the pair ofoutput nodes differential output signal 210 including the +OUTPUT SIGNAL and the −OUTPUT SIGNAL at the pair of second amplifierstage output nodes - In
FIG. 2 , for the purpose of clarity in the illustration, theCLOCK SIGNAL 204 and the DELAYEDCLOCK SIGNAL 206 are shown as being one-hundred and eighty degrees out of phase. However, in a preferred embodiment, theDELAYED CLOCK SIGNAL 206 lags theCLOCK SIGNAL 204 by about one gate delay (for example one inverter delay). In an alternative embodiment, the DELAYEDCLOCK SIGNAL 206 has a phase delay with respect to theCLOCK SIGNAL 204 of about ten degrees. - The timing diagram 200 shows the signals described above during the four time periods T1, T2, T3 and T4. During the T1 time period, in the
first amplifier stage 102, theswitch 114 is closed by theCLOCK SIGNAL 204 to equalize the pair ofoutput nodes differential signal 208. During the T2 time period, in thefirst amplifier stage 102, theswitch 114 is opened by theCLOCK SIGNAL 204, and in thesecond amplifier stage 104, theswitch 186 is closed by the DELAYEDCLOCK SIGNAL 206. The pair ofoutput nodes differential signal 208, and the pair of secondstage output nodes differential output signal 210. During the T3 time period, in thefirst amplifier stage 102, theswitch 114 is closed by theCLOCK SIGNAL 204, and in thesecond amplifier stage 104, theswitch 186 is opened by the DELAYEDCLOCK SIGNAL 206. The pair ofoutput nodes differential signal 208, and the pair of secondstage output nodes stage input nodes differential output signal 210. - For the
CLOCK SIGNAL 204, the time periods T1 and T3 are sometimes referred to as equalization phases, and the time periods T2 and T4 are sometimes referred to as evaluation phases. Similarly, for theDELAYED CLOCK SIGNAL 206, the time periods T2 and T4 are sometimes referred to as equalization phases, and the time periods T1 and T3 are sometimes referred to as evaluation phases. As described above, in an equalization phase a pair of nodes are equalized to a potential, and in an evaluation phase an amplifier amplifies an input signal. -
FIG. 3 is a flow diagram of one embodiment of amethod 300 of processing a differential signal, according to the teachings of the present invention. Themethod 300 includes the operations shown inblocks - In 302, an equalization phase in a first amplifier stage begins. For example, referring to
FIG. 1A , to begin an equalization phase in the first amplifier stage 102 a phase of the clock signal is provided to theswitch 114 to close theswitch 114 to equalize the potential at thenodes - In 304, an equalization phase in a second amplifier stage begins about one gate delay after the beginning of the equalization phase in the first amplifier stage. For example, referring to
FIG. 1A , to begin an equalization phase in the second amplifier stage 104 a phase of the delayed clock signal is provided to theswitch 186 to close theswitch 186 about one gate delay (or about 10% of the period of the clock signal) after applying a phase of the clock signal to theswitch 114 to close theswitch 1 14. - In 306, the differential signal in the first amplifier output stage is evaluated to form a first stage output differential signal after completing the equalization phase in the first amplifier stage. For example, referring to
FIG. 1A , to evaluate the differential signal in the firstamplifier output stage 102, the differential input signal is amplified in thefirst amplifier stage 102 after the end of an equalization phase of the clock signal. - In 308, the first stage output differential signal is evaluated in the second amplifier stage after completing the equalization phase in the second amplifier stage. For example, referring to
FIG. 1A , to evaluate thefirst stage 102 output differential signal in thesecond stage amplifier 104, thefirst stage amplifier 102 output differential signal is amplified by a non-linear amplifier in thesecond amplifier stage 104 after the end of an equalization phase of the delayed clock signal. - Referring again to
FIG. 1A , thefirst amplifier stage 102, in an alternative embodiment, includes thedifferential amplifier 106,switches non-linear load 116. Thedifferential amplifier 106 includes the pair ofinput nodes output nodes non-linear load 116 is connected across the pair ofoutput nodes switch 164 is connected between theoutput node 111 and acommon node 168, and theswitch 166 is connected between theoutput node 112 and acommon node 168. - The
switches output nodes common node 168 and, when closed, equalize the voltage at thenodes nodes common node 168. Theswitches switches effect transistor 142 shown inFIG. 1E . In an alternative embodiment, theswitches transistor 144 shown inFIG. 1F . In still another alternative embodiment theswitch 164 is an electrically controllable switch and theswitch 166 is an optically controllable switch. Selecting an optically controllable switch for theswitch 166 reduces electrical noise in thecomparator unit 100. - In operation, the
comparator 100, in the above-described embodiment, functions as shown inFIG. 2 , except that the signal 204 (shown inFIG. 2 ) opens and closesswitches 164 and 166 (instead of switch 114) to equalize theoutput nodes common node 168. -
FIG. 4 is a block diagram of some embodiments of a sample-and-hold unit 400 coupled to acomparator unit 100, according to the teachings of the present invention. The sample-and-hold unit 400 includesinput nodes switches switches capacitors capacitors nodes comparator unit 100. - In operation, the sample-and-
hold unit 400 receives a differential signal at theinput nodes hold unit 400 samples the differential signal when the switches are closed and holds the differential signal at thecapacitors switches comparator unit 100 processes the sampled signal during the hold time. Sampling the differential signal prior to processing by thecomparator unit 100 reduces the probability of thecomparator unit 100 processing spurious noise signals. -
FIG. 5 is a block diagram of some embodiments of asignal transmission unit 500, according to the teachings of the present invention. Thesignal transmission unit 500, in one embodiment, includes adifferential signal source 502, acomparator unit 100, and atransmission line 506. Thetransmission line 506 couples thedifferential signal source 502 to thecomparator unit 100. - The
signal transmission unit 500, in an alternative embodiment, includes thedifferential signal source 502 formed on a first integrated circuit die 508, thecomparator unit 100 formed on a second integrated circuit die 510, and the first integrated circuit die 508 and the second integrated circuit die 510 and thetransmission line 506 formed on a substrate 512. In one embodiment, the first integrated circuit die 508 comprises a processor unit, and the second integrated circuit die 510 comprises a processor unit. In an alternative embodiment, the first integrated circuit die 503 comprises a communication unit, and the second integrated circuit die 510 comprises a processor unit. In another alternative embodiment, the first integrated circuit die 508 comprises a data storage unit, and the second integrated circuit die 510 comprises a processor unit. - The substrate 512 is not limited to being fabricated from a particular material. In one embodiment, the substrate 512 comprises a semiconductor. In an alternative embodiment, the substrate 512 comprises a ceramic. In still another alternative embodiment, the substrate 512 comprises a dielectric.
- In operation, the
differential signal source 502 transmits a differential signal (such as thedifferential signal 202 shown inFIG. 2 ) on thetransmission line 506. The differential signal is received and processed, as described above, by thecomparator unit 100 shown inFIG. 1A . - Biasing circuits for the comparator embodiments described above have not been included in the figures because, as those skilled in the art will appreciate, there are many bias circuits suitable for use in connection with the comparators of the present invention and the design of such circuits are known to those skilled in the art.
- Although specific embodiments have been described and illustrated herein, it will be appreciated by those skilled in the art, having the benefit of the present disclosure, that any arrangement which is intended to achieve the same purpose may be substituted for a specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
Claims (26)
1-9. (canceled)
10. A comparator unit comprising:
a first amplifier stage including a differential amplifier having a pair of input nodes and a pair of output nodes including a first output node and a second output node, a non-linear load connected across the pair of output nodes, and a first switch connected between the first output node and a common node and a second switch connected between the second output node and the common node; and
a second amplifier stage coupled to the pair of output nodes.
11. The comparator unit of claim 10 , wherein the differential amplifier comprises a pair of differential pairs of isolated gate field-effect transistors.
12. The comparator unit of claim 11 , wherein the switch comprises an optically controllable switch.
13. The comparator unit of claim 12 , wherein the optically controllable switch comprises a photo-transistor.
14. The comparator unit of claim 13 , wherein the non-linear load comprises a pair of cross-coupled bipolar transistors.
15. The comparator unit of claim 14 , wherein the second amplifier stage comprises a non-linear amplifier.
16. The comparator unit of claim 15 , wherein the non-linear amplifier includes a pair of second stage output nodes and a switch connected across the pair of second stage output nodes.
17. The comparator unit of 16, wherein the non-linear amplifier includes a pair of cross-coupled p-channel isolated gate field-effect transistors connected across the pair of second stage output nodes, a non-linear load connected across the pair of second stage output nodes, and a pair of input transistors connected across the non-linear load.
18. A signal transmission unit comprising:
a differential signal source;
a comparator unit comprising:
a first amplifier stage including a pair of differential amplifiers having a pair of input nodes and a pair of output nodes, a switch connected across the pair of output nodes, and a non-linear load connected across the pair of output nodes; and
a second amplifier stage coupled to the pair of output nodes; and
a transmission line to couple the differential signal source to the comparator unit.
19. The signal transmission unit of claim 18 , wherein the differential signal source is formed on a first integrated circuit die, the comparator unit is formed on a second integrated circuit die, and the transmission line is formed on a substrate on which the first integrated circuit die and the second integrated circuit die are mounted.
20. The signal transmission unit of claim 19 , wherein the second integrated circuit die comprises a processor.
21. The signal transmission unit of claim 20 , wherein the first integrated circuit die comprises a communication unit.
22. The signal transmission unit of claim 20 , wherein the first integrated circuit die comprises a data storage unit.
23. The signal transmission unit of claim 20 , wherein the first integrated circuit die comprises an amplifier.
24. A method of processing a differential signal, the method comprising:
beginning an equalization phase in a first amplifier stage;
beginning an equalization phase in a second amplifier stage about one gate delay after beginning the equalization phase in the first amplifier stage;
evaluating the differential signal in the first amplifier stage to form a first stage output differential signal after completing the equalization phase in the first amplifier stage; and
evaluating the first stage output differential signal in the second amplifier stage after completing the equalization phase in the second amplifier stage.
25. The method of claim 24 , wherein beginning an equalization phase in a first amplifier stage comprises:
closing a switch in the first amplifier stage.
26. The method of claim 24 , wherein beginning an equalization phase in a first amplifier stage comprises:
closing a plurality of switches in the first amplifier stage.
27. The method of claim 26 , wherein evaluating the differential signal in the first amplifier stage to form a first stage output differential signal after completing the equalization phase in the first amplifier stage comprises:
applying linear amplification to the differential signal to form an amplified differential signal; and
applying non-linear amplification to the amplified differential signal to form the first stage output differential signal.
28. The method of claim 27 , wherein evaluating the first stage output differential signal in the second amplifier stage after completing the equalization phase in the second amplifier stage comprises:
applying non-linear amplification to the first stage output signal.
29. A comparator unit comprising:
a first amplifier stage including a differential amplifier having a pair of input nodes and a pair of output nodes including a first output node and a second output node, a non-linear load connected across the pair of output nodes, and a first switch connected between the first output node and a common node, a second switch connected between the second output node and the common node, and a third switch connected between the first output node and the second output node; and
a second amplifier stage coupled to the pair of output nodes.
30. The comparator unit of claim 29 , wherein the third switch comprises an electronically controllable switch.
31. The comparator unit of claim 30 , wherein the electronically controllable switch comprises an isolated gate field-effect transistor.
32. The comparator unit of claim 29 , wherein the non-linear load comprises a pair of cross-coupled isolated gate field-effect transistors.
33. The comparator unit of claim 29 , wherein the second amplifier stage comprises a non-linear amplifier.
34. The comparator unit of claim 29 , wherein the second amplifier stage includes a pair of second stage output nodes and a switch connected across the pair of second stage output nodes.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/995,950 US20050151566A1 (en) | 2001-06-27 | 2004-11-23 | Dual-stage comparator unit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/893,184 US6825696B2 (en) | 2001-06-27 | 2001-06-27 | Dual-stage comparator unit |
US10/995,950 US20050151566A1 (en) | 2001-06-27 | 2004-11-23 | Dual-stage comparator unit |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/893,184 Division US6825696B2 (en) | 2001-06-27 | 2001-06-27 | Dual-stage comparator unit |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050151566A1 true US20050151566A1 (en) | 2005-07-14 |
Family
ID=25401156
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/893,184 Expired - Fee Related US6825696B2 (en) | 2001-06-27 | 2001-06-27 | Dual-stage comparator unit |
US10/995,950 Abandoned US20050151566A1 (en) | 2001-06-27 | 2004-11-23 | Dual-stage comparator unit |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/893,184 Expired - Fee Related US6825696B2 (en) | 2001-06-27 | 2001-06-27 | Dual-stage comparator unit |
Country Status (1)
Country | Link |
---|---|
US (2) | US6825696B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080042692A1 (en) * | 2006-08-15 | 2008-02-21 | International Business Machines Corporation | Voltage comparator apparatus and method having improved kickback and jitter characteristics |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6956941B1 (en) * | 2000-04-12 | 2005-10-18 | Austin Logistics Incorporated | Method and system for scheduling inbound inquiries |
US7142662B2 (en) * | 2000-07-11 | 2006-11-28 | Austin Logistics Incorporated | Method and system for distributing outbound telephone calls |
US7103173B2 (en) * | 2001-07-09 | 2006-09-05 | Austin Logistics Incorporated | System and method for preemptive goals based routing of contact records |
US6639430B2 (en) * | 2001-02-27 | 2003-10-28 | Broadcom Corporation | High speed latch comparators |
US6825696B2 (en) * | 2001-06-27 | 2004-11-30 | Intel Corporation | Dual-stage comparator unit |
US7054434B2 (en) | 2001-07-09 | 2006-05-30 | Austin Logistics Incorporated | System and method for common account based routing of contact records |
US7715546B2 (en) * | 2001-07-09 | 2010-05-11 | Austin Logistics Incorporated | System and method for updating contact records |
US6819156B1 (en) * | 2001-11-26 | 2004-11-16 | Xilinx, Inc. | High-speed differential flip-flop |
US7308044B2 (en) * | 2003-09-30 | 2007-12-11 | Rambus Inc | Technique for receiving differential multi-PAM signals |
US20060012408A1 (en) * | 2004-07-06 | 2006-01-19 | Kenet, Inc. | Differential clock input buffer |
TWI242928B (en) * | 2004-09-10 | 2005-11-01 | Richtek Techohnology Corp | Electronic circuit using normally-on junction field effect transistor |
US7701256B2 (en) * | 2006-09-29 | 2010-04-20 | Analog Devices, Inc. | Signal conditioning circuit, a comparator including such a conditioning circuit and a successive approximation converter including such a circuit |
US7786771B2 (en) * | 2008-05-27 | 2010-08-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Phase lock loop (PLL) with gain control |
KR100967481B1 (en) * | 2008-11-14 | 2010-07-07 | 주식회사 동부하이텍 | Data transmitting system |
US8736334B2 (en) | 2012-06-13 | 2014-05-27 | Fujitsu Limited | Current mode logic latch |
JP2014039214A (en) * | 2012-08-20 | 2014-02-27 | Lapis Semiconductor Co Ltd | Data reception circuit and semiconductor device |
TWI506958B (en) | 2012-09-27 | 2015-11-01 | Ind Tech Res Inst | Dynamic comparator with equalization function |
US8829942B2 (en) * | 2012-11-13 | 2014-09-09 | University Of Macau | Comparator and calibration thereof |
US9967505B1 (en) * | 2017-04-13 | 2018-05-08 | Omnivision Technologies, Inc. | Comparators for double ramp analog to digital converter |
US10431608B2 (en) * | 2017-04-13 | 2019-10-01 | Omnivision Technologies, Inc. | Dual conversion gain high dynamic range readout for comparator of double ramp analog to digital converter |
Citations (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4333025A (en) * | 1978-03-13 | 1982-06-01 | Texas Instruments Incorporated | N-Channel MOS comparator |
US4602167A (en) * | 1982-11-26 | 1986-07-22 | Nec Corporation | Voltage comparator circuit |
US4670671A (en) * | 1986-02-19 | 1987-06-02 | Advanced Micro Devices, Inc. | High speed comparator having controlled hysteresis |
US4710724A (en) * | 1986-04-02 | 1987-12-01 | Motorola, Inc. | Differential CMOS comparator for switched capacitor applications |
US4754169A (en) * | 1987-04-24 | 1988-06-28 | American Telephone And Telegraph Company, At&T Bell Laboratories | Differential circuit with controllable offset |
US4868417A (en) * | 1988-08-23 | 1989-09-19 | Motorola, Inc. | Complementary voltage comparator |
US4987327A (en) * | 1989-05-30 | 1991-01-22 | Motorola, Inc. | Apparatus for adjusting DC offset voltage |
US5245223A (en) * | 1992-03-17 | 1993-09-14 | Hewlett-Packard Company | CMOS latching comparator |
US5455802A (en) * | 1992-12-22 | 1995-10-03 | Sgs-Thomson Microelectronics, Inc. | Dual dynamic sense amplifiers for a memory array |
US5508643A (en) * | 1994-11-16 | 1996-04-16 | Intel Corporation | Bitline level insensitive sense amplifier |
US5541538A (en) * | 1994-09-01 | 1996-07-30 | Harris Corporation | High speed comparator |
US5563533A (en) * | 1995-02-28 | 1996-10-08 | Motorola, Inc. | Method and apparatus for a high speed low power comparator using positive feedback |
US5563598A (en) * | 1994-10-14 | 1996-10-08 | Technoconcepts, Inc. | Differential comparator cirucit |
US5608757A (en) * | 1994-06-03 | 1997-03-04 | Dsc Communications Corporation | High speed transport system |
US5844428A (en) * | 1997-05-02 | 1998-12-01 | Integrated Silicon Solution Inc. | Driver circuit for use with a sensing amplifier in a memory |
US5942919A (en) * | 1997-06-25 | 1999-08-24 | Sun Microsystems, Inc. | Differential receiver including an enable circuit |
US5955899A (en) * | 1997-01-27 | 1999-09-21 | Intel Corporation | Compact comparator |
US5963060A (en) * | 1997-10-07 | 1999-10-05 | Intel Corporation | Latching sense amplifier |
US5982690A (en) * | 1998-04-15 | 1999-11-09 | Cirrus Logic, Inc. | Static low-power differential sense amplifier circuits, systems and methods |
US6028457A (en) * | 1996-09-18 | 2000-02-22 | Siemens Aktiengesellschaft | CMOS comparator |
US6114882A (en) * | 1997-08-15 | 2000-09-05 | Texas Instruments Incorporated | Current comparator and method therefor |
US6147514A (en) * | 1997-12-11 | 2000-11-14 | Kabushiki Kaisha Toshiba | Sense amplifier circuit |
US6172535B1 (en) * | 1999-11-04 | 2001-01-09 | Analog Devices, Inc. | High-speed analog comparator structures and methods |
US6255875B1 (en) * | 1997-08-06 | 2001-07-03 | Agere Systems Guardian Corp. | High-speed clock-enabled latch circuit |
US6344761B2 (en) * | 2000-03-29 | 2002-02-05 | Matsushita Electric Industrial Co., Ltd. | Current comparison type latch |
US6348882B1 (en) * | 2000-07-25 | 2002-02-19 | Philips Electronics North America Corporation | 5-ary receiver utilizing common mode insensitive differential offset comparator |
US6359473B1 (en) * | 1998-12-16 | 2002-03-19 | Hyundai Electronics Industries Co. | Amplifier for use in semiconductor integrated circuits |
US6388521B1 (en) * | 2000-09-22 | 2002-05-14 | National Semiconductor Corporation | MOS differential amplifier with offset compensation |
US6744284B2 (en) * | 2002-01-11 | 2004-06-01 | Samsung Electronics Co, Ltd. | Receiver circuit of semiconductor integrated circuit |
US6825696B2 (en) * | 2001-06-27 | 2004-11-30 | Intel Corporation | Dual-stage comparator unit |
-
2001
- 2001-06-27 US US09/893,184 patent/US6825696B2/en not_active Expired - Fee Related
-
2004
- 2004-11-23 US US10/995,950 patent/US20050151566A1/en not_active Abandoned
Patent Citations (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4333025A (en) * | 1978-03-13 | 1982-06-01 | Texas Instruments Incorporated | N-Channel MOS comparator |
US4602167A (en) * | 1982-11-26 | 1986-07-22 | Nec Corporation | Voltage comparator circuit |
US4670671A (en) * | 1986-02-19 | 1987-06-02 | Advanced Micro Devices, Inc. | High speed comparator having controlled hysteresis |
US4710724A (en) * | 1986-04-02 | 1987-12-01 | Motorola, Inc. | Differential CMOS comparator for switched capacitor applications |
US4754169A (en) * | 1987-04-24 | 1988-06-28 | American Telephone And Telegraph Company, At&T Bell Laboratories | Differential circuit with controllable offset |
US4868417A (en) * | 1988-08-23 | 1989-09-19 | Motorola, Inc. | Complementary voltage comparator |
US4987327A (en) * | 1989-05-30 | 1991-01-22 | Motorola, Inc. | Apparatus for adjusting DC offset voltage |
US5245223A (en) * | 1992-03-17 | 1993-09-14 | Hewlett-Packard Company | CMOS latching comparator |
US5455802A (en) * | 1992-12-22 | 1995-10-03 | Sgs-Thomson Microelectronics, Inc. | Dual dynamic sense amplifiers for a memory array |
US5608757A (en) * | 1994-06-03 | 1997-03-04 | Dsc Communications Corporation | High speed transport system |
US5541538A (en) * | 1994-09-01 | 1996-07-30 | Harris Corporation | High speed comparator |
US5563598A (en) * | 1994-10-14 | 1996-10-08 | Technoconcepts, Inc. | Differential comparator cirucit |
US5508643A (en) * | 1994-11-16 | 1996-04-16 | Intel Corporation | Bitline level insensitive sense amplifier |
US5563533A (en) * | 1995-02-28 | 1996-10-08 | Motorola, Inc. | Method and apparatus for a high speed low power comparator using positive feedback |
US6028457A (en) * | 1996-09-18 | 2000-02-22 | Siemens Aktiengesellschaft | CMOS comparator |
US5955899A (en) * | 1997-01-27 | 1999-09-21 | Intel Corporation | Compact comparator |
US5844428A (en) * | 1997-05-02 | 1998-12-01 | Integrated Silicon Solution Inc. | Driver circuit for use with a sensing amplifier in a memory |
US5942919A (en) * | 1997-06-25 | 1999-08-24 | Sun Microsystems, Inc. | Differential receiver including an enable circuit |
US6255875B1 (en) * | 1997-08-06 | 2001-07-03 | Agere Systems Guardian Corp. | High-speed clock-enabled latch circuit |
US6114882A (en) * | 1997-08-15 | 2000-09-05 | Texas Instruments Incorporated | Current comparator and method therefor |
US5963060A (en) * | 1997-10-07 | 1999-10-05 | Intel Corporation | Latching sense amplifier |
US6147514A (en) * | 1997-12-11 | 2000-11-14 | Kabushiki Kaisha Toshiba | Sense amplifier circuit |
US5982690A (en) * | 1998-04-15 | 1999-11-09 | Cirrus Logic, Inc. | Static low-power differential sense amplifier circuits, systems and methods |
US6359473B1 (en) * | 1998-12-16 | 2002-03-19 | Hyundai Electronics Industries Co. | Amplifier for use in semiconductor integrated circuits |
US6172535B1 (en) * | 1999-11-04 | 2001-01-09 | Analog Devices, Inc. | High-speed analog comparator structures and methods |
US6344761B2 (en) * | 2000-03-29 | 2002-02-05 | Matsushita Electric Industrial Co., Ltd. | Current comparison type latch |
US6348882B1 (en) * | 2000-07-25 | 2002-02-19 | Philips Electronics North America Corporation | 5-ary receiver utilizing common mode insensitive differential offset comparator |
US6388521B1 (en) * | 2000-09-22 | 2002-05-14 | National Semiconductor Corporation | MOS differential amplifier with offset compensation |
US6825696B2 (en) * | 2001-06-27 | 2004-11-30 | Intel Corporation | Dual-stage comparator unit |
US6744284B2 (en) * | 2002-01-11 | 2004-06-01 | Samsung Electronics Co, Ltd. | Receiver circuit of semiconductor integrated circuit |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080042692A1 (en) * | 2006-08-15 | 2008-02-21 | International Business Machines Corporation | Voltage comparator apparatus and method having improved kickback and jitter characteristics |
US20090153196A1 (en) * | 2006-08-15 | 2009-06-18 | International Business Machines Corporation | Voltage comparator having improved kickback and jitter characteristics |
US7570082B2 (en) * | 2006-08-15 | 2009-08-04 | International Business Machines Corporation | Voltage comparator apparatus and method having improved kickback and jitter characteristics |
US8111090B2 (en) | 2006-08-15 | 2012-02-07 | International Business Machines Corporation | Voltage comparator having improved kickback and jitter characteristics |
Also Published As
Publication number | Publication date |
---|---|
US20030001625A1 (en) | 2003-01-02 |
US6825696B2 (en) | 2004-11-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6825696B2 (en) | Dual-stage comparator unit | |
Wu et al. | A 100-MHz pipelined CMOS comparator | |
JP3939122B2 (en) | Receiver circuit | |
US7362153B2 (en) | Receiver latch circuit and method | |
US5210506A (en) | Large swing output buffer amplifier | |
US20160233833A1 (en) | Apparatus and system for rail-to-rail amplifier | |
EP0585115B1 (en) | Analog multiplexer with standby mode | |
US4523107A (en) | Switched capacitor comparator | |
US6304206B1 (en) | Voltage comparator, operational amplifier and analog-to-digital conversion circuit employing the same | |
EP0613240B1 (en) | High gain rail-to-rail CMOS amplifier | |
US6400220B1 (en) | Autotracking feedback circuit and high speed A/D converter using same | |
US7180939B2 (en) | Active filter circuit with dynamically modifiable internal gain | |
US6778010B1 (en) | Amplifier slew-rate enhancement systems for use with switched-capacitor structures | |
US7091741B2 (en) | Input buffer capable of reducing input capacitance seen by input signal | |
US20060114061A1 (en) | Class AB CMOS output circuit equiped with CMOS circuit operating by predetermined operating current | |
US6831521B1 (en) | Method and apparatus for detecting interruption of an input signal with cancellation of offset level | |
US6219166B1 (en) | Optical receiver suitable for optical interconnects | |
US6617899B2 (en) | Ultra high speed clocked analog latch | |
WO2002097976A1 (en) | Ultra high speed clocked limiting preamplifier | |
US6480065B1 (en) | CMOS folding amplifier having high resolution and low power consumption | |
US6788136B2 (en) | Methods and apparatus for amplification in high temperature environments | |
US20040246030A1 (en) | Speeded up multistage comparator with power reduction and reliable output | |
US6593769B1 (en) | Differential, reduced swing buffer design | |
US5381060A (en) | Differential current switch to super buffer logic level translator | |
US6710660B1 (en) | Class B power buffer with rail to rail output swing and small deadband |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |