US20050153549A1 - Method of forming metal wiring for high voltage element - Google Patents

Method of forming metal wiring for high voltage element Download PDF

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US20050153549A1
US20050153549A1 US11/030,786 US3078605A US2005153549A1 US 20050153549 A1 US20050153549 A1 US 20050153549A1 US 3078605 A US3078605 A US 3078605A US 2005153549 A1 US2005153549 A1 US 2005153549A1
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copper
insulating film
film
etch process
hydrogen peroxide
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Ihl Cho
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Sk Keyfoundry Inc
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MagnaChip Semiconductor Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47J—KITCHEN EQUIPMENT; COFFEE MILLS; SPICE MILLS; APPARATUS FOR MAKING BEVERAGES
    • A47J37/00—Baking; Roasting; Grilling; Frying
    • A47J37/06—Roasters; Grills; Sandwich grills
    • A47J37/0694—Broiling racks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a method of forming metal wirings for high voltage elements, and more specifically, to a method of forming metal wirings of a semiconductor device for a high voltage power.
  • Cu copper having low resistance
  • the copper wirings is formed by depositing an interlayer insulating film, patterning the interlayer insulating film to fill the copper metal in an electroplating mode, and then polishing the copper metal.
  • the pattern density of copper exceeds about 90% or more. Therefore, the space of the metal wiring is very narrower than that of an existing copper wirings. If existing damascene techniques are employed, the amount of etching in an oxide film becomes very high since the space between coppers is very narrow. Even upon etching, it becomes difficult to secure the space. Furthermore, even in a polishing process, there is a problem in that copper is seriously eroded in a chemical mechanical polishing (CMP) process because the pattern density of copper is high.
  • CMP chemical mechanical polishing
  • the present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of forming metal wirings for high voltage elements in which the space between copper metals can be secured by forming a copper film on the entire surface and then patterning the copper film to form copper wirings.
  • a method of forming metal wirings for high voltage elements comprising the steps of: forming a copper anti-diffusion metal film, a copper film, a first copper anti-diffusion insulating film and a first interlayer insulating film on a semiconductor substrate in which high voltage elements are formed, patterning the first interlayer insulating film and the first copper anti-diffusion insulating film, wherein the copper film in a region where copper wirings are not formed is opened, and removing the copper film and the copper anti-diffusion metal film by performing an etch process using a chemical aqueous solution in which the first inferlayer insulating film is used as an etch mask, thus forming the copper wirings.
  • the etch process using the chemical aqueous solution is performed by using an etchant where sulfuric acid (H 2 SO 4 )/hydrogen peroxide (H 2 O 2 )/water (H 2 O) are mixed, wherein the ratio of sulfuric acid to hydrogen peroxide is 2:1, 4:1 or 6:1, and the etch process is performed at a temperature ranging from 100 to 140° C. for 2 to 10 minutes.
  • the etch process using the chemical aqueous solution is performed by using an etchant where ammonium hydroxide(NH 4 OH)/hydrogen peroxide(H 2 O 2 )/water (H 2 O) are mixed, wherein the ratio of ammonium hydroxide to hydrogen peroxide is 1:4 or 1:5, and the etch process is performed at a temperature ranging from 25 to 80° C. for 2 to 10 minutes.
  • an etchant where ammonium hydroxide(NH 4 OH)/hydrogen peroxide(H 2 O 2 )/water (H 2 O) are mixed, wherein the ratio of ammonium hydroxide to hydrogen peroxide is 1:4 or 1:5, and the etch process is performed at a temperature ranging from 25 to 80° C. for 2 to 10 minutes.
  • the etch process using the chemical aqueous solution is performed by using an etchant where hydrochloric acid (HCI)/hydrogen peroxide (H 2 O 2 )/water (H 2 O) are mixed, wherein the ratio of hydrochloric acid to hydrogen peroxide is 1:1 or 1:2, and the etch process is performed at a temperature ranging from 25 to 80° C. for 2 to 10 minutes.
  • HCI hydrochloric acid
  • H 2 O 2 hydrogen peroxide
  • water H 2 O
  • the etch process using the chemical aqueous solution is performed by using an etchant where hydrogen fluoride (HF)/hydrogen peroxide (H 2 O 2 )/water (H 2 O) are mixed, wherein the ratio of hydrogen fluoride to hydrogen peroxide is 1:5 or 1:10, and the etch process is performed at a temperature ranging from 15 to 35° C. for 2 to 10 minutes.
  • HF hydrogen fluoride
  • H 2 O 2 hydrogen peroxide
  • water H 2 O
  • the method further comprises the steps of, after the copper wirings are formed, forming a second copper anti-diffusion insulating film on the entire surface along the step of the surface, forming a second interlayer insulating film on the entire surface, patterning the second interlayer insulating film and the second copper anti-diffusion insulating film to form via holes, and burying the via holes with copper and then polishing the via holes.
  • the method further comprises the step of, after the step (d) of forming the second copper anti-diffusion insulating film, performing a polishing process using the first interlayer insulating film as a stop layer.
  • FIGS. 1 a to 1 d are sectional views for explaining a method of forming copper wirings according to an embodiment of the present invention.
  • FIGS. 1 a to 1 d are sectional views for explaining a method of forming copper wirings according to an embodiment of the present invention.
  • a copper anti-diffusion metal film 20 , a copper film 30 , a first copper anti-diffusion insulating film 40 and a first interlayer insulating film 50 are sequentially formed on a semiconductor substrate 10 in which various elements (semiconductor structure) including high voltage elements (not shown) such as a well, an element isolation film, a transistor and a contact plug are formed.
  • Photoresist patterns 60 for forming copper wirings are formed on the first interlayer insulating film 50 .
  • a predetermined ion implant process is performed on the semiconductor substrate 10 to form the well (not shown).
  • An element isolation process is performed to form the element isolation film (not shown) for electrical isolation between elements.
  • a gate oxide film (not shown) for the high voltage elements and a conductive film (not shown) are formed and are then patterned to form a gate electrode (not shown) for high voltage power electronics.
  • An ion implant process is then carried out to form a junction region.
  • a spacer (not shown) is formed on the sidewall of the gate electrode.
  • another ion implant process can be performed to form source/drain (not shown).
  • An insulating film is deposited on the entire surface and is then patterned to form a contact hole. The contact hole can be filled with a copper film in order to form a copper contact plug (not shown).
  • the copper anti-diffusion metal film 20 is then formed on the semiconductor substrate 10 in which various elements such as the high voltage elements are formed as such.
  • the copper anti-diffusion metal film 20 can be formed by using at least one of Ta, TaN, Ta/TaN, Ti, TiN, Ti/TiN, W, WN and W/WN. It is also preferred that the first copper anti-diffusion insulating film 40 is formed by using at least one of SiN, SiC, SiCN and SiOCN.
  • the first interlayer insulating film 50 is preferably formed by using an IMD (Inter-Metal Dielectric) oxide film.
  • the copper film 30 can be formed by depositing a copper seed film (not shown) on the copper anti-diffusion metal film 20 and then performing a metal plating method.
  • the copper seed film is deposited by means of a sputtering method.
  • the copper film 30 is preferably formed to have a given thickness by performing an electroplating method.
  • the photoresist pattern 60 can be formed in such a manner that a photoresist is coated on the entire surface, and the photoresist remains in a region where the copper wirings will be formed and the space region between the metal wirings is opened, by means of a photolithography process using the photoresist mask.
  • the photoresist pattern 60 is preferably formed in the same pattern as the metal wiring, which will be formed by a subsequent process, but has the region where the photoresist remains, the width of which is 5 to 200 times wider than that of the opened region. More preferably, the width of the region where the photoresist remains is 60 to 150 times wider than that of the opened region. This allows high voltage and high current to transmitted, lower resistance of the metal wiring, and improves reliability of wirings.
  • an etch process using the photoresist pattern 60 as an etch mask is performed to remove the first interlayer insulating film 50 and the first copper anti-diffusion insulating film 40 .
  • a predetermined strip process is performed to strip the photoresist pattern 60 .
  • a wet etch process using a chemical solution is carried out to etch the copper film 40 , thus forming copper wirings 35 .
  • the first interlayer insulating film 50 and the first copper anti-diffusion insulating film 40 are stripped by sequentially performing a dry etch process.
  • the chemical solution is preferably an aqueous solution containing an oxidant such as H 2 O 2 , which can remove the copper metal.
  • the wet etch process using the chemical solution is performed for a predetermined time by using the first interlayer insulating film 50 as the etch mask, thereby removing the copper film 30 .
  • the chemical solution may employ an etchant in which sulfuric acid (H 2 SO 4 )/hydrogen peroxide (H 2 O 2 )/water (H 2 O) are mixed, wherein the ratio of sulfuric acid to hydrogen peroxide is preferably 2:1, 4:1 or 6:1.
  • a temperature of the etchant (chemical solution) in which sulfuric acid/hydrogen peroxide/water are mixed is set to 100 to 140° C., and the semiconductor substrate is dipped into the etchant for 2 to 10 minutes.
  • the chemical solution may employ an etchant where ammonium hydroxide (NH 4 OH)/hydrogen peroxide (H 2 O 2 )/water (H 2 O) are mixed.
  • the ratio of ammonium hydroxide to hydrogen peroxide is preferably 1:4 or 1:5. This can prevent excessive etch of the copper metal, which is caused by the ratio of ammonium hydroxide and hydrogen peroxide.
  • the wet etch process is performed under the condition where a temperature of the etchant (chemical solution) where ammonia/hydrogen peroxide/water are mixed is set to 25 to 80° C. and the semiconductor substrate is dipped into the etchant for 2 to 10 minutes.
  • the chemical solution may employ an etchant in which hydrochloric acid (HCI)/hydrogen peroxide (H 2 O 2 )/water (H 2 O) are mixed, wherein the ratio of hydrochloric acid to hydrogen peroxide is preferably 1:1 or 1:2.
  • HCI hydrochloric acid
  • H 2 O 2 hydrochloric acid
  • water H 2 O
  • the ratio of hydrochloric acid to hydrogen peroxide is preferably 1:1 or 1:2.
  • the wet etch process is performed under the condition where a temperature of the etchant (chemical solution) where hydrochloric acid/hydrogen peroxide/water are mixed is set to 25 to 80° C., and the semiconductor substrate is dipped into the etchant for 2 to 10 minutes.
  • the chemical solution may employ an etchant in which hydrogen fluoride (HF)/hydrogen peroxide (H 2 O 2 )/water (H 2 O) are mixed, wherein the ratio of hydrogen fluoride to hydrogen peroxide is preferably 1:5 or 1:10.
  • HF hydrogen fluoride
  • H 2 O 2 hydrogen peroxide
  • water H 2 O
  • the ratio of hydrogen fluoride to hydrogen peroxide is preferably 1:5 or 1:10.
  • the wet etch process is performed under the condition where a temperature of the etchant (the chemical solution) in which ammonia/hydrogen peroxide/water are mixed is set to 15 to 35° C., and the semiconductor substrate is dipped into the etchant for 2 to 10 minutes.
  • the time where the semiconductor substrate 10 is dipped in the etchant is performed until electrical isolation between the copper wirings 35 is completely accomplished. That is, it is possible to secure the space between the metal wirings, which is narrower than the width of the metal wiring by controlling the wet etch time. It is also possible to cut manufacture cost by forming the copper wirings by means of the wet etch process not forming the copper wirings by means of a damascene process.
  • a second copper anti-diffusion insulating film 70 is formed on the entire surface along the step of the surface. After depositing a second interlayer insulating film 80 on the entire surface, a polishing process is performed to polish the second interlayer insulating film 80 .
  • the second copper anti-diffusion insulating film 70 is preferably formed by using at least one of SiN, SiC, SiCN and SiOCN.
  • the second copper anti-diffusion insulating film 70 is formed in the space between the copper wirings, and it can prevent copper atoms of the copper wirings 35 , which is exposed by means of the wet etch process using the chemical solution, from diffusing.
  • the second interlayer insulating film 80 is formed using an IMD oxide film. In this time, it is preferred that a polishing process using CMP is carried out so as to reduce the step caused by a region which is removed by means of the wet etch.
  • the second interlayer insulating film 80 and the second copper anti-diffusion insulating film 70 are patterned to form a via hole.
  • the via hole is buried and polished by using a copper film, thus forming copper via plugs 90 .
  • a photoresist is coated on the second interlayer insulating film 80 .
  • a photolithography process is then performed to form a photoresist pattern (not shown) through which some regions of the top of the copper wirings are opened.
  • An etch process using the photoresist pattern as an etch mask is then performed to remove the second interlayer insulating film 80 and the second copper anti-diffusion insulating film 70 , thereby forming a via hole.
  • the photoresist pattern is then removed.
  • a copper plating film is formed by performing an electroplating method.
  • a predetermined thermal treatment process is performed. Then, the copper plating film, the copper seed film and the anti-diffusion metal film on the second interlayer insulating film 80 are removed to form the copper via plugs 90 .
  • a wet etch process using an interlayer insulating film as an etch mask is performed to pattern the copper film. It is thus possible to form copper wirings for high voltage elements the width of which is very wide.
  • the space between metal wirings which is narrower than a width of the metal wiring, can be secured sufficiently.

Abstract

Disclosed herein is a method of forming metal wirings for high voltage elements. According to the present invention, after a copper film is formed, a wet etch process using an interlayer insulating film as an etch mask is performed to pattern the copper film. It is thus possible to form copper wirings for high voltage elements the width of which is very wide. Furthermore, a wet etch process using a chemical aqueous solution is performed instead of a copper polishing process. The cost for forming a metal wiring can be thus saved. Moreover, by controlling a wet etch time, the space between metal wirings, which is narrower than a width of the metal wiring, can be secured sufficiently.

Description

    BACKGROUND
  • 1. Field of the Invention
  • The present invention relates to a method of forming metal wirings for high voltage elements, and more specifically, to a method of forming metal wirings of a semiconductor device for a high voltage power.
  • 2. Discussion of Related Art
  • Recently, as semiconductor devices are gradually higher integrated and becoming high density, copper (Cu) having low resistance has been used in a metal wiring, which is formed by means of a damascene process. That is, the copper wirings is formed by depositing an interlayer insulating film, patterning the interlayer insulating film to fill the copper metal in an electroplating mode, and then polishing the copper metal.
  • However, in a metal wiring for a high voltage power, the pattern density of copper exceeds about 90% or more. Therefore, the space of the metal wiring is very narrower than that of an existing copper wirings. If existing damascene techniques are employed, the amount of etching in an oxide film becomes very high since the space between coppers is very narrow. Even upon etching, it becomes difficult to secure the space. Furthermore, even in a polishing process, there is a problem in that copper is seriously eroded in a chemical mechanical polishing (CMP) process because the pattern density of copper is high.
    • SUMMARY OF THE INVENTION
  • Accordingly, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of forming metal wirings for high voltage elements in which the space between copper metals can be secured by forming a copper film on the entire surface and then patterning the copper film to form copper wirings.
  • To achieve the above object, according to an aspect of the present invention, there is provided a method of forming metal wirings for high voltage elements, comprising the steps of: forming a copper anti-diffusion metal film, a copper film, a first copper anti-diffusion insulating film and a first interlayer insulating film on a semiconductor substrate in which high voltage elements are formed, patterning the first interlayer insulating film and the first copper anti-diffusion insulating film, wherein the copper film in a region where copper wirings are not formed is opened, and removing the copper film and the copper anti-diffusion metal film by performing an etch process using a chemical aqueous solution in which the first inferlayer insulating film is used as an etch mask, thus forming the copper wirings.
  • Preferably, the etch process using the chemical aqueous solution is performed by using an etchant where sulfuric acid (H2SO4)/hydrogen peroxide (H2O2)/water (H2O) are mixed, wherein the ratio of sulfuric acid to hydrogen peroxide is 2:1, 4:1 or 6:1, and the etch process is performed at a temperature ranging from 100 to 140° C. for 2 to 10 minutes.
  • Preferably, the etch process using the chemical aqueous solution is performed by using an etchant where ammonium hydroxide(NH4OH)/hydrogen peroxide(H2O2)/water (H2O) are mixed, wherein the ratio of ammonium hydroxide to hydrogen peroxide is 1:4 or 1:5, and the etch process is performed at a temperature ranging from 25 to 80° C. for 2 to 10 minutes.
  • Preferably, the etch process using the chemical aqueous solution is performed by using an etchant where hydrochloric acid (HCI)/hydrogen peroxide (H2O2)/water (H2O) are mixed, wherein the ratio of hydrochloric acid to hydrogen peroxide is 1:1 or 1:2, and the etch process is performed at a temperature ranging from 25 to 80° C. for 2 to 10 minutes.
  • Preferably, the etch process using the chemical aqueous solution is performed by using an etchant where hydrogen fluoride (HF)/hydrogen peroxide (H2O2)/water (H2O) are mixed, wherein the ratio of hydrogen fluoride to hydrogen peroxide is 1:5 or 1:10, and the etch process is performed at a temperature ranging from 15 to 35° C. for 2 to 10 minutes.
  • Preferably, the method further comprises the steps of, after the copper wirings are formed, forming a second copper anti-diffusion insulating film on the entire surface along the step of the surface, forming a second interlayer insulating film on the entire surface, patterning the second interlayer insulating film and the second copper anti-diffusion insulating film to form via holes, and burying the via holes with copper and then polishing the via holes.
  • Preferably, the method further comprises the step of, after the step (d) of forming the second copper anti-diffusion insulating film, performing a polishing process using the first interlayer insulating film as a stop layer.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1 a to 1 d are sectional views for explaining a method of forming copper wirings according to an embodiment of the present invention.
    • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • Now, the preferred embodiments according to the present invention will be described with reference to the accompanying drawings.
  • FIGS. 1 a to 1 d are sectional views for explaining a method of forming copper wirings according to an embodiment of the present invention.
  • Referring to FIG. 1 a, a copper anti-diffusion metal film 20, a copper film 30, a first copper anti-diffusion insulating film 40 and a first interlayer insulating film 50 are sequentially formed on a semiconductor substrate 10 in which various elements (semiconductor structure) including high voltage elements (not shown) such as a well, an element isolation film, a transistor and a contact plug are formed. Photoresist patterns 60 for forming copper wirings are formed on the first interlayer insulating film 50.
  • In the above, a predetermined ion implant process is performed on the semiconductor substrate 10 to form the well (not shown). An element isolation process is performed to form the element isolation film (not shown) for electrical isolation between elements. A gate oxide film (not shown) for the high voltage elements and a conductive film (not shown) are formed and are then patterned to form a gate electrode (not shown) for high voltage power electronics. An ion implant process is then carried out to form a junction region. A spacer (not shown) is formed on the sidewall of the gate electrode. In this time, another ion implant process can be performed to form source/drain (not shown). An insulating film is deposited on the entire surface and is then patterned to form a contact hole. The contact hole can be filled with a copper film in order to form a copper contact plug (not shown). The copper anti-diffusion metal film 20 is then formed on the semiconductor substrate 10 in which various elements such as the high voltage elements are formed as such.
  • Preferably, the copper anti-diffusion metal film 20 can be formed by using at least one of Ta, TaN, Ta/TaN, Ti, TiN, Ti/TiN, W, WN and W/WN. It is also preferred that the first copper anti-diffusion insulating film 40 is formed by using at least one of SiN, SiC, SiCN and SiOCN. The first interlayer insulating film 50 is preferably formed by using an IMD (Inter-Metal Dielectric) oxide film.
  • Preferably, the copper film 30 can be formed by depositing a copper seed film (not shown) on the copper anti-diffusion metal film 20 and then performing a metal plating method. The copper seed film is deposited by means of a sputtering method. The copper film 30 is preferably formed to have a given thickness by performing an electroplating method.
  • The photoresist pattern 60 can be formed in such a manner that a photoresist is coated on the entire surface, and the photoresist remains in a region where the copper wirings will be formed and the space region between the metal wirings is opened, by means of a photolithography process using the photoresist mask. The photoresist pattern 60 is preferably formed in the same pattern as the metal wiring, which will be formed by a subsequent process, but has the region where the photoresist remains, the width of which is 5 to 200 times wider than that of the opened region. More preferably, the width of the region where the photoresist remains is 60 to 150 times wider than that of the opened region. This allows high voltage and high current to transmitted, lower resistance of the metal wiring, and improves reliability of wirings.
  • Referring to FIG. 1 b, an etch process using the photoresist pattern 60 as an etch mask is performed to remove the first interlayer insulating film 50 and the first copper anti-diffusion insulating film 40. A predetermined strip process is performed to strip the photoresist pattern 60. A wet etch process using a chemical solution is carried out to etch the copper film 40, thus forming copper wirings 35.
  • The first interlayer insulating film 50 and the first copper anti-diffusion insulating film 40 are stripped by sequentially performing a dry etch process. In this time, the chemical solution is preferably an aqueous solution containing an oxidant such as H2O2, which can remove the copper metal.
  • Furthermore, the wet etch process using the chemical solution is performed for a predetermined time by using the first interlayer insulating film 50 as the etch mask, thereby removing the copper film 30.
  • In the above, the chemical solution may employ an etchant in which sulfuric acid (H2SO4)/hydrogen peroxide (H2O2)/water (H2O) are mixed, wherein the ratio of sulfuric acid to hydrogen peroxide is preferably 2:1, 4:1 or 6:1. In this time, it is preferred that the wet etch process is performed under the condition where a temperature of the etchant (chemical solution) in which sulfuric acid/hydrogen peroxide/water are mixed is set to 100 to 140° C., and the semiconductor substrate is dipped into the etchant for 2 to 10 minutes.
  • Furthermore, the chemical solution may employ an etchant where ammonium hydroxide (NH4OH)/hydrogen peroxide (H2O2)/water (H2O) are mixed. The ratio of ammonium hydroxide to hydrogen peroxide is preferably 1:4 or 1:5. This can prevent excessive etch of the copper metal, which is caused by the ratio of ammonium hydroxide and hydrogen peroxide. It is preferred that the wet etch process is performed under the condition where a temperature of the etchant (chemical solution) where ammonia/hydrogen peroxide/water are mixed is set to 25 to 80° C. and the semiconductor substrate is dipped into the etchant for 2 to 10 minutes.
  • Furthermore, the chemical solution may employ an etchant in which hydrochloric acid (HCI)/hydrogen peroxide (H2O2)/water (H2O) are mixed, wherein the ratio of hydrochloric acid to hydrogen peroxide is preferably 1:1 or 1:2. This can prevent excessive etch of the copper metal, which is caused by the ratio of hydrochloric acid and hydrogen peroxide. It is preferred that the wet etch process is performed under the condition where a temperature of the etchant (chemical solution) where hydrochloric acid/hydrogen peroxide/water are mixed is set to 25 to 80° C., and the semiconductor substrate is dipped into the etchant for 2 to 10 minutes.
  • Furthermore, the chemical solution may employ an etchant in which hydrogen fluoride (HF)/hydrogen peroxide (H2O2)/water (H2O) are mixed, wherein the ratio of hydrogen fluoride to hydrogen peroxide is preferably 1:5 or 1:10. This can prevent excessive etch of the copper metal, which is caused by the ratio of ammonium hydroxide and hydrogen peroxide. It is preferred that the wet etch process is performed under the condition where a temperature of the etchant (the chemical solution) in which ammonia/hydrogen peroxide/water are mixed is set to 15 to 35° C., and the semiconductor substrate is dipped into the etchant for 2 to 10 minutes.
  • It is preferred that the time where the semiconductor substrate 10 is dipped in the etchant is performed until electrical isolation between the copper wirings 35 is completely accomplished. That is, it is possible to secure the space between the metal wirings, which is narrower than the width of the metal wiring by controlling the wet etch time. It is also possible to cut manufacture cost by forming the copper wirings by means of the wet etch process not forming the copper wirings by means of a damascene process.
  • Referring to FIG. 1 c, a second copper anti-diffusion insulating film 70 is formed on the entire surface along the step of the surface. After depositing a second interlayer insulating film 80 on the entire surface, a polishing process is performed to polish the second interlayer insulating film 80.
  • The second copper anti-diffusion insulating film 70 is preferably formed by using at least one of SiN, SiC, SiCN and SiOCN. The second copper anti-diffusion insulating film 70 is formed in the space between the copper wirings, and it can prevent copper atoms of the copper wirings 35, which is exposed by means of the wet etch process using the chemical solution, from diffusing. The second interlayer insulating film 80 is formed using an IMD oxide film. In this time, it is preferred that a polishing process using CMP is carried out so as to reduce the step caused by a region which is removed by means of the wet etch.
  • In this time, after the second copper anti-diffusion insulating film 70 is formed, a polishing process using the first interlayer insulating film 50 as a stop layer is performed, so that the second copper anti-diffusion insulating film 70 is formed only in the region between the copper wirings 35.
  • Referring to FIG. 1 d, the second interlayer insulating film 80 and the second copper anti-diffusion insulating film 70 are patterned to form a via hole. The via hole is buried and polished by using a copper film, thus forming copper via plugs 90.
  • A photoresist is coated on the second interlayer insulating film 80. A photolithography process is then performed to form a photoresist pattern (not shown) through which some regions of the top of the copper wirings are opened. An etch process using the photoresist pattern as an etch mask is then performed to remove the second interlayer insulating film 80 and the second copper anti-diffusion insulating film 70, thereby forming a via hole. The photoresist pattern is then removed. After an anti-diffusion metal film (not shown) and a copper seed film (not shown) are formed on the entire surface, a copper plating film is formed by performing an electroplating method. A predetermined thermal treatment process is performed. Then, the copper plating film, the copper seed film and the anti-diffusion metal film on the second interlayer insulating film 80 are removed to form the copper via plugs 90.
  • According to the present invention described above, after a copper film is formed, a wet etch process using an interlayer insulating film as an etch mask is performed to pattern the copper film. It is thus possible to form copper wirings for high voltage elements the width of which is very wide.
  • Furthermore, a wet etch process using a chemical aqueous solution is performed instead of a copper polishing process. The cost for forming a metal wiring can be thus saved.
  • Moreover, by controlling a wet etch time, the space between metal wirings, which is narrower than a width of the metal wiring, can be secured sufficiently.
  • Although the foregoing description has been made with reference to the preferred embodiments, it is to be understood that changes and modifications of the present invention may be made by the ordinary skilled in the art without departing from the spirit and scope of the present invention and appended claims.

Claims (7)

1. A method of forming metal wirings for high voltage elements, comprising the steps of:
(a) forming a copper anti-diffusion metal film, a copper film, a first copper anti-diffusion insulating film and a first interlayer insulating film on a semiconductor substrate in which high voltage elements are formed;
(b) patterning the first interlayer insulating film and the first copper anti-diffusion insulating film, wherein the copper film in a region where copper wirings are not formed is opened; and
(c) removing the copper film and the copper anti-diffusion metal film by performing an etch process using a chemical aqueous solution in which the first interlayer insulating film is used as an etch mask, thus forming the copper wirings.
2. The method as claimed in claim 1, wherein the etch process using the chemical aqueous solution is performed by using an etchant where sulfuric acid (H2SO4)/hydrogen peroxide (H2O2)/water (H2O) are mixed, wherein the ratio of sulfuric acid to hydrogen peroxide is 2:1, 4:1 or 6:1, and the etch process is performed at a temperature ranging from 100 to 140° C. for 2 to 10 minutes.
3. The method as claimed in claim 1, wherein the etch process using the chemical aqueous solution is performed by using an etchant where ammonium hydroxide(NH4OH)/hydrogen peroxide(H2O2)/water (H2O) are mixed, wherein the ratio of ammonium hydroxide to hydrogen peroxide is 1:4 or 1:5, and the etch process is performed at a temperature ranging from 25 to 80° C. for 2 to 10 minutes.
4. The method as claimed in claim 1, wherein the etch process using the chemical aqueous solution is performed by using an etchant where hydrochloric acid (HCI)/hydrogen peroxide (H2O2)/water (H2O) are mixed, wherein the ratio of hydrochloric acid to hydrogen peroxide is 1:1 or 1:2, and the etch process is performed at a temperature ranging from 25 to 80° C. for 2 to 10 minutes.
5. The method as claimed in claim 1, wherein the etch process using the chemical aqueous solution is performed by using an etchant where hydrogen fluoride (HF)/hydrogen peroxide (H2O2)/water (H2O) are mixed, wherein the ratio of hydrogen fluoride to hydrogen peroxide is 1:5 or 1:10, and the etch process is performed at a temperature ranging from 15 to 35° C. for 2 to 10 minutes.
6. The method as claimed in claim 1, further comprising the steps of, after the copper wirings are formed,
(d) forming a second copper anti-diffusion insulating film on the entire surface along the step of the surface;
(e) forming a second interlayer insulating film on the entire surface;
(f) patterning the second interlayer insulating film and the second copper anti-diffusion insulating film to form via holes; and
(g) burying the via holes with copper and then polishing the via holes.
7. The method as claimed in claim 6, further comprising the step of, after the step (d) of forming the second copper anti-diffusion insulating film, performing a polishing process using the first interlayer insulating film as a stop layer.
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