US20050156154A1 - Protecting Silicon Germanium Sidewall with Silicon for Strained Silicon/Silicon Germanium MOSFETs - Google Patents

Protecting Silicon Germanium Sidewall with Silicon for Strained Silicon/Silicon Germanium MOSFETs Download PDF

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US20050156154A1
US20050156154A1 US10/707,840 US70784004A US2005156154A1 US 20050156154 A1 US20050156154 A1 US 20050156154A1 US 70784004 A US70784004 A US 70784004A US 2005156154 A1 US2005156154 A1 US 2005156154A1
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silicon
silicon layer
raised
semiconductor structure
drain region
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Huilong Zhu
Bruce Doris
Dan Mocuta
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GlobalFoundries Inc
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors

Definitions

  • the invention generally relates to a semiconductor device and method of manufacture and, more particularly, to a semiconductor device that includes strained silicon/silicon germanium field effect transistors with a protective silicon layer.
  • SOI Silicon On Insulator
  • RSD raised source/drain
  • selective epitaxial growth of silicon has been used to grow silicon on the source/drain and the top of poly gates, leaving no silicon on gate sidewall spacers.
  • epitaxial growth must take place at temperatures as high as 750° C., which may cause significant transient enhanced diffusion of dopants.
  • the unnecessary dopant redistribution in halo/extension regions degrades the performance of devices and short channel immunity.
  • SOI film it can be difficult to form epitaxial silicon without causing silicon agglomeration due to possible contamination of carbon in certain chemical vapor deposition tools.
  • Another technique involves SiGe selective epitaxial growth on source/drain regions.
  • this technique eliminates transient enhanced diffusion of dopants which may otherwise occur at high temperatures.
  • Ge degrades silicide contact formation and contact resistance due to its inherent function as a diffusion barrier.
  • the surface of SiGe may be capped with additional epitaxial silicon, using a high temperature process, which may cause transient enhanced diffusion.
  • the invention is directed to overcoming one or more of the problems as set forth above.
  • a method of fabricating a semiconductor structure entails forming a raised source region on a substrate. A raised drain region is also formed on the substrate. Next, a first silicon layer is formed over the raised source region and a second silicon layer is formed over the raised drain region.
  • the method includes forming sacrificial spacers along the sidewalls of the first silicon layer and the second silicon layer. After forming the spacers, third and fourth silicon layers are formed on the raised source and raised drain regions, respectively.
  • a semiconductor structure in a third aspect of the invention, includes a substrate; a raised source region on the substrate, a raised drain region on the substrate; a first silicon layer over the raised source region and a second silicon layer over the raised drain region.
  • the raised source and drain regions thus include one or more silicon layers on sidewalls of the source and drain regions.
  • the silicon prevents adverse effects of Ge during silicidation, including Ge out diffusion and silicide line breakage.
  • the Si also increases the active area.
  • FIG. 1 shows a first side cutaway view of an exemplary semiconductor structure with a raised source and drain according to the principles of the invention
  • FIG. 2 shows a top view of an exemplary semiconductor structure with a raised source and drain according to the principles of the invention
  • FIG. 3 shows a second side cutaway view of an exemplary semiconductor structure with a raised source and drain according to the principles of the invention
  • FIG. 4 shows cutaway view of an exemplary semiconductor structure with a raised source and drain and a protective silicon layer according to the principles of the invention.
  • FIG. 5 shows cutaway view of an exemplary semiconductor structure with a raised source and drain, a protective silicon layer and sacrificial spacers according to the principles of the invention.
  • the invention enables fabrication of raised Si/SiGe source and drain regions with epitaxially grown silicon on SiGe sidewalls.
  • the silicon prevents adverse effects of Ge during silicidation, including Ge out diffusion and silicide line breakage.
  • the Si also increases the active area.
  • the exemplary initial structure is comprised of an SOI substrate 105 having a patterned gate stack region 110 formed on the surface thereof.
  • the SOI substrate 105 may include a buried oxide layer 125 sandwiched between a top Si-containing layer 130 and a bottom Si-containing layer 140 .
  • the top Si-containing layer 130 is an area upon which devices may be formed.
  • the Si-containing layer 130 may be comprised of various semiconducting materials that include silicon, such as Si, SiGe, SiC, SiGeC, Si/Si, or Si/SiGe.
  • the SOI substrate 105 employed in the present invention may be fabricated using techniques well known to those skilled in the art.
  • the SOI substrate may be formed by a conventional bonding and cutting processes, or alternatively, a conventional separation by implantation of oxygen (SIMOX) process.
  • SIMOX separation by implantation of oxygen
  • the top Si-containing layer 130 may have a thickness of about 5 to 250 nm.
  • Isolation structures such as shallow-trench isolations (STIs) 180 and 185 , are also provided in the exemplary initial structure.
  • Techniques known in the art may be utilized to form STIs 180 and 185 .
  • a conventional technique entails patterning with a photoresist, etching the trench, chemical vapor deposition of oxide to fill the trench, and planarizing the surface such as by chemical mechanical polishing. Subsequently, the top surface of the STI form ations 180 and 185 may be etched down, as discussed more fully below.
  • the patterned gate stack region 110 may be formed atop the Si-containing layer using processing techniques well known in the art.
  • the patterned gate stack region 110 may be fabricated by first forming gate dielectric 125 on an exposed surface of the top Si-containing layer 130 .
  • the gate dielectric layer 125 may be formed by a conventional deposition process such as CVD or plasma-assisted CVD, or a thermal growing process such as oxidation, nitridation or oxynitridation.
  • the gate dielectric may include any device quality dielectric material such as an oxide, nitride, oxynitride or any combination and multilayer thereof. The thickness of the gate dielectric is not critical to the present invention.
  • the gate stack 110 is formed on the gate dielectric 125 utilizing a conventional deposition process such as CVD, plasma-assisted CVD or plating.
  • the gate stack 110 may include a gate material such as polysilicon, amorphous silicon or other materials suitable for MOSFET gate composition.
  • the gate material may be formed on the surface of gate dielectric 125 utilizing conventional deposition processes well known in the art such as, for example, CVD or plasma-assisted CVD.
  • An optional dielectric-capping layer (not shown) may be present atop the gate material.
  • the optional dielectric-capping layer may typically be comprised of an oxide, nitride or oxynitride and formed utilizing a conventional deposition process such as, for example, CVD or plasma-assisted CVD.
  • a conventional thermal growing process such as, for example, oxidation, may be used in forming an optional dielectric-capping layer.
  • the gate stack 110 and gate dielectric layer 125 are subjected to a conventional patterning process which includes lithography and etching steps.
  • the lithography step may entails applying a photoresist, exposing the photoresist to a pattern of radiation, and developing the pattern utilizing a conventional resist developer.
  • a conventional etching process such as reactive-ion etching, plasma etching, ion beam etching or laser ablation may be employed in transferring the pattern to the gate stack 110 and the gate dielectric 125 .
  • Spacers 115 and 120 are formed along gate sidewalls.
  • spacer material such as a nitride (e.g., Si 3 N 4 ) may be deposited in a conventional manner, such as by chemical vapor deposition (CVD) using a silane source.
  • CVD chemical vapor deposition
  • Other techniques which may be suitable for deposition of a nitride layer, include low-pressure CVD (LPCVD) and atmospheric pressure (CVD) (APCVD). Portions of the deposited nitride layer are subsequently etched away in a conventional manner to form the spacers 115 and 120 .
  • LPCVD low-pressure CVD
  • APCVD atmospheric pressure
  • exemplary source and drain regions 160 and 175 are comprised of SiGe layers 150 and 165 capped with strained silicon layers 155 and 170 .
  • the SiGe layers 150 and 165 may be selectively epitaxially grown in a conventional manner using ultrahigh-vacuum chemical vapor deposition (UHVCVD), molecular beam epitaxy (MBE), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), and low energy plasma enhanced chemical vapor deposition (LEPECVD).
  • UHVCVD ultrahigh-vacuum chemical vapor deposition
  • MBE molecular beam epitaxy
  • LPCVD low pressure chemical vapor deposition
  • RTCVD rapid thermal chemical vapor deposition
  • LEPECVD low energy plasma enhanced chemical vapor deposition
  • the SiGe layers 150 and 165 may be comprised, in whole or in part, of the top silicon-containing layer 130 of the SOI substrate 105 .
  • Silicon layers 155 and 170 may be formed on the SiGe layers 150 and 165 of the raised source and drain regions 160 and 175 , respectively, using a conventional selective epitaxial silicon formation technique. For example, molecular beam epitaxy (MBE) may be used to selectively grow device quality silicon. Because Si has a smaller lattice constant (i.e., atom spacing) than Ge, when Si 155 and 170 is grown on the SiGe layer 160 and 165 , the Si 155 and 170 is strained in tension. A suitable thickness for the strained Si layers 155 and 170 is below the critical thickness, which is the maximum thickness that strained Si can grow on the SiGe SiGe layers 150 and 165 without forming defects in the crystal structure (e.g., dislocations). By way of example but not limitation, the strained Si layer 155 may be approximately 5 to 100 nm thick.
  • FIG. 2 a top view of the exemplary initial structure is shown.
  • Raised drain 160 and source 175 regions are provided adjacent to nitride spacer sides 115 and 120 , respectively.
  • the nitride spacer 210 surrounds the sidewalls of the gate 110 .
  • the shallow trench isolation 220 including STI sides 180 and 185 , surround the active area.
  • the cutaway view represented in FIG. 1 is denoted by cutaway line A-A in FIG. 2 .
  • FIG. 3 a side view of a cutaway section represented by line B-B in FIG. 2 is shown.
  • STI oxide portions 230 and 240 are shown alongside the raised drain 160 comprised of SiGe layer 150 and strained Si layer 160 .
  • the top layer 130 of the exemplary SOI substrate may be comprised of the same material as the raised drain layer 150 , namely SiGe.
  • SiGe layers 150 and 165 may be comprised of the top layer of the exemplary SOI substrate.
  • STIs may be formed from the SOI substrate surface to the top of the buried oxide layer 135 .
  • the STI oxide may be etched to reveal the raised SiGe portions of raised source and drain regions, such as SiGe layer 150 in FIG. 3 . This approach for raised source and drain formation may obviate the need to form layer 150 separately by epitaxial growth as described above.
  • the raised drain 160 is protected with a silicon layer 400 , as shown in FIG. 4 .
  • silicon is selectively epitaxially grown on the SiGe sidewalls of the raised drain 160 , forming protective silicon sidewalls 410 and 420 .
  • the selective epitaxial process also results in growth of silicon on the strained silicon layer 155 , forming silicon cap 430 for the raised drain 160 .
  • the epitaxial silicon layer 400 may be formed using conventional selective epitaxial growing processes known in the art, such as molecular beam epitaxy.
  • a thick silicon layer 400 along the sidewalls 410 and 420 may run the risk of bridging, i.e., forming an undesired connection between features (such as source and gate or drain and gate) of the device or between features of adjacent devices.
  • sacrificial oxide spacers 505 and 525 may be formed after an initial layer of silicon 500 is selectively epitaxially formed on the raised drain 160 .
  • silicon may be selectively epitaxially grown on the SiGe sidewalls of the raised drain 160 , forming protective silicon sidewalls 510 and 520 .
  • the selective epitaxial process also results in growth of silicon 515 on the strained silicon layer 155 .
  • the epitaxial silicon layer 500 may be formed using conventional selective epitaxial growing processes known in the art, such as molecular beam epitaxy.
  • the spacers 505 and 525 may be formed along the Si coated SiGe sidewalls of the raised drain in a conventional manner, such as by oxide deposition, patterning and etching using processes known in the art. After formation of the spacers, an additional selective epitaxial growth step may be performed to complete formation of the raised drain. The oxide spacers 505 and 525 will prevent further formation of Si along the sidewalls during the additional selective epitaxial growth step. After completing the sadditional selective epitaxial growth step, the oxide spacers may be removed, such as by dry etching.
  • silicide contacts may be formed on the epitaxial silicon layer utilizing a conventional silicidation process.
  • the presence of Ge in the SiGe underlying the silicon layer 400 (or 500 ) will not interfere with, degrade or otherwise adversely impact the silicidation process.
  • FIG. 1 shows only one patterned gate stack region and corresponding raised source and drain regions
  • the invention applies equally as well when a plurality of patterned gate stacks and corresponding raised source and drain regions are formed on the SOI substrate.
  • the invention is not limited to the embodiment wherein a single patterned gate stack region is employed.

Abstract

Raised Si/SiGe source and drain regions include epitaxially grown silicon on SiGe sidewalls. The epi silicon prevents adverse effects of Ge during silicidation, including Ge out diffusion and silicide line breakage. The Si also increases the active area.

Description

    BACKGROUND OF INVENTION
  • The invention generally relates to a semiconductor device and method of manufacture and, more particularly, to a semiconductor device that includes strained silicon/silicon germanium field effect transistors with a protective silicon layer.
  • As silicon film thickness of Silicon On Insulator (SOI) is reduced, for high-performance CMOS fabrication, it becomes necessary to increase the thickness of source/drain regions above the SOI thickness. This results from the fact that, as the SOI film becomes thinner, a reduced amount of Si material is available from which to form silicide for source/drain contacts. Additionally, thinner source/drain regions can degrade on-current due to increased series resistance.
  • To maintain or reduce overall source/drain series resistance, including the silicide contact resistance, techniques have emerged to form raised source/drain (RSD) structures. For example, selective epitaxial growth of silicon has been used to grow silicon on the source/drain and the top of poly gates, leaving no silicon on gate sidewall spacers. One problem with this technique is that epitaxial growth must take place at temperatures as high as 750° C., which may cause significant transient enhanced diffusion of dopants. The unnecessary dopant redistribution in halo/extension regions degrades the performance of devices and short channel immunity. Moreover, with a very thin SOI film, it can be difficult to form epitaxial silicon without causing silicon agglomeration due to possible contamination of carbon in certain chemical vapor deposition tools.
  • Another technique involves SiGe selective epitaxial growth on source/drain regions. Advantageously, this technique eliminates transient enhanced diffusion of dopants which may otherwise occur at high temperatures. Unfortunately, however, Ge degrades silicide contact formation and contact resistance due to its inherent function as a diffusion barrier. To reduce such undesirable effects, the surface of SiGe may be capped with additional epitaxial silicon, using a high temperature process, which may cause transient enhanced diffusion.
  • Another problem with raised silicon/silicon germanium source and drain regions involves contact formation. High quality contacts to silicon-based field effect transistors are typically achieved through a silicide process, where a metal such as cobalt or titanium is alloyed with silicon to form the contact. However, this process is generally not as effective with semiconductor materials other than silicon. For example, a cobalt silicide contact formed to a source disposed in a strained Si layer and an underlying SiGe layer may form a high-resistivity compound in the SiGe layer, thereby compromising the functionality of the contact.
  • The invention is directed to overcoming one or more of the problems as set forth above.
    • SUMMARY OF INVENTION
  • In a first aspect of the invention, a method of fabricating a semiconductor structure is provided. The method entails forming a raised source region on a substrate. A raised drain region is also formed on the substrate. Next, a first silicon layer is formed over the raised source region and a second silicon layer is formed over the raised drain region.
  • In a second aspect of the invention, the method includes forming sacrificial spacers along the sidewalls of the first silicon layer and the second silicon layer. After forming the spacers, third and fourth silicon layers are formed on the raised source and raised drain regions, respectively.
  • In a third aspect of the invention, a semiconductor structure is provided. The semiconductor structure includes a substrate; a raised source region on the substrate, a raised drain region on the substrate; a first silicon layer over the raised source region and a second silicon layer over the raised drain region.
  • The raised source and drain regions thus include one or more silicon layers on sidewalls of the source and drain regions. The silicon prevents adverse effects of Ge during silicidation, including Ge out diffusion and silicide line breakage. The Si also increases the active area.
    • BRIEF DESCRIPTION OF DRAWINGS
  • FIG. 1 shows a first side cutaway view of an exemplary semiconductor structure with a raised source and drain according to the principles of the invention;
  • FIG. 2 shows a top view of an exemplary semiconductor structure with a raised source and drain according to the principles of the invention;
  • FIG. 3 shows a second side cutaway view of an exemplary semiconductor structure with a raised source and drain according to the principles of the invention;
  • FIG. 4 shows cutaway view of an exemplary semiconductor structure with a raised source and drain and a protective silicon layer according to the principles of the invention; and
  • FIG. 5, shows cutaway view of an exemplary semiconductor structure with a raised source and drain, a protective silicon layer and sacrificial spacers according to the principles of the invention.
    • DETAILED DESCRIPTION
  • The invention enables fabrication of raised Si/SiGe source and drain regions with epitaxially grown silicon on SiGe sidewalls. The silicon prevents adverse effects of Ge during silicidation, including Ge out diffusion and silicide line breakage. The Si also increases the active area.
  • Referring to FIG. 1, an exemplary initial structure employed in the invention is shown. Specifically, the exemplary initial structure is comprised of an SOI substrate 105 having a patterned gate stack region 110 formed on the surface thereof. The SOI substrate 105 may include a buried oxide layer 125 sandwiched between a top Si-containing layer 130 and a bottom Si-containing layer 140. The top Si-containing layer 130 is an area upon which devices may be formed. The Si-containing layer 130 may be comprised of various semiconducting materials that include silicon, such as Si, SiGe, SiC, SiGeC, Si/Si, or Si/SiGe.
  • The SOI substrate 105 employed in the present invention may be fabricated using techniques well known to those skilled in the art. For example, the SOI substrate may be formed by a conventional bonding and cutting processes, or alternatively, a conventional separation by implantation of oxygen (SIMOX) process. While the thickness of the various layers is not critical to the present invention, the top Si-containing layer 130 may have a thickness of about 5 to 250 nm.
  • Isolation structures, such as shallow-trench isolations (STIs) 180 and 185, are also provided in the exemplary initial structure. Techniques known in the art may be utilized to form STIs 180 and 185. A conventional technique entails patterning with a photoresist, etching the trench, chemical vapor deposition of oxide to fill the trench, and planarizing the surface such as by chemical mechanical polishing. Subsequently, the top surface of the STI form ations 180 and 185 may be etched down, as discussed more fully below.
  • The patterned gate stack region 110 may be formed atop the Si-containing layer using processing techniques well known in the art. For example, the patterned gate stack region 110 may be fabricated by first forming gate dielectric 125 on an exposed surface of the top Si-containing layer 130. The gate dielectric layer 125 may be formed by a conventional deposition process such as CVD or plasma-assisted CVD, or a thermal growing process such as oxidation, nitridation or oxynitridation. The gate dielectric may include any device quality dielectric material such as an oxide, nitride, oxynitride or any combination and multilayer thereof. The thickness of the gate dielectric is not critical to the present invention.
  • The gate stack 110 is formed on the gate dielectric 125 utilizing a conventional deposition process such as CVD, plasma-assisted CVD or plating. The gate stack 110 may include a gate material such as polysilicon, amorphous silicon or other materials suitable for MOSFET gate composition. The gate material may be formed on the surface of gate dielectric 125 utilizing conventional deposition processes well known in the art such as, for example, CVD or plasma-assisted CVD. An optional dielectric-capping layer (not shown) may be present atop the gate material. When present, the optional dielectric-capping layer may typically be comprised of an oxide, nitride or oxynitride and formed utilizing a conventional deposition process such as, for example, CVD or plasma-assisted CVD. Alternatively, a conventional thermal growing process such as, for example, oxidation, may be used in forming an optional dielectric-capping layer.
  • Following formation of the gate stack 110 on the gate dielectric layer 125, the gate stack 110 and gate dielectric layer 125 are subjected to a conventional patterning process which includes lithography and etching steps. By way of example, the lithography step may entails applying a photoresist, exposing the photoresist to a pattern of radiation, and developing the pattern utilizing a conventional resist developer. Following the lithography step, a conventional etching process such as reactive-ion etching, plasma etching, ion beam etching or laser ablation may be employed in transferring the pattern to the gate stack 110 and the gate dielectric 125.
  • Spacers 115 and 120 are formed along gate sidewalls. For example, spacer material such as a nitride (e.g., Si3N4) may be deposited in a conventional manner, such as by chemical vapor deposition (CVD) using a silane source. Other techniques, which may be suitable for deposition of a nitride layer, include low-pressure CVD (LPCVD) and atmospheric pressure (CVD) (APCVD). Portions of the deposited nitride layer are subsequently etched away in a conventional manner to form the spacers 115 and 120.
  • After spacer formation, raised source and drain regions are formed in a conventional manner. As illustrated in FIG. 1, exemplary source and drain regions 160 and 175 are comprised of SiGe layers 150 and 165 capped with strained silicon layers 155 and 170. The SiGe layers 150 and 165 may be selectively epitaxially grown in a conventional manner using ultrahigh-vacuum chemical vapor deposition (UHVCVD), molecular beam epitaxy (MBE), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), and low energy plasma enhanced chemical vapor deposition (LEPECVD). Alternatively, the SiGe layers 150 and 165 may be comprised, in whole or in part, of the top silicon-containing layer 130 of the SOI substrate 105.
  • Silicon layers 155 and 170 may be formed on the SiGe layers 150 and 165 of the raised source and drain regions 160 and 175, respectively, using a conventional selective epitaxial silicon formation technique. For example, molecular beam epitaxy (MBE) may be used to selectively grow device quality silicon. Because Si has a smaller lattice constant (i.e., atom spacing) than Ge, when Si 155 and 170 is grown on the SiGe layer 160 and 165, the Si 155 and 170 is strained in tension. A suitable thickness for the strained Si layers 155 and 170 is below the critical thickness, which is the maximum thickness that strained Si can grow on the SiGe SiGe layers 150 and 165 without forming defects in the crystal structure (e.g., dislocations). By way of example but not limitation, the strained Si layer 155 may be approximately 5 to 100 nm thick.
  • Referring now to FIG. 2, a top view of the exemplary initial structure is shown. Raised drain 160 and source 175 regions are provided adjacent to nitride spacer sides 115 and 120, respectively. The nitride spacer 210 surrounds the sidewalls of the gate 110. The shallow trench isolation 220, including STI sides 180 and 185, surround the active area. The cutaway view represented in FIG. 1 is denoted by cutaway line A-A in FIG. 2.
  • Referring now to FIG. 3, a side view of a cutaway section represented by line B-B in FIG. 2 is shown. Those skilled in the art will appreciate that the structure and process steps described below for the raised drain region apply equally as well to the raised source region.
  • STI oxide portions 230 and 240 are shown alongside the raised drain 160 comprised of SiGe layer 150 and strained Si layer 160. The top layer 130 of the exemplary SOI substrate may be comprised of the same material as the raised drain layer 150, namely SiGe. Thus, referring again to FIG. 1, SiGe layers 150 and 165 may be comprised of the top layer of the exemplary SOI substrate. In such a case, STIs may be formed from the SOI substrate surface to the top of the buried oxide layer 135. Then, the STI oxide may be etched to reveal the raised SiGe portions of raised source and drain regions, such as SiGe layer 150 in FIG. 3. This approach for raised source and drain formation may obviate the need to form layer 150 separately by epitaxial growth as described above.
  • Next, the raised drain 160 is protected with a silicon layer 400, as shown in FIG. 4. In particular, silicon is selectively epitaxially grown on the SiGe sidewalls of the raised drain 160, forming protective silicon sidewalls 410 and 420. The selective epitaxial process also results in growth of silicon on the strained silicon layer 155, forming silicon cap 430 for the raised drain 160. The epitaxial silicon layer 400 may be formed using conventional selective epitaxial growing processes known in the art, such as molecular beam epitaxy.
  • In the event the width of the STI is small, a thick silicon layer 400 along the sidewalls 410 and 420 may run the risk of bridging, i.e., forming an undesired connection between features (such as source and gate or drain and gate) of the device or between features of adjacent devices. Referring now to FIG. 5, to limit the thickness of the Si sidewalls 510 and 520 and avoid or reduce the risk of bridging, sacrificial oxide spacers 505 and 525 may be formed after an initial layer of silicon 500 is selectively epitaxially formed on the raised drain 160. Thus, silicon may be selectively epitaxially grown on the SiGe sidewalls of the raised drain 160, forming protective silicon sidewalls 510 and 520. The selective epitaxial process also results in growth of silicon 515 on the strained silicon layer 155. The epitaxial silicon layer 500 may be formed using conventional selective epitaxial growing processes known in the art, such as molecular beam epitaxy.
  • The spacers 505 and 525 may be formed along the Si coated SiGe sidewalls of the raised drain in a conventional manner, such as by oxide deposition, patterning and etching using processes known in the art. After formation of the spacers, an additional selective epitaxial growth step may be performed to complete formation of the raised drain. The oxide spacers 505 and 525 will prevent further formation of Si along the sidewalls during the additional selective epitaxial growth step. After completing the sadditional selective epitaxial growth step, the oxide spacers may be removed, such as by dry etching.
  • Following formation of the epitaxial silicon sidewalls 410 and 420 (or 510 and 520) and cap 430 (or 515), silicide contacts may be formed on the epitaxial silicon layer utilizing a conventional silicidation process. The presence of Ge in the SiGe underlying the silicon layer 400 (or 500) will not interfere with, degrade or otherwise adversely impact the silicidation process.
  • Those skilled in the art will appreciate that although FIG. 1 shows only one patterned gate stack region and corresponding raised source and drain regions, the invention applies equally as well when a plurality of patterned gate stacks and corresponding raised source and drain regions are formed on the SOI substrate. Thus, the invention is not limited to the embodiment wherein a single patterned gate stack region is employed.
  • While the invention has been described in terms of exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with modifications and in the spirit and scope of the appended claims.

Claims (28)

1. A method of fabricating a semiconductor structure, comprising the steps of:
forming a raised source region on a substrate;
forming a raised drain region on the substrate; and
forming a first silicon layer over the raised source region and a second silicon layer over the raised drain region.
2. A method according to claim 1, wherein the substrate includes a SiGe layer atop a buried oxide layer.
3. A method according to claim 1, further comprising a step of forming a gate stack on the substrate.
4. A method according to claim 3, further comprising a step of forming a trench isolation surrounding the gate stack, source region and drain region.
5. A method according to claim 1, further comprising a step of forming a first silicide contact on the first silicon layer.
6. A method according to claim 1, further comprising a step of forming a second silicide contact on the second silicon layer.
7. A method according to claim 1, wherein the first silicon layer is epitaxially formed silicon and the second silicon layer is epitaxially grown silicon.
8. A method according to claim 1, wherein the raised drain region is comprised of a strained silicon layer atop a SiGe layer.
9. A method according to claim 8, wherein the strained silicon layer is comprised of epitaxially grown silicon.
10. A method according to claim 1, wherein the raised source region is comprised of a strained silicon layer atop a SiGe layer.
11. A method according to claim 10, wherein the strained silicon layer is comprised of epitaxially grown silicon.
12. A method according to claim 1, wherein the first silicon layer formed over the raised source region and the second silicon layer over the raised drain region include cap portions and sidewall portions, the method further comprising a step of forming sacrificial spacers along the silicon sidewall portions.
13. A method according to claim 12, further comprising steps of:
forming a third silicon layer over the cap of the first silicon layer over the raised source region; and
forming a fourth silicon layer over the cap of the second silicon layer over the raised drain region.
14. A method according to claim 13, further comprising a step of removing the sacrificial spacers.
15. A method according to claim 14, wherein the step of removing the sacrificial spacers includes etching away the sacrificial spacers.
16. A semiconductor structure, comprising:
a substrate;
a raised source region on the substrate;
a raised drain region on the substrate; and
a first silicon layer over the raised source region and a second silicon layer over the raised drain region.
17. A semiconductor structure according to claim 16, wherein the substrate includes a SiGe layer atop a buried oxide layer.
18. A semiconductor structure according to claim 16, further comprising a gate stack on the substrate.
19. A semiconductor structure according to claim 18, further comprising a trench isolation surrounding the gate stack, source region and drain region.
20. A semiconductor structure according to claim 16, further comprising a a first silicide contact on the first silicon layer.
21. A semiconductor structure according to claim 16, further comprising a second silicide contact on the second silicon layer.
22. A semiconductor structure according to claim 16, wherein the first silicon layer is epitaxially formed silicon and the second silicon layer is epitaxially grown silicon.
23. A semiconductor structure according to claim 1, wherein the raised drain region is comprised of a strained silicon layer atop a SiGe layer.
24. A semiconductor structure according to claim 23, wherein the strained silicon layer is comprised of epitaxially grown silicon.
25. A semiconductor structure according to claim 1, wherein the raised source region and the raised drain region are comprised of a strained silicon layer atop a SiGe layer.
26. A semiconductor structure according to claim 1, wherein the first silicon layer formed over the raised source region and the second silicon layer over the raised drain region include cap portions and sidewall portions, the semiconductor structure further comprising sacrificial spacers along the silicon sidewall portions.
27. A semiconductor structure according to claim 26, further comprising:
a third silicon layer over the cap of the first silicon layer over the raised source region; and
a fourth silicon layer over the cap of the second silicon layer over the raised drain region.
28. A semiconductor structure according to claim 27, wherein the sacrificial spacers have been removed.
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