US20050164441A1 - Semiconductor device and process for producing the same - Google Patents

Semiconductor device and process for producing the same Download PDF

Info

Publication number
US20050164441A1
US20050164441A1 US11/087,612 US8761205A US2005164441A1 US 20050164441 A1 US20050164441 A1 US 20050164441A1 US 8761205 A US8761205 A US 8761205A US 2005164441 A1 US2005164441 A1 US 2005164441A1
Authority
US
United States
Prior art keywords
layer
metallic
silicon
metal
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/087,612
Inventor
Kazuhiro Ohnishi
Naoki Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US11/087,612 priority Critical patent/US20050164441A1/en
Publication of US20050164441A1 publication Critical patent/US20050164441A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Definitions

  • the present invention relates to a semiconductor device and a process for producing the same and, more particularly, to a semiconductor device with an MIS type transistor and a process for producing the same.
  • CMOS devices In the case of high-speed CMOS devices, on the other hand, low threshold voltage and low gate resistance alone are not enough to attain both higher performance and higher integration. It is also required to reduce the gate/contact pitch.
  • Conventional technologies of satisfying these requirements include a SALICIDE technology of self-aligned silicidation of gate polycrystalline silicon and source/drain regions, a technology using POLICIDE structure, i.e. using a gate of polycrystalline silicon/silicide-stacked structure, a technology using a gate electrode of polycrystalline silicon/high melting point metal-stacked structure, etc.
  • the SALICIDE technology is difficult to use together with a self-aligned contact technology and thus is difficult to reduce the layout pitch.
  • the POLICIDE structure is so high in the sheet resistance that it is difficult to obtain a sufficiently low gate resistance. This is a problem of the POLICIDE structure.
  • the desirable gate electrode structure capable of satisfying the aforementioned requirements is a metal/polycrystalline silicon-stacked structure.
  • An object of the present invention is to provide a semiconductor device with reduced contact resistance between the reaction barrier layer and the polycrystalline silicon in the metal/reaction barrier/polycrystalline silicon-stacked structure, and a process for producing the same.
  • the present invention provides a semiconductor device with an MOS transistor, wherein the gate electrode of the MOS transistor is in a stacked structure comprising a silicon layer, a metal silicide layer, a reaction barrier layer such as a metal nitride layer and a metallic layer formed in this order from the bottom upwards.
  • the present invention also provides a process for producing a semiconductor device, which comprises a step of forming a first insulation layer on the surface of a semiconductor substrate, a step of depositing a silicon layer on the first insulation layer, a step of depositing a first metallic layer on the silicon layer, a step of depositing a reaction barrier layer such as a metal nitride layer on the first metallic layer, a step of depositing a second metallic layer on the metal nitride layer, a step of processing the stacked structure comprising the silicon layer, the first metallic layer, the metal nitride layer and the second metallic layer into a gate electrode form, a step of ion implanting an impurity onto the surface of the semiconductor substrate, using the gate electrode as a mask, and a step of reacting the first metallic layer with the silicon layer by heat treatment, thereby forming a metal silicide layer.
  • FIGS. 1A to 1 E are cross-sectional views showing process steps of Example 1 according to the present invention.
  • FIGS. 2A to 2 D are cross-sectional views showing process steps of Example 2 according to the present invention.
  • FIGS. 3A to 3 D are cross-sectional views showing process steps of Example 3 according to the present invention.
  • FIGS. 4A to 4 C are cross-sectional views showing part of process steps of Example 4 according to the present invention.
  • FIGS. 5A to 5 C are cross-sectional views showing part of process steps of Example 4 according to the present invention.
  • FIGS. 6A to 6 C are cross-sectional views showing part of process steps of Example 5 according to the present invention.
  • FIGS. 7A to 7 C are cross-sectional views showing part of process steps of Example 5 according to the present invention.
  • 101 and 301 semiconductor substrate, 102 and 310 : gate oxide layer, 103 : polycrystalline silicon layer, 104 and 309 : metallic layer, 105 and 308 : metal nitride layer, 106 and 307 : metallic layer, 107 and 306 : silicon oxide layer, 108 and 320 : metal silicide layer, 109 : metal silicide layer, 302 : silicon oxide layer, 303 and 305 : silicon nitride layer, 304 : silicon oxide layer, 311 : n-type polycrystalline silicon layer, 312 : p-type polycrystalline silicon layer. 313 : silicon oxide layer, 315 and 317 : punch-through stopper, 314 and 316 : diffusion layer, and 318 and 319 : deep diffusion layer.
  • a metal/reaction barrier/metal silicide/polycrystalline silicon-stacked structure is applied to the present semiconductor device as a gate electrode.
  • the semiconductor device of the present invention is characterized by having a metal/reaction barrier/metal silicide/polycrystalline silicon stacked gate electrode.
  • the lowest layer is made of polycrystalline silicon which can be doped with an impurity, and stacked thereon a metal silicide layer made of; for example, tungsten silicide, molybdenum silicide, nickel silicide, tantalum silicide, hafnium silicide, zirconium silicide, cobalt silicide, etc, and stacked thereon a reaction barrier layer made of, for example, tungsten nitride, titanium nitride, molybdenum nitride, tantalum nitride, tungsten carbide, titanium carbide, molybdenum carbide, tantalum carbide, etc.
  • the uppermost layer is a metal layer made of, for example, tungsten, molybdenum, etc.
  • FIGS. 1A to 1 E are cross-sectional views showing process steps for forming a gate electrode according to Example 1 of the present invention.
  • Gate insulation layer 102 is formed on the surface of semiconductor substrate 101 e.g., by thermal oxidation, and then polycrystalline silicon layer 103 is deposited thereon e.g. by CVD ( FIG. 1A ).
  • Polycrystalline silicon layer 103 is doped with an impurity of any desired conductivity type (e.g. phosphorus or boron) by ion implanting, followed by activation annealing at 950°-1,000° C.
  • metallic layer 104 of e.g. tungsten is deposited thereon to a thickness of about 5 nm e.g. by sputtering, where precleaning e.g. with hydrofluoric acid is carried out beforehand to remove natural oxide, etc. remaining on the surface of polycrystalline silicon layer 103 .
  • metal nitride layer 105 of e.g. tungsten nitride as a reaction barrier and metallic layer 106 of e.g. tungsten are deposited thereon one after the other to a thickness of about 5 to about 10 nm and to a thickness of about 50 nm, respectively, e.g. by sputtering ( FIG. 1B ).
  • metallic layers 104 and 106 or metal nitride layer 105 are deposited continuously without exposure to the air. Then, silicon oxide layer 107 is deposited on metallic layer 6 e.g. by plasma CVD ( FIG. 1C ).
  • the stacked structure of these deposited layers is processed into a gate electrode e.g. by lithography and anisotropic dry etching, using a resist ( FIG. 1D ).
  • metallic layer 104 is made to react with polycrystalline silicon layer 103 by heat treatment at 650° C. or higher in a process for forming a CMOS device, thereby forming metal silicide layer 108 of e.g. tungsten silicide to a thickness about twice as large as that of deposited metallic layer 104 .
  • the gate electrode thus formed has a contact resistance by about ⁇ fraction (1/10) ⁇ to about ⁇ fraction (1/40) ⁇ lower than that of the conventional gate electrode without insertion of a metal silicide layer, because a desirable metal/semiconductor contact can be formed between metal silicide layer 108 and polycrystalline silicon layer 103 in the present Example.
  • FIG. 2A to 2 D are cross-sectional views showing process steps for forming a gate electrode according to Example 2 of the present invention.
  • FIGS. 2A and 2B are identical with those of FIGS. 1A and 1B of Example 1.
  • gate insulation layer 102 polycrystalline silicon layer 103 , metallic layer 104 of e.g. tungsten, metal nitride layer 105 of e.g. tungsten nitride, and metallic layer 106 of e.g. tungsten have been deposited on silicon substrate 101 as a stacked structure ( FIG. 26 )
  • heat treatment of the stacked structure is carried out at 650° C. or higher in the present Example to react metallic layer 104 with polycrystalline silicon layer 103 , thereby forming metal silicide layer 108 of e.g.
  • the stacked structure is processed into a gate electrode e.g. by lithography and anisotropic dry etching using a resist ( FIG. 2D )
  • the gate electrode thus formed has a contact resistance by about ⁇ fraction (1/10) ⁇ to about ⁇ fraction (1/40) ⁇ lower than that of the conventional gate electrode without insertion of a metal silicide layer, because a desirable metal/semiconductor contact can be formed between metal silicide layer 108 and polycrystalline silicon layer 103 in the present Example.
  • FIGS. 3A to 3 D are cross-sectional views showing process steps for forming a gate electrode according to Example 3 of the present invention.
  • Gate insulation layer 102 is formed on the surface of semiconductor substrate 101 e.g. by thermal oxidation, and then polycrystalline silicon layer 103 is deposited thereon e.g. by CVD ( FIG. 3A ).
  • Polycrystalline silicon layer 103 is doped with an impurity of any desired conductivity type (e.g. phosphorus or boron) by ion implanting, followed by activation annealing at 950°-1,000° C.
  • metal silicide layer 109 of e.g. tungsten silicide is deposited thereon to a thickness of 5-20 nm e.g. by sputtering or CVD, where precleaning e.g. with hydrofluoric acid is carried out beforehand to remove natural oxide, etc. remaining on the surface of polycrystalline silicon layer 103 .
  • metal nitride layer 105 of e.g. tungsten nitride as a reaction barrier and metallic layer 106 of e.g. tungsten are deposited thereon one after the other to a thickness of about 5 to about 10 nm and to thickness of about 50 nm, respectively, e.g. by sputtering ( FIG. 3B ).
  • metal silicide layer 109 metal silicide layer 109 , metal nitride layer 105 and metallic layer 106 continuously without exposure to the air. Then, silicon oxide layer 107 is deposited on metallic layer 106 , e.g. by plasma CVD ( FIG. 3C ).
  • the stacked structure of these deposited layers is processed into a gate electrode, e.g. by lithography and anisotropic dry etching using a resist ( FIG. 3D ).
  • the gate electrode thus formed has a contact resistance by about ⁇ fraction (1/10) ⁇ to about ⁇ fraction (1/40) ⁇ lower than that of the conventional gate electrode without insertion of a metal silicide layer, because a desirable metal/semiconductor contact can be formed between metal silicide layer 109 and polycrystalline silicon layer 103 in the present Example.
  • FIGS. 4A to 4 C and FIGS. 5A to 5 C are cross-sectional views showing process steps for producing CMOS (complementary MOS) transistors according to Example 4 of the present invention.
  • silicon substrate 301 is oxidized to a thickness of about 10 nm e.g. by thermal oxidation to form oxide layer 302 , and silicon nitride layer 303 is deposited thereon to a thickness of about 150 nm e.g. by thermal CVD. Then, a trench is formed to a depth of about 0.3 ⁇ m in a region serving as isolation area of silicon substrate 301 by photolithography and dry etching and then the inside surface of the trench is thermally oxidized to a thickness of about 10 nm ( FIG. 4A ).
  • silicon oxide layer 304 is deposited e.g. by CVD to fill the trench, and the silicon nitride layer 305 is deposited thereon e.g. by thermal CVD.
  • Silicon nitride layer 305 is removed only from the surface of device-active region e.g. by photolithography and dry etching, as shown in FIG. 4B , followed by flattening by CMP (Chemical Mechanical Polishing). Polishing rate of silicon nitride layers 303 and 305 is lower than that of silicon oxide layer 304 , so that the polishing can be discontinued at the level of silicon nitride layers 303 and 305 .
  • silicon nitride layers 303 and 305 and silicon oxide layer 302 are removed by wet cleaning ( FIG. 4C ).
  • gate insulation layer 310 is formed on the surface of semiconductor substrate 301 e.g. by thermal oxidation, and polycrystalline silicon layer is formed thereon e.g. by CVD.
  • the polycrystalline silicon layer is locally doped with an impurity of n-type (e.g. phosphorus) and with another impurity of p-type (e.g. boron) by ion implanting, thereby forming n-type polycrystalline silicon layer 311 as an NMOS gate electrode and p-type polycrystalline silicon layer 312 as a PMOS gate electrode, respectively, followed by activation annealing at 950° C.
  • metallic layer 309 of e.g.
  • tungsten is deposited thereon to a thickness of about 5 nm e.g. by sputtering, where precleaning e.g. with hydrofluoric acid is carried out beforehand to remove natural oxide, etc. remaining on the surfaces of polycrystalline silicon layers 311 and 312 .
  • metal nitride layer 308 of e.g. tungsten nitride as a reaction barrier and metallic layer 307 of e.g. tungsten are deposited thereon one after the other to a thickness of about 5 to about 10 nm and to a thickness of about 50 nm, respectively, e.g. by sputtering. It is desirable to deposit these metallic layer 309 , metal nitride layer 308 and metallic layer 307 continuously without exposing to the air.
  • silicon oxide layer 306 is deposited on metallic layer 307 e.g. by plasma CVD.
  • the stacked structure of these deposited layers is processed into gate electrodes e.g. by lithography and anisotropic dry etching using a resist.
  • NMOS diffusion layer region 314 and punch-through stopper region 315 , and PMOS diffusion layer region 316 and punch-through stopper region 317 are formed by photolithography and ion implanting ( FIG. 5A ).
  • NMOS and PMOS diffusion layer regions 318 and 319 are formed by photolithography and ion implanting ( FIG. 5B ).
  • metallic layer 309 is made to react with polycrystalline silicon layers 311 and 312 by activation annealing of transistor [e.g. RTA(Rapid Thermal Annealing) at 950° C. for 10 seconds], thereby forming metal silicide layer 320 of e.g. tungsten silicide to a thickness about, twice as large as that of deposited metallic layer 309 ( FIG. 5C ).
  • RTA Rapid Thermal Annealing
  • the gate electrodes thus formed have a contact resistance by about ⁇ fraction (1/10) ⁇ to about ⁇ fraction (1/40) ⁇ lower than that of the conventional gate electrodes without insertion of a metal silicide layer, because a desirable metal/semiconductor contact can be formed between metal silicide layer 320 and polycrystalline silicon layer 311 or 312 in the present Example.
  • Device circuit performance propagation delay of CMOS device under no load
  • FIGS. 6A to 6 C and FIGS. 7A to 7 C are cross-sectional views showing process steps for producing CMOS transistors according to Example 5 of the present invention.
  • silicon substrate 301 is oxidized to a thickness of about 10 nm e.g. by thermal oxidation to form oxide layer 302 , and silicon nitride layer 303 is deposited thereon to a thickness of about 150 nm e.g. by thermal CVD. Then, a trench is formed to a depth of about 0.3 pm in a region serving as isolation area of silicon substrate 301 by photolithography and dry etching and then the inside surface of the trench is thermally oxidized to a thickness of about 10 nm ( FIG. 6A ).
  • silicon oxide layer 304 is deposited e.g. by CVD to fill the trench and then silicon nitride layer 305 is deposited thereon e.g. by thermal CVD.
  • Silicon nitride layer 305 is removed only from the surface of device-active region e.g. by photolithography and dry etching as shown in FIG. 6B , followed by flattening by CMP (Chemical Mechanical Polishing). Polishing rate of silicon nitride layer 303 and 305 is lower than that of silicon oxide layer 304 , so that the polishing can be discontinued at the level of silicon nitride layers 303 and 305 .
  • silicon nitride layers 303 and 305 and silicon oxide layers 302 are removed by wet cleaning ( FIG. 6C ).
  • gate insulation layer 310 is formed on the surface of semiconductor substrate 301 e.g. by thermal oxidation, and polycrystalline silicon layer is formed thereon e.g. by CVD.
  • the polycrystalline silicon layer is locally doped with an impurity of n-type (e.g. phosphorus) and with another impurity of p-type (e.g. boron) by ion implanting, thereby forming n-type polycrystalline silicon layer 311 as an NMOS gate electrode and p-type polycrystalline silicon layer 312 as a PMOS gate electrode, respectively, followed by activation annealing at 950° C.
  • metallic layer 309 of e.g.
  • tungsten is deposited thereon to a thickness of about S nm e.g. by sputtering, where precleaning e.g. with hydrofluoric acid is carried out beforehand to remove natural oxide, etc. remaining on the surfaces of polycrystalline silicon layers 311 and 312 .
  • metal nitride layer 308 of e.g. tungsten nitride as a reaction barrier and metallic layer 307 of e.g. tungsten are deposited thereon one after the other to a thickness of about 5 to about 10 nm and to a thickness of about 50 nm, respectively, e.g. by sputtering.
  • metallic layer 309 metal nitride layer 308 and metallic layer 307 continuously without exposing to the air.
  • silicon oxide layer 306 is deposited on metallic layer 307 e.g. by plasma CVD ( FIG. 7A ).
  • heat treatment is carried out at 650° C. or higher at this stage to make metallic layer 309 to react with polycrystalline silicon layers 311 and 312 , thereby forming metal silicide layer 320 of e.g. tungsten silicide to a thickness about twice as large as that of deposited metallic layer 309 ( FIG. 7B ).
  • the stacked structure of these deposited layers is processed into gate electrodes e.g. by lithography and anisotropic dry etching using a resist.
  • NMOS diffusion layer region 314 and punch-through stopper region 315 , and PMOS diffusion layer region 316 and punch-through stopper region 317 are formed by photolithography and ion implanting. Furthermore, after a silicon oxide layer is deposited thereon e.g. by plasma CVD, side walls 313 of silicon oxide are formed on the gate electrode sides by, removing the deposited silicon oxide layer only by a corresponding deposited thickness portion by isotropic dry etching. Then, deeper NMOS diffusion layer region 318 and deeper PMOS diffusion layer region 319 are formed by photolithography and ion implanting ( FIG. 7C ).
  • the gate electrodes thus formed have a contact resistance by about ⁇ fraction (1/10) ⁇ to about ⁇ fraction (1/40) ⁇ lower than that of the conventional gate electrodes without insertion of a metal silicide, because a desirable metal/semiconductor contact can be formed between metal silicide layer 320 and polycrystalline silicon layer 311 or 312 in the present Example.
  • Device circuit performance propagation delay of CMOS device under no load
  • CMOS device with gate length generation of 0.10 pm owing to these effects.
  • Contact resistance at the conventional tungsten nitride/polycrystalline silicon boundary is in the order of 10 ⁇ 5 ⁇ cm 2 irrespective of whether the polycrystalline silicon is of n- or p-type conductivity, thereby failing to achieve a metal/semiconductor boundary with desirable ohmic characteristics.
  • the present invention can provide a substantially desirable metal/semiconductor boundary by making a tungsten nitride/tungsten silicide/polycrystalline silicon-stacked structure, i.e. can provide a low contact resistance boundary capable of realizing desirable ohmic characteristics.
  • circuit performance can be increased owing to the gate resistance-reducing effect of the present invention.

Abstract

Process for producing a semiconductor device includes forming an insulation layer on a semiconductor substrate surface and depositing a silicon layer on the insulation layer, a reaction barrier layer such as a metal nitride layer on the first metallic layer and a second metallic layer on the barrier layer, processing a stacked structure of the silicon layer, first metallic layer, barrier layer and second metallic layer to form a gate electrode, using the gate electrode as a mask and doping an impurity into the surface of the semiconductor substrate to form active regions of the device, heat reacting the first metallic layer with the silicon layer to form a metal silicide layer between the reaction barrier layer and the silicon layer. The heat reaction process effected may be performed prior to or after the formation of the gate electrode. The metal silicide film may be a deposited film.

Description

  • This application is a continuation of U.S. application Ser. No. 10/812,995, filed Mar. 31, 2004; which, in turn, is a divisional of U.S. application Ser. No. 09/829,969, filed Apr. 11, 2001 (now U.S. Pat. No. 6,750,503); and the entire disclosures of which are incorporated herein by reference.
    • BACKGROUND OF THE INVENTION
  • The present invention relates to a semiconductor device and a process for producing the same and, more particularly, to a semiconductor device with an MIS type transistor and a process for producing the same.
  • To attain higher performance and higher integration of devices, semiconductor devices have been progressively scaled down over the years, necessitating incorporation of low-resistance materials into the electrode materials. It is thus desirable to incorporate a metal also into the MOS transistor gate electrode.
  • In the case of high-speed CMOS devices, on the other hand, low threshold voltage and low gate resistance alone are not enough to attain both higher performance and higher integration. It is also required to reduce the gate/contact pitch. Conventional technologies of satisfying these requirements include a SALICIDE technology of self-aligned silicidation of gate polycrystalline silicon and source/drain regions, a technology using POLICIDE structure, i.e. using a gate of polycrystalline silicon/silicide-stacked structure, a technology using a gate electrode of polycrystalline silicon/high melting point metal-stacked structure, etc.
  • However, the SALICIDE technology is difficult to use together with a self-aligned contact technology and thus is difficult to reduce the layout pitch. The POLICIDE structure is so high in the sheet resistance that it is difficult to obtain a sufficiently low gate resistance. This is a problem of the POLICIDE structure. Thus, the desirable gate electrode structure capable of satisfying the aforementioned requirements is a metal/polycrystalline silicon-stacked structure.
  • However, such a stacked structure has a low thermal stability and even if tungsten, i.e. high melting point metal, is used as the metal, reaction takes place between the metal and silicon during the heat treatment at about 650° C., resulting in an increase in resistance, degradation of layer surface state, dielectric breakdown, etc., which are examples of other problems arising. To solve these problems, a structure of inserting a metal nitride layer as a reaction barrier between the metal and the polycrystalline silicon (metal/reaction barrier/polycrystalline silicon-stacked structure) has been proposed (e.g. '98 IEDM Technical Digest. pp. 397-400).
  • Use of the tungsten nitride layer as a reaction barrier as mentioned above, still suffers from the following problems:
      • (1) Contact resistance between tungsten nitride and polycrystalline silicon is very high, e.g. up to 2×10−5 Q-cm2.
      • (2) Device circuit performance is not improved due to the high contact resistance, etc.
    BRIEF SUMMARY OF THE INVENTION
  • An object of the present invention is to provide a semiconductor device with reduced contact resistance between the reaction barrier layer and the polycrystalline silicon in the metal/reaction barrier/polycrystalline silicon-stacked structure, and a process for producing the same.
  • The present invention provides a semiconductor device with an MOS transistor, wherein the gate electrode of the MOS transistor is in a stacked structure comprising a silicon layer, a metal silicide layer, a reaction barrier layer such as a metal nitride layer and a metallic layer formed in this order from the bottom upwards.
  • The present invention also provides a process for producing a semiconductor device, which comprises a step of forming a first insulation layer on the surface of a semiconductor substrate, a step of depositing a silicon layer on the first insulation layer, a step of depositing a first metallic layer on the silicon layer, a step of depositing a reaction barrier layer such as a metal nitride layer on the first metallic layer, a step of depositing a second metallic layer on the metal nitride layer, a step of processing the stacked structure comprising the silicon layer, the first metallic layer, the metal nitride layer and the second metallic layer into a gate electrode form, a step of ion implanting an impurity onto the surface of the semiconductor substrate, using the gate electrode as a mask, and a step of reacting the first metallic layer with the silicon layer by heat treatment, thereby forming a metal silicide layer.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1A to 1E are cross-sectional views showing process steps of Example 1 according to the present invention.
  • FIGS. 2A to 2D are cross-sectional views showing process steps of Example 2 according to the present invention.
  • FIGS. 3A to 3D are cross-sectional views showing process steps of Example 3 according to the present invention.
  • FIGS. 4A to 4C are cross-sectional views showing part of process steps of Example 4 according to the present invention.
  • FIGS. 5A to 5C are cross-sectional views showing part of process steps of Example 4 according to the present invention.
  • FIGS. 6A to 6C are cross-sectional views showing part of process steps of Example 5 according to the present invention.
  • FIGS. 7A to 7C are cross-sectional views showing part of process steps of Example 5 according to the present invention.
  • In the drawings, reference numerals have the following meanings:
  • 101 and 301: semiconductor substrate, 102 and 310: gate oxide layer, 103: polycrystalline silicon layer, 104 and 309: metallic layer, 105 and 308: metal nitride layer, 106 and 307: metallic layer, 107 and 306: silicon oxide layer, 108 and 320: metal silicide layer, 109: metal silicide layer, 302: silicon oxide layer, 303 and 305: silicon nitride layer, 304: silicon oxide layer, 311: n-type polycrystalline silicon layer, 312: p-type polycrystalline silicon layer. 313: silicon oxide layer, 315 and 317: punch-through stopper, 314 and 316: diffusion layer, and 318 and 319: deep diffusion layer.
    • DETAILED DESCRIPTION OF THE INVENTION
  • To reduce the contact resistance between reaction barrier film and polycrystalline silicon, a metal/reaction barrier/metal silicide/polycrystalline silicon-stacked structure is applied to the present semiconductor device as a gate electrode.
  • Specific modes of the present semiconductor device and the present process for producing the same are as follows:
      • (1) A semiconductor device with an MOS transistor, wherein the gate electrode of the MOS transistor is provided as a stacked structure comprising a silicon layer, a metal silicide layer, a reaction barrier layer such as a metal nitride layer and a metallic layer formed in this order from the bottom upwards.
      • (2) A semiconductor device according to item (1), wherein the silicon layer is doped with an impurity of any desired conductivity type.
      • (3) A semiconductor device according to item (1), wherein the metal silicide layer has a thickness of 5-20 nm.
      • (4) A semiconductor device according to item (1), wherein metal silicide layer is a tungsten silicide layer, the metal nitride layer is a tungsten nitride layer, and the metallic layer is a tungsten layer.
      • (5) A semiconductor device with an MOS transistor whose gate electrode is provided as a stacked structure comprising a silicon layer and a metallic layer, as the uppermost layer thereof, provided above the silicon layer, wherein a metal silicide layer is provided on the silicon layer side and a reaction barrier layer such as a metal nitride layer is provided under the metallic layer side between the silicon layer and the metallic layer.
      • (6) A semiconductor device according to item (5), wherein the silicon layer is doped with an impurity of any desired conductivity type.
      • (7) A semiconductor device according to item (5), wherein the metal silicide layer has a thickness of 5-20 nm.
      • (8) A semiconductor device according to item (5), wherein the metal silicide layer is a tungsten silicide layer, the metal nitride layer is a tungsten nitride layer and the metallic layer is a tungsten layer.
      • (9) A process for producing a semiconductor device, which comprises a step of forming a first insulation layer on the surface of a semiconductor substrate, a step of depositing a silicon layer on the first insulation layer, a step of depositing a first metallic layer on the silicon layer, a step of depositing a reaction barrier layer such as a metal nitride layer on the first metallic layer, a step of depositing a second metallic layer on the metal nitride layer, a step of processing a stacked structure of the silicon layer, the first metallic layer, the metal nitride layer and the second metallic layer into a gate electrode form, a step of ion implanting an impurity onto the surface of the semiconductor substrate, using the gate electrode as a mask, and a step of reacting the first metallic layer with the silicon layer by heat treatment, thereby forming a metal silicide layer.
      • (10) A process according to item (9), wherein in the last step the heat treatment is carried out at 650° C. or higher, preferably up to 1100° C.
      • (11) A process according to item (9), wherein the metal silicide layer is a tungsten silicide layer, the metal nitride layer is a tungsten nitride layer and the first and second metallic layers are tungsten layers.
      • (12) A process for producing a semiconductor device; which comprises a first step of forming a first insulation layer on the surface of a semiconductor substrate, a second step of depositing a silicon layer on the first insulation layer, a third step of depositing a first metallic layer on the silicon layer a fourth step of depositing a reaction barrier layer such as a metal nitride layer on the first metallic layer, a fifth step of depositing a second metallic layer on the metal nitride layer, a sixth step of reacting the first metallic layer with the silicon layer by heat treatment, thereby forming a metal silicide layer, a seventh step of processing the stacked structure comprising the silicon layer, the metal silicide layer, the metal nitride layer and the second metallic layer into a gate electrode form, and an eighth step of ion implanting an impurity onto the surface of the semiconductor substrate, using the gate electrode as a mask.
      • (13) A process according to item (12), wherein in the sixth step the heat treatment is carried out at 650° C. or higher, preferably up to 1100° C.
      • (14) A process according to item (12), wherein the metal silicide layer is a tungsten silicide layer, the metal nitride layer is a tungsten nitride layer and the first and second metallic layers are tungsten layers.
      • (15) A process for producing a semiconductor device, which comprises a step of forming a first insulation layer on the surface of a semiconductor substrate, a step of depositing a silicon layer on the first insulation layer, a step of depositing a metal silicide layer on the silicon layer, a step of depositing a reaction barrier layer such as a metal nitride layer on the metal silicide layer, a step of depositing a metallic layer on the metal nitride layer, a step of processing the stacked structure comprising the silicon layer, the metal silicide layer, the metal nitride layer and the metallic layer into a gate electrode form, and a step of ion implanting an impurity onto the surface of the semiconductor substrate, using the gate electrode as a mask.
      • (16) A process according to item (15), wherein the metal silicide layer is a tungsten silicide layer, the metal nitride layer is a tungsten nitride layer and the metallic layer is a tungsten layer.
  • As mentioned above, the semiconductor device of the present invention is characterized by having a metal/reaction barrier/metal silicide/polycrystalline silicon stacked gate electrode.
  • The lowest layer is made of polycrystalline silicon which can be doped with an impurity, and stacked thereon a metal silicide layer made of; for example, tungsten silicide, molybdenum silicide, nickel silicide, tantalum silicide, hafnium silicide, zirconium silicide, cobalt silicide, etc, and stacked thereon a reaction barrier layer made of, for example, tungsten nitride, titanium nitride, molybdenum nitride, tantalum nitride, tungsten carbide, titanium carbide, molybdenum carbide, tantalum carbide, etc. The uppermost layer is a metal layer made of, for example, tungsten, molybdenum, etc.
  • The present invention will be described in detail below, referring to Examples and Drawings.
    • EXAMPLE 1
  • FIGS. 1A to 1E are cross-sectional views showing process steps for forming a gate electrode according to Example 1 of the present invention.
  • Gate insulation layer 102 is formed on the surface of semiconductor substrate 101 e.g., by thermal oxidation, and then polycrystalline silicon layer 103 is deposited thereon e.g. by CVD (FIG. 1A).
  • Polycrystalline silicon layer 103 is doped with an impurity of any desired conductivity type (e.g. phosphorus or boron) by ion implanting, followed by activation annealing at 950°-1,000° C. Then, metallic layer 104 of e.g. tungsten is deposited thereon to a thickness of about 5 nm e.g. by sputtering, where precleaning e.g. with hydrofluoric acid is carried out beforehand to remove natural oxide, etc. remaining on the surface of polycrystalline silicon layer 103. Then, metal nitride layer 105 of e.g. tungsten nitride as a reaction barrier and metallic layer 106 of e.g. tungsten are deposited thereon one after the other to a thickness of about 5 to about 10 nm and to a thickness of about 50 nm, respectively, e.g. by sputtering (FIG. 1B).
  • It is desirable to deposit these metallic layers 104 and 106 or metal nitride layer 105 continuously without exposure to the air. Then, silicon oxide layer 107 is deposited on metallic layer 6 e.g. by plasma CVD (FIG. 1C).
  • The stacked structure of these deposited layers is processed into a gate electrode e.g. by lithography and anisotropic dry etching, using a resist (FIG. 1D).
  • Then, metallic layer 104 is made to react with polycrystalline silicon layer 103 by heat treatment at 650° C. or higher in a process for forming a CMOS device, thereby forming metal silicide layer 108 of e.g. tungsten silicide to a thickness about twice as large as that of deposited metallic layer 104.
  • The gate electrode thus formed has a contact resistance by about {fraction (1/10)} to about {fraction (1/40)} lower than that of the conventional gate electrode without insertion of a metal silicide layer, because a desirable metal/semiconductor contact can be formed between metal silicide layer 108 and polycrystalline silicon layer 103 in the present Example.
    • EXAMPLE 2
  • FIG. 2A to 2D are cross-sectional views showing process steps for forming a gate electrode according to Example 2 of the present invention.
  • The process steps of FIGS. 2A and 2B are identical with those of FIGS. 1A and 1B of Example 1. After gate insulation layer 102, polycrystalline silicon layer 103, metallic layer 104 of e.g. tungsten, metal nitride layer 105 of e.g. tungsten nitride, and metallic layer 106 of e.g. tungsten have been deposited on silicon substrate 101 as a stacked structure (FIG. 26), heat treatment of the stacked structure is carried out at 650° C. or higher in the present Example to react metallic layer 104 with polycrystalline silicon layer 103, thereby forming metal silicide layer 108 of e.g. tungsten silicide only to a thickness about twice as large as that of deposited metallic layer 104 (FIG. 2C) Then, the stacked structure is processed into a gate electrode e.g. by lithography and anisotropic dry etching using a resist (FIG. 2D)
  • The gate electrode thus formed has a contact resistance by about {fraction (1/10)} to about {fraction (1/40)} lower than that of the conventional gate electrode without insertion of a metal silicide layer, because a desirable metal/semiconductor contact can be formed between metal silicide layer 108 and polycrystalline silicon layer 103 in the present Example.
    • EXAMPLE 3
  • FIGS. 3A to 3D are cross-sectional views showing process steps for forming a gate electrode according to Example 3 of the present invention.
  • Gate insulation layer 102 is formed on the surface of semiconductor substrate 101 e.g. by thermal oxidation, and then polycrystalline silicon layer 103 is deposited thereon e.g. by CVD (FIG. 3A).
  • Polycrystalline silicon layer 103 is doped with an impurity of any desired conductivity type (e.g. phosphorus or boron) by ion implanting, followed by activation annealing at 950°-1,000° C. Then, metal silicide layer 109 of e.g. tungsten silicide is deposited thereon to a thickness of 5-20 nm e.g. by sputtering or CVD, where precleaning e.g. with hydrofluoric acid is carried out beforehand to remove natural oxide, etc. remaining on the surface of polycrystalline silicon layer 103. Then, metal nitride layer 105 of e.g. tungsten nitride as a reaction barrier and metallic layer 106 of e.g. tungsten are deposited thereon one after the other to a thickness of about 5 to about 10 nm and to thickness of about 50 nm, respectively, e.g. by sputtering (FIG. 3B).
  • It is desirable to deposit these metal silicide layer 109, metal nitride layer 105 and metallic layer 106 continuously without exposure to the air. Then, silicon oxide layer 107 is deposited on metallic layer 106, e.g. by plasma CVD (FIG. 3C).
  • The stacked structure of these deposited layers is processed into a gate electrode, e.g. by lithography and anisotropic dry etching using a resist (FIG. 3D).
  • The gate electrode thus formed has a contact resistance by about {fraction (1/10)} to about {fraction (1/40)} lower than that of the conventional gate electrode without insertion of a metal silicide layer, because a desirable metal/semiconductor contact can be formed between metal silicide layer 109 and polycrystalline silicon layer 103 in the present Example.
    • EXAMPLE 4
  • FIGS. 4A to 4C and FIGS. 5A to 5C are cross-sectional views showing process steps for producing CMOS (complementary MOS) transistors according to Example 4 of the present invention.
  • The surface of silicon substrate 301 is oxidized to a thickness of about 10 nm e.g. by thermal oxidation to form oxide layer 302, and silicon nitride layer 303 is deposited thereon to a thickness of about 150 nm e.g. by thermal CVD. Then, a trench is formed to a depth of about 0.3 μm in a region serving as isolation area of silicon substrate 301 by photolithography and dry etching and then the inside surface of the trench is thermally oxidized to a thickness of about 10 nm (FIG. 4A).
  • Then, silicon oxide layer 304 is deposited e.g. by CVD to fill the trench, and the silicon nitride layer 305 is deposited thereon e.g. by thermal CVD. Silicon nitride layer 305 is removed only from the surface of device-active region e.g. by photolithography and dry etching, as shown in FIG. 4B, followed by flattening by CMP (Chemical Mechanical Polishing). Polishing rate of silicon nitride layers 303 and 305 is lower than that of silicon oxide layer 304, so that the polishing can be discontinued at the level of silicon nitride layers 303 and 305. Then, silicon nitride layers 303 and 305 and silicon oxide layer 302 are removed by wet cleaning (FIG. 4C).
  • Then, gate insulation layer 310 is formed on the surface of semiconductor substrate 301 e.g. by thermal oxidation, and polycrystalline silicon layer is formed thereon e.g. by CVD. The polycrystalline silicon layer is locally doped with an impurity of n-type (e.g. phosphorus) and with another impurity of p-type (e.g. boron) by ion implanting, thereby forming n-type polycrystalline silicon layer 311 as an NMOS gate electrode and p-type polycrystalline silicon layer 312 as a PMOS gate electrode, respectively, followed by activation annealing at 950° C. Then, metallic layer 309 of e.g. tungsten is deposited thereon to a thickness of about 5 nm e.g. by sputtering, where precleaning e.g. with hydrofluoric acid is carried out beforehand to remove natural oxide, etc. remaining on the surfaces of polycrystalline silicon layers 311 and 312. Then, metal nitride layer 308 of e.g. tungsten nitride as a reaction barrier and metallic layer 307 of e.g. tungsten are deposited thereon one after the other to a thickness of about 5 to about 10 nm and to a thickness of about 50 nm, respectively, e.g. by sputtering. It is desirable to deposit these metallic layer 309, metal nitride layer 308 and metallic layer 307 continuously without exposing to the air. Then, silicon oxide layer 306 is deposited on metallic layer 307 e.g. by plasma CVD.
  • The stacked structure of these deposited layers is processed into gate electrodes e.g. by lithography and anisotropic dry etching using a resist.
  • Then, NMOS diffusion layer region 314 and punch-through stopper region 315, and PMOS diffusion layer region 316 and punch-through stopper region 317 are formed by photolithography and ion implanting (FIG. 5A).
  • Furthermore, after a silicon oxide layer is deposited thereon e.g. by plasma CVD, side walls 313 of silicon oxide are formed on the gate electrode sides by removing the deposited silicon oxide layer only by a corresponding deposited thickness portion by isotropic dry etching. Then, deeper NMOS and PMOS diffusion layer regions 318 and 319, respectively, are formed by photolithography and ion implanting (FIG. 5B).
  • Then, metallic layer 309 is made to react with polycrystalline silicon layers 311 and 312 by activation annealing of transistor [e.g. RTA(Rapid Thermal Annealing) at 950° C. for 10 seconds], thereby forming metal silicide layer 320 of e.g. tungsten silicide to a thickness about, twice as large as that of deposited metallic layer 309 (FIG. 5C).
  • The gate electrodes thus formed have a contact resistance by about {fraction (1/10)} to about {fraction (1/40)} lower than that of the conventional gate electrodes without insertion of a metal silicide layer, because a desirable metal/semiconductor contact can be formed between metal silicide layer 320 and polycrystalline silicon layer 311 or 312 in the present Example. Device circuit performance (propagation delay of CMOS device under no load) can be also increased to about 12 ps from about 28 ps (CMOS device with gate length generation of 0.10 μm) owing to these effects.
    • EXAMPLE 5
  • FIGS. 6A to 6C and FIGS. 7A to 7C are cross-sectional views showing process steps for producing CMOS transistors according to Example 5 of the present invention.
  • The surface of silicon substrate 301 is oxidized to a thickness of about 10 nm e.g. by thermal oxidation to form oxide layer 302, and silicon nitride layer 303 is deposited thereon to a thickness of about 150 nm e.g. by thermal CVD. Then, a trench is formed to a depth of about 0.3 pm in a region serving as isolation area of silicon substrate 301 by photolithography and dry etching and then the inside surface of the trench is thermally oxidized to a thickness of about 10 nm (FIG. 6A).
  • Then, silicon oxide layer 304 is deposited e.g. by CVD to fill the trench and then silicon nitride layer 305 is deposited thereon e.g. by thermal CVD. Silicon nitride layer 305 is removed only from the surface of device-active region e.g. by photolithography and dry etching as shown in FIG. 6B, followed by flattening by CMP (Chemical Mechanical Polishing). Polishing rate of silicon nitride layer 303 and 305 is lower than that of silicon oxide layer 304, so that the polishing can be discontinued at the level of silicon nitride layers 303 and 305. Then, silicon nitride layers 303 and 305 and silicon oxide layers 302 are removed by wet cleaning (FIG. 6C).
  • Then, gate insulation layer 310 is formed on the surface of semiconductor substrate 301 e.g. by thermal oxidation, and polycrystalline silicon layer is formed thereon e.g. by CVD. The polycrystalline silicon layer is locally doped with an impurity of n-type (e.g. phosphorus) and with another impurity of p-type (e.g. boron) by ion implanting, thereby forming n-type polycrystalline silicon layer 311 as an NMOS gate electrode and p-type polycrystalline silicon layer 312 as a PMOS gate electrode, respectively, followed by activation annealing at 950° C. Then, metallic layer 309 of e.g. tungsten is deposited thereon to a thickness of about S nm e.g. by sputtering, where precleaning e.g. with hydrofluoric acid is carried out beforehand to remove natural oxide, etc. remaining on the surfaces of polycrystalline silicon layers 311 and 312. Then, metal nitride layer 308 of e.g. tungsten nitride as a reaction barrier and metallic layer 307 of e.g. tungsten are deposited thereon one after the other to a thickness of about 5 to about 10 nm and to a thickness of about 50 nm, respectively, e.g. by sputtering. It is desirable to deposit these metallic layer 309, metal nitride layer 308 and metallic layer 307 continuously without exposing to the air. Then, silicon oxide layer 306 is deposited on metallic layer 307 e.g. by plasma CVD (FIG. 7A).
  • In the present Example, heat treatment is carried out at 650° C. or higher at this stage to make metallic layer 309 to react with polycrystalline silicon layers 311 and 312, thereby forming metal silicide layer 320 of e.g. tungsten silicide to a thickness about twice as large as that of deposited metallic layer 309 (FIG. 7B).
  • The stacked structure of these deposited layers is processed into gate electrodes e.g. by lithography and anisotropic dry etching using a resist.
  • Then, NMOS diffusion layer region 314 and punch-through stopper region 315, and PMOS diffusion layer region 316 and punch-through stopper region 317 are formed by photolithography and ion implanting. Furthermore, after a silicon oxide layer is deposited thereon e.g. by plasma CVD, side walls 313 of silicon oxide are formed on the gate electrode sides by, removing the deposited silicon oxide layer only by a corresponding deposited thickness portion by isotropic dry etching. Then, deeper NMOS diffusion layer region 318 and deeper PMOS diffusion layer region 319 are formed by photolithography and ion implanting (FIG. 7C).
  • The gate electrodes thus formed have a contact resistance by about {fraction (1/10)} to about {fraction (1/40)} lower than that of the conventional gate electrodes without insertion of a metal silicide, because a desirable metal/semiconductor contact can be formed between metal silicide layer 320 and polycrystalline silicon layer 311 or 312 in the present Example. Device circuit performance (propagation delay of CMOS device under no load) can be also increased to about 12 Ps from about 28 ps (CMOS device with gate length generation of 0.10 pm) owing to these effects.
  • Contact resistance at the conventional tungsten nitride/polycrystalline silicon boundary is in the order of 10−5 Ω cm2 irrespective of whether the polycrystalline silicon is of n- or p-type conductivity, thereby failing to achieve a metal/semiconductor boundary with desirable ohmic characteristics. The present invention, however, can provide a substantially desirable metal/semiconductor boundary by making a tungsten nitride/tungsten silicide/polycrystalline silicon-stacked structure, i.e. can provide a low contact resistance boundary capable of realizing desirable ohmic characteristics. When the present stacked structure is used in the MOS transistor gate electrode, circuit performance can be increased owing to the gate resistance-reducing effect of the present invention.

Claims (16)

1. A process for producing a semiconductor device, comprising the steps of:
(a) forming a first insulation layer on a surface of a semiconductor substrate;
(b) forming a silicon layer on the first insulation layer;
(c) forming a first metallic layer on the silicon layer;
(d) forming a metal nitride layer on the first metallic layer;
(e) forming a second metallic layer on the metal nitride layer;
(f) etching a stacked structure of the silicon layer, the first metallic layer, the metal nitride layer and the second metallic layer and forming a gate electrode; and
(g) annealing the gate electrode and reacting the first metallic layer with the silicon layer, thereby forming a metal silicide layer between the metal nitride layer and the silicon layer.
2. A process according to claim 1, wherein the step (g) is carried out at 650° C. or higher.
3. A process according to claim 1, wherein the metal silicide layer is a tungsten silicide layer, the metal nitride layer is a tungsten nitride layer, and the first and second metallic layers are tungsten layers.
4. A process according to claim 1, wherein the silicon layer is doped with an impurity.
5. A process according to claim 1, wherein the silicon layer is a polycrystalline silicon layer.
6. A process according to claim 1, wherein, in the step (g), the reaction of the first metallic layer with the silicon layer during annealing is such that the metal silicide layer is formed to have a thickness of about twice as large as the first metallic layer.
7. A process for producing a semiconductor device, comprising the steps of:
(a) forming a first insulation layer on a surface of a semiconductor substrate;
(b) forming a silicon layer on the first insulation layer;
(c) forming a first metallic layer on the silicon layer;
(d) forming a metal nitride layer on the first metallic layer;
(e) forming a second metallic layer on the metal nitride layer;
(f) annealing a stacked layer comprising the silicon layer, the first metallic layer, the metal nitride layer and the second metallic layer and reacting the first metallic layer with the silicon layer, thereby forming a metal silicide layer between the metal nitride layer and the silicon layer; and
(g) etching the stacked layer and forming a gate electrode.
8. A process according to claim 7, wherein the step (f) is carried out at 650° C. or higher.
9. A process according to claim 7, wherein the metal silicide layer is a tungsten silicide layer, the metal nitride layer is a tungsten nitride layer and the first and second metallic layers are tungsten layers.
10. A process according to claim 7, wherein the silicon layer is doped with an impurity.
11. A process according to claim 7, wherein the silicon layer is a polycrystalline silicon layer.
12. A process according to claim 7, wherein, in the step (f), the reaction of the first metallic layer with the silicon layer is such that the metal silicide layer is formed to have a thickness of about twice as large as the first metallic layer.
13. A process for producing a semiconductor device, comprising the steps of:
(a) forming a first insulation layer on a surface of a semiconductor substrate;
(b) forming a silicon layer on the first insulation layer;
(c) forming a metal silicide layer on the silicon layer;
(d) forming a metal nitride layer on the metal silicide layer;
(e) forming a metallic layer on the metal nitride layer; and
(f) etching the stacked layer comprising the silicon layer, the metal silicide layer, the metal nitride layer and the metallic layer, and forming a gate electrode.
14. A process according to claim 13, wherein the metal silicide layer is a tungsten silicide layer, the metal nitride layer is a tungsten nitride layer and the metallic layer is a tungsten layer.
15. A process according to claim 13, wherein the silicon layer is doped with an impurity.
16. A process according to claim 13, wherein the silicon layer is a polycrystalline silicon layer.
US11/087,612 2000-04-14 2005-03-24 Semiconductor device and process for producing the same Abandoned US20050164441A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/087,612 US20050164441A1 (en) 2000-04-14 2005-03-24 Semiconductor device and process for producing the same

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2000-118491 2000-04-14
JP2000118491A JP2001298186A (en) 2000-04-14 2000-04-14 Semiconductor device and manufacturing method thereof
US09/829,969 US6750503B2 (en) 2000-04-14 2001-04-11 Stacked gate electrode for a MOS transistor of a semiconductor device
US10/812,995 US20040178440A1 (en) 2000-04-14 2004-03-31 Semiconductor device and process for producing the same
US11/087,612 US20050164441A1 (en) 2000-04-14 2005-03-24 Semiconductor device and process for producing the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/812,995 Continuation US20040178440A1 (en) 2000-04-14 2004-03-31 Semiconductor device and process for producing the same

Publications (1)

Publication Number Publication Date
US20050164441A1 true US20050164441A1 (en) 2005-07-28

Family

ID=18629618

Family Applications (3)

Application Number Title Priority Date Filing Date
US09/829,969 Expired - Fee Related US6750503B2 (en) 2000-04-14 2001-04-11 Stacked gate electrode for a MOS transistor of a semiconductor device
US10/812,995 Abandoned US20040178440A1 (en) 2000-04-14 2004-03-31 Semiconductor device and process for producing the same
US11/087,612 Abandoned US20050164441A1 (en) 2000-04-14 2005-03-24 Semiconductor device and process for producing the same

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US09/829,969 Expired - Fee Related US6750503B2 (en) 2000-04-14 2001-04-11 Stacked gate electrode for a MOS transistor of a semiconductor device
US10/812,995 Abandoned US20040178440A1 (en) 2000-04-14 2004-03-31 Semiconductor device and process for producing the same

Country Status (4)

Country Link
US (3) US6750503B2 (en)
JP (1) JP2001298186A (en)
KR (1) KR20010098593A (en)
TW (1) TW492186B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040119089A1 (en) * 2002-01-25 2004-06-24 International Rectifier Corporation Compression assembled electronic package having a plastic molded insulation ring
US20050124127A1 (en) * 2003-12-04 2005-06-09 Tzu-En Ho Method for manufacturing gate structure for use in semiconductor device
US20080277736A1 (en) * 2007-05-08 2008-11-13 Kazuaki Nakajima Semiconductor device and method of manufacturing the same
US20140070417A1 (en) * 2012-09-10 2014-03-13 Kabushiki Kaisha Toshiba Semiconductor device having barrier metal layer

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4651848B2 (en) * 2000-07-21 2011-03-16 ルネサスエレクトロニクス株式会社 Semiconductor device, manufacturing method thereof, and CMOS transistor
JP4926329B2 (en) 2001-03-27 2012-05-09 株式会社半導体エネルギー研究所 Semiconductor device, method for manufacturing the same, and electric appliance
US6833556B2 (en) 2002-08-12 2004-12-21 Acorn Technologies, Inc. Insulated gate field effect transistor having passivated schottky barriers to the channel
US7084423B2 (en) 2002-08-12 2006-08-01 Acorn Technologies, Inc. Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US6902993B2 (en) * 2003-03-28 2005-06-07 Cypress Semiconductor Corporation Gate electrode for MOS transistors
JP2004319722A (en) 2003-04-16 2004-11-11 Hitachi Ltd Semiconductor integrated circuit device and its manufacturing method
US7534709B2 (en) 2003-05-29 2009-05-19 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
KR100693878B1 (en) 2004-12-08 2007-03-12 삼성전자주식회사 Semiconductor Device having low resistance and Method of manufacturing the same
US7183221B2 (en) * 2003-11-06 2007-02-27 Texas Instruments Incorporated Method of fabricating a semiconductor having dual gate electrodes using a composition-altered metal layer
DE102004004864B4 (en) * 2004-01-30 2008-09-11 Qimonda Ag Method for producing a gate structure and gate structure for a transistor
JP2005327848A (en) * 2004-05-13 2005-11-24 Toshiba Corp Semiconductor device and its manufacturing method
KR100681211B1 (en) * 2005-06-30 2007-02-09 주식회사 하이닉스반도체 Gate electrode with double diffusion barrier and method for manufacturing the same
KR100655658B1 (en) * 2005-07-26 2006-12-08 삼성전자주식회사 Gate electrode structure and method of manufacturing the gate electrode structure, and semiconductor transistor having the gate electrode structure and method of manufacturing the semiconductor transistor
KR100654358B1 (en) * 2005-08-10 2006-12-08 삼성전자주식회사 Semiconductor integrated circuit device and fabrication method for the same
KR100642761B1 (en) * 2005-09-07 2006-11-10 삼성전자주식회사 Semiconductor device and fabrication method for the same
KR100694660B1 (en) * 2006-03-08 2007-03-13 삼성전자주식회사 Transistor and method of manufacturing the same
JP4327820B2 (en) * 2006-06-05 2009-09-09 株式会社東芝 Semiconductor device and manufacturing method thereof
KR100914283B1 (en) * 2006-12-28 2009-08-27 주식회사 하이닉스반도체 Method for fabricating poly metal gate in semicondutor device
KR20100100178A (en) * 2009-03-05 2010-09-15 삼성전자주식회사 Semiconductor device
CN104170058B (en) 2011-11-23 2017-08-08 阿科恩科技公司 Improved by inserting interface atoms individual layer and contacted with the metal of IV races semiconductors
KR20140007609A (en) * 2012-07-09 2014-01-20 삼성전자주식회사 Method of manufacturing semiconductor devices
US20170054032A1 (en) 2015-01-09 2017-02-23 SanDisk Technologies, Inc. Non-volatile memory having individually optimized silicide contacts and process therefor
US9620611B1 (en) 2016-06-17 2017-04-11 Acorn Technology, Inc. MIS contact structure with metal oxide conductor
US10170627B2 (en) 2016-11-18 2019-01-01 Acorn Technologies, Inc. Nanowire transistor with source and drain induced by electrical contacts with negative schottky barrier height
CN108807163A (en) * 2017-06-05 2018-11-13 长鑫存储技术有限公司 A kind of semiconductor device structure and preparation method thereof
WO2019093206A1 (en) * 2017-11-09 2019-05-16 国立研究開発法人産業技術総合研究所 Semiconductor device, and method for manufacturing same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5010032A (en) * 1985-05-01 1991-04-23 Texas Instruments Incorporated Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects
US6265297B1 (en) * 1999-09-01 2001-07-24 Micron Technology, Inc. Ammonia passivation of metal gate electrodes to inhibit oxidation of metal
US6291868B1 (en) * 1998-02-26 2001-09-18 Micron Technology, Inc. Forming a conductive structure in a semiconductor device
US6306743B1 (en) * 2000-11-17 2001-10-23 Hyundai Electronics Industries Co., Ltd. Method for forming a gate electrode on a semiconductor substrate
US20020008294A1 (en) * 2000-07-21 2002-01-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method for manufacturing same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5010032A (en) * 1985-05-01 1991-04-23 Texas Instruments Incorporated Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects
US6291868B1 (en) * 1998-02-26 2001-09-18 Micron Technology, Inc. Forming a conductive structure in a semiconductor device
US6265297B1 (en) * 1999-09-01 2001-07-24 Micron Technology, Inc. Ammonia passivation of metal gate electrodes to inhibit oxidation of metal
US20020008294A1 (en) * 2000-07-21 2002-01-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method for manufacturing same
US6306743B1 (en) * 2000-11-17 2001-10-23 Hyundai Electronics Industries Co., Ltd. Method for forming a gate electrode on a semiconductor substrate

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040119089A1 (en) * 2002-01-25 2004-06-24 International Rectifier Corporation Compression assembled electronic package having a plastic molded insulation ring
US20050124127A1 (en) * 2003-12-04 2005-06-09 Tzu-En Ho Method for manufacturing gate structure for use in semiconductor device
US20080277736A1 (en) * 2007-05-08 2008-11-13 Kazuaki Nakajima Semiconductor device and method of manufacturing the same
US7768076B2 (en) * 2007-05-08 2010-08-03 Kabushiki Kaisha Toshiba Semiconductor device comprising an n-channel and p-channel MISFET
US20140070417A1 (en) * 2012-09-10 2014-03-13 Kabushiki Kaisha Toshiba Semiconductor device having barrier metal layer
US9018764B2 (en) * 2012-09-10 2015-04-28 Kabushiki Kaisha Toshiba Semiconductor device having barrier metal layer
US9412683B2 (en) 2012-09-10 2016-08-09 Kabushiki Kaisha Toshiba Semiconductor device having barrier metal layer

Also Published As

Publication number Publication date
US6750503B2 (en) 2004-06-15
JP2001298186A (en) 2001-10-26
TW492186B (en) 2002-06-21
US20010030342A1 (en) 2001-10-18
KR20010098593A (en) 2001-11-08
US20040178440A1 (en) 2004-09-16

Similar Documents

Publication Publication Date Title
US20050164441A1 (en) Semiconductor device and process for producing the same
US6551885B1 (en) Low temperature process for a thin film transistor
US6787424B1 (en) Fully depleted SOI transistor with elevated source and drain
US7633127B2 (en) Silicide gate transistors and method of manufacture
US6765273B1 (en) Device structure and method for reducing silicide encroachment
KR100352758B1 (en) Semiconductor device and method for manufacturing the same
US6777759B1 (en) Device structure and method for reducing silicide encroachment
US6495437B1 (en) Low temperature process to locally form high-k gate dielectrics
US6608354B2 (en) Semiconductor device and method of manufacturing the same
JP2008022027A (en) Method for forming self-aligned silicide in semiconductor device
JP4134001B2 (en) Manufacturing method of semiconductor device
US20030047781A1 (en) Semiconductor device on silicon-on-insulator and method for manufacturing the semiconductor device
US8004050B2 (en) Semiconductor device comprising gate electrode having arsenic and phosphorous
US6847086B2 (en) Semiconductor device and method of forming the same
US6258682B1 (en) Method of making ultra shallow junction MOSFET
US6395606B1 (en) MOSFET with metal in gate for reduced gate resistance
US6509253B1 (en) T-shaped gate electrode for reduced resistance
JP4745187B2 (en) Manufacturing method of semiconductor device
US7427796B2 (en) Semiconductor device and method of manufacturing a semiconductor device
US6287966B1 (en) Low sheet resistance of titanium salicide process
US6291301B1 (en) Fabrication method of a gate junction conductive structure
JP2007519217A (en) Semiconductor device and manufacturing method thereof
JP2005026707A (en) Semiconductor device and manufacturing method therefor
JPS6362379A (en) Manufacture of semiconductor device
JPH11177085A (en) Semiconductor device

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION