US20050178741A1

US20050178741A1 - Method of etching porous dielectric

Info

Publication number: US20050178741A1
Application number: US10/836,618
Authority: US
Inventors: Joon Yeoh
Original assignee: Trikon Technologies Ltd
Current assignee: Aviza Europe Ltd
Priority date: 2003-05-03
Filing date: 2004-05-03
Publication date: 2005-08-18

Abstract

The present invention relates to methods of etching a porous dielectric. The method includes etching the film in a plasma etch chamber with CF₄, H₂and a noble gas, wherein the CF₄to H₂gas flow ratio is between 1.33:1 and 2.7:1 and the noble gas is greater than about 42% of the total gas flow to the plasma chamber.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

A claim of priority is made to U.S. provisional application Ser. No. 60/468,263, filed May 7, 2003, and to British patent application no. 0310238.1, filed May 3, 2003.

BACKGROUND OF THE INVENTION

The present invention relates to methods of etching a porous dielectric layer that forms part of an interconnect structure on a substrate such as a wafer or multi chip module. In particular, but not exclusively, it relates to a method of etching a porous dielectric layer forming part of a dual damascene structure. More particularly it relates to a method of etching the upper part of a dual damascene structure.
To reduce the RC product in interconnect layers there is a requirement to reduce the capacitive coupling between adjoining conductors. Low dielectric constant (k) materials are therefore desirable and it is known that a vacuum gap has the lowest k value of 1. A known method of reducing bulk insulators' k values is to introduce porosity such that there is a matrix material and voids, thereby reducing the k value to less than that of the matrix.
Such porous materials present numerous problems for integration into practical devices and an additional complexity is introduced by the requirement to make ever smaller structures. As yet no porous dielectrics have been successfully integrated into state of the art devices in volume manufacturing for public sale.
At e.g. the 65 nm technology node there is a potential integration scheme whereby the total thickness of the dual damascene dielectric is deposited without an etch stop layer within it. The trench is then etched for a timed period into the dielectric and the etching terminated part way through the thickness of the dielectric. Over and above all the well known desirable aspects of anisotropic etching there is an additional requirement that the base of the etched trench is smooth. If the dielectric is porous (i.e. containing voids) then this is clearly a challenge. If the voids are very small then stopping in the voided dielectric may be acceptable though some degree of ‘healing’ of these voids is also desirable.
The Applicants have developed a porous dielectric known as Orion™ as is described in various patent applications in the name of the Applicants, e.g. WO/03/009364. This material has a k value in the range of 1.8 to 2.6 and is under evaluation at this time for integration into 65 nm (and below 65 nm) design rule logic devices at a k value of 2.2 to 2.5. It is this material that has been etched in this invention, though the invention also relates to any porous carbon doped silicon dioxide low-k dielectric e.g. a SiCOH type material. Typically such carbon doped oxides have methyl groups contained within them. Carbon (and thereby hydrogen) concentrations may be varied, higher concentrations leading to porosity under certain circumstances.
It should be made clear that this application is not related to the etched sidewalls. It is well known that to achieve anisotropic (directional) etching polymer is deposited on sidewalls to protect them from chemical attack whilst bombardment of the etch front (base of trench) removes this protective layer enabling downward etching. After etching the photoresist and any remaining polymer is then removed.
It should also be understood that in almost all cases layers of material forming interconnect layers are completely etched through such that the etch process stops on an ‘etch stop’ layer or some other layer that etches more slowly in the etchant than the layer being etched. It is somewhat unusual to terminate an etch part way through a layer but elimination of a device etch-stop layer is highly desirable as it reduces the effective k value of the structure and reduces the number of interfaces between layers. The Applicants have found (in unpublished work) that, perhaps not surprisingly, when such a partial etch is performed on a porous dielectric then a rough trench base is formed. This can be seen in FIGS. 1 (a) and 1 (b).
FIG. 1 (a) and (b) show rough etch front on SEM images after partial etch using CF₄and CH₂F₂gases, at 1250 W helicon source plasma power, 400 W platen (wafer) bias power, 2 mTorr, with wafer helium back pressure of 15 Torr (giving a wafer surface temperature of approximately 90-100° C. as indicated by temperature sensitive labels) in a MORI™ process chamber, as supplied by the Applicants.
FIG. 1 (a) shows a dual damascene structure. The etched porous oxide surface is at 1.
There is therefore a need for an improved etch process to provide a smooth base to an etched feature formed within a carbon doped silicon oxide type porous dielectric layer.

SUMMARY OF THE INVENTION

From one aspect the invention consists in a method of etching a porous carbon-doped silicon dioxide type dielectric film including plasma etching the film in a plasma etch chamber with CF₄H₂and a noble gas, wherein the CF₄to H₂gas flow ratio is between 1.33:1 and 2.7:1 and the noble gas is greater than about 42% of the total gas flow to the plasma chamber.

From another aspect the invention provides a method of plasma etching a porous dielectric layer of carbon doped silicon oxide material such as a SiCOH material with the following desirable characteristics:



Characteristic	Target result

Etch depth	40-70% of film thickness
Etch rate	200-500 nm/min
Selectivity to photoresist	Greater than 5:1
ARDE percentage	less than 5%

(Aspect Ratio Dependent Etch rate: the difference in etch rate in features

of different aspect ratio)

Side wall angle	90 degrees
Micro-trenching	none visible in an electron micrograph
Roughness	none visible in an electron micrograph
	when surface viewed in plan view or at
	45° degree glancing angle (at minimum
	magnification of 20,000)

Although the invention has been defined above it includes any inventive combination of the features set out above or in the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be performed in various ways and specific embodiments will now be described with reference to the accompanying drawings:
FIGS. 1(a) and (b), are SEM images of an etch front and partial etch using CF₄and CH₂F₂gases;
FIGS. 2(a), (b) and (c) illustrate similar etch fronts using CF₄and H₂with increasing amounts of argon present;
FIG. 3(a)a shows the etch front resulting from a non optimised process, whilst FIG. 3(b) illustrates the effect of a partial oxygen based resist step on the material of 3 (a);
FIGS. 4(a), (b) and (c) illustrate the effect of reducing amounts of backside cooling whilst FIGS. 5(a) and 5(b) are similar SEM's for a specified set of process conditions;
FIGS. 6(a) and (b) illustrate the results of the process using reduced cooling for particular process conditions and can be compared with FIG. 7 where the same process was run, but with increased cooling; and
FIGS. 8(a) and (b) show the etch front surfaces before and after resist etch has taken place.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Whilst a rough etch front 1(a) and (b) exhibited in FIG. 5 might be thought of as an obvious consequence of the film's porosity, it was observed that the surface roughness was greater than the mean pore size of 1-4 nm. This therefore suggested that the roughness of the etch front was not simply the result of exposure of pores and it was therefore postulated that an improved etch process could yield a smoother etch front/base of trench.
Initially the Applicants determined that noble gas additions, such as argon improved the smoothness of the etch front as illustrated in FIGS. 2, a, b and c.
Each of the processes illustrated in FIG. 2 was carried out in the MORI™ chamber referred to above with the chamber pressure being 110 mT, the plasma power 700 w applied to the wafer platen only and wafer helium backside pressure of 15 T (i.e. the water temperature was approximately 90-100° C.).
The gas flow rates, in seem, for the samples illustrated in FIGS. 2(a), (b) and (c) respectively were as follows:

CF₄ 80 60 60

H₂ 30 30 30

Ar 0 90 120
At 1 can be seen the etch front/base surface of the porous oxide where a) is no argon additions, b) has argon added, and c) has the most argon added to a reactive ion etch process of CF₄+H₂. It will be seen that the addition of argon results in a smoother etch front 1, with that of 2(c) being the smoothest. This is contrary to expectation, as it would be anticipated that increasing the physical sputter etch component by adding a heavy noble gas would increase roughness of etch front of a material of non-uniform density.
The process of FIG. 2 c is still not acceptable and shows for example pronounced microtrenching at 2.
It will be noted that in all cases the Applicants had selected a CF₄and H₂mix, rather than the more usual CF₄/O₂for the etch gas for the following reasons.
CF₄is a well known and readily available fluorine source and can etch with lower wafer bias power levels than other well known fluorine containing etch gasses because of its low polymer generation. Whilst silicon dioxide films are generally etched in a CF₄+Oxygen gas mix it was determined that oxygen should be excluded from the etch process, because the Applicants anticipated that there may be methyl groups formed in the film, which would be stripped from the film by O₂.
Hydrogen was then selected as an additional process gas on the basis of its ability to scavenge fluorine and increase selectivity by depressing the etch rate of silicon compared to silicon dioxide or carbide. Hydrogen plasma is known to cure or treat low-k materials from Applicants GB-A-0020 509. Increasing levels of hydrogen are known to have only a limited effect on silicon dioxide etch rate and to increase polymerization. Therefore the plasma would provide hydrogen radicals from hydrogen gas directly, rather than from CH₂F₂gas.
Argon was selected as a heavy noble gas (others may have been selected, such as krypton or xenon) because of its ability to increase ionization efficiency.
Considerable DOE (Design of Experiment) experimentation was then performed yielding the conclusions that a CF₄:H₂ratio of 2:1 was the best for this application, and a range of CF₄to H₂gas flow ratios of between 1.33:1 and 2.7:1 were acceptable.
This is an unusually high hydrogen concentration. It is generally held that in a CF₄+Hydrogen gas mix, the etch rate of both silicon dioxide and silicon falls to about zero at about 40% hydrogen in the CF₄+H₂gas mix due to the level of polymerization.
It was further discovered that for the CF₄and H₂flows rates being used, the argon flow should be at least 90 sccm and preferably about 77 percent of total gas flow. In a process of 80 sccm CF₄and 40 sccm of hydrogen, then argon gas flow was preferably 400 sccm and at least 90 sccm.
A further non-optimized process is shown at FIG. 3 a. At 1 the etch front can be seen and shows some surface roughness e.g. at 4 and micro trenching e.g. at 2 after etch completion into approximately 80 percent of Orion porous SICOH material with a k value of 2.2. ARDE is less than 2% (0.25 nanometres /1.25 micron structures), selectivity to photoresist 3 is greater than 6:1 and the etch rate is greater than 300 nm/min. The same structure as at FIG. 3 a was then subjected to a partial oxygen based resist strip and the results are shown at FIG. 3 b. As can be seen there is severe roughening of the etched base of the trench.
It has been discovered that to further improve etch results stopping within the thickness of the porous carbon-doped oxide then two further variations are necessary. Firstly, the porous SICOH material should have small pores with tightly controlled distribution. A material with average pore sizes in the range 1-4 nm etches more smoothly that a porous dielectric with a larger average pore size e.g. 4-5 nm and pores ranging in size from 2 nm-12 nm. It has also been found that the wafer temperature during etching has an effect on the surface roughness of the etch front.
Higher wafer temperatures yield smoother etch fronts. However, the maximum temperature is limited by photoresist reticulation.
It is notoriously difficult to specify the temperature of a film during an etch (or deposition) process as it is practically impossible to measure. Attempts at estimation may be made using temperature indicating stickers or ‘Sensarray™’ wafers with embedded thermocouples, but these are only approximations. It has however been noted that reducing the pressure of helium to the backside of the electrostatically clamped wafer (thereby reducing the thermal coupling of the wafer to the chilled electrostatic chuck) improved etch front smoothness as illustrated in FIGS. 4 a and b. These are submicron structures etched to 86% of the Orion film thickness both with the electrostatic chuck coolant set to −15° C. At FIG. 4 a is the etch result with 15 torr of helium pressure (sufficient to thermally couple the wafer to the chuck with a small thermal gradient) and in the case of FIG. 4 b the helium pressure is 2 torr. As can be seen the etch front 1 at FIG. 4 b is smoother than at FIG. 4 a.
Temperature sensing stickers on the face of a wafer indicate a wafer surface temperature of 93-99° C. for 15 torr pressure, −15° C. coolant temperature, and 143-149° C. for 2 torr helium backpressure and −15° C. coolant temperature.
An acceptable wafer surface temperature for the process of this invention is therefore estimated as above 100° C., preferably within the range 130° C. to 220° C., more preferably between 130-170° C. and most preferably about 150° C. (the upper temperature limited by the photoresist, higher temperatures being otherwise at least potentially equally preferable).
Minimum preferred pressure for the process is 80 mTorr. FIG. 5 (a) and (b) show the onset of etch front 1 surface roughness 4, for gas flows of 70 sccm CF₄, 30 sccm H₂, 90 sccm Ar, 700 W, with a wafer helium back pressure of 15 T (wafer ‘cold’).
FIG. 6 (a) and (b) show smooth etch front 1 after etching at higher wafer surface temperature (130° to 170° C.). This is achieved by reducing the Helium back pressure to 2 Torr, thereby lowering the thermal coupling of platen to wafer. The process conditions where otherwise revise CF₄—84 sccm; H₂—42 sccm; Ar—400 sccm; pressure 200 ml and power 1000 W.
FIG. 7 shows rougher etch fronts after processing at lower wafer surface temperature (−10 to +99° C.), when Helium back pressure is 15 Torr. Here the process conditions where essentially identical to those for FIG. 6 with slight variations in the CF₄and H₂flow rates being 82.55 sccm and 37.5 sccm respectively.
In order to prove that smooth etch front surface of the invention is not due to polymer residues covering the etch front/base, a N₂+H₂plasma strip was used to remove the photoresist post-etch. FIG. 8 (a) shows the smooth etch front 1 and photoresist 3 in place after hot etch. Figure 8 (b) shows the equally smooth etch front surface 1 after N₂+H₂plasma strip to remove the photoresist. There is no visible polymer residue remaining.

The first order major responses of each individual factor can thus be summarized below.



	etch front
increasing	smoothness	μ-trenching	ARDE	side wall angle

CF₄/H₂	↓	↓	↑	—
Ar Flow	↑	—	↓	—
pressure	—	↓	↑	—
power	—	↑	↓	↑
temperature	↑	↓	—	—

Best known process conditions to partially etch a porous SICOH type dielectric to leave a smooth etch front are therefore:



Etch gasses:	80 sccm CF₄, 40 sccm H₂, 400 sccm Ar, 5%
	variation in CF₄and H₂would yield similar
	result, so long as the CF₄:H₂ratio is kept at
	about 2:1.
Etch process pressure:	200 mTorr,
Plasma power:1000 W:	13.56 MHz applied to the wafer plate (RIE)
	(Power needs to be increased as pressure
	increases to avoid “wafer lens effect”)
wafer surface temp.:	100 to 170° C. (e.g. by adjusting platen
	temperature and/or Helium wafer back
	pressure thermal coupling)

Claims

1. A method of etching a porous carbon-doped silicon dioxide type dielectric film including plasma etching the film in a plasma etch chamber with CF₄, H₂and a noble gas, wherein the CF₄to H₂gas flow ratio is between 1.33:1 and 2.7:1 and the noble gas is greater than about 42% of the total gas flow to the plasma chamber.

2. A method as claimed in claim 1 wherein the CF₄:H₂ratio is about 2:1.

3. A method as claimed in claim 1 wherein the noble gas is argon.

4. A method as claimed in claim 3 wherein argon is present at up to about 77% of the total gas flow to the plasma etch chamber.

5. A method as claimed in claim 1 wherein film temperature is in the range of 100° C. and 170° C.

6. A method as claimed in claim 1 wherein the chamber pressure is in the range 90 mT to 300 mT.

7. A method as claimed in claim 1 wherein the power supplied to the plasma is between 700 and 1000 Watts.

8. A method as claimed in claim 1 wherein the etch is terminated within the film.

9. A method as claimed in claim 8 wherein the film is within an interconnect structure.

10. A method as claimed in claim 1 wherein the plasma etch is forming an interconnect structure or other relevant structure in the film.

11. A device incorporating a film as etched by the method of claim 1.